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https://github.com/espressif/esp-idf.git
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esp32h2: add stub code for efuse/esp_gdbstub/esp_phy
Only stub code for these components: * efuse * esp_gdbstub * esp_phy
This commit is contained in:
Shu Chen
parent
6fce2930d0
commit
e9a51e410a
63
components/efuse/esp32h2/esp_efuse_fields.c
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63
components/efuse/esp32h2/esp_efuse_fields.c
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@ -0,0 +1,63 @@
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/*
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* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp_efuse.h"
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#include "esp_efuse_utility.h"
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#include "esp_efuse_table.h"
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#include "stdlib.h"
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#include "esp_types.h"
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#include "esp32h2/rom/efuse.h"
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#include "assert.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "soc/efuse_periph.h"
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#include "bootloader_random.h"
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#include "sys/param.h"
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static __attribute__((unused)) const char *TAG = "efuse";
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// Contains functions that provide access to efuse fields which are often used in IDF.
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// Returns chip version from efuse
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uint8_t esp_efuse_get_chip_ver(void)
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{
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uint32_t chip_ver = 0;
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esp_efuse_read_field_blob(ESP_EFUSE_WAFER_VERSION, &chip_ver, ESP_EFUSE_WAFER_VERSION[0]->bit_count);
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return chip_ver;
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}
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// Returns chip package from efuse
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uint32_t esp_efuse_get_pkg_ver(void)
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{
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uint32_t pkg_ver = 0;
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esp_efuse_read_field_blob(ESP_EFUSE_PKG_VERSION, &pkg_ver, ESP_EFUSE_PKG_VERSION[0]->bit_count);
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return pkg_ver;
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}
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esp_err_t esp_efuse_set_rom_log_scheme(esp_efuse_rom_log_scheme_t log_scheme)
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{
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int cur_log_scheme = 0;
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esp_efuse_read_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &cur_log_scheme, 2);
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if (!cur_log_scheme) { // not burned yet
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return esp_efuse_write_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &log_scheme, 2);
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} else {
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return ESP_ERR_INVALID_STATE;
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}
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}
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esp_err_t esp_efuse_disable_rom_download_mode(void)
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{
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return esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE);
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}
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esp_err_t esp_efuse_enable_rom_secure_download_mode(void)
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{
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if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) {
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return ESP_ERR_INVALID_STATE;
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}
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return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD);
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}
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89
components/efuse/esp32h2/esp_efuse_rtc_calib.c
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89
components/efuse/esp32h2/esp_efuse_rtc_calib.c
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/*
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* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <esp_bit_defs.h>
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#include "esp_efuse.h"
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#include "esp_efuse_table.h"
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int esp_efuse_rtc_calib_get_ver(void)
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{
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uint32_t result = 0;
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esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &result, 3);
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return result;
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}
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uint16_t esp_efuse_rtc_calib_get_init_code(int version, int atten)
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{
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assert(version == 1);
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const esp_efuse_desc_t** init_code_efuse;
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assert(atten < 4);
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if (atten == 0) {
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init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0;
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} else if (atten == 1) {
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init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN1;
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} else if (atten == 2) {
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init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN2;
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} else {
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init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN3;
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}
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int init_code_size = esp_efuse_get_field_size(init_code_efuse);
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assert(init_code_size == 10);
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uint32_t init_code = 0;
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ESP_ERROR_CHECK(esp_efuse_read_field_blob(init_code_efuse, &init_code, init_code_size));
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return init_code + 1000; // version 1 logic
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}
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esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv)
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{
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const esp_efuse_desc_t** cal_vol_efuse;
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uint32_t calib_vol_expected_mv;
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if (version != 1) {
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return ESP_ERR_INVALID_ARG;
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}
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if (atten >= 4) {
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return ESP_ERR_INVALID_ARG;
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}
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if (atten == 0) {
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cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN0;
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calib_vol_expected_mv = 400;
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} else if (atten == 1) {
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cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN1;
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calib_vol_expected_mv = 550;
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} else if (atten == 2) {
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cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN2;
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calib_vol_expected_mv = 750;
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} else {
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cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN3;
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calib_vol_expected_mv = 1370;
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}
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assert(cal_vol_efuse[0]->bit_count == 10);
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uint32_t cal_vol = 0;
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ESP_ERROR_CHECK(esp_efuse_read_field_blob(cal_vol_efuse, &cal_vol, cal_vol_efuse[0]->bit_count));
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*out_digi = 2000 + ((cal_vol & BIT(9))? -(cal_vol & ~BIT9): cal_vol);
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*out_vol_mv = calib_vol_expected_mv;
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return ESP_OK;
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}
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float esp_efuse_rtc_calib_get_cal_temp(int version)
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{
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assert(version == 1);
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const esp_efuse_desc_t** cal_temp_efuse;
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cal_temp_efuse = ESP_EFUSE_TEMP_CALIB;
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int cal_temp_size = esp_efuse_get_field_size(cal_temp_efuse);
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assert(cal_temp_size == 9);
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uint32_t cal_temp = 0;
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esp_err_t err = esp_efuse_read_field_blob(cal_temp_efuse, &cal_temp, cal_temp_size);
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assert(err == ESP_OK);
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(void)err;
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// BIT(8) stands for sign: 1: negtive, 0: positive
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return ((cal_temp & BIT(8)) != 0)? -(uint8_t)cal_temp: (uint8_t)cal_temp;
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}
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1128
components/efuse/esp32h2/esp_efuse_table.c
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1128
components/efuse/esp32h2/esp_efuse_table.c
Normal file
File diff suppressed because it is too large
Load Diff
165
components/efuse/esp32h2/esp_efuse_table.csv
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165
components/efuse/esp32h2/esp_efuse_table.csv
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@ -0,0 +1,165 @@
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# field_name, | efuse_block, | bit_start, | bit_count, |comment #
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# | (EFUSE_BLK0 | (0..255) | (1..-) | #
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# | EFUSE_BLK1 | |MAX_BLK_LEN*| #
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# | ... | | | #
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# | EFUSE_BLK10)| | | #
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##########################################################################
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# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128.
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# !!!!!!!!!!! #
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# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse_common_table"
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# this will generate new source files, next rebuild all the sources.
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# !!!!!!!!!!! #
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# ESP32H2-TODO: IDF-3390
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# EFUSE_RD_REPEAT_DATA BLOCK #
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##############################
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# EFUSE_RD_WR_DIS_REG #
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WR_DIS, EFUSE_BLK0, 0, 32, Write protection
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WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
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WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
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WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for WDT_DELAY_SEL
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WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT
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WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0
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WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1
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WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2
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WR_DIS.KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0
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WR_DIS.KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1
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WR_DIS.KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2
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WR_DIS.KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3
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WR_DIS.KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4
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WR_DIS.KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5
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WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN
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WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
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WR_DIS.GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_TINY_BASIC DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
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WR_DIS.BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS
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WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1
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WR_DIS.USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA
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WR_DIS.KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0
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WR_DIS.KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1
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WR_DIS.KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2
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WR_DIS.KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3
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WR_DIS.KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4
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WR_DIS.KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5
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WR_DIS.SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2
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# EFUSE_RD_REPEAT_DATA0_REG #
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RD_DIS, EFUSE_BLK0, 32, 7, Read protection
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RD_DIS.KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0
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RD_DIS.KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1
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RD_DIS.KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2
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RD_DIS.KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3
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RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4
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RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5
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RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2
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DIS_RTC_RAM_BOOT, EFUSE_BLK0, 39, 1, Disable boot from RTC RAM
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DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache
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DIS_USB_JTAG, EFUSE_BLK0, 41, 1, Disable USB JTAG
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DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode
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DIS_USB_DEVICE, EFUSE_BLK0, 43, 1, Disable USB_DEVICE
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DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function
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DIS_USB, EFUSE_BLK0, 45, 1, Disable USB function
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DIS_CAN, EFUSE_BLK0, 46, 1, Disable CAN function
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JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
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SOFT_DIS_JTAG, EFUSE_BLK0, 48, 2, Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.
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DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, Disable JTAG in the hard way. JTAG is disabled permanently.
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DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encryption when in download boot modes.
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USB_DREFH, EFUSE_BLK0, 53, 2, Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.
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USB_DREFL, EFUSE_BLK0, 55, 2, Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.
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USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins
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VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, Set this bit to vdd spi pin function as gpio
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BTLC_GPIO_ENABLE, EFUSE_BLK0, 59, 2, Enable btlc gpio
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POWERGLITCH_EN, EFUSE_BLK0, 61, 1, Set this bit to enable power glitch function
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POWER_GLITCH_DSENSE, EFUSE_BLK0, 62, 2, Sample delay configuration of power glitch
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# EFUSE_RD_REPEAT_DATA1_REG #
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WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold
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SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
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SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key
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SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key
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SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key
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KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose
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KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose
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# EFUSE_RD_REPEAT_DATA2_REG #
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KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose
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KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose
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KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose
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KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose
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SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable
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SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke
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FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
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# EFUSE_RD_REPEAT_DATA3_REG #
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DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
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DIS_LEGACY_SPI_BOOT, EFUSE_BLK0, 129, 1, Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4
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UART_PRINT_CHANNEL, EFUSE_BLK0, 130, 1, 0: UART0. 1: UART1
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FLASH_ECC_MODE, EFUSE_BLK0, 131, 1, Set this bit to set flsah ecc mode. 0:flash ecc 16to18 byte mode. 1:flash ecc 16to17 byte mode
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DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, Disable download through USB
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ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode
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UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.
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PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI.
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FLASH_TYPE, EFUSE_BLK0, 137, 1, Connected Flash interface type. 0: 4 data line. 1: 8 data line
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FLASH_PAGE_SIZE, EFUSE_BLK0, 138, 2, Flash page size
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FLASH_ECC_EN, EFUSE_BLK0, 140, 1, Enable ECC for flash boot
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FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot
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SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback
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# EFUSE_RD_REPEAT_DATA4_REG #
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# MAC_SPI_SYS BLOCK#
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#######################
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MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0]
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, EFUSE_BLK1, 32, 8, Factory MAC addr [1]
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, EFUSE_BLK1, 24, 8, Factory MAC addr [2]
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, EFUSE_BLK1, 16, 8, Factory MAC addr [3]
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, EFUSE_BLK1, 8, 8, Factory MAC addr [4]
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, EFUSE_BLK1, 0, 8, Factory MAC addr [5]
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SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK
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SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1)
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SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0)
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SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS
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SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3)
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SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2)
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SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS
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SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4
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SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5
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SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
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SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
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WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version
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PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32H2
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BLOCK1_VERSION, EFUSE_BLK1, 120, 3, BLOCK1 efuse version
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# SYS_DATA_PART1 BLOCK# - System configuration
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#######################
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OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
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BLOCK2_VERSION, EFUSE_BLK2, 128, 3, Version of BLOCK2
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||||
TEMP_CALIB, EFUSE_BLK2, 131, 9, Temperature calibration data
|
||||
OCODE, EFUSE_BLK2, 140, 8, ADC OCode
|
||||
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, ADC1 init code at atten0
|
||||
ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, ADC1 init code at atten1
|
||||
ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, ADC1 init code at atten2
|
||||
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, ADC1 init code at atten3
|
||||
ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, ADC1 calibration voltage at atten0
|
||||
ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 198, 10, ADC1 calibration voltage at atten1
|
||||
ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 208, 10, ADC1 calibration voltage at atten2
|
||||
ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 218, 10, ADC1 calibration voltage at atten3
|
||||
|
||||
################
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, User data
|
||||
KEY0, EFUSE_BLK4, 0, 256, Key0 or user data
|
||||
KEY1, EFUSE_BLK5, 0, 256, Key1 or user data
|
||||
KEY2, EFUSE_BLK6, 0, 256, Key2 or user data
|
||||
KEY3, EFUSE_BLK7, 0, 256, Key3 or user data
|
||||
KEY4, EFUSE_BLK8, 0, 256, Key4 or user data
|
||||
KEY5, EFUSE_BLK9, 0, 256, Key5 or user data
|
||||
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration
|
||||
|
||||
# AUTO CONFIG DIG&RTC DBIAS#
|
||||
################
|
||||
K_RTC_LDO, EFUSE_BLK1, 135, 7, BLOCK1 K_RTC_LDO
|
||||
K_DIG_LDO, EFUSE_BLK1, 142, 7, BLOCK1 K_DIG_LDO
|
||||
V_RTC_DBIAS20, EFUSE_BLK1, 149, 8, BLOCK1 voltage of rtc dbias20
|
||||
V_DIG_DBIAS20, EFUSE_BLK1, 157, 8, BLOCK1 voltage of digital dbias20
|
||||
DIG_DBIAS_HVT, EFUSE_BLK1, 165, 5, BLOCK1 digital dbias when hvt
|
||||
THRES_HVT, EFUSE_BLK1, 170, 10, BLOCK1 pvt threshold when hvt
|
||||
|
Can't render this file because it contains an unexpected character in line 7 and column 87.
|
141
components/efuse/esp32h2/esp_efuse_utility.c
Normal file
141
components/efuse/esp32h2/esp_efuse_utility.c
Normal file
@ -0,0 +1,141 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_log.h"
|
||||
#include "assert.h"
|
||||
#include "esp_efuse_utility.h"
|
||||
#include "soc/efuse_periph.h"
|
||||
#include "esp32h2/clk.h"
|
||||
#include "esp32h2/rom/efuse.h"
|
||||
|
||||
static const char *TAG = "efuse";
|
||||
|
||||
#ifdef CONFIG_EFUSE_VIRTUAL
|
||||
extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK];
|
||||
#endif // CONFIG_EFUSE_VIRTUAL
|
||||
|
||||
/*Range addresses to read blocks*/
|
||||
const esp_efuse_range_addr_t range_read_addr_blocks[] = {
|
||||
{EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT
|
||||
{EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_RD_MAC_SPI_SYS_5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M
|
||||
{EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA
|
||||
{EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA
|
||||
{EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0
|
||||
{EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1
|
||||
{EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2
|
||||
{EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3
|
||||
{EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4
|
||||
{EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5
|
||||
{EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG} // range address of EFUSE_BLK10 KEY6
|
||||
};
|
||||
|
||||
static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 };
|
||||
|
||||
/*Range addresses to write blocks (it is not real regs, it is buffer) */
|
||||
const esp_efuse_range_addr_t range_write_addr_blocks[] = {
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK0][0], (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK1][0], (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK2][0], (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK3][0], (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK4][0], (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK5][0], (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK6][0], (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK7][0], (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK8][0], (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK9][0], (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]},
|
||||
};
|
||||
|
||||
#ifndef CONFIG_EFUSE_VIRTUAL
|
||||
// Update Efuse timing configuration
|
||||
static esp_err_t esp_efuse_set_timing(void)
|
||||
{
|
||||
// efuse clock is fixed in ESP32-C3, so the ets_efuse_set_timing() function
|
||||
// takes an argument for compatibility with older ROM functions but it's ignored.
|
||||
int res = ets_efuse_set_timing(0);
|
||||
assert(res == 0);
|
||||
(void)res;
|
||||
|
||||
REG_SET_FIELD(EFUSE_WR_TIM_CONF2_REG, EFUSE_PWR_OFF_NUM, 0x60);
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
#endif // ifndef CONFIG_EFUSE_VIRTUAL
|
||||
|
||||
// Efuse read operation: copies data from physical efuses to efuse read registers.
|
||||
void esp_efuse_utility_clear_program_registers(void)
|
||||
{
|
||||
ets_efuse_read();
|
||||
ets_efuse_clear_program_registers();
|
||||
}
|
||||
|
||||
// Burn values written to the efuse write registers
|
||||
void esp_efuse_utility_burn_efuses(void)
|
||||
{
|
||||
#ifdef CONFIG_EFUSE_VIRTUAL
|
||||
ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses");
|
||||
for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
|
||||
int subblock = 0;
|
||||
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
|
||||
virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block);
|
||||
}
|
||||
}
|
||||
#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
|
||||
esp_efuse_utility_write_efuses_to_flash();
|
||||
#endif
|
||||
#else
|
||||
if (esp_efuse_set_timing() != ESP_OK) {
|
||||
ESP_LOGE(TAG, "Efuse fields are not burnt");
|
||||
} else {
|
||||
// Permanently update values written to the efuse write registers
|
||||
// It is necessary to process blocks in the order from MAX-> EFUSE_BLK0, because EFUSE_BLK0 has protection bits for other blocks.
|
||||
for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
|
||||
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
|
||||
if (REG_READ(addr_wr_block) != 0) {
|
||||
if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
|
||||
uint8_t block_rs[12];
|
||||
ets_efuse_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs);
|
||||
memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs));
|
||||
}
|
||||
int data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t);
|
||||
memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len);
|
||||
ets_efuse_program(num_block);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif // CONFIG_EFUSE_VIRTUAL
|
||||
esp_efuse_utility_reset();
|
||||
}
|
||||
|
||||
// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values.
|
||||
// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme.
|
||||
// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this.
|
||||
// They will be filled during the burn operation.
|
||||
esp_err_t esp_efuse_utility_apply_new_coding_scheme()
|
||||
{
|
||||
// start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE.
|
||||
for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) {
|
||||
if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
|
||||
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
|
||||
if (REG_READ(addr_wr_block)) {
|
||||
int num_reg = 0;
|
||||
for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) {
|
||||
if (esp_efuse_utility_read_reg(num_block, num_reg)) {
|
||||
ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden.");
|
||||
return ESP_ERR_CODING;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return ESP_OK;
|
||||
}
|
||||
79
components/efuse/esp32h2/include/esp_efuse.h
Normal file
79
components/efuse/esp32h2/include/esp_efuse.h
Normal file
@ -0,0 +1,79 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Type of eFuse blocks ESP32H2
|
||||
*/
|
||||
typedef enum {
|
||||
EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */
|
||||
|
||||
EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */
|
||||
|
||||
EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
|
||||
EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA*/
|
||||
EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA*/
|
||||
|
||||
EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */
|
||||
EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */
|
||||
|
||||
EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */
|
||||
EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */
|
||||
|
||||
EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */
|
||||
EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */
|
||||
|
||||
EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */
|
||||
EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */
|
||||
|
||||
EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */
|
||||
EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */
|
||||
|
||||
EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK_KEY_MAX = 10,
|
||||
|
||||
EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
|
||||
EFUSE_BLK_MAX
|
||||
} esp_efuse_block_t;
|
||||
|
||||
/**
|
||||
* @brief Type of coding scheme
|
||||
*/
|
||||
typedef enum {
|
||||
EFUSE_CODING_SCHEME_NONE = 0, /**< None */
|
||||
EFUSE_CODING_SCHEME_RS = 3, /**< Reed-Solomon coding */
|
||||
} esp_efuse_coding_scheme_t;
|
||||
|
||||
/**
|
||||
* @brief Type of key purpose
|
||||
*/
|
||||
typedef enum {
|
||||
ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */
|
||||
ESP_EFUSE_KEY_PURPOSE_RESERVED = 1, /**< Reserved */
|
||||
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Digital Signature peripheral key (uses HMAC Downstream mode) */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8, /**< HMAC Upstream mode */
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_MAX, /**< MAX PURPOSE */
|
||||
} esp_efuse_purpose_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
54
components/efuse/esp32h2/include/esp_efuse_rtc_calib.h
Normal file
54
components/efuse/esp32h2/include/esp_efuse_rtc_calib.h
Normal file
@ -0,0 +1,54 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <esp_types.h>
|
||||
#include <esp_err.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Get the RTC calibration efuse version
|
||||
*
|
||||
* @return Version of the stored efuse
|
||||
*/
|
||||
int esp_efuse_rtc_calib_get_ver(void);
|
||||
|
||||
/**
|
||||
* @brief Get the init code in the efuse, for the corresponding attenuation.
|
||||
*
|
||||
* @param version Version of the stored efuse
|
||||
* @param atten Attenuation of the init code
|
||||
* @return The init code stored in efuse
|
||||
*/
|
||||
uint16_t esp_efuse_rtc_calib_get_init_code(int version, int atten);
|
||||
|
||||
/**
|
||||
* @brief Get the calibration digits stored in the efuse, and the corresponding voltage.
|
||||
*
|
||||
* @param version Version of the stored efuse
|
||||
* @param atten Attenuation to use
|
||||
* @param out_digi Output buffer of the digits
|
||||
* @param out_vol_mv Output of the voltage, in mV
|
||||
* @return
|
||||
* - ESP_ERR_INVALID_ARG: If efuse version or attenuation is invalid
|
||||
* - ESP_OK: if success
|
||||
*/
|
||||
esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv);
|
||||
|
||||
/**
|
||||
* @brief Get the temperature sensor calibration number delta_T stored in the efuse.
|
||||
*
|
||||
* @param version Version of the stored efuse
|
||||
*
|
||||
* @return The specification of temperature sensor calibration number in efuse.
|
||||
*/
|
||||
float esp_efuse_rtc_calib_get_cal_temp(int version);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
144
components/efuse/esp32h2/include/esp_efuse_table.h
Normal file
144
components/efuse/esp32h2/include/esp_efuse_table.h
Normal file
@ -0,0 +1,144 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
// md5_digest_table 9e42b2f9dd879191ca75ad0cf50841a1
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
// To show efuse_table run the command 'show_efuse_table'.
|
||||
|
||||
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DEVICE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_DSENSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_LEGACY_SPI_BOOT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CHANNEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
21
components/efuse/esp32h2/private_include/esp_efuse_utility.h
Normal file
21
components/efuse/esp32h2/private_include/esp_efuse_utility.h
Normal file
@ -0,0 +1,21 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define COUNT_EFUSE_REG_PER_BLOCK 8 /* The number of registers per block. */
|
||||
|
||||
#define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK0
|
||||
|
||||
#define ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(scheme, max_num_bit)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
4
components/efuse/esp32h2/sources.cmake
Normal file
4
components/efuse/esp32h2/sources.cmake
Normal file
@ -0,0 +1,4 @@
|
||||
set(EFUSE_SOC_SRCS "esp_efuse_table.c"
|
||||
"esp_efuse_fields.c"
|
||||
"esp_efuse_rtc_calib.c"
|
||||
"esp_efuse_utility.c")
|
||||
124
components/esp_gdbstub/esp32h2/gdbstub_esp32h2.c
Normal file
124
components/esp_gdbstub/esp32h2/gdbstub_esp32h2.c
Normal file
@ -0,0 +1,124 @@
|
||||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include "soc/uart_periph.h"
|
||||
#include "soc/gpio_periph.h"
|
||||
#include "soc/soc.h"
|
||||
#include "soc/usb_serial_jtag_struct.h"
|
||||
#include "hal/usb_serial_jtag_ll.h"
|
||||
#include "esp_gdbstub_common.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
#define UART_NUM CONFIG_ESP_CONSOLE_UART_NUM
|
||||
|
||||
#define GDBSTUB_MEM_REGION_COUNT 9
|
||||
|
||||
#define UART_REG_FIELD_LEN 0x84
|
||||
|
||||
typedef struct {
|
||||
intptr_t lower;
|
||||
intptr_t upper;
|
||||
} mem_bound_t;
|
||||
|
||||
static const mem_bound_t mem_region_table [GDBSTUB_MEM_REGION_COUNT] =
|
||||
{
|
||||
{SOC_DROM_LOW, SOC_DROM_HIGH},
|
||||
{SOC_IROM_LOW, SOC_IROM_HIGH},
|
||||
{SOC_IRAM_LOW, SOC_IRAM_HIGH},
|
||||
{SOC_DRAM_LOW, SOC_DRAM_HIGH},
|
||||
{SOC_IROM_MASK_LOW, SOC_IROM_MASK_HIGH},
|
||||
{SOC_DROM_MASK_LOW, SOC_DROM_MASK_HIGH},
|
||||
{SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH},
|
||||
// RTC DRAM and RTC DATA are identical with RTC IRAM, hence we skip them
|
||||
// We shouldn't read the uart registers since it will disturb the debugging via UART,
|
||||
// so skip UART part of the peripheral registers.
|
||||
{DR_REG_UART_BASE + UART_REG_FIELD_LEN, SOC_PERIPHERAL_HIGH},
|
||||
{SOC_DEBUG_LOW, SOC_DEBUG_HIGH},
|
||||
};
|
||||
|
||||
static inline bool check_inside_valid_region(intptr_t addr)
|
||||
{
|
||||
for (size_t i = 0; i < GDBSTUB_MEM_REGION_COUNT; i++) {
|
||||
if (addr >= mem_region_table[i].lower && addr < mem_region_table[i].upper) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
void esp_gdbstub_target_init()
|
||||
{
|
||||
}
|
||||
|
||||
#if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
|
||||
|
||||
int esp_gdbstub_getchar()
|
||||
{
|
||||
uint8_t c;
|
||||
//retry the read until we succeed
|
||||
while (usb_serial_jtag_ll_read_rxfifo(&c, 1)==0) ;
|
||||
return c;
|
||||
}
|
||||
|
||||
void esp_gdbstub_putchar(int c)
|
||||
{
|
||||
uint8_t cc=c;
|
||||
//retry the write until we succeed
|
||||
while (usb_serial_jtag_ll_write_txfifo(&cc, 1)<1) ;
|
||||
}
|
||||
|
||||
void esp_gdbstub_flush()
|
||||
{
|
||||
usb_serial_jtag_ll_txfifo_flush();
|
||||
}
|
||||
|
||||
|
||||
#else
|
||||
|
||||
//assume UART gdbstub channel
|
||||
|
||||
int esp_gdbstub_getchar()
|
||||
{
|
||||
while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_RXFIFO_CNT) == 0) {
|
||||
;
|
||||
}
|
||||
return REG_READ(UART_FIFO_AHB_REG(UART_NUM));
|
||||
}
|
||||
|
||||
void esp_gdbstub_putchar(int c)
|
||||
{
|
||||
while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_TXFIFO_CNT) >= 126) {
|
||||
;
|
||||
}
|
||||
REG_WRITE(UART_FIFO_AHB_REG(UART_NUM), c);
|
||||
}
|
||||
|
||||
void esp_gdbstub_flush()
|
||||
{
|
||||
//not needed for uart
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
int esp_gdbstub_readmem(intptr_t addr)
|
||||
{
|
||||
if (!check_inside_valid_region(addr)) {
|
||||
/* see esp_cpu_configure_region_protection */
|
||||
return -1;
|
||||
}
|
||||
uint32_t val_aligned = *(uint32_t *)(addr & (~3));
|
||||
uint32_t shift = (addr & 3) * 8;
|
||||
return (val_aligned >> shift) & 0xff;
|
||||
}
|
||||
15
components/esp_gdbstub/esp32h2/gdbstub_target_config.h
Normal file
15
components/esp_gdbstub/esp32h2/gdbstub_target_config.h
Normal file
@ -0,0 +1,15 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
@ -8,7 +8,13 @@ else()
|
||||
set(ldfragments "linker.lf")
|
||||
endif()
|
||||
|
||||
idf_component_register(SRCS "src/phy_init.c"
|
||||
if(IDF_TARGET STREQUAL "esp32h2")
|
||||
set(srcs "src/esp32h2/phy_init.c")
|
||||
else()
|
||||
set(srcs "src/phy_init.c")
|
||||
endif()
|
||||
|
||||
idf_component_register(SRCS "${srcs}"
|
||||
INCLUDE_DIRS "include" "${idf_target}/include"
|
||||
PRIV_REQUIRES nvs_flash
|
||||
LDFRAGMENTS "${ldfragments}")
|
||||
|
||||
30
components/esp_phy/esp32h2/include/phy_init_data.h
Normal file
30
components/esp_phy/esp32h2/include/phy_init_data.h
Normal file
@ -0,0 +1,30 @@
|
||||
// Copyright 2016-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef PHY_INIT_DATA_H
|
||||
#define PHY_INIT_DATA_H /* don't use #pragma once here, we compile this file sometimes */
|
||||
#include "esp_phy_init.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// ESP32H2-TODO: IDF-3398
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PHY_INIT_DATA_H */
|
||||
@ -1 +1 @@
|
||||
Subproject commit f2c056340505399429dbc8792e7109b7c69f5d77
|
||||
Subproject commit 5fd56f1692128209056fea699f9d118e88e176f6
|
||||
15
components/esp_phy/src/esp32h2/phy_init.c
Normal file
15
components/esp_phy/src/esp32h2/phy_init.c
Normal file
@ -0,0 +1,15 @@
|
||||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
// ESP32H2-TODO: IDF-3398
|
||||
Loading…
Reference in New Issue
Block a user