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Merge branch 'feature/Kconfig_rename' into 'master'

Browse Source 
Rename Kconfig options

Closes IDF-265

See merge request idf/esp-idf!4883
This commit is contained in:
Angus Gratton 2019-05-22 11:08:36 +08:00
commit e8ade3c68d
320 changed files with 3050 additions and 2550 deletions
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16
CMakeLists.txt
View File

@ -18,19 +18,19 @@ endif()
list(APPEND compile_definitions "-DGCC_NOT_5_2_0=${GCC_NOT_5_2_0}")
if(CONFIG_OPTIMIZATION_LEVEL_RELEASE)
if(CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE)
list(APPEND compile_options "-Os")
else()
list(APPEND compile_options "-Og")
endif()
if(CONFIG_CXX_EXCEPTIONS)
if(CONFIG_COMPILER_CXX_EXCEPTIONS)
list(APPEND cxx_compile_options "-fexceptions")
else()
list(APPEND cxx_compile_options "-fno-exceptions")
endif()
if(CONFIG_DISABLE_GCC8_WARNINGS)
if(CONFIG_COMPILER_DISABLE_GCC8_WARNINGS)
list(APPEND compile_options "-Wno-parentheses"
"-Wno-sizeof-pointer-memaccess"
"-Wno-clobbered")
@ -50,15 +50,15 @@ if(CONFIG_DISABLE_GCC8_WARNINGS)
endif()
endif()
if(CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED)
if(CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE)
list(APPEND compile_definitions "NDEBUG")
endif()
if(CONFIG_STACK_CHECK_NORM)
if(CONFIG_COMPILER_STACK_CHECK_MODE_NORM)
list(APPEND compile_options "-fstack-protector")
elseif(CONFIG_STACK_CHECK_STRONG)
elseif(CONFIG_COMPILER_STACK_CHECK_MODE_STRONG)
list(APPEND compile_options "-fstack-protector-strong")
elseif(CONFIG_STACK_CHECK_ALL)
elseif(CONFIG_COMPILER_STACK_CHECK_MODE_ALL)
list(APPEND compile_options "-fstack-protector-all")
endif()
@ -114,4 +114,4 @@ foreach(build_component ${build_components})
endif()
endforeach()
endif()
endforeach()
endforeach()

52
Kconfig
View File

@ -4,6 +4,12 @@
#
mainmenu "Espressif IoT Development Framework Configuration"
# Hidden option to support checking for this specific target in C code and Kconfig files
config IDF_TARGET_ESP32
bool
default "y" if IDF_TARGET="esp32"
default "n"
config IDF_CMAKE
bool
option env="IDF_CMAKE"
@ -60,9 +66,9 @@ mainmenu "Espressif IoT Development Framework Configuration"
menu "Compiler options"
choice OPTIMIZATION_COMPILER
choice COMPILER_OPTIMIZATION
prompt "Optimization Level"
default OPTIMIZATION_LEVEL_DEBUG
default COMPILER_OPTIMIZATION_LEVEL_DEBUG
help
This option sets compiler optimization level (gcc -O argument).
@ -76,15 +82,15 @@ mainmenu "Espressif IoT Development Framework Configuration"
in project makefile, before including $(IDF_PATH)/make/project.mk. Note that
custom optimization levels may be unsupported.
config OPTIMIZATION_LEVEL_DEBUG
config COMPILER_OPTIMIZATION_LEVEL_DEBUG
bool "Debug (-Og)"
config OPTIMIZATION_LEVEL_RELEASE
config COMPILER_OPTIMIZATION_LEVEL_RELEASE
bool "Release (-Os)"
endchoice
choice OPTIMIZATION_ASSERTION_LEVEL
choice COMPILER_OPTIMIZATION_ASSERTION_LEVEL
prompt "Assertion level"
default OPTIMIZATION_ASSERTIONS_ENABLED
default COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE
help
Assertions can be:
@ -96,20 +102,20 @@ mainmenu "Espressif IoT Development Framework Configuration"
- Disabled entirely (not recommended for most configurations.) -DNDEBUG is added
to CPPFLAGS in this case.
config OPTIMIZATION_ASSERTIONS_ENABLED
config COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE
prompt "Enabled"
bool
help
Enable assertions. Assertion content and line number will be printed on failure.
config OPTIMIZATION_ASSERTIONS_SILENT
config COMPILER_OPTIMIZATION_ASSERTIONS_SILENT
prompt "Silent (saves code size)"
bool
help
Enable silent assertions. Failed assertions will abort(), user needs to
use the aborting address to find the line number with the failed assertion.
config OPTIMIZATION_ASSERTIONS_DISABLED
config COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE
prompt "Disabled (sets -DNDEBUG)"
bool
help
@ -117,7 +123,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
endchoice # assertions
menuconfig CXX_EXCEPTIONS
menuconfig COMPILER_CXX_EXCEPTIONS
bool "Enable C++ exceptions"
default n
help
@ -129,17 +135,17 @@ mainmenu "Espressif IoT Development Framework Configuration"
Enabling this option currently adds an additional ~500 bytes of heap overhead
when an exception is thrown in user code for the first time.
config CXX_EXCEPTIONS_EMG_POOL_SIZE
config COMPILER_CXX_EXCEPTIONS_EMG_POOL_SIZE
int "Emergency Pool Size"
default 0
depends on CXX_EXCEPTIONS
depends on COMPILER_CXX_EXCEPTIONS
help
Size (in bytes) of the emergency memory pool for C++ exceptions. This pool will be used to allocate
memory for thrown exceptions when there is not enough memory on the heap.
choice STACK_CHECK_MODE
choice COMPILER_STACK_CHECK_MODE
prompt "Stack smashing protection mode"
default STACK_CHECK_NONE
default COMPILER_STACK_CHECK_MODE_NONE
help
Stack smashing protection mode. Emit extra code to check for buffer overflows, such as stack
smashing attacks. This is done by adding a guard variable to functions with vulnerable objects.
@ -162,23 +168,23 @@ mainmenu "Espressif IoT Development Framework Configuration"
- coverage: NORMAL < STRONG < OVERALL
config STACK_CHECK_NONE
config COMPILER_STACK_CHECK_MODE_NONE
bool "None"
config STACK_CHECK_NORM
config COMPILER_STACK_CHECK_MODE_NORM
bool "Normal"
config STACK_CHECK_STRONG
config COMPILER_STACK_CHECK_MODE_STRONG
bool "Strong"
config STACK_CHECK_ALL
config COMPILER_STACK_CHECK_MODE_ALL
bool "Overall"
endchoice
config STACK_CHECK
config COMPILER_STACK_CHECK
bool
default !STACK_CHECK_NONE
default !COMPILER_STACK_CHECK_MODE_NONE
help
Stack smashing protection.
config WARN_WRITE_STRINGS
config COMPILER_WARN_WRITE_STRINGS
bool "Enable -Wwrite-strings warning flag"
default "n"
help
@ -192,7 +198,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
For C++, this warns about the deprecated conversion from string
literals to ``char *``.
config DISABLE_GCC8_WARNINGS
config COMPILER_DISABLE_GCC8_WARNINGS
bool "Disable new warnings introduced in GCC 6 - 8"
default "n"
help
@ -223,4 +229,4 @@ mainmenu "Espressif IoT Development Framework Configuration"
You can still include these headers in a legacy way until it
is totally deprecated by enable this option.
endmenu #Compatibility options
endmenu #Compatibility options

6
components/app_trace/Kconfig
View File

@ -16,8 +16,8 @@ menu "Application Level Tracing"
config ESP32_APPTRACE_ENABLE
bool
depends on !ESP32_TRAX
select MEMMAP_TRACEMEM
select MEMMAP_TRACEMEM_TWOBANKS
select ESP32_MEMMAP_TRACEMEM
select ESP32_MEMMAP_TRACEMEM_TWOBANKS
default n
help
Enables/disable application tracing module.
@ -37,7 +37,7 @@ menu "Application Level Tracing"
Timeout for flushing last trace data to host in case of panic. In ms.
Use -1 to disable timeout and wait forever.
config ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH
config ESP32_APPTRACE_POSTMORTEM_FLUSH_THRESH
int "Threshold for flushing last trace data to host on panic"
depends on ESP32_APPTRACE_DEST_TRAX
range 0 16384

3
components/app_trace/app_trace.c
View File

@ -75,7 +75,8 @@
// trace data are necessary, e.g. for analyzing crashes. On panic the latest data from current input block are exposed to host and host can read them.
// It can happen that system panic occurs when there are very small amount of data which are not exposed to host yet (e.g. crash just after the
// TRAX block switch). In this case the previous 16KB of collected data will be dropped and host will see the latest, but very small piece of trace.
// It can be insufficient to diagnose the problem. To avoid such situations there is menuconfig option CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH
// It can be insufficient to diagnose the problem. To avoid such situations there is menuconfig option
// CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_THRESH
// which controls the threshold for flushing data in case of panic.
// - Streaming mode. Tracing module enters this mode when host connects to target and sets respective bits in control registers (per core).
// In this mode before switching the block tracing module waits for the host to read all the data from the previously exposed block.

4
components/app_trace/sdkconfig.rename Normal file
View File

@ -0,0 +1,4 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_THRESH

4
components/app_update/esp_app_desc.c
View File

@ -34,8 +34,8 @@ const __attribute__((section(".rodata_desc"))) esp_app_desc_t esp_app_desc = {
#endif
.idf_ver = IDF_VER,
#ifdef CONFIG_APP_SECURE_VERSION
.secure_version = CONFIG_APP_SECURE_VERSION,
#ifdef CONFIG_BOOTLOADER_APP_SECURE_VERSION
.secure_version = CONFIG_BOOTLOADER_APP_SECURE_VERSION,
#else
.secure_version = 0,
#endif

14
components/app_update/esp_ota_ops.c
View File

@ -113,7 +113,7 @@ static esp_err_t image_validate(const esp_partition_t *partition, esp_image_load
static esp_ota_img_states_t set_new_state_otadata(void)
{
#ifdef CONFIG_APP_ROLLBACK_ENABLE
#ifdef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
ESP_LOGD(TAG, "Monitoring the first boot of the app is enabled.");
return ESP_OTA_IMG_NEW;
#else
@ -144,7 +144,7 @@ esp_err_t esp_ota_begin(const esp_partition_t *partition, size_t image_size, esp
return ESP_ERR_OTA_PARTITION_CONFLICT;
}
#ifdef CONFIG_APP_ROLLBACK_ENABLE
#ifdef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
esp_ota_img_states_t ota_state_running_part;
if (esp_ota_get_state_partition(running_partition, &ota_state_running_part) == ESP_OK) {
if (ota_state_running_part == ESP_OTA_IMG_PENDING_VERIFY) {
@ -394,7 +394,7 @@ esp_err_t esp_ota_set_boot_partition(const esp_partition_t *partition)
return ESP_ERR_NOT_FOUND;
}
} else {
#ifdef CONFIG_APP_ANTI_ROLLBACK
#ifdef CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
esp_app_desc_t partition_app_desc;
esp_err_t err = esp_ota_get_partition_description(partition, &partition_app_desc);
if (err != ESP_OK) {
@ -582,7 +582,7 @@ esp_err_t esp_ota_get_partition_description(const esp_partition_t *partition, es
return ESP_OK;
}
#ifdef CONFIG_APP_ANTI_ROLLBACK
#ifdef CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
static esp_err_t esp_ota_set_anti_rollback(void) {
const esp_app_desc_t *app_desc = esp_ota_get_app_description();
return esp_efuse_update_secure_version(app_desc->secure_version);
@ -614,7 +614,7 @@ bool esp_ota_check_rollback_is_possible(void)
int last_active_ota = (~active_ota)&1;
const esp_partition_t *partition = NULL;
#ifndef CONFIG_APP_ANTI_ROLLBACK
#ifndef CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
if (valid_otadata[last_active_ota] == false) {
partition = esp_partition_find_first(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_APP_FACTORY, NULL);
if (partition != NULL) {
@ -630,7 +630,7 @@ bool esp_ota_check_rollback_is_possible(void)
partition = esp_partition_find_first(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_APP_OTA_MIN + slot, NULL);
if (partition != NULL) {
if(image_validate(partition, ESP_IMAGE_VERIFY_SILENT) == ESP_OK) {
#ifdef CONFIG_APP_ANTI_ROLLBACK
#ifdef CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
esp_app_desc_t app_desc;
if (esp_ota_get_partition_description(partition, &app_desc) == ESP_OK &&
esp_efuse_check_secure_version(app_desc.secure_version) == true) {
@ -661,7 +661,7 @@ static esp_err_t esp_ota_current_ota_is_workable(bool valid)
otadata[active_otadata].ota_state = ESP_OTA_IMG_VALID;
ESP_LOGD(TAG, "OTA[current] partition is marked as VALID");
esp_err_t err = rewrite_ota_seq(otadata, otadata[active_otadata].ota_seq, active_otadata, otadata_partition);
#ifdef CONFIG_APP_ANTI_ROLLBACK
#ifdef CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
if (err == ESP_OK) {
return esp_ota_set_anti_rollback();
}

16
components/app_update/test/test_switch_ota.c
View File

@ -240,7 +240,7 @@ static void reset_output_pin(uint32_t num_pin)
static void mark_app_valid(void)
{
#ifdef CONFIG_APP_ROLLBACK_ENABLE
#ifdef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
TEST_ESP_OK(esp_ota_mark_app_valid_cancel_rollback());
#endif
}
@ -519,7 +519,7 @@ static void test_rollback1(void)
TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_ota_get_state_partition(cur_app, &ota_state));
update_partition = app_update();
TEST_ESP_OK(esp_ota_get_state_partition(update_partition, &ota_state));
#ifndef CONFIG_APP_ROLLBACK_ENABLE
#ifndef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
TEST_ASSERT_EQUAL(ESP_OTA_IMG_UNDEFINED, ota_state);
#else
TEST_ASSERT_EQUAL(ESP_OTA_IMG_NEW, ota_state);
@ -531,7 +531,7 @@ static void test_rollback1(void)
TEST_ASSERT_EQUAL(ESP_PARTITION_SUBTYPE_APP_OTA_0, cur_app->subtype);
TEST_ASSERT_NULL(esp_ota_get_last_invalid_partition());
TEST_ESP_OK(esp_ota_get_state_partition(cur_app, &ota_state));
#ifndef CONFIG_APP_ROLLBACK_ENABLE
#ifndef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
TEST_ASSERT_EQUAL(ESP_OTA_IMG_UNDEFINED, ota_state);
#else
TEST_ASSERT_EQUAL(ESP_OTA_IMG_PENDING_VERIFY, ota_state);
@ -598,7 +598,7 @@ static void test_rollback2(void)
TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_ota_get_state_partition(cur_app, &ota_state));
update_partition = app_update();
TEST_ESP_OK(esp_ota_get_state_partition(update_partition, &ota_state));
#ifndef CONFIG_APP_ROLLBACK_ENABLE
#ifndef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
TEST_ASSERT_EQUAL(ESP_OTA_IMG_UNDEFINED, ota_state);
#else
TEST_ASSERT_EQUAL(ESP_OTA_IMG_NEW, ota_state);
@ -610,7 +610,7 @@ static void test_rollback2(void)
TEST_ASSERT_EQUAL(ESP_PARTITION_SUBTYPE_APP_OTA_0, cur_app->subtype);
TEST_ASSERT_NULL(esp_ota_get_last_invalid_partition());
TEST_ESP_OK(esp_ota_get_state_partition(cur_app, &ota_state));
#ifndef CONFIG_APP_ROLLBACK_ENABLE
#ifndef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
TEST_ASSERT_EQUAL(ESP_OTA_IMG_UNDEFINED, ota_state);
#else
TEST_ASSERT_EQUAL(ESP_OTA_IMG_PENDING_VERIFY, ota_state);
@ -621,7 +621,7 @@ static void test_rollback2(void)
TEST_ASSERT_EQUAL(ESP_OTA_IMG_VALID, ota_state);
update_partition = app_update();
TEST_ESP_OK(esp_ota_get_state_partition(update_partition, &ota_state));
#ifndef CONFIG_APP_ROLLBACK_ENABLE
#ifndef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
TEST_ASSERT_EQUAL(ESP_OTA_IMG_UNDEFINED, ota_state);
#else
TEST_ASSERT_EQUAL(ESP_OTA_IMG_NEW, ota_state);
@ -633,7 +633,7 @@ static void test_rollback2(void)
TEST_ASSERT_EQUAL(ESP_PARTITION_SUBTYPE_APP_OTA_1, cur_app->subtype);
TEST_ASSERT_NULL(esp_ota_get_last_invalid_partition());
TEST_ESP_OK(esp_ota_get_state_partition(cur_app, &ota_state));
#ifndef CONFIG_APP_ROLLBACK_ENABLE
#ifndef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
TEST_ASSERT_EQUAL(ESP_OTA_IMG_UNDEFINED, ota_state);
TEST_ESP_OK(esp_ota_mark_app_invalid_rollback_and_reboot());
#else
@ -666,7 +666,7 @@ static void test_rollback2_1(void)
TEST_ESP_OK(esp_ota_get_state_partition(cur_app, &ota_state));
TEST_ASSERT_EQUAL(ESP_OTA_IMG_VALID, ota_state);
TEST_ESP_OK(esp_ota_get_state_partition(invalid_partition, &ota_state));
#ifndef CONFIG_APP_ROLLBACK_ENABLE
#ifndef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
TEST_ASSERT_EQUAL(ESP_OTA_IMG_INVALID, ota_state);
#else
TEST_ASSERT_EQUAL(ESP_OTA_IMG_ABORTED, ota_state);

4
components/asio/port/include/esp_asio_config.h
View File

@ -18,9 +18,9 @@
// Enabling exceptions only when they are enabled in menuconfig
//
# include <sdkconfig.h>
# ifndef CONFIG_CXX_EXCEPTIONS
# ifndef CONFIG_COMPILER_CXX_EXCEPTIONS
# define ASIO_NO_EXCEPTIONS
# endif // CONFIG_CXX_EXCEPTIONS
# endif // CONFIG_COMPILER_CXX_EXCEPTIONS
//
// LWIP compatifility inet and address macros/functions

4
components/asio/port/include/esp_exception.h
View File

@ -18,7 +18,7 @@
//
// This exception stub is enabled only if exceptions are disabled in menuconfig
//
#if !defined(CONFIG_CXX_EXCEPTIONS) && defined (ASIO_NO_EXCEPTIONS)
#if !defined(CONFIG_COMPILER_CXX_EXCEPTIONS) && defined (ASIO_NO_EXCEPTIONS)
#include "esp_log.h"
@ -34,6 +34,6 @@ void throw_exception(const Exception& e)
abort();
}
}}
#endif // CONFIG_CXX_EXCEPTIONS==1 && defined (ASIO_NO_EXCEPTIONS)
#endif // CONFIG_COMPILER_CXX_EXCEPTIONS==1 && defined (ASIO_NO_EXCEPTIONS)
#endif // _ESP_EXCEPTION_H_

80
components/bootloader/Kconfig.projbuild
View File

@ -1,38 +1,38 @@
menu "Bootloader config"
choice LOG_BOOTLOADER_LEVEL
choice BOOTLOADER_LOG_LEVEL
bool "Bootloader log verbosity"
default LOG_BOOTLOADER_LEVEL_INFO
default BOOTLOADER_LOG_LEVEL_INFO
help
Specify how much output to see in bootloader logs.
config LOG_BOOTLOADER_LEVEL_NONE
config BOOTLOADER_LOG_LEVEL_NONE
bool "No output"
config LOG_BOOTLOADER_LEVEL_ERROR
config BOOTLOADER_LOG_LEVEL_ERROR
bool "Error"
config LOG_BOOTLOADER_LEVEL_WARN
config BOOTLOADER_LOG_LEVEL_WARN
bool "Warning"
config LOG_BOOTLOADER_LEVEL_INFO
config BOOTLOADER_LOG_LEVEL_INFO
bool "Info"
config LOG_BOOTLOADER_LEVEL_DEBUG
config BOOTLOADER_LOG_LEVEL_DEBUG
bool "Debug"
config LOG_BOOTLOADER_LEVEL_VERBOSE
config BOOTLOADER_LOG_LEVEL_VERBOSE
bool "Verbose"
endchoice
config LOG_BOOTLOADER_LEVEL
config BOOTLOADER_LOG_LEVEL
int
default 0 if LOG_BOOTLOADER_LEVEL_NONE
default 1 if LOG_BOOTLOADER_LEVEL_ERROR
default 2 if LOG_BOOTLOADER_LEVEL_WARN
default 3 if LOG_BOOTLOADER_LEVEL_INFO
default 4 if LOG_BOOTLOADER_LEVEL_DEBUG
default 5 if LOG_BOOTLOADER_LEVEL_VERBOSE
default 0 if BOOTLOADER_LOG_LEVEL_NONE
default 1 if BOOTLOADER_LOG_LEVEL_ERROR
default 2 if BOOTLOADER_LOG_LEVEL_WARN
default 3 if BOOTLOADER_LOG_LEVEL_INFO
default 4 if BOOTLOADER_LOG_LEVEL_DEBUG
default 5 if BOOTLOADER_LOG_LEVEL_VERBOSE
config BOOTLOADER_SPI_WP_PIN
int "SPI Flash WP Pin when customising pins via eFuse (read help)"
range 0 33
default 7
depends on FLASHMODE_QIO || FLASHMODE_QOUT
depends on ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT
help
This value is ignored unless flash mode is set to QIO or QOUT *and* the SPI flash pins have been
overriden by setting the eFuses SPI_PAD_CONFIG_xxx.
@ -140,7 +140,7 @@ menu "Bootloader config"
source for slow_clk - and ends calling app_main.
Re-set timeout is needed due to WDT uses a SLOW_CLK clock source. After changing a frequency slow_clk a
time of WDT needs to re-set for new frequency.
slow_clk depends on ESP32_RTC_CLOCK_SOURCE (INTERNAL_RC or EXTERNAL_CRYSTAL).
slow_clk depends on ESP32_RTC_CLK_SRC (INTERNAL_RC or EXTERNAL_CRYSTAL).
config BOOTLOADER_WDT_DISABLE_IN_USER_CODE
bool "Allows RTC watchdog disable in user code"
@ -163,7 +163,7 @@ menu "Bootloader config"
- these options can increase the execution time.
Note: RTC_WDT will reset while encryption operations will be performed.
config APP_ROLLBACK_ENABLE
config BOOTLOADER_APP_ROLLBACK_ENABLE
bool "Enable app rollback support"
default n
help
@ -175,22 +175,22 @@ menu "Bootloader config"
Note: If during the first boot a new app the power goes out or the WDT works, then roll back will happen.
Rollback is possible only between the apps with the same security versions.
config APP_ANTI_ROLLBACK
config BOOTLOADER_APP_ANTI_ROLLBACK
bool "Enable app anti-rollback support"
depends on APP_ROLLBACK_ENABLE
depends on BOOTLOADER_APP_ROLLBACK_ENABLE
default n
help
This option prevents rollback to previous firmware/application image with lower security version.
config APP_SECURE_VERSION
config BOOTLOADER_APP_SECURE_VERSION
int "eFuse secure version of app"
depends on APP_ANTI_ROLLBACK
depends on BOOTLOADER_APP_ANTI_ROLLBACK
default 0
help
The secure version is the sequence number stored in the header of each firmware.
The security version is set in the bootloader, version is recorded in the eFuse field
as the number of set ones. The allocated number of bits in the efuse field
for storing the security version is limited (see APP_SECURE_VERSION_SIZE_EFUSE_FIELD option).
for storing the security version is limited (see BOOTLOADER_APP_SEC_VER_SIZE_EFUSE_FIELD option).
Bootloader: When bootloader selects an app to boot, an app is selected that has
a security version greater or equal that recorded in eFuse field.
@ -201,19 +201,19 @@ menu "Bootloader config"
Your partition table should has a scheme with ota_0 + ota_1 (without factory).
config APP_SECURE_VERSION_SIZE_EFUSE_FIELD
config BOOTLOADER_APP_SEC_VER_SIZE_EFUSE_FIELD
int "Size of the efuse secure version field"
depends on APP_ANTI_ROLLBACK
depends on BOOTLOADER_APP_ANTI_ROLLBACK
range 1 32
default 32
help
The size of the efuse secure version field. Its length is limited to 32 bits.
This determines how many times the security version can be increased.
config EFUSE_SECURE_VERSION_EMULATE
config BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE
bool "Emulate operations with efuse secure version(only test)"
default n
depends on APP_ANTI_ROLLBACK
depends on BOOTLOADER_APP_ANTI_ROLLBACK
help
This option allow emulate read/write operations with efuse secure version.
It allow to test anti-rollback implemention without permanent write eFuse bits.
@ -400,7 +400,7 @@ menu "Security features"
Refer to https://docs.espressif.com/projects/esp-idf/en/latest/security/secure-boot.html before enabling.
config FLASH_ENCRYPTION_ENABLED
config SECURE_FLASH_ENC_ENABLED
bool "Enable flash encryption on boot (READ DOCS FIRST)"
default N
help
@ -411,9 +411,9 @@ menu "Security features"
Read https://docs.espressif.com/projects/esp-idf/en/latest/security/flash-encryption.html before enabling.
config FLASH_ENCRYPTION_INSECURE
config SECURE_FLASH_ENC_INSECURE
bool "Allow potentially insecure options"
depends on FLASH_ENCRYPTION_ENABLED
depends on SECURE_FLASH_ENC_ENABLED
default N
help
You can disable some of the default protections offered by flash encryption, in order to enable testing or
@ -425,17 +425,17 @@ menu "Security features"
https://docs.espressif.com/projects/esp-idf/en/latest/security/flash-encryption.html for details.
menu "Potentially insecure options"
visible if FLASH_ENCRYPTION_INSECURE || SECURE_BOOT_INSECURE
visible if SECURE_FLASH_ENC_INSECURE || SECURE_BOOT_INSECURE
# NOTE: Options in this menu NEED to have SECURE_BOOT_INSECURE
# and/or FLASH_ENCRYPTION_INSECURE in "depends on", as the menu
# and/or SECURE_FLASH_ENC_INSECURE in "depends on", as the menu
# itself doesn't enable/disable its children (if it's not set,
# it's possible for the insecure menu to be disabled but the insecure option
# to remain on which is very bad.)
config SECURE_BOOT_ALLOW_ROM_BASIC
bool "Leave ROM BASIC Interpreter available on reset"
depends on SECURE_BOOT_INSECURE || FLASH_ENCRYPTION_INSECURE
depends on SECURE_BOOT_INSECURE || SECURE_FLASH_ENC_INSECURE
default N
help
By default, the BASIC ROM Console starts on reset if no valid bootloader is
@ -449,7 +449,7 @@ menu "Security features"
config SECURE_BOOT_ALLOW_JTAG
bool "Allow JTAG Debugging"
depends on SECURE_BOOT_INSECURE || FLASH_ENCRYPTION_INSECURE
depends on SECURE_BOOT_INSECURE || SECURE_FLASH_ENC_INSECURE
default N
help
If not set (default), the bootloader will permanently disable JTAG (across entire chip) on first boot
@ -474,9 +474,9 @@ menu "Security features"
image to this length. It is generally not recommended to set this option, unless you have a legacy
partitioning scheme which doesn't support 64KB aligned partition lengths.
config FLASH_ENCRYPTION_UART_BOOTLOADER_ALLOW_ENCRYPT
config SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC
bool "Leave UART bootloader encryption enabled"
depends on FLASH_ENCRYPTION_INSECURE
depends on SECURE_FLASH_ENC_INSECURE
default N
help
If not set (default), the bootloader will permanently disable UART bootloader encryption access on
@ -484,9 +484,9 @@ menu "Security features"
It is recommended to only set this option in testing environments.
config FLASH_ENCRYPTION_UART_BOOTLOADER_ALLOW_DECRYPT
config SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC
bool "Leave UART bootloader decryption enabled"
depends on FLASH_ENCRYPTION_INSECURE
depends on SECURE_FLASH_ENC_INSECURE
default N
help
If not set (default), the bootloader will permanently disable UART bootloader decryption access on
@ -495,9 +495,9 @@ menu "Security features"
Only set this option in testing environments. Setting this option allows complete bypass of flash
encryption.
config FLASH_ENCRYPTION_UART_BOOTLOADER_ALLOW_CACHE
config SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE
bool "Leave UART bootloader flash cache enabled"
depends on FLASH_ENCRYPTION_INSECURE
depends on SECURE_FLASH_ENC_INSECURE
default N
help
If not set (default), the bootloader will permanently disable UART bootloader flash cache access on

22
components/bootloader/sdkconfig.rename Normal file
View File

@ -0,0 +1,22 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_LOG_BOOTLOADER_LEVEL CONFIG_BOOTLOADER_LOG_LEVEL
CONFIG_LOG_BOOTLOADER_LEVEL_NONE CONFIG_BOOTLOADER_LOG_LEVEL_NONE
CONFIG_LOG_BOOTLOADER_LEVEL_ERROR CONFIG_BOOTLOADER_LOG_LEVEL_ERROR
CONFIG_LOG_BOOTLOADER_LEVEL_WARN CONFIG_BOOTLOADER_LOG_LEVEL_WARN
CONFIG_LOG_BOOTLOADER_LEVEL_INFO CONFIG_BOOTLOADER_LOG_LEVEL_INFO
CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG
CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE
CONFIG_APP_ROLLBACK_ENABLE CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
CONFIG_APP_ANTI_ROLLBACK CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
CONFIG_APP_SECURE_VERSION CONFIG_BOOTLOADER_APP_SECURE_VERSION
CONFIG_APP_SECURE_VERSION_SIZE_EFUSE_FIELD CONFIG_BOOTLOADER_APP_SEC_VER_SIZE_EFUSE_FIELD
CONFIG_EFUSE_SECURE_VERSION_EMULATE CONFIG_BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE
CONFIG_FLASH_ENCRYPTION_ENABLED CONFIG_SECURE_FLASH_ENC_ENABLED
CONFIG_FLASH_ENCRYPTION_INSECURE CONFIG_SECURE_FLASH_ENC_INSECURE
CONFIG_FLASH_ENCRYPTION_UART_BOOTLOADER_ALLOW_ENCRYPT CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC
CONFIG_FLASH_ENCRYPTION_UART_BOOTLOADER_ALLOW_DECRYPT CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC
CONFIG_FLASH_ENCRYPTION_UART_BOOTLOADER_ALLOW_CACHE CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE

2
components/bootloader_support/src/bootloader_clock.c
View File

@ -53,7 +53,7 @@ void bootloader_clock_configure()
* part of the start up time by enabling 32k XTAL early.
* App startup code will wait until the oscillator has started up.
*/
#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
#ifdef CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
if (!rtc_clk_32k_enabled()) {
rtc_clk_32k_bootstrap(CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES);
}

20
components/bootloader_support/src/bootloader_init.c
View File

@ -173,7 +173,7 @@ static esp_err_t bootloader_main()
ESP_LOGI(TAG, "Enabling RNG early entropy source...");
bootloader_random_enable();
#if CONFIG_FLASHMODE_QIO || CONFIG_FLASHMODE_QOUT
#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
bootloader_enable_qio_mode();
#endif
@ -412,11 +412,11 @@ static void IRAM_ATTR flash_gpio_configure(const esp_image_header_t* pfhdr)
static void uart_console_configure(void)
{
#if CONFIG_CONSOLE_UART_NONE
#if CONFIG_ESP_CONSOLE_UART_NONE
ets_install_putc1(NULL);
ets_install_putc2(NULL);
#else // CONFIG_CONSOLE_UART_NONE
const int uart_num = CONFIG_CONSOLE_UART_NUM;
#else // CONFIG_ESP_CONSOLE_UART_NONE
const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM;
uartAttach();
ets_install_uart_printf();
@ -424,10 +424,10 @@ static void uart_console_configure(void)
// Wait for UART FIFO to be empty.
uart_tx_wait_idle(0);
#if CONFIG_CONSOLE_UART_CUSTOM
#if CONFIG_ESP_CONSOLE_UART_CUSTOM
// Some constants to make the following code less upper-case
const int uart_tx_gpio = CONFIG_CONSOLE_UART_TX_GPIO;
const int uart_rx_gpio = CONFIG_CONSOLE_UART_RX_GPIO;
const int uart_tx_gpio = CONFIG_ESP_CONSOLE_UART_TX_GPIO;
const int uart_rx_gpio = CONFIG_ESP_CONSOLE_UART_RX_GPIO;
// Switch to the new UART (this just changes UART number used for
// ets_printf in ROM code).
uart_tx_switch(uart_num);
@ -450,13 +450,13 @@ static void uart_console_configure(void)
gpio_matrix_out(uart_tx_gpio, tx_idx, 0, 0);
gpio_matrix_in(uart_rx_gpio, rx_idx, 0);
}
#endif // CONFIG_CONSOLE_UART_CUSTOM
#endif // CONFIG_ESP_CONSOLE_UART_CUSTOM
// Set configured UART console baud rate
const int uart_baud = CONFIG_CONSOLE_UART_BAUDRATE;
const int uart_baud = CONFIG_ESP_CONSOLE_UART_BAUDRATE;
uart_div_modify(uart_num, (rtc_clk_apb_freq_get() << 4) / uart_baud);
#endif // CONFIG_CONSOLE_UART_NONE
#endif // CONFIG_ESP_CONSOLE_UART_NONE
}
static void wdt_reset_cpu0_info_enable(void)

28
components/bootloader_support/src/bootloader_utility.c
View File

@ -169,7 +169,7 @@ bool bootloader_utility_load_partition_table(bootloader_state_t* bs)
break;
case PART_SUBTYPE_DATA_EFUSE_EM:
partition_usage = "efuse";
#ifdef CONFIG_EFUSE_SECURE_VERSION_EMULATE
#ifdef CONFIG_BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE
esp_efuse_init(partition->pos.offset, partition->pos.size);
#endif
break;
@ -243,7 +243,7 @@ static esp_err_t write_otadata(esp_ota_select_entry_t *otadata, uint32_t offset,
static bool check_anti_rollback(const esp_partition_pos_t *partition)
{
#ifdef CONFIG_APP_ANTI_ROLLBACK
#ifdef CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
esp_app_desc_t app_desc;
esp_err_t err = bootloader_common_get_partition_description(partition, &app_desc);
return err == ESP_OK && esp_efuse_check_secure_version(app_desc.secure_version) == true;
@ -252,7 +252,7 @@ static bool check_anti_rollback(const esp_partition_pos_t *partition)
#endif
}
#ifdef CONFIG_APP_ANTI_ROLLBACK
#ifdef CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
static void update_anti_rollback(const esp_partition_pos_t *partition)
{
esp_app_desc_t app_desc;
@ -306,7 +306,7 @@ int bootloader_utility_get_selected_boot_partition(const bootloader_state_t *bs)
ESP_LOGD(TAG, "otadata[0]: sequence values 0x%08x", otadata[0].ota_seq);
ESP_LOGD(TAG, "otadata[1]: sequence values 0x%08x", otadata[1].ota_seq);
#ifdef CONFIG_APP_ROLLBACK_ENABLE
#ifdef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
bool write_encrypted = esp_flash_encryption_enabled();
for (int i = 0; i < 2; ++i) {
if (otadata[i].ota_state == ESP_OTA_IMG_PENDING_VERIFY) {
@ -317,7 +317,7 @@ int bootloader_utility_get_selected_boot_partition(const bootloader_state_t *bs)
}
#endif
#ifndef CONFIG_APP_ANTI_ROLLBACK
#ifndef CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
if ((bootloader_common_ota_select_invalid(&otadata[0]) &&
bootloader_common_ota_select_invalid(&otadata[1])) ||
bs->app_count == 0) {
@ -341,7 +341,7 @@ int bootloader_utility_get_selected_boot_partition(const bootloader_state_t *bs)
#else
ESP_LOGI(TAG, "Enabled a check secure version of app for anti rollback");
ESP_LOGI(TAG, "Secure version (from eFuse) = %d", esp_efuse_read_secure_version());
// When CONFIG_APP_ANTI_ROLLBACK is enabled factory partition should not be in partition table, only two ota_app are there.
// When CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK is enabled factory partition should not be in partition table, only two ota_app are there.
if ((otadata[0].ota_seq == UINT32_MAX || otadata[0].crc != bootloader_common_ota_select_crc(&otadata[0])) &&
(otadata[1].ota_seq == UINT32_MAX || otadata[1].crc != bootloader_common_ota_select_crc(&otadata[1]))) {
ESP_LOGI(TAG, "otadata[0..1] in initial state");
@ -356,19 +356,19 @@ int bootloader_utility_get_selected_boot_partition(const bootloader_state_t *bs)
uint32_t ota_seq = otadata[active_otadata].ota_seq - 1; // Raw OTA sequence number. May be more than # of OTA slots
boot_index = ota_seq % bs->app_count; // Actual OTA partition selection
ESP_LOGD(TAG, "Mapping seq %d -> OTA slot %d", ota_seq, boot_index);
#ifdef CONFIG_APP_ROLLBACK_ENABLE
#ifdef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
if (otadata[active_otadata].ota_state == ESP_OTA_IMG_NEW) {
ESP_LOGD(TAG, "otadata[%d] is selected as new and marked PENDING_VERIFY state", active_otadata);
otadata[active_otadata].ota_state = ESP_OTA_IMG_PENDING_VERIFY;
write_otadata(&otadata[active_otadata], bs->ota_info.offset + FLASH_SECTOR_SIZE * active_otadata, write_encrypted);
}
#endif // CONFIG_APP_ROLLBACK_ENABLE
#endif // CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
#ifdef CONFIG_APP_ANTI_ROLLBACK
#ifdef CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
if(otadata[active_otadata].ota_state == ESP_OTA_IMG_VALID) {
update_anti_rollback(&bs->ota[boot_index]);
}
#endif // CONFIG_APP_ANTI_ROLLBACK
#endif // CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
} else if (bs->factory.offset != 0) {
ESP_LOGE(TAG, "ota data partition invalid, falling back to factory");
@ -414,7 +414,7 @@ static void set_actual_ota_seq(const bootloader_state_t *bs, int index)
bool write_encrypted = esp_flash_encryption_enabled();
write_otadata(&otadata, bs->ota_info.offset + FLASH_SECTOR_SIZE * 0, write_encrypted);
ESP_LOGI(TAG, "Set actual ota_seq=%d in otadata[0]", otadata.ota_seq);
#ifdef CONFIG_APP_ANTI_ROLLBACK
#ifdef CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
update_anti_rollback(&bs->ota[index]);
#endif
}
@ -521,7 +521,7 @@ static void load_image(const esp_image_metadata_t* image_data)
* then Step 6 enables secure boot.
*/
#if defined(CONFIG_SECURE_BOOT_ENABLED) || defined(CONFIG_FLASH_ENCRYPTION_ENABLED)
#if defined(CONFIG_SECURE_BOOT_ENABLED) || defined(CONFIG_SECURE_FLASH_ENC_ENABLED)
esp_err_t err;
#endif
@ -537,7 +537,7 @@ static void load_image(const esp_image_metadata_t* image_data)
}
#endif
#ifdef CONFIG_FLASH_ENCRYPTION_ENABLED
#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED
/* Steps 3, 4 & 5 (see above for full description):
* 3) Generate flash encryption EFUSE key
* 4) Encrypt flash contents
@ -566,7 +566,7 @@ static void load_image(const esp_image_metadata_t* image_data)
}
#endif
#ifdef CONFIG_FLASH_ENCRYPTION_ENABLED
#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED
if (!flash_encryption_enabled && esp_flash_encryption_enabled()) {
/* Flash encryption was just enabled for the first time,
so issue a system reset to ensure flash encryption

6
components/bootloader_support/src/esp32/flash_encrypt.c
View File

@ -114,19 +114,19 @@ static esp_err_t initialise_flash_encryption(void)
esp_efuse_burn_new_values();
uint32_t new_wdata6 = 0;
#ifndef CONFIG_FLASH_ENCRYPTION_UART_BOOTLOADER_ALLOW_ENCRYPT
#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC
ESP_LOGI(TAG, "Disable UART bootloader encryption...");
new_wdata6 |= EFUSE_DISABLE_DL_ENCRYPT;
#else
ESP_LOGW(TAG, "Not disabling UART bootloader encryption");
#endif
#ifndef CONFIG_FLASH_ENCRYPTION_UART_BOOTLOADER_ALLOW_DECRYPT
#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC
ESP_LOGI(TAG, "Disable UART bootloader decryption...");
new_wdata6 |= EFUSE_DISABLE_DL_DECRYPT;
#else
ESP_LOGW(TAG, "Not disabling UART bootloader decryption - SECURITY COMPROMISED");
#endif
#ifndef CONFIG_FLASH_ENCRYPTION_UART_BOOTLOADER_ALLOW_CACHE
#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE
ESP_LOGI(TAG, "Disable UART bootloader MMU cache...");
new_wdata6 |= EFUSE_DISABLE_DL_CACHE;
#else

2
components/bootloader_support/src/flash_qio_mode.c
View File

@ -211,7 +211,7 @@ static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn,
ESP_LOGD(TAG, "Enabling QIO mode...");
esp_rom_spiflash_read_mode_t mode;
#if CONFIG_FLASHMODE_QOUT
#if CONFIG_ESPTOOLPY_FLASHMODE_QOUT
mode = ESP_ROM_SPIFLASH_QOUT_MODE;
#else
mode = ESP_ROM_SPIFLASH_QIO_MODE;

2
components/bt/CMakeLists.txt
View File

@ -3,7 +3,7 @@ if(CONFIG_BT_ENABLED)
set(COMPONENT_SRCS "bt.c")
set(COMPONENT_ADD_INCLUDEDIRS include)
if(CONFIG_BLUEDROID_ENABLED)
if(CONFIG_BT_BLUEDROID_ENABLED)
list(APPEND COMPONENT_PRIV_INCLUDEDIRS
bluedroid/bta/include

1058
components/bt/Kconfig
View File

File diff suppressed because it is too large Load Diff

2
components/bt/bluedroid/api/esp_bt_main.c
View File

@ -128,7 +128,7 @@ esp_err_t esp_bluedroid_init(void)
return ESP_ERR_INVALID_STATE;
}
#ifdef CONFIG_BLUEDROID_MEM_DEBUG
#ifdef CONFIG_BT_BLUEDROID_MEM_DEBUG
osi_mem_dbg_init();
#endif

8
components/bt/bluedroid/btc/core/btc_task.c
View File

@ -30,7 +30,7 @@
#include "btc/btc_dm.h"
#include "btc/btc_alarm.h"
#include "bta/bta_gatt_api.h"
#if CONFIG_CLASSIC_BT_ENABLED
#if CONFIG_BT_CLASSIC_ENABLED
#include "btc/btc_profile_queue.h"
#if (BTC_GAP_BT_INCLUDED == TRUE)
#include "btc_gap_bt.h"
@ -45,7 +45,7 @@
#if BTC_HF_CLIENT_INCLUDED
#include "btc_hf_client.h"
#endif /* #if BTC_HF_CLIENT_INCLUDED */
#endif /* #if CONFIG_CLASSIC_BT_ENABLED */
#endif /* #if CONFIG_BT_CLASSIC_ENABLED */
static xTaskHandle xBtcTaskHandle = NULL;
@ -71,7 +71,7 @@ static btc_func_t profile_tab[BTC_PID_NUM] = {
#endif ///GATTS_INCLUDED == TRUE
[BTC_PID_DM_SEC] = {NULL, btc_dm_sec_cb_handler },
[BTC_PID_ALARM] = {btc_alarm_handler, NULL },
#if CONFIG_CLASSIC_BT_ENABLED
#if CONFIG_BT_CLASSIC_ENABLED
#if (BTC_GAP_BT_INCLUDED == TRUE)
[BTC_PID_GAP_BT] = {btc_gap_bt_call_handler, btc_gap_bt_cb_handler },
#endif /* (BTC_GAP_BT_INCLUDED == TRUE) */
@ -87,7 +87,7 @@ static btc_func_t profile_tab[BTC_PID_NUM] = {
#if BTC_HF_CLIENT_INCLUDED
[BTC_PID_HF_CLIENT] = {btc_hf_client_call_handler, btc_hf_client_cb_handler},
#endif /* #if BTC_HF_CLIENT_INCLUDED */
#endif /* #if CONFIG_CLASSIC_BT_ENABLED */
#endif /* #if CONFIG_BT_CLASSIC_ENABLED */
};
/*****************************************************************************

4
components/bt/bluedroid/btc/include/btc/btc_task.h
View File

@ -53,7 +53,7 @@ typedef enum {
BTC_PID_BLUFI,
BTC_PID_DM_SEC,
BTC_PID_ALARM,
#if CONFIG_CLASSIC_BT_ENABLED
#if CONFIG_BT_CLASSIC_ENABLED
BTC_PID_GAP_BT,
BTC_PID_PRF_QUE,
BTC_PID_A2DP,
@ -63,7 +63,7 @@ typedef enum {
#if BTC_HF_CLIENT_INCLUDED
BTC_PID_HF_CLIENT,
#endif /* BTC_HF_CLIENT_INCLUDED */
#endif /* CONFIG_CLASSIC_BT_ENABLED */
#endif /* CONFIG_BT_CLASSIC_ENABLED */
BTC_PID_NUM,
} btc_pid_t; //btc profile id

2
components/bt/bluedroid/btc/profile/std/hf_client/btc_hf_client.c
View File

@ -174,7 +174,7 @@ bt_status_t btc_hf_client_init(void)
btc_hf_client_cb.initialized = true;
#if CONFIG_HFP_AUDIO_DATA_PATH_HCI
#if CONFIG_BT_HFP_AUDIO_DATA_PATH_HCI
data_path = ESP_SCO_DATA_PATH_HCI;
#else
data_path = ESP_SCO_DATA_PATH_PCM;

74
components/bt/bluedroid/common/include/common/bt_target.h
View File

@ -44,7 +44,7 @@
** Classic BT features
**
******************************************************************************/
#if CONFIG_CLASSIC_BT_ENABLED
#if CONFIG_BT_CLASSIC_ENABLED
#define CLASSIC_BT_INCLUDED TRUE
#define BTC_SM_INCLUDED TRUE
#define BTC_PRF_QUEUE_INCLUDED TRUE
@ -53,7 +53,7 @@
#define BTA_DM_PM_INCLUDED TRUE
#define SDP_INCLUDED TRUE
#if CONFIG_A2DP_ENABLE
#if CONFIG_BT_A2DP_ENABLE
#define BTA_AR_INCLUDED TRUE
#define BTA_AV_INCLUDED TRUE
#define AVDT_INCLUDED TRUE
@ -66,7 +66,7 @@
#define SBC_DEC_INCLUDED TRUE
#define BTC_AV_SRC_INCLUDED TRUE
#define SBC_ENC_INCLUDED TRUE
#endif /* CONFIG_A2DP_ENABLE */
#endif /* CONFIG_BT_A2DP_ENABLE */
#if CONFIG_BT_SPP_ENABLED
#define RFCOMM_INCLUDED TRUE
@ -74,7 +74,7 @@
#define BTC_SPP_INCLUDED TRUE
#endif /* CONFIG_BT_SPP_ENABLED */
#if CONFIG_HFP_CLIENT_ENABLE
#if CONFIG_BT_HFP_CLIENT_ENABLE
#define BTC_HF_CLIENT_INCLUDED TRUE
#define BTA_HF_INCLUDED TRUE
#ifndef RFCOMM_INCLUDED
@ -92,49 +92,49 @@
#define BT_SSP_INCLUDED TRUE
#endif /* CONFIG_BT_SSP_ENABLED */
#endif /* #if CONFIG_CLASSIC_BT_ENABLED */
#endif /* #if CONFIG_BT_CLASSIC_ENABLED */
#ifndef CLASSIC_BT_INCLUDED
#define CLASSIC_BT_INCLUDED FALSE
#endif /* CLASSIC_BT_INCLUDED */
#ifndef CONFIG_GATTC_CACHE_NVS_FLASH
#define CONFIG_GATTC_CACHE_NVS_FLASH FALSE
#endif /* CONFIG_GATTC_CACHE_NVS_FLASH */
#ifndef CONFIG_BT_GATTC_CACHE_NVS_FLASH
#define CONFIG_BT_GATTC_CACHE_NVS_FLASH FALSE
#endif /* CONFIG_BT_GATTC_CACHE_NVS_FLASH */
/******************************************************************************
**
** BLE features
**
******************************************************************************/
#if (CONFIG_GATTS_ENABLE)
#if (CONFIG_BT_GATTS_ENABLE)
#define GATTS_INCLUDED TRUE
#else
#define GATTS_INCLUDED FALSE
#endif /* CONFIG_GATTS_ENABLE */
#endif /* CONFIG_BT_GATTS_ENABLE */
#if (CONFIG_GATTC_ENABLE)
#if (CONFIG_BT_GATTC_ENABLE)
#define GATTC_INCLUDED TRUE
#else
#define GATTC_INCLUDED FALSE
#endif /* CONFIG_GATTC_ENABLE */
#endif /* CONFIG_BT_GATTC_ENABLE */
#if (CONFIG_GATTC_ENABLE && CONFIG_GATTC_CACHE_NVS_FLASH)
#if (CONFIG_BT_GATTC_ENABLE && CONFIG_BT_GATTC_CACHE_NVS_FLASH)
#define GATTC_CACHE_NVS TRUE
#else
#define GATTC_CACHE_NVS FALSE
#endif /* CONFIG_GATTC_CACHE_NVS_FLASH */
#endif /* CONFIG_BT_GATTC_CACHE_NVS_FLASH */
#if (CONFIG_SMP_ENABLE)
#if (CONFIG_BT_SMP_ENABLE)
#define SMP_INCLUDED TRUE
#define BLE_PRIVACY_SPT TRUE
#else
#define SMP_INCLUDED FALSE
#define BLE_PRIVACY_SPT FALSE
#endif /* CONFIG_SMP_ENABLE */
#endif /* CONFIG_BT_SMP_ENABLE */
#ifdef CONFIG_SMP_SLAVE_CON_PARAMS_UPD_ENABLE
#if(CONFIG_SMP_SLAVE_CON_PARAMS_UPD_ENABLE)
#ifdef CONFIG_BT_SMP_SLAVE_CON_PARAMS_UPD_ENABLE
#if(CONFIG_BT_SMP_SLAVE_CON_PARAMS_UPD_ENABLE)
#define SMP_SLAVE_CON_PARAMS_UPD_ENABLE TRUE
#else
#define SMP_SLAVE_CON_PARAMS_UPD_ENABLE FALSE
@ -143,31 +143,31 @@
#define SMP_SLAVE_CON_PARAMS_UPD_ENABLE FALSE
#endif
#ifndef CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_SUPPORTED
#ifndef CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP
#define BLE_ADV_REPORT_FLOW_CONTROL FALSE
#else
#define BLE_ADV_REPORT_FLOW_CONTROL CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_SUPPORTED
#endif /* CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_SUPPORTED */
#define BLE_ADV_REPORT_FLOW_CONTROL CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP
#endif /* CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP */
#ifndef CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_NUM
#ifndef CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_NUM
#define BLE_ADV_REPORT_FLOW_CONTROL_NUM 100
#else
#define BLE_ADV_REPORT_FLOW_CONTROL_NUM CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_NUM
#endif /* CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_NUM */
#define BLE_ADV_REPORT_FLOW_CONTROL_NUM CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_NUM
#endif /* CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_NUM */
#ifndef CONFIG_BLE_ADV_REPORT_DISCARD_THRSHOLD
#ifndef CONFIG_BTDM_BLE_ADV_REPORT_DISCARD_THRSHOLD
#define BLE_ADV_REPORT_DISCARD_THRSHOLD 20
#else
#define BLE_ADV_REPORT_DISCARD_THRSHOLD CONFIG_BLE_ADV_REPORT_DISCARD_THRSHOLD
#endif /* CONFIG_BLE_ADV_REPORT_DISCARD_THRSHOLD */
#define BLE_ADV_REPORT_DISCARD_THRSHOLD CONFIG_BTDM_BLE_ADV_REPORT_DISCARD_THRSHOLD
#endif /* CONFIG_BTDM_BLE_ADV_REPORT_DISCARD_THRSHOLD */
#if (CONFIG_BT_ACL_CONNECTIONS)
#define MAX_ACL_CONNECTIONS CONFIG_BT_ACL_CONNECTIONS
#define GATT_MAX_PHY_CHANNEL CONFIG_BT_ACL_CONNECTIONS
#endif /* CONFIG_BT_ACL_CONNECTIONS */
#if(CONFIG_BLE_ESTABLISH_LINK_CONNECTION_TIMEOUT)
#define BLE_ESTABLISH_LINK_CONNECTION_TIMEOUT CONFIG_BLE_ESTABLISH_LINK_CONNECTION_TIMEOUT
#if(CONFIG_BT_BLE_ESTAB_LINK_CONN_TOUT)
#define BLE_ESTABLISH_LINK_CONNECTION_TIMEOUT CONFIG_BT_BLE_ESTAB_LINK_CONN_TOUT
#else
#define BLE_ESTABLISH_LINK_CONNECTION_TIMEOUT 30
#endif
@ -349,22 +349,22 @@
#define QUEUE_CONGEST_SIZE 40
#endif
#ifndef CONFIG_BLE_HOST_QUEUE_CONGESTION_CHECK
#ifndef CONFIG_BT_BLE_HOST_QUEUE_CONG_CHECK
#define SCAN_QUEUE_CONGEST_CHECK FALSE
#else
#define SCAN_QUEUE_CONGEST_CHECK CONFIG_BLE_HOST_QUEUE_CONGESTION_CHECK
#define SCAN_QUEUE_CONGEST_CHECK CONFIG_BT_BLE_HOST_QUEUE_CONG_CHECK
#endif
#ifndef CONFIG_GATTS_SEND_SERVICE_CHANGE_MODE
#ifndef CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MODE
#define GATTS_SEND_SERVICE_CHANGE_MODE GATTS_SEND_SERVICE_CHANGE_AUTO
#else
#define GATTS_SEND_SERVICE_CHANGE_MODE CONFIG_GATTS_SEND_SERVICE_CHANGE_MODE
#define GATTS_SEND_SERVICE_CHANGE_MODE CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MODE
#endif
#ifndef CONFIG_BLE_ACTIVE_SCAN_REPORT_ADV_SCAN_RSP_INDIVIDUALLY
#ifndef CONFIG_BT_BLE_ACT_SCAN_REP_ADV_SCAN
#define BTM_BLE_ACTIVE_SCAN_REPORT_ADV_SCAN_RSP_INDIVIDUALLY FALSE
#else
#define BTM_BLE_ACTIVE_SCAN_REPORT_ADV_SCAN_RSP_INDIVIDUALLY CONFIG_BLE_ACTIVE_SCAN_REPORT_ADV_SCAN_RSP_INDIVIDUALLY
#define BTM_BLE_ACTIVE_SCAN_REPORT_ADV_SCAN_RSP_INDIVIDUALLY CONFIG_BT_BLE_ACT_SCAN_REP_ADV_SCAN
#endif
/* This feature is used to eanble interleaved scan*/
@ -582,11 +582,11 @@
/* Includes SCO if TRUE */
#ifndef BTM_SCO_HCI_INCLUDED
#if CONFIG_HFP_AUDIO_DATA_PATH_HCI
#if CONFIG_BT_HFP_AUDIO_DATA_PATH_HCI
#define BTM_SCO_HCI_INCLUDED TRUE /* TRUE includes SCO over HCI code */
#else
#define BTM_SCO_HCI_INCLUDED FALSE
#endif /* CONFIG_HFP_AUDIO_DATA_PATH_HCI */
#endif /* CONFIG_BT_HFP_AUDIO_DATA_PATH_HCI */
#endif
/* Includes WBS if TRUE */

82
components/bt/bluedroid/common/include/common/bt_trace.h
View File

@ -29,7 +29,7 @@
#ifndef BOOTLOADER_BUILD
#define LOG_LOCAL_LEVEL CONFIG_LOG_DEFAULT_LEVEL
#else
#define LOG_LOCAL_LEVEL CONFIG_LOG_BOOTLOADER_LEVEL
#define LOG_LOCAL_LEVEL CONFIG_BOOTLOADER_LOG_LEVEL
#endif
#endif
@ -217,26 +217,26 @@ inline void trc_dump_buffer(const char *prefix, uint8_t *data, uint16_t len)
// btla-specific ++
/* Core Stack default trace levels */
#ifdef CONFIG_HCI_INITIAL_TRACE_LEVEL
#define HCI_INITIAL_TRACE_LEVEL CONFIG_HCI_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_HCI_TRACE_LEVEL
#define HCI_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_HCI_TRACE_LEVEL
#else
#define HCI_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
#ifdef CONFIG_BTM_INITIAL_TRACE_LEVEL
#define BTM_INITIAL_TRACE_LEVEL CONFIG_BTM_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_BTM_TRACE_LEVEL
#define BTM_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_BTM_TRACE_LEVEL
#else
#define BTM_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
#ifdef CONFIG_L2CAP_INITIAL_TRACE_LEVEL
#define L2CAP_INITIAL_TRACE_LEVEL CONFIG_L2CAP_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_L2CAP_TRACE_LEVEL
#define L2CAP_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_L2CAP_TRACE_LEVEL
#else
#define L2CAP_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
#ifdef CONFIG_RFCOMM_INITIAL_TRACE_LEVEL
#define RFCOMM_INITIAL_TRACE_LEVEL CONFIG_RFCOMM_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_RFCOMM_TRACE_LEVEL
#define RFCOMM_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_RFCOMM_TRACE_LEVEL
#else
#define RFCOMM_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
@ -247,98 +247,98 @@ inline void trc_dump_buffer(const char *prefix, uint8_t *data, uint16_t len)
#define SDP_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
#ifdef CONFIG_GAP_INITIAL_TRACE_LEVEL
#define GAP_INITIAL_TRACE_LEVEL CONFIG_GAP_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_GAP_TRACE_LEVEL
#define GAP_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_GAP_TRACE_LEVEL
#else
#define GAP_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
#ifdef CONFIG_BNEP_INITIAL_TRACE_LEVEL
#define BNEP_INITIAL_TRACE_LEVEL CONFIG_BNEP_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_BNEP_TRACE_LEVEL
#define BNEP_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_BNEP_TRACE_LEVEL
#else
#define BNEP_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
#ifdef CONFIG_PAN_INITIAL_TRACE_LEVEL
#define PAN_INITIAL_TRACE_LEVEL CONFIG_PAN_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_PAN_TRACE_LEVEL
#define PAN_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_PAN_TRACE_LEVEL
#else
#define PAN_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
#ifdef CONFIG_A2D_INITIAL_TRACE_LEVEL
#define A2D_INITIAL_TRACE_LEVEL CONFIG_A2D_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_A2D_TRACE_LEVEL
#define A2D_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_A2D_TRACE_LEVEL
#else
#define A2D_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
#ifdef CONFIG_AVDT_INITIAL_TRACE_LEVEL
#define AVDT_INITIAL_TRACE_LEVEL CONFIG_AVDT_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_AVDT_TRACE_LEVEL
#define AVDT_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_AVDT_TRACE_LEVEL
#else
#define AVDT_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
#ifdef CONFIG_AVCT_INITIAL_TRACE_LEVEL
#define AVCT_INITIAL_TRACE_LEVEL CONFIG_AVCT_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_AVCT_TRACE_LEVEL
#define AVCT_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_AVCT_TRACE_LEVEL
#else
#define AVCT_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
#ifdef CONFIG_AVRC_INITIAL_TRACE_LEVEL
#define AVRC_INITIAL_TRACE_LEVEL CONFIG_AVRC_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_AVRC_TRACE_LEVEL
#define AVRC_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_AVRC_TRACE_LEVEL
#else
#define AVRC_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
#ifdef CONFIG_MCA_INITIAL_TRACE_LEVEL
#define MCA_INITIAL_TRACE_LEVEL CONFIG_MCA_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_MCA_TRACE_LEVEL
#define MCA_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_MCA_TRACE_LEVEL
#else
#define MCA_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
#ifdef CONFIG_HID_INITIAL_TRACE_LEVEL
#define HID_INITIAL_TRACE_LEVEL CONFIG_HID_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_HID_TRACE_LEVEL
#define HID_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_HID_TRACE_LEVEL
#else
#define HID_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
#ifdef CONFIG_APPL_INITIAL_TRACE_LEVEL
#define APPL_INITIAL_TRACE_LEVEL CONFIG_APPL_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_APPL_TRACE_LEVEL
#define APPL_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_APPL_TRACE_LEVEL
#else
#define APPL_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
#ifdef CONFIG_GATT_INITIAL_TRACE_LEVEL
#define GATT_INITIAL_TRACE_LEVEL CONFIG_GATT_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_GATT_TRACE_LEVEL
#define GATT_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_GATT_TRACE_LEVEL
#else
#define GATT_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
#ifdef CONFIG_SMP_INITIAL_TRACE_LEVEL
#define SMP_INITIAL_TRACE_LEVEL CONFIG_SMP_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_SMP_TRACE_LEVEL
#define SMP_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_SMP_TRACE_LEVEL
#else
#define SMP_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
#ifdef CONFIG_BTIF_INITIAL_TRACE_LEVEL
#define BTIF_INITIAL_TRACE_LEVEL CONFIG_BTIF_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_BTIF_TRACE_LEVEL
#define BTIF_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_BTIF_TRACE_LEVEL
#else
#define BTIF_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
#ifdef CONFIG_BTC_INITIAL_TRACE_LEVEL
#define BTC_INITIAL_TRACE_LEVEL CONFIG_BTC_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_BTC_TRACE_LEVEL
#define BTC_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_BTC_TRACE_LEVEL
#else
#define BTC_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
#ifdef CONFIG_OSI_INITIAL_TRACE_LEVEL
#define OSI_INITIAL_TRACE_LEVEL CONFIG_OSI_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_OSI_TRACE_LEVEL
#define OSI_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_OSI_TRACE_LEVEL
#else
#define OSI_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif
#ifdef CONFIG_BLUFI_INITIAL_TRACE_LEVEL
#define BLUFI_INITIAL_TRACE_LEVEL CONFIG_BLUFI_INITIAL_TRACE_LEVEL
#ifdef CONFIG_BT_LOG_BLUFI_TRACE_LEVEL
#define BLUFI_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_BLUFI_TRACE_LEVEL
#else
#define BLUFI_INITIAL_TRACE_LEVEL BT_TRACE_LEVEL_WARNING
#endif

12
components/bt/bluedroid/osi/allocator.c
View File

@ -24,7 +24,7 @@
extern void *pvPortZalloc(size_t size);
extern void vPortFree(void *pv);
#ifdef CONFIG_BLUEDROID_MEM_DEBUG
#ifdef CONFIG_BT_BLUEDROID_MEM_DEBUG
#define OSI_MEM_DBG_INFO_MAX 1024*3
typedef struct {
@ -130,7 +130,7 @@ char *osi_strdup(const char *str)
void *osi_malloc_func(size_t size)
{
#ifdef CONFIG_BLUEDROID_MEM_DEBUG
#ifdef CONFIG_BT_BLUEDROID_MEM_DEBUG
void *p;
#if CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST
p = heap_caps_malloc_prefer(size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL);
@ -145,12 +145,12 @@ void *osi_malloc_func(size_t size)
#else
return malloc(size);
#endif /* #if CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST */
#endif /* #ifdef CONFIG_BLUEDROID_MEM_DEBUG */
#endif /* #ifdef CONFIG_BT_BLUEDROID_MEM_DEBUG */
}
void *osi_calloc_func(size_t size)
{
#ifdef CONFIG_BLUEDROID_MEM_DEBUG
#ifdef CONFIG_BT_BLUEDROID_MEM_DEBUG
void *p;
#if CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST
p = heap_caps_calloc_prefer(1, size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL);
@ -165,12 +165,12 @@ void *osi_calloc_func(size_t size)
#else
return calloc(1, size);
#endif /* #if CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST */
#endif /* #ifdef CONFIG_BLUEDROID_MEM_DEBUG */
#endif /* #ifdef CONFIG_BT_BLUEDROID_MEM_DEBUG */
}
void osi_free_func(void *ptr)
{
#ifdef CONFIG_BLUEDROID_MEM_DEBUG
#ifdef CONFIG_BT_BLUEDROID_MEM_DEBUG
osi_mem_dbg_clean(ptr, __func__, __LINE__);
#endif
free(ptr);

4
components/bt/bluedroid/osi/include/osi/allocator.h
View File

@ -30,7 +30,7 @@ void *osi_malloc_func(size_t size);
void *osi_calloc_func(size_t size);
void osi_free_func(void *ptr);
#ifdef CONFIG_BLUEDROID_MEM_DEBUG
#ifdef CONFIG_BT_BLUEDROID_MEM_DEBUG
void osi_mem_dbg_init(void);
void osi_mem_dbg_record(void *p, int size, const char *func, int line);
@ -127,7 +127,7 @@ do { \
#endif /* #if CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST */
#define osi_free(p) free((p))
#endif /* CONFIG_BLUEDROID_MEM_DEBUG */
#endif /* CONFIG_BT_BLUEDROID_MEM_DEBUG */
#define FREE_AND_RESET(a) \
do { \

10
components/bt/bluedroid/osi/include/osi/thread.h
View File

@ -57,7 +57,7 @@ typedef enum {
SIG_BTU_NUM,
} SIG_BTU_t;
#define TASK_PINNED_TO_CORE (CONFIG_BLUEDROID_PINNED_TO_CORE < portNUM_PROCESSORS ? CONFIG_BLUEDROID_PINNED_TO_CORE : tskNO_AFFINITY)
#define TASK_PINNED_TO_CORE (CONFIG_BT_BLUEDROID_PINNED_TO_CORE < portNUM_PROCESSORS ? CONFIG_BT_BLUEDROID_PINNED_TO_CORE : tskNO_AFFINITY)
#define HCI_HOST_TASK_PINNED_TO_CORE (TASK_PINNED_TO_CORE)
#define HCI_HOST_TASK_STACK_SIZE (2048 + BT_TASK_EXTRA_STACK_SIZE)
@ -72,19 +72,19 @@ typedef enum {
#define HCI_H4_QUEUE_LEN 1
#define BTU_TASK_PINNED_TO_CORE (TASK_PINNED_TO_CORE)
#define BTU_TASK_STACK_SIZE (CONFIG_BTU_TASK_STACK_SIZE + BT_TASK_EXTRA_STACK_SIZE)
#define BTU_TASK_STACK_SIZE (CONFIG_BT_BTU_TASK_STACK_SIZE + BT_TASK_EXTRA_STACK_SIZE)
#define BTU_TASK_PRIO (configMAX_PRIORITIES - 5)
#define BTU_TASK_NAME "btuT"
#define BTU_QUEUE_LEN 50
#define BTC_TASK_PINNED_TO_CORE (TASK_PINNED_TO_CORE)
#define BTC_TASK_STACK_SIZE (CONFIG_BTC_TASK_STACK_SIZE + BT_TASK_EXTRA_STACK_SIZE) //by menuconfig
#define BTC_TASK_STACK_SIZE (CONFIG_BT_BTC_TASK_STACK_SIZE + BT_TASK_EXTRA_STACK_SIZE) //by menuconfig
#define BTC_TASK_NAME "btcT"
#define BTC_TASK_PRIO (configMAX_PRIORITIES - 6)
#define BTC_TASK_QUEUE_LEN 60
#define BTC_A2DP_SINK_TASK_PINNED_TO_CORE (TASK_PINNED_TO_CORE)
#define BTC_A2DP_SINK_TASK_STACK_SIZE (CONFIG_A2DP_SINK_TASK_STACK_SIZE + BT_TASK_EXTRA_STACK_SIZE) // by menuconfig
#define BTC_A2DP_SINK_TASK_STACK_SIZE (CONFIG_BT_A2DP_SINK_TASK_STACK_SIZE + BT_TASK_EXTRA_STACK_SIZE) // by menuconfig
#define BTC_A2DP_SINK_TASK_NAME "BtA2dSinkT"
#define BTC_A2DP_SINK_TASK_PRIO (configMAX_PRIORITIES - 3)
#define BTC_A2DP_SINK_DATA_QUEUE_LEN (3)
@ -92,7 +92,7 @@ typedef enum {
#define BTC_A2DP_SINK_TASK_QUEUE_SET_LEN (BTC_A2DP_SINK_DATA_QUEUE_LEN + BTC_A2DP_SINK_CTRL_QUEUE_LEN)
#define BTC_A2DP_SOURCE_TASK_PINNED_TO_CORE (TASK_PINNED_TO_CORE)
#define BTC_A2DP_SOURCE_TASK_STACK_SIZE (CONFIG_A2DP_SOURCE_TASK_STACK_SIZE + BT_TASK_EXTRA_STACK_SIZE) // by menuconfig
#define BTC_A2DP_SOURCE_TASK_STACK_SIZE (CONFIG_BT_A2DP_SOURCE_TASK_STACK_SIZE + BT_TASK_EXTRA_STACK_SIZE) // by menuconfig
#define BTC_A2DP_SOURCE_TASK_NAME "BtA2dSourceT"
#define BTC_A2DP_SOURCE_TASK_PRIO (configMAX_PRIORITIES - 3)
#define BTC_A2DP_SOURCE_DATA_QUEUE_LEN (3)

2
components/bt/bluedroid/stack/btm/include/btm_int.h
View File

@ -871,7 +871,7 @@ typedef struct {
#endif ///SMP_INCLUDED == TRUE
#if SMP_INCLUDED == TRUE || CLASSIC_BT_INCLUDED == TRUE
tBTM_SEC_SERV_REC sec_serv_rec[BTM_SEC_MAX_SERVICE_RECORDS];
#endif // SMP_INCLUDED == TRUE || CLASSIC_BT_ENABLED == TRUE
#endif // SMP_INCLUDED == TRUE || BT_CLASSIC_ENABLED == TRUE
tBTM_SEC_DEV_REC sec_dev_rec[BTM_SEC_MAX_DEVICE_RECORDS];
tBTM_SEC_SERV_REC *p_out_serv;
tBTM_MKEY_CALLBACK *mkey_cback;

10
components/bt/bt.c
View File

@ -900,15 +900,15 @@ static uint32_t btdm_config_mask_load(void)
{
uint32_t mask = 0x0;
#if CONFIG_BTDM_CONTROLLER_HCI_MODE_UART_H4
#if CONFIG_BTDM_CTRL_HCI_MODE_UART_H4
mask |= BTDM_CFG_HCI_UART;
#endif
#if CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE == 1
#if CONFIG_BTDM_CTRL_PINNED_TO_CORE == 1
mask |= BTDM_CFG_CONTROLLER_RUN_APP_CPU;
#endif
#if CONFIG_BTDM_CONTROLLER_FULL_SCAN_SUPPORTED
#if CONFIG_BTDM_CTRL_FULL_SCAN_SUPPORTED
mask |= BTDM_CFG_BLE_FULL_SCAN_SUPPORTED;
#endif /* CONFIG_BTDM_CONTROLLER_FULL_SCAN_SUPPORTED */
#endif /* CONFIG_BTDM_CTRL_FULL_SCAN_SUPPORTED */
mask |= BTDM_CFG_SCAN_DUPLICATE_OPTIONS;
mask |= BTDM_CFG_SEND_ADV_RESERVED_SIZE;
@ -1073,7 +1073,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
}
//overwrite some parameters
cfg->bt_max_sync_conn = CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF;
cfg->bt_max_sync_conn = CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF;
cfg->magic = ESP_BT_CONTROLLER_CONFIG_MAGIC_VAL;
if (((cfg->mode & ESP_BT_MODE_BLE) && (cfg->ble_max_conn <= 0 || cfg->ble_max_conn > BTDM_CONTROLLER_BLE_MAX_CONN_LIMIT))

2
components/bt/component.mk
View File

@ -25,7 +25,7 @@ endif
endif
ifdef CONFIG_BLUEDROID_ENABLED
ifdef CONFIG_BT_BLUEDROID_ENABLED
COMPONENT_PRIV_INCLUDEDIRS += bluedroid/bta/include \
bluedroid/bta/ar/include \

30
components/bt/include/esp_bt.h
View File

@ -56,30 +56,30 @@ the adv packet will be discarded until the memory is restored. */
#define BT_HCI_UART_BAUDRATE_DEFAULT 921600
#endif /* BT_HCI_UART_BAUDRATE_DEFAULT */
#ifdef CONFIG_SCAN_DUPLICATE_TYPE
#define SCAN_DUPLICATE_TYPE_VALUE CONFIG_SCAN_DUPLICATE_TYPE
#ifdef CONFIG_BTDM_SCAN_DUPL_TYPE
#define SCAN_DUPLICATE_TYPE_VALUE CONFIG_BTDM_SCAN_DUPL_TYPE
#else
#define SCAN_DUPLICATE_TYPE_VALUE 0
#endif
/* normal adv cache size */
#ifdef CONFIG_DUPLICATE_SCAN_CACHE_SIZE
#define NORMAL_SCAN_DUPLICATE_CACHE_SIZE CONFIG_DUPLICATE_SCAN_CACHE_SIZE
#ifdef CONFIG_BTDM_SCAN_DUPL_CACHE_SIZE
#define NORMAL_SCAN_DUPLICATE_CACHE_SIZE CONFIG_BTDM_SCAN_DUPL_CACHE_SIZE
#else
#define NORMAL_SCAN_DUPLICATE_CACHE_SIZE 20
#endif
#ifndef CONFIG_BLE_MESH_SCAN_DUPLICATE_EN
#define CONFIG_BLE_MESH_SCAN_DUPLICATE_EN FALSE
#ifndef CONFIG_BTDM_BLE_MESH_SCAN_DUPL_EN
#define CONFIG_BTDM_BLE_MESH_SCAN_DUPL_EN FALSE
#endif
#define SCAN_DUPLICATE_MODE_NORMAL_ADV_ONLY 0
#define SCAN_DUPLICATE_MODE_NORMAL_ADV_MESH_ADV 1
#if CONFIG_BLE_MESH_SCAN_DUPLICATE_EN
#if CONFIG_BTDM_BLE_MESH_SCAN_DUPL_EN
#define SCAN_DUPLICATE_MODE SCAN_DUPLICATE_MODE_NORMAL_ADV_MESH_ADV
#ifdef CONFIG_MESH_DUPLICATE_SCAN_CACHE_SIZE
#define MESH_DUPLICATE_SCAN_CACHE_SIZE CONFIG_MESH_DUPLICATE_SCAN_CACHE_SIZE
#ifdef CONFIG_BTDM_MESH_DUPL_SCAN_CACHE_SIZE
#define MESH_DUPLICATE_SCAN_CACHE_SIZE CONFIG_BTDM_MESH_DUPL_SCAN_CACHE_SIZE
#else
#define MESH_DUPLICATE_SCAN_CACHE_SIZE 50
#endif
@ -88,9 +88,9 @@ the adv packet will be discarded until the memory is restored. */
#define MESH_DUPLICATE_SCAN_CACHE_SIZE 0
#endif
#if defined(CONFIG_BTDM_CONTROLLER_MODE_BLE_ONLY)
#if defined(CONFIG_BTDM_CTRL_MODE_BLE_ONLY)
#define BTDM_CONTROLLER_MODE_EFF ESP_BT_MODE_BLE
#elif defined(CONFIG_BTDM_CONTROLLER_MODE_BR_EDR_ONLY)
#elif defined(CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY)
#define BTDM_CONTROLLER_MODE_EFF ESP_BT_MODE_CLASSIC_BT
#else
#define BTDM_CONTROLLER_MODE_EFF ESP_BT_MODE_BTDM
@ -112,9 +112,9 @@ the adv packet will be discarded until the memory is restored. */
.send_adv_reserved_size = SCAN_SEND_ADV_RESERVED_SIZE, \
.controller_debug_flag = CONTROLLER_ADV_LOST_DEBUG_BIT, \
.mode = BTDM_CONTROLLER_MODE_EFF, \
.ble_max_conn = CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF, \
.bt_max_acl_conn = CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF, \
.bt_max_sync_conn = CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF, \
.ble_max_conn = CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF, \
.bt_max_acl_conn = CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF, \
.bt_max_sync_conn = CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF, \
.magic = ESP_BT_CONTROLLER_CONFIG_MAGIC_VAL, \
};
@ -408,7 +408,7 @@ esp_err_t esp_bt_mem_release(esp_bt_mode_t mode);
* There are currently two options for bluetooth modem sleep, one is ORIG mode, and another is EVED Mode. EVED Mode is intended for BLE only.
*
* For ORIG mode:
* Bluetooth modem sleep is enabled in controller start up by default if CONFIG_BTDM_CONTROLLER_MODEM_SLEEP is set and "ORIG mode" is selected. In ORIG modem sleep mode, bluetooth controller will switch off some components and pause to work every now and then, if there is no event to process; and wakeup according to the scheduled interval and resume the work. It can also wakeup earlier upon external request using function "esp_bt_controller_wakeup_request".
* Bluetooth modem sleep is enabled in controller start up by default if CONFIG_BTDM_MODEM_SLEEP is set and "ORIG mode" is selected. In ORIG modem sleep mode, bluetooth controller will switch off some components and pause to work every now and then, if there is no event to process; and wakeup according to the scheduled interval and resume the work. It can also wakeup earlier upon external request using function "esp_bt_controller_wakeup_request".
*
* @return
* - ESP_OK : success

227
components/bt/sdkconfig.rename Normal file
View File

@ -0,0 +1,227 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_BTDM_CONTROLLER_MODE CONFIG_BTDM_CTRL_MODE
CONFIG_BTDM_CONTROLLER_MODE_BLE_ONLY CONFIG_BTDM_CTRL_MODE_BLE_ONLY
CONFIG_BTDM_CONTROLLER_MODE_BR_EDR_ONLY CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY
CONFIG_BTDM_CONTROLLER_MODE_BTDM CONFIG_BTDM_CTRL_MODE_BTDM
CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN CONFIG_BTDM_CTRL_BLE_MAX_CONN
CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN
CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN
CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF
CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF
CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF
CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE_CHOICE CONFIG_BTDM_CTRL_PINNED_TO_CORE_CHOICE
CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE CONFIG_BTDM_CTRL_PINNED_TO_CORE
CONFIG_BTDM_CONTROLLER_HCI_MODE_CHOICE CONFIG_BTDM_CTRL_HCI_MODE_CHOICE
CONFIG_BTDM_CONTROLLER_HCI_MODE_VHCI CONFIG_BTDM_CTRL_HCI_MODE_VHCI
CONFIG_BTDM_CONTROLLER_HCI_MODE_UART_H4 CONFIG_BTDM_CTRL_HCI_MODE_UART_H4
CONFIG_BTDM_CONTROLLER_MODEM_SLEEP CONFIG_BTDM_MODEM_SLEEP
CONFIG_BLE_SCAN_DUPLICATE CONFIG_BTDM_BLE_SCAN_DUPL
CONFIG_SCAN_DUPLICATE_TYPE CONFIG_BTDM_SCAN_DUPL_TYPE
CONFIG_SCAN_DUPLICATE_BY_DEVICE_ADDR CONFIG_BTDM_SCAN_DUPL_TYPE_DEVICE
CONFIG_SCAN_DUPLICATE_BY_ADV_DATA CONFIG_BTDM_SCAN_DUPL_TYPE_DATA
CONFIG_SCAN_DUPLICATE_BY_ADV_DATA_AND_DEVICE_ADDR CONFIG_BTDM_SCAN_DUPL_TYPE_DATA_DEVICE
CONFIG_DUPLICATE_SCAN_CACHE_SIZE CONFIG_BTDM_SCAN_DUPL_CACHE_SIZE
CONFIG_BLE_MESH_SCAN_DUPLICATE_EN CONFIG_BTDM_BLE_MESH_SCAN_DUPL_EN
CONFIG_MESH_DUPLICATE_SCAN_CACHE_SIZE CONFIG_BTDM_MESH_DUPL_SCAN_CACHE_SIZE
CONFIG_BTDM_CONTROLLER_FULL_SCAN_SUPPORTED CONFIG_BTDM_CTRL_FULL_SCAN_SUPPORTED
CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_SUPPORTED CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP
CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_NUM CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_NUM
CONFIG_BLE_ADV_REPORT_DISCARD_THRSHOLD CONFIG_BTDM_BLE_ADV_REPORT_DISCARD_THRSHOLD
CONFIG_BLUEDROID_ENABLED CONFIG_BT_BLUEDROID_ENABLED
CONFIG_BLUEDROID_PINNED_TO_CORE_CHOICE CONFIG_BT_BLUEDROID_PINNED_TO_CORE_CHOICE
CONFIG_BLUEDROID_PINNED_TO_CORE CONFIG_BT_BLUEDROID_PINNED_TO_CORE
CONFIG_BLUEDROID_PINNED_TO_CORE_0 CONFIG_BT_BLUEDROID_PINNED_TO_CORE_0
CONFIG_BLUEDROID_PINNED_TO_CORE_1 CONFIG_BT_BLUEDROID_PINNED_TO_CORE_1
CONFIG_BTC_TASK_STACK_SIZE CONFIG_BT_BTC_TASK_STACK_SIZE
CONFIG_BTU_TASK_STACK_SIZE CONFIG_BT_BTU_TASK_STACK_SIZE
CONFIG_BLUEDROID_MEM_DEBUG CONFIG_BT_BLUEDROID_MEM_DEBUG
CONFIG_CLASSIC_BT_ENABLED CONFIG_BT_CLASSIC_ENABLED
CONFIG_A2DP_ENABLE CONFIG_BT_A2DP_ENABLE
CONFIG_A2DP_SINK_TASK_STACK_SIZE CONFIG_BT_A2DP_SINK_TASK_STACK_SIZE
CONFIG_A2DP_SOURCE_TASK_STACK_SIZE CONFIG_BT_A2DP_SOURCE_TASK_STACK_SIZE
CONFIG_HFP_ENABLE CONFIG_BT_HFP_ENABLE
CONFIG_HFP_ROLE CONFIG_BT_HFP_ROLE
CONFIG_HFP_CLIENT_ENABLE CONFIG_BT_HFP_CLIENT_ENABLE
CONFIG_HFP_AUDIO_DATA_PATH CONFIG_BT_HFP_AUDIO_DATA_PATH
CONFIG_HFP_AUDIO_DATA_PATH_PCM CONFIG_BT_HFP_AUDIO_DATA_PATH_PCM
CONFIG_HFP_AUDIO_DATA_PATH_HCI CONFIG_BT_HFP_AUDIO_DATA_PATH_HCI
CONFIG_GATTS_ENABLE CONFIG_BT_GATTS_ENABLE
CONFIG_GATTS_SEND_SERVICE_CHANGE_MODE CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MODE
CONFIG_GATTS_SEND_SERVICE_CHANGE_MANUAL CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL
CONFIG_GATTS_SEND_SERVICE_CHANGE_AUTO CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_AUTO
CONFIG_GATTC_ENABLE CONFIG_BT_GATTC_ENABLE
CONFIG_GATTC_CACHE_NVS_FLASH CONFIG_BT_GATTC_CACHE_NVS_FLASH
CONFIG_BLE_SMP_ENABLE CONFIG_BT_BLE_SMP_ENABLE
CONFIG_SMP_SLAVE_CON_PARAMS_UPD_ENABLE CONFIG_BT_SMP_SLAVE_CON_PARAMS_UPD_ENABLE
CONFIG_HCI_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_HCI_TRACE_LEVEL
CONFIG_HCI_TRACE_LEVEL_NONE CONFIG_BT_LOG_HCI_TRACE_LEVEL_NONE
CONFIG_HCI_TRACE_LEVEL_ERROR CONFIG_BT_LOG_HCI_TRACE_LEVEL_ERROR
CONFIG_HCI_TRACE_LEVEL_WARNING CONFIG_BT_LOG_HCI_TRACE_LEVEL_WARNING
CONFIG_HCI_TRACE_LEVEL_API CONFIG_BT_LOG_HCI_TRACE_LEVEL_API
CONFIG_HCI_TRACE_LEVEL_EVENT CONFIG_BT_LOG_HCI_TRACE_LEVEL_EVENT
CONFIG_HCI_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_HCI_TRACE_LEVEL_DEBUG
CONFIG_HCI_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_HCI_TRACE_LEVEL_VERBOSE
CONFIG_BTM_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_BTM_TRACE_LEVEL
CONFIG_BTM_TRACE_LEVEL_NONE CONFIG_BT_LOG_BTM_TRACE_LEVEL_NONE
CONFIG_BTM_TRACE_LEVEL_ERROR CONFIG_BT_LOG_BTM_TRACE_LEVEL_ERROR
CONFIG_BTM_TRACE_LEVEL_WARNING CONFIG_BT_LOG_BTM_TRACE_LEVEL_WARNING
CONFIG_BTM_TRACE_LEVEL_API CONFIG_BT_LOG_BTM_TRACE_LEVEL_API
CONFIG_BTM_TRACE_LEVEL_EVENT CONFIG_BT_LOG_BTM_TRACE_LEVEL_EVENT
CONFIG_BTM_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_BTM_TRACE_LEVEL_DEBUG
CONFIG_BTM_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_BTM_TRACE_LEVEL_VERBOSE
CONFIG_L2CAP_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_L2CAP_TRACE_LEVEL
CONFIG_L2CAP_TRACE_LEVEL_NONE CONFIG_BT_LOG_L2CAP_TRACE_LEVEL_NONE
CONFIG_L2CAP_TRACE_LEVEL_ERROR CONFIG_BT_LOG_L2CAP_TRACE_LEVEL_ERROR
CONFIG_L2CAP_TRACE_LEVEL_WARNING CONFIG_BT_LOG_L2CAP_TRACE_LEVEL_WARNING
CONFIG_L2CAP_TRACE_LEVEL_API CONFIG_BT_LOG_L2CAP_TRACE_LEVEL_API
CONFIG_L2CAP_TRACE_LEVEL_EVENT CONFIG_BT_LOG_L2CAP_TRACE_LEVEL_EVENT
CONFIG_L2CAP_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_L2CAP_TRACE_LEVEL_DEBUG
CONFIG_L2CAP_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_L2CAP_TRACE_LEVEL_VERBOSE
CONFIG_RFCOMM_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_RFCOMM_TRACE_LEVEL
CONFIG_RFCOMM_TRACE_LEVEL_NONE CONFIG_BT_LOG_RFCOMM_TRACE_LEVEL_NONE
CONFIG_RFCOMM_TRACE_LEVEL_ERROR CONFIG_BT_LOG_RFCOMM_TRACE_LEVEL_ERROR
CONFIG_RFCOMM_TRACE_LEVEL_WARNING CONFIG_BT_LOG_RFCOMM_TRACE_LEVEL_WARNING
CONFIG_RFCOMM_TRACE_LEVEL_API CONFIG_BT_LOG_RFCOMM_TRACE_LEVEL_API
CONFIG_RFCOMM_TRACE_LEVEL_EVENT CONFIG_BT_LOG_RFCOMM_TRACE_LEVEL_EVENT
CONFIG_RFCOMM_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_RFCOMM_TRACE_LEVEL_DEBUG
CONFIG_RFCOMM_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_RFCOMM_TRACE_LEVEL_VERBOSE
CONFIG_BTH_LOG_SDP_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_SDP_TRACE_LEVEL
CONFIG_SDP_TRACE_LEVEL_NONE CONFIG_BT_LOG_SDP_TRACE_LEVEL_NONE
CONFIG_SDP_TRACE_LEVEL_ERROR CONFIG_BT_LOG_SDP_TRACE_LEVEL_ERROR
CONFIG_SDP_TRACE_LEVEL_WARNING CONFIG_BT_LOG_SDP_TRACE_LEVEL_WARNING
CONFIG_SDP_TRACE_LEVEL_API CONFIG_BT_LOG_SDP_TRACE_LEVEL_API
CONFIG_SDP_TRACE_LEVEL_EVENT CONFIG_BT_LOG_SDP_TRACE_LEVEL_EVENT
CONFIG_SDP_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_SDP_TRACE_LEVEL_DEBUG
CONFIG_SDP_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_SDP_TRACE_LEVEL_VERBOSE
CONFIG_GAP_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_GAP_TRACE_LEVEL
CONFIG_GAP_TRACE_LEVEL_NONE CONFIG_BT_LOG_GAP_TRACE_LEVEL_NONE
CONFIG_GAP_TRACE_LEVEL_ERROR CONFIG_BT_LOG_GAP_TRACE_LEVEL_ERROR
CONFIG_GAP_TRACE_LEVEL_WARNING CONFIG_BT_LOG_GAP_TRACE_LEVEL_WARNING
CONFIG_GAP_TRACE_LEVEL_API CONFIG_BT_LOG_GAP_TRACE_LEVEL_API
CONFIG_GAP_TRACE_LEVEL_EVENT CONFIG_BT_LOG_GAP_TRACE_LEVEL_EVENT
CONFIG_GAP_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_GAP_TRACE_LEVEL_DEBUG
CONFIG_GAP_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_GAP_TRACE_LEVEL_VERBOSE
CONFIG_BNEP_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_BNEP_TRACE_LEVEL
CONFIG_PAN_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_PAN_TRACE_LEVEL
CONFIG_PAN_TRACE_LEVEL_NONE CONFIG_BT_LOG_PAN_TRACE_LEVEL_NONE
CONFIG_PAN_TRACE_LEVEL_ERROR CONFIG_BT_LOG_PAN_TRACE_LEVEL_ERROR
CONFIG_PAN_TRACE_LEVEL_WARNING CONFIG_BT_LOG_PAN_TRACE_LEVEL_WARNING
CONFIG_PAN_TRACE_LEVEL_API CONFIG_BT_LOG_PAN_TRACE_LEVEL_API
CONFIG_PAN_TRACE_LEVEL_EVENT CONFIG_BT_LOG_PAN_TRACE_LEVEL_EVENT
CONFIG_PAN_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_PAN_TRACE_LEVEL_DEBUG
CONFIG_PAN_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_PAN_TRACE_LEVEL_VERBOSE
CONFIG_A2D_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_A2D_TRACE_LEVEL
CONFIG_A2D_TRACE_LEVEL_NONE CONFIG_BT_LOG_A2D_TRACE_LEVEL_NONE
CONFIG_A2D_TRACE_LEVEL_ERROR CONFIG_BT_LOG_A2D_TRACE_LEVEL_ERROR
CONFIG_A2D_TRACE_LEVEL_WARNING CONFIG_BT_LOG_A2D_TRACE_LEVEL_WARNING
CONFIG_A2D_TRACE_LEVEL_API CONFIG_BT_LOG_A2D_TRACE_LEVEL_API
CONFIG_A2D_TRACE_LEVEL_EVENT CONFIG_BT_LOG_A2D_TRACE_LEVEL_EVENT
CONFIG_A2D_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_A2D_TRACE_LEVEL_DEBUG
CONFIG_A2D_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_A2D_TRACE_LEVEL_VERBOSE
CONFIG_AVDT_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_AVDT_TRACE_LEVEL
CONFIG_AVDT_TRACE_LEVEL_NONE CONFIG_BT_LOG_AVDT_TRACE_LEVEL_NONE
CONFIG_AVDT_TRACE_LEVEL_ERROR CONFIG_BT_LOG_AVDT_TRACE_LEVEL_ERROR
CONFIG_AVDT_TRACE_LEVEL_WARNING CONFIG_BT_LOG_AVDT_TRACE_LEVEL_WARNING
CONFIG_AVDT_TRACE_LEVEL_API CONFIG_BT_LOG_AVDT_TRACE_LEVEL_API
CONFIG_AVDT_TRACE_LEVEL_EVENT CONFIG_BT_LOG_AVDT_TRACE_LEVEL_EVENT
CONFIG_AVDT_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_AVDT_TRACE_LEVEL_DEBUG
CONFIG_AVDT_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_AVDT_TRACE_LEVEL_VERBOSE
CONFIG_AVCT_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_AVCT_TRACE_LEVEL
CONFIG_AVCT_TRACE_LEVEL_NONE CONFIG_BT_LOG_AVCT_TRACE_LEVEL_NONE
CONFIG_AVCT_TRACE_LEVEL_ERROR CONFIG_BT_LOG_AVCT_TRACE_LEVEL_ERROR
CONFIG_AVCT_TRACE_LEVEL_WARNING CONFIG_BT_LOG_AVCT_TRACE_LEVEL_WARNING
CONFIG_AVCT_TRACE_LEVEL_API CONFIG_BT_LOG_AVCT_TRACE_LEVEL_API
CONFIG_AVCT_TRACE_LEVEL_EVENT CONFIG_BT_LOG_AVCT_TRACE_LEVEL_EVENT
CONFIG_AVCT_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_AVCT_TRACE_LEVEL_DEBUG
CONFIG_AVCT_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_AVCT_TRACE_LEVEL_VERBOSE
CONFIG_AVRC_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_AVRC_TRACE_LEVEL
CONFIG_AVRC_TRACE_LEVEL_NONE CONFIG_BT_LOG_AVRC_TRACE_LEVEL_NONE
CONFIG_AVRC_TRACE_LEVEL_ERROR CONFIG_BT_LOG_AVRC_TRACE_LEVEL_ERROR
CONFIG_AVRC_TRACE_LEVEL_WARNING CONFIG_BT_LOG_AVRC_TRACE_LEVEL_WARNING
CONFIG_AVRC_TRACE_LEVEL_API CONFIG_BT_LOG_AVRC_TRACE_LEVEL_API
CONFIG_AVRC_TRACE_LEVEL_EVENT CONFIG_BT_LOG_AVRC_TRACE_LEVEL_EVENT
CONFIG_AVRC_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_AVRC_TRACE_LEVEL_DEBUG
CONFIG_AVRC_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_AVRC_TRACE_LEVEL_VERBOSE
CONFIG_MCA_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_MCA_TRACE_LEVEL
CONFIG_MCA_TRACE_LEVEL_NONE CONFIG_BT_LOG_MCA_TRACE_LEVEL_NONE
CONFIG_MCA_TRACE_LEVEL_ERROR CONFIG_BT_LOG_MCA_TRACE_LEVEL_ERROR
CONFIG_MCA_TRACE_LEVEL_WARNING CONFIG_BT_LOG_MCA_TRACE_LEVEL_WARNING
CONFIG_MCA_TRACE_LEVEL_API CONFIG_BT_LOG_MCA_TRACE_LEVEL_API
CONFIG_MCA_TRACE_LEVEL_EVENT CONFIG_BT_LOG_MCA_TRACE_LEVEL_EVENT
CONFIG_MCA_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_MCA_TRACE_LEVEL_DEBUG
CONFIG_MCA_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_MCA_TRACE_LEVEL_VERBOSE
CONFIG_HID_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_HID_TRACE_LEVEL
CONFIG_HID_TRACE_LEVEL_NONE CONFIG_BT_LOG_HID_TRACE_LEVEL_NONE
CONFIG_HID_TRACE_LEVEL_ERROR CONFIG_BT_LOG_HID_TRACE_LEVEL_ERROR
CONFIG_HID_TRACE_LEVEL_WARNING CONFIG_BT_LOG_HID_TRACE_LEVEL_WARNING
CONFIG_HID_TRACE_LEVEL_API CONFIG_BT_LOG_HID_TRACE_LEVEL_API
CONFIG_HID_TRACE_LEVEL_EVENT CONFIG_BT_LOG_HID_TRACE_LEVEL_EVENT
CONFIG_HID_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_HID_TRACE_LEVEL_DEBUG
CONFIG_HID_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_HID_TRACE_LEVEL_VERBOSE
CONFIG_APPL_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_APPL_TRACE_LEVEL
CONFIG_APPL_TRACE_LEVEL_NONE CONFIG_BT_LOG_APPL_TRACE_LEVEL_NONE
CONFIG_APPL_TRACE_LEVEL_ERROR CONFIG_BT_LOG_APPL_TRACE_LEVEL_ERROR
CONFIG_APPL_TRACE_LEVEL_WARNING CONFIG_BT_LOG_APPL_TRACE_LEVEL_WARNING
CONFIG_APPL_TRACE_LEVEL_API CONFIG_BT_LOG_APPL_TRACE_LEVEL_API
CONFIG_APPL_TRACE_LEVEL_EVENT CONFIG_BT_LOG_APPL_TRACE_LEVEL_EVENT
CONFIG_APPL_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_APPL_TRACE_LEVEL_DEBUG
CONFIG_APPL_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_APPL_TRACE_LEVEL_VERBOSE
CONFIG_GATT_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_GATT_TRACE_LEVEL
CONFIG_GATT_TRACE_LEVEL_NONE CONFIG_BT_LOG_GATT_TRACE_LEVEL_NONE
CONFIG_GATT_TRACE_LEVEL_ERROR CONFIG_BT_LOG_GATT_TRACE_LEVEL_ERROR
CONFIG_GATT_TRACE_LEVEL_WARNING CONFIG_BT_LOG_GATT_TRACE_LEVEL_WARNING
CONFIG_GATT_TRACE_LEVEL_API CONFIG_BT_LOG_GATT_TRACE_LEVEL_API
CONFIG_GATT_TRACE_LEVEL_EVENT CONFIG_BT_LOG_GATT_TRACE_LEVEL_EVENT
CONFIG_GATT_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_GATT_TRACE_LEVEL_DEBUG
CONFIG_GATT_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_GATT_TRACE_LEVEL_VERBOSE
CONFIG_SMP_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_SMP_TRACE_LEVEL
CONFIG_SMP_TRACE_LEVEL_NONE CONFIG_BT_LOG_SMP_TRACE_LEVEL_NONE
CONFIG_SMP_TRACE_LEVEL_ERROR CONFIG_BT_LOG_SMP_TRACE_LEVEL_ERROR
CONFIG_SMP_TRACE_LEVEL_WARNING CONFIG_BT_LOG_SMP_TRACE_LEVEL_WARNING
CONFIG_SMP_TRACE_LEVEL_API CONFIG_BT_LOG_SMP_TRACE_LEVEL_API
CONFIG_SMP_TRACE_LEVEL_EVENT CONFIG_BT_LOG_SMP_TRACE_LEVEL_EVENT
CONFIG_SMP_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_SMP_TRACE_LEVEL_DEBUG
CONFIG_SMP_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_SMP_TRACE_LEVEL_VERBOSE
CONFIG_BTIF_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_BTIF_TRACE_LEVEL
CONFIG_BTIF_TRACE_LEVEL_NONE CONFIG_BT_LOG_BTIF_TRACE_LEVEL_NONE
CONFIG_BTIF_TRACE_LEVEL_ERROR CONFIG_BT_LOG_BTIF_TRACE_LEVEL_ERROR
CONFIG_BTIF_TRACE_LEVEL_WARNING CONFIG_BT_LOG_BTIF_TRACE_LEVEL_WARNING
CONFIG_BTIF_TRACE_LEVEL_API CONFIG_BT_LOG_BTIF_TRACE_LEVEL_API
CONFIG_BTIF_TRACE_LEVEL_EVENT CONFIG_BT_LOG_BTIF_TRACE_LEVEL_EVENT
CONFIG_BTIF_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_BTIF_TRACE_LEVEL_DEBUG
CONFIG_BTIF_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_BTIF_TRACE_LEVEL_VERBOSE
CONFIG_BTC_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_BTC_TRACE_LEVEL
CONFIG_BTC_TRACE_LEVEL_NONE CONFIG_BT_LOG_BTC_TRACE_LEVEL_NONE
CONFIG_BTC_TRACE_LEVEL_ERROR CONFIG_BT_LOG_BTC_TRACE_LEVEL_ERROR
CONFIG_BTC_TRACE_LEVEL_WARNING CONFIG_BT_LOG_BTC_TRACE_LEVEL_WARNING
CONFIG_BTC_TRACE_LEVEL_API CONFIG_BT_LOG_BTC_TRACE_LEVEL_API
CONFIG_BTC_TRACE_LEVEL_EVENT CONFIG_BT_LOG_BTC_TRACE_LEVEL_EVENT
CONFIG_BTC_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_BTC_TRACE_LEVEL_DEBUG
CONFIG_BTC_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_BTC_TRACE_LEVEL_VERBOSE
CONFIG_OSI_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_OSI_TRACE_LEVEL
CONFIG_OSI_TRACE_LEVEL_NONE CONFIG_BT_LOG_OSI_TRACE_LEVEL_NONE
CONFIG_OSI_TRACE_LEVEL_ERROR CONFIG_BT_LOG_OSI_TRACE_LEVEL_ERROR
CONFIG_OSI_TRACE_LEVEL_WARNING CONFIG_BT_LOG_OSI_TRACE_LEVEL_WARNING
CONFIG_OSI_TRACE_LEVEL_API CONFIG_BT_LOG_OSI_TRACE_LEVEL_API
CONFIG_OSI_TRACE_LEVEL_EVENT CONFIG_BT_LOG_OSI_TRACE_LEVEL_EVENT
CONFIG_OSI_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_OSI_TRACE_LEVEL_DEBUG
CONFIG_OSI_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_OSI_TRACE_LEVEL_VERBOSE
CONFIG_BLUFI_INITIAL_TRACE_LEVEL CONFIG_BT_LOG_BLUFI_TRACE_LEVEL
CONFIG_BLUFI_TRACE_LEVEL_NONE CONFIG_BT_LOG_BLUFI_TRACE_LEVEL_NONE
CONFIG_BLUFI_TRACE_LEVEL_ERROR CONFIG_BT_LOG_BLUFI_TRACE_LEVEL_ERROR
CONFIG_BLUFI_TRACE_LEVEL_WARNING CONFIG_BT_LOG_BLUFI_TRACE_LEVEL_WARNING
CONFIG_BLUFI_TRACE_LEVEL_API CONFIG_BT_LOG_BLUFI_TRACE_LEVEL_API
CONFIG_BLUFI_TRACE_LEVEL_EVENT CONFIG_BT_LOG_BLUFI_TRACE_LEVEL_EVENT
CONFIG_BLUFI_TRACE_LEVEL_DEBUG CONFIG_BT_LOG_BLUFI_TRACE_LEVEL_DEBUG
CONFIG_BLUFI_TRACE_LEVEL_VERBOSE CONFIG_BT_LOG_BLUFI_TRACE_LEVEL_VERBOSE
CONFIG_BLE_HOST_QUEUE_CONGESTION_CHECK CONFIG_BT_BLE_HOST_QUEUE_CONG_CHECK
CONFIG_SMP_ENABLE CONFIG_BT_SMP_ENABLE
CONFIG_BLE_ACTIVE_SCAN_REPORT_ADV_SCAN_RSP_INDIVIDUALLY CONFIG_BT_BLE_ACT_SCAN_REP_ADV_SCAN
CONFIG_BLE_ESTABLISH_LINK_CONNECTION_TIMEOUT CONFIG_BT_BLE_ESTAB_LINK_CONN_TOUT

2
components/cxx/CMakeLists.txt
View File

@ -5,6 +5,6 @@ register_component()
target_link_libraries(${COMPONENT_LIB} stdc++)
target_link_libraries(${COMPONENT_LIB} "-u __cxa_guard_dummy")
if(NOT CONFIG_CXX_EXCEPTIONS)
if(NOT CONFIG_COMPILER_CXX_EXCEPTIONS)
target_link_libraries(${COMPONENT_LIB} "-u __cxx_fatal_exception")
endif()

2
components/cxx/component.mk
View File

@ -2,7 +2,7 @@
# is taken from cxx_guards.o instead of libstdc++.a
COMPONENT_ADD_LDFLAGS += -u __cxa_guard_dummy
ifndef CONFIG_CXX_EXCEPTIONS
ifndef CONFIG_COMPILER_CXX_EXCEPTIONS
# If exceptions are disabled, ensure our fatal exception
# hooks are preferentially linked over libstdc++ which
# has full exception support

4
components/cxx/cxx_exception_stubs.cpp
View File

@ -4,7 +4,7 @@
#include <bits/functexcept.h>
#include <sdkconfig.h>
#ifndef CONFIG_CXX_EXCEPTIONS
#ifndef CONFIG_COMPILER_CXX_EXCEPTIONS
const char *FATAL_EXCEPTION = "Fatal C++ exception: ";
@ -81,4 +81,4 @@ extern "C" void __cxa_call_terminate(void) __attribute__((alias("__cxx_fatal_exc
bool std::uncaught_exception() __attribute__((alias("__cxx_fatal_exception_bool")));
#endif // CONFIG_CXX_EXCEPTIONS
#endif // CONFIG_COMPILER_CXX_EXCEPTIONS

6
components/cxx/test/test_cxx.cpp
View File

@ -196,7 +196,7 @@ TEST_CASE("before scheduler has started, static initializers work correctly", "[
TEST_ASSERT_EQUAL(2, StaticInitTestBeforeScheduler::order);
}
#ifdef CONFIG_CXX_EXCEPTIONS
#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS
TEST_CASE("c++ exceptions work", "[cxx]")
{
@ -259,7 +259,7 @@ TEST_CASE("c++ exceptions emergency pool", "[cxx] [ignore]")
thrown_value = e;
printf("Got exception %d\n", thrown_value);
}
#if CONFIG_CXX_EXCEPTIONS_EMG_POOL_SIZE > 0
#if CONFIG_COMPILER_CXX_EXCEPTIONS_EMG_POOL_SIZE > 0
// free all memory
while (pprev) {
p = (void **)(*pprev);
@ -274,7 +274,7 @@ TEST_CASE("c++ exceptions emergency pool", "[cxx] [ignore]")
#endif
}
#else // !CONFIG_CXX_EXCEPTIONS
#else // !CONFIG_COMPILER_CXX_EXCEPTIONS
TEST_CASE("std::out_of_range exception when -fno-exceptions", "[cxx][reset=abort,SW_CPU_RESET]")
{

4
components/driver/Kconfig
View File

@ -10,11 +10,11 @@ menu "Driver configurations"
be shut off when it is not working leading to lower power consumption. However
using the FSM control ADC power will increase the noise of ADC.
config ADC2_DISABLE_DAC
config ADC_DISABLE_DAC
bool "Disable DAC when ADC2 is used on GPIO 25 and 26"
default y
help
If this is set, the ADC2 driver will disables the output of the DAC corresponding to the specified
If this is set, the ADC2 driver will disable the output of the DAC corresponding to the specified
channel. This is the default value.
For testing, disable this option so that we can measure the output of DAC by internal ADC.

2
components/driver/rtc_module.c
View File

@ -1706,7 +1706,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int*
}
//disable other peripherals
#ifdef CONFIG_ADC2_DISABLE_DAC
#ifdef CONFIG_ADC_DISABLE_DAC
adc2_dac_disable( channel );
#endif
// set controller

4
components/driver/sdkconfig.rename Normal file
View File

@ -0,0 +1,4 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_ADC2_DISABLE_DAC CONFIG_ADC_DISABLE_DAC

2
components/driver/test/test_spi_master.c
View File

@ -544,7 +544,7 @@ static const uint8_t data_drom[320+3] = {
TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]")
{
#ifdef CONFIG_SPIRAM_SUPPORT
#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
//test psram if enabled
ESP_LOGI(TAG, "testing PSRAM...");
uint32_t* data_malloc = (uint32_t*)heap_caps_malloc(324, MALLOC_CAP_SPIRAM);

4
components/driver/test/test_spi_slave.c
View File

@ -11,7 +11,7 @@
#include "sdkconfig.h"
#include "test/test_common_spi.h"
#ifndef CONFIG_SPIRAM_SUPPORT
#ifndef CONFIG_ESP32_SPIRAM_SUPPORT
//This test should be removed once the timing test is merged.
@ -140,4 +140,4 @@ TEST_CASE("test slave send unaligned","[spi]")
ESP_LOGI(MASTER_TAG, "test passed.");
}
#endif // !CONFIG_SPIRAM_SUPPORT
#endif // !CONFIG_ESP32_SPIRAM_SUPPORT

2
components/driver/uart.c
View File

@ -1452,7 +1452,7 @@ esp_err_t uart_driver_delete(uart_port_t uart_num)
free(p_uart_obj[uart_num]);
p_uart_obj[uart_num] = NULL;
if (uart_num != CONFIG_CONSOLE_UART_NUM ) {
if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM ) {
if(uart_num == UART_NUM_0) {
periph_module_disable(PERIPH_UART0_MODULE);
} else if(uart_num == UART_NUM_1) {

2
components/efuse/include/esp_efuse.h
View File

@ -347,7 +347,7 @@ esp_err_t esp_efuse_update_secure_version(uint32_t secure_version);
/* @brief Initializes variables: offset and size to simulate the work of an eFuse.
*
* Note: To simulate the work of an eFuse need to set CONFIG_EFUSE_SECURE_VERSION_EMULATE option
* Note: To simulate the work of an eFuse need to set CONFIG_BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE option
* and to add in the partition.csv file a line `efuse_em, data, efuse, , 0x2000,`.
*
* @param[in] offset The starting address of the partition where the eFuse data will be located.

22
components/efuse/src/esp_efuse_fields.c
View File

@ -117,7 +117,7 @@ void esp_efuse_write_random_key(uint32_t blk_wdata0_reg)
bzero(raw, sizeof(raw));
}
#ifdef CONFIG_EFUSE_SECURE_VERSION_EMULATE
#ifdef CONFIG_BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE
#include "../include_bootloader/bootloader_flash.h"
#include "esp_flash_encrypt.h"
@ -172,25 +172,25 @@ static void emulate_secure_version_write(uint32_t secure_version)
uint32_t esp_efuse_read_secure_version()
{
#ifdef CONFIG_APP_ANTI_ROLLBACK
#ifdef CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
uint32_t secure_version;
#ifdef CONFIG_EFUSE_SECURE_VERSION_EMULATE
#ifdef CONFIG_BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE
secure_version = emulate_secure_version_read();
#else
secure_version = REG_READ(EFUSE_BLK_RD_ANTI_ROLLBACK);
#endif // CONFIG_EFUSE_SECURE_VERSION_EMULATE
#endif // CONFIG_BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE
return __builtin_popcount(secure_version & ((1ULL << CONFIG_APP_SECURE_VERSION_SIZE_EFUSE_FIELD) - 1));
return __builtin_popcount(secure_version & ((1ULL << CONFIG_BOOTLOADER_APP_SEC_VER_SIZE_EFUSE_FIELD) - 1));
#else
return 0;
#endif
}
#ifdef CONFIG_APP_ANTI_ROLLBACK
#ifdef CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
static void write_anti_rollback(uint32_t new_bits)
{
#ifdef CONFIG_EFUSE_SECURE_VERSION_EMULATE
#ifdef CONFIG_BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE
emulate_secure_version_write(new_bits);
#else
esp_efuse_reset();
@ -208,12 +208,12 @@ bool esp_efuse_check_secure_version(uint32_t secure_version)
esp_err_t esp_efuse_update_secure_version(uint32_t secure_version)
{
#ifdef CONFIG_APP_ANTI_ROLLBACK
if (CONFIG_APP_SECURE_VERSION_SIZE_EFUSE_FIELD < secure_version) {
ESP_LOGE(TAG, "Max secure version is %d. Given %d version can not be written.", CONFIG_APP_SECURE_VERSION_SIZE_EFUSE_FIELD, secure_version);
#ifdef CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
if (CONFIG_BOOTLOADER_APP_SEC_VER_SIZE_EFUSE_FIELD < secure_version) {
ESP_LOGE(TAG, "Max secure version is %d. Given %d version can not be written.", CONFIG_BOOTLOADER_APP_SEC_VER_SIZE_EFUSE_FIELD, secure_version);
return ESP_ERR_INVALID_ARG;
}
#ifndef CONFIG_EFUSE_SECURE_VERSION_EMULATE
#ifndef CONFIG_BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE
uint32_t coding_scheme = REG_READ(EFUSE_BLK0_RDATA6_REG) & EFUSE_CODING_SCHEME_M;
if (coding_scheme != EFUSE_CODING_SCHEME_VAL_NONE) {
ESP_LOGE(TAG, "Anti rollback is not supported with a 3/4 coding scheme.");

425
components/esp32/Kconfig
View File

@ -1,11 +1,5 @@
menu "ESP32-specific"
# Hidden option to support checking for this specific target in C code and Kconfig files
config IDF_TARGET_ESP32
bool
default "y" if IDF_TARGET="esp32"
default "n"
choice ESP32_DEFAULT_CPU_FREQ_MHZ
prompt "CPU frequency"
default ESP32_DEFAULT_CPU_FREQ_160
@ -26,7 +20,7 @@ menu "ESP32-specific"
default 160 if ESP32_DEFAULT_CPU_FREQ_160
default 240 if ESP32_DEFAULT_CPU_FREQ_240
config SPIRAM_SUPPORT
config ESP32_SPIRAM_SUPPORT
bool "Support for external, SPI-connected RAM"
default "n"
help
@ -34,7 +28,7 @@ menu "ESP32-specific"
main SPI flash chip.
menu "SPI RAM config"
depends on SPIRAM_SUPPORT
depends on ESP32_SPIRAM_SUPPORT
config SPIRAM_BOOT_INIT
bool "Initialize SPI RAM when booting the ESP32"
@ -68,7 +62,7 @@ menu "ESP32-specific"
bool "Make RAM allocatable using heap_caps_malloc(..., MALLOC_CAP_SPIRAM)"
config SPIRAM_USE_MALLOC
bool "Make RAM allocatable using malloc() as well"
select SUPPORT_STATIC_ALLOCATION
select FREERTOS_SUPPORT_STATIC_ALLOCATION
endchoice
choice SPIRAM_TYPE
@ -175,7 +169,7 @@ menu "ESP32-specific"
from the non-preferred region instead, so malloc() will not suddenly fail when either internal or
external memory is full.
config WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
config SPIRAM_TRY_ALLOCATE_WIFI_LWIP
bool "Try to allocate memories of WiFi and LWIP in SPIRAM firstly. If failed, allocate internal memory"
depends on SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC
default "n"
@ -219,7 +213,7 @@ menu "ESP32-specific"
config SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
bool "Allow .bss segment placed in external memory"
default n
depends on SPIRAM_SUPPORT
depends on ESP32_SPIRAM_SUPPORT
help
If enabled the option,and add EXT_RAM_ATTR defined your variable,then your variable will be placed in
PSRAM instead of internal memory, and placed most of variables of lwip,net802.11,pp,bluedroid library
@ -239,9 +233,9 @@ menu "ESP32-specific"
bool "VSPI host (SPI3)"
endchoice
config PICO_PSRAM_CS_IO
config SPIRAM_PICO_PSRAM_CS_IO
int "PSRAM CS IO for ESP32-PICO chip"
depends on SPIRAM_SUPPORT
depends on ESP32_SPIRAM_SUPPORT
range 0 33
default 10
help
@ -250,18 +244,18 @@ menu "ESP32-specific"
endmenu
config MEMMAP_TRACEMEM
config ESP32_MEMMAP_TRACEMEM
bool
default "n"
config MEMMAP_TRACEMEM_TWOBANKS
config ESP32_MEMMAP_TRACEMEM_TWOBANKS
bool
default "n"
config ESP32_TRAX
bool "Use TRAX tracing feature"
default "n"
select MEMMAP_TRACEMEM
select ESP32_MEMMAP_TRACEMEM
help
The ESP32 contains a feature which allows you to trace the execution path the processor
has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
@ -272,7 +266,7 @@ menu "ESP32-specific"
bool "Reserve memory for tracing both pro as well as app cpu execution"
default "n"
depends on ESP32_TRAX && !FREERTOS_UNICORE
select MEMMAP_TRACEMEM_TWOBANKS
select ESP32_MEMMAP_TRACEMEM_TWOBANKS
help
The ESP32 contains a feature which allows you to trace the execution path the processor
has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
@ -280,15 +274,15 @@ menu "ESP32-specific"
what this is.
# Memory to reverse for trace, used in linker script
config TRACEMEM_RESERVE_DRAM
config ESP32_TRACEMEM_RESERVE_DRAM
hex
default 0x8000 if MEMMAP_TRACEMEM && MEMMAP_TRACEMEM_TWOBANKS
default 0x4000 if MEMMAP_TRACEMEM && !MEMMAP_TRACEMEM_TWOBANKS
default 0x8000 if ESP32_MEMMAP_TRACEMEM && ESP32_MEMMAP_TRACEMEM_TWOBANKS
default 0x4000 if ESP32_MEMMAP_TRACEMEM && !ESP32_MEMMAP_TRACEMEM_TWOBANKS
default 0x0
choice NUMBER_OF_UNIVERSAL_MAC_ADDRESS
choice ESP32_UNIVERSAL_MAC_ADDRESSES
bool "Number of universally administered (by IEEE) MAC address"
default FOUR_UNIVERSAL_MAC_ADDRESS
default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
help
Configure the number of universally administered (by IEEE) MAC addresses.
During initialisation, MAC addresses for each network interface are generated or derived from a
@ -305,195 +299,19 @@ menu "ESP32-specific"
a custom universal MAC address range, the correct setting will depend on the allocation of MAC
addresses in this range (either 2 or 4 per device.)
config TWO_UNIVERSAL_MAC_ADDRESS
config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
bool "Two"
config FOUR_UNIVERSAL_MAC_ADDRESS
config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
bool "Four"
endchoice
config NUMBER_OF_UNIVERSAL_MAC_ADDRESS
config ESP32_UNIVERSAL_MAC_ADDRESSES
int
default 2 if TWO_UNIVERSAL_MAC_ADDRESS
default 4 if FOUR_UNIVERSAL_MAC_ADDRESS
default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
config SYSTEM_EVENT_QUEUE_SIZE
int "System event queue size"
default 32
help
Config system event queue size in different application.
config SYSTEM_EVENT_TASK_STACK_SIZE
int "Event loop task stack size"
default 2304
help
Config system event task stack size in different application.
config MAIN_TASK_STACK_SIZE
int "Main task stack size"
default 3584
help
Configure the "main task" stack size. This is the stack of the task
which calls app_main(). If app_main() returns then this task is deleted
and its stack memory is freed.
config IPC_TASK_STACK_SIZE
int "Inter-Processor Call (IPC) task stack size"
default 1024
range 512 65536 if !ESP32_APPTRACE_ENABLE
range 2048 65536 if ESP32_APPTRACE_ENABLE
help
Configure the IPC tasks stack size. One IPC task runs on each core
(in dual core mode), and allows for cross-core function calls.
See IPC documentation for more details.
The default stack size should be enough for most common use cases.
It can be shrunk if you are sure that you do not use any custom
IPC functionality.
config TIMER_TASK_STACK_SIZE
int "High-resolution timer task stack size"
default 3584
range 2048 65536
help
Configure the stack size of esp_timer/ets_timer task. This task is used
to dispatch callbacks of timers created using ets_timer and esp_timer
APIs. If you are seing stack overflow errors in timer task, increase
this value.
Note that this is not the same as FreeRTOS timer task. To configure
FreeRTOS timer task size, see "FreeRTOS timer task stack size" option
in "FreeRTOS" menu.
choice NEWLIB_STDOUT_LINE_ENDING
prompt "Line ending for UART output"
default NEWLIB_STDOUT_LINE_ENDING_CRLF
help
This option allows configuring the desired line endings sent to UART
when a newline ('\n', LF) appears on stdout.
Three options are possible:
CRLF: whenever LF is encountered, prepend it with CR
LF: no modification is applied, stdout is sent as is
CR: each occurence of LF is replaced with CR
This option doesn't affect behavior of the UART driver (drivers/uart.h).
config NEWLIB_STDOUT_LINE_ENDING_CRLF
bool "CRLF"
config NEWLIB_STDOUT_LINE_ENDING_LF
bool "LF"
config NEWLIB_STDOUT_LINE_ENDING_CR
bool "CR"
endchoice
choice NEWLIB_STDIN_LINE_ENDING
prompt "Line ending for UART input"
default NEWLIB_STDIN_LINE_ENDING_CR
help
This option allows configuring which input sequence on UART produces
a newline ('\n', LF) on stdin.
Three options are possible:
CRLF: CRLF is converted to LF
LF: no modification is applied, input is sent to stdin as is
CR: each occurence of CR is replaced with LF
This option doesn't affect behavior of the UART driver (drivers/uart.h).
config NEWLIB_STDIN_LINE_ENDING_CRLF
bool "CRLF"
config NEWLIB_STDIN_LINE_ENDING_LF
bool "LF"
config NEWLIB_STDIN_LINE_ENDING_CR
bool "CR"
endchoice
config NEWLIB_NANO_FORMAT
bool "Enable 'nano' formatting options for printf/scanf family"
default n
help
ESP32 ROM contains parts of newlib C library, including printf/scanf family
of functions. These functions have been compiled with so-called "nano"
formatting option. This option doesn't support 64-bit integer formats and C99
features, such as positional arguments.
For more details about "nano" formatting option, please see newlib readme file,
search for '--enable-newlib-nano-formatted-io':
https://sourceware.org/newlib/README
If this option is enabled, build system will use functions available in
ROM, reducing the application binary size. Functions available in ROM run
faster than functions which run from flash. Functions available in ROM can
also run when flash instruction cache is disabled.
If you need 64-bit integer formatting support or C99 features, keep this
option disabled.
choice CONSOLE_UART
prompt "UART for console output"
default CONSOLE_UART_DEFAULT
help
Select whether to use UART for console output (through stdout and stderr).
- Default is to use UART0 on pins GPIO1(TX) and GPIO3(RX).
- If "Custom" is selected, UART0 or UART1 can be chosen,
and any pins can be selected.
- If "None" is selected, there will be no console output on any UART, except
for initial output from ROM bootloader. This output can be further suppressed by
bootstrapping GPIO13 pin to low logic level.
config CONSOLE_UART_DEFAULT
bool "Default: UART0, TX=GPIO1, RX=GPIO3"
config CONSOLE_UART_CUSTOM
bool "Custom"
config CONSOLE_UART_NONE
bool "None"
endchoice
choice CONSOLE_UART_NUM
prompt "UART peripheral to use for console output (0-1)"
depends on CONSOLE_UART_CUSTOM
default CONSOLE_UART_CUSTOM_NUM_0
help
Due of a ROM bug, UART2 is not supported for console output
via ets_printf.
config CONSOLE_UART_CUSTOM_NUM_0
bool "UART0"
config CONSOLE_UART_CUSTOM_NUM_1
bool "UART1"
endchoice
config CONSOLE_UART_NUM
int
default 0 if CONSOLE_UART_DEFAULT || CONSOLE_UART_NONE
default 0 if CONSOLE_UART_CUSTOM_NUM_0
default 1 if CONSOLE_UART_CUSTOM_NUM_1
config CONSOLE_UART_TX_GPIO
int "UART TX on GPIO#"
depends on CONSOLE_UART_CUSTOM
range 0 33
default 19
config CONSOLE_UART_RX_GPIO
int "UART RX on GPIO#"
depends on CONSOLE_UART_CUSTOM
range 0 39
default 21
config CONSOLE_UART_BAUDRATE
int "UART console baud rate"
depends on !CONSOLE_UART_NONE
default 115200
range 1200 4000000
config ULP_COPROC_ENABLED
config ESP32_ULP_COPROC_ENABLED
bool "Enable Ultra Low Power (ULP) Coprocessor"
default "n"
help
@ -501,13 +319,13 @@ menu "ESP32-specific"
If this option is enabled, further coprocessor configuration will appear in the Components menu.
config ULP_COPROC_RESERVE_MEM
config ESP32_ULP_COPROC_RESERVE_MEM
int
prompt "RTC slow memory reserved for coprocessor" if ULP_COPROC_ENABLED
default 512 if ULP_COPROC_ENABLED
range 32 8192 if ULP_COPROC_ENABLED
default 0 if !ULP_COPROC_ENABLED
range 0 0 if !ULP_COPROC_ENABLED
prompt "RTC slow memory reserved for coprocessor" if ESP32_ULP_COPROC_ENABLED
default 512 if ESP32_ULP_COPROC_ENABLED
range 32 8192 if ESP32_ULP_COPROC_ENABLED
default 0 if !ESP32_ULP_COPROC_ENABLED
range 0 0 if !ESP32_ULP_COPROC_ENABLED
help
Bytes of memory to reserve for ULP coprocessor firmware & data.
@ -544,23 +362,6 @@ menu "ESP32-specific"
of the crash.
endchoice
config GDBSTUB_SUPPORT_TASKS
bool "GDBStub: enable listing FreeRTOS tasks"
default y
depends on ESP32_PANIC_GDBSTUB
help
If enabled, GDBStub can supply the list of FreeRTOS tasks to GDB.
Thread list can be queried from GDB using 'info threads' command.
Note that if GDB task lists were corrupted, this feature may not work.
If GDBStub fails, try disabling this feature.
config GDBSTUB_MAX_TASKS
int "GDBStub: maximum number of tasks supported"
default 32
depends on GDBSTUB_SUPPORT_TASKS
help
Set the number of tasks which GDB Stub will support.
config ESP32_DEBUG_OCDAWARE
bool "Make exception and panic handlers JTAG/OCD aware"
default y
@ -570,84 +371,13 @@ menu "ESP32-specific"
config ESP32_DEBUG_STUBS_ENABLE
bool "OpenOCD debug stubs"
default OPTIMIZATION_LEVEL_DEBUG
default COMPILER_OPTIMIZATION_LEVEL_DEBUG
depends on !ESP32_TRAX
help
Debug stubs are used by OpenOCD to execute pre-compiled onboard code which does some useful debugging,
e.g. GCOV data dump.
config INT_WDT
bool "Interrupt watchdog"
default y
help
This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time,
either because a task turned off interrupts and did not turn them on for a long time, or because an
interrupt handler did not return. It will try to invoke the panic handler first and failing that
reset the SoC.
config INT_WDT_TIMEOUT_MS
int "Interrupt watchdog timeout (ms)"
depends on INT_WDT
default 300 if !SPIRAM_SUPPORT
default 800 if SPIRAM_SUPPORT
range 10 10000
help
The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate.
config INT_WDT_CHECK_CPU1
bool "Also watch CPU1 tick interrupt"
depends on INT_WDT && !FREERTOS_UNICORE
default y
help
Also detect if interrupts on CPU 1 are disabled for too long.
config TASK_WDT
bool "Initialize Task Watchdog Timer on startup"
default y
help
The Task Watchdog Timer can be used to make sure individual tasks are still
running. Enabling this option will cause the Task Watchdog Timer to be
initialized automatically at startup. The Task Watchdog timer can be
initialized after startup as well (see Task Watchdog Timer API Reference)
config TASK_WDT_PANIC
bool "Invoke panic handler on Task Watchdog timeout"
depends on TASK_WDT
default n
help
If this option is enabled, the Task Watchdog Timer will be configured to
trigger the panic handler when it times out. This can also be configured
at run time (see Task Watchdog Timer API Reference)
config TASK_WDT_TIMEOUT_S
int "Task Watchdog timeout period (seconds)"
depends on TASK_WDT
range 1 60
default 5
help
Timeout period configuration for the Task Watchdog Timer in seconds.
This is also configurable at run time (see Task Watchdog Timer API Reference)
config TASK_WDT_CHECK_IDLE_TASK_CPU0
bool "Watch CPU0 Idle Task"
depends on TASK_WDT
default y
help
If this option is enabled, the Task Watchdog Timer will watch the CPU0
Idle Task. Having the Task Watchdog watch the Idle Task allows for detection
of CPU starvation as the Idle Task not being called is usually a symptom of
CPU starvation. Starvation of the Idle Task is detrimental as FreeRTOS household
tasks depend on the Idle Task getting some runtime every now and then.
config TASK_WDT_CHECK_IDLE_TASK_CPU1
bool "Watch CPU1 Idle Task"
depends on TASK_WDT && !FREERTOS_UNICORE
default y
help
If this option is enabled, the Task Wtachdog Timer will wach the CPU1
Idle Task.
config BROWNOUT_DET
config ESP32_BROWNOUT_DET
#The brownout detector code is disabled (by making it depend on a nonexisting symbol) because the current
#revision of ESP32 silicon has a bug in the brown-out detector, rendering it unusable for resetting the CPU.
bool "Hardware brownout detect & reset"
@ -657,9 +387,9 @@ menu "ESP32-specific"
a specific value. If this happens, it will reset the chip in order to prevent unintended
behaviour.
choice BROWNOUT_DET_LVL_SEL
choice ESP32_BROWNOUT_DET_LVL_SEL
prompt "Brownout voltage level"
depends on BROWNOUT_DET
depends on ESP32_BROWNOUT_DET
default BROWNOUT_DET_LVL_SEL_25
help
The brownout detector will reset the chip when the supply voltage is approximately
@ -668,40 +398,40 @@ menu "ESP32-specific"
#The voltage levels here are estimates, more work needs to be done to figure out the exact voltages
#of the brownout threshold levels.
config BROWNOUT_DET_LVL_SEL_0
config ESP32_BROWNOUT_DET_LVL_SEL_0
bool "2.43V +/- 0.05"
config BROWNOUT_DET_LVL_SEL_1
config ESP32_BROWNOUT_DET_LVL_SEL_1
bool "2.48V +/- 0.05"
config BROWNOUT_DET_LVL_SEL_2
config ESP32_BROWNOUT_DET_LVL_SEL_2
bool "2.58V +/- 0.05"
config BROWNOUT_DET_LVL_SEL_3
config ESP32_BROWNOUT_DET_LVL_SEL_3
bool "2.62V +/- 0.05"
config BROWNOUT_DET_LVL_SEL_4
config ESP32_BROWNOUT_DET_LVL_SEL_4
bool "2.67V +/- 0.05"
config BROWNOUT_DET_LVL_SEL_5
config ESP32_BROWNOUT_DET_LVL_SEL_5
bool "2.70V +/- 0.05"
config BROWNOUT_DET_LVL_SEL_6
config ESP32_BROWNOUT_DET_LVL_SEL_6
bool "2.77V +/- 0.05"
config BROWNOUT_DET_LVL_SEL_7
config ESP32_BROWNOUT_DET_LVL_SEL_7
bool "2.80V +/- 0.05"
endchoice
config BROWNOUT_DET_LVL
config ESP32_BROWNOUT_DET_LVL
int
default 0 if BROWNOUT_DET_LVL_SEL_0
default 1 if BROWNOUT_DET_LVL_SEL_1
default 2 if BROWNOUT_DET_LVL_SEL_2
default 3 if BROWNOUT_DET_LVL_SEL_3
default 4 if BROWNOUT_DET_LVL_SEL_4
default 5 if BROWNOUT_DET_LVL_SEL_5
default 6 if BROWNOUT_DET_LVL_SEL_6
default 7 if BROWNOUT_DET_LVL_SEL_7
default 0 if ESP32_BROWNOUT_DET_LVL_SEL_0
default 1 if ESP32_BROWNOUT_DET_LVL_SEL_1
default 2 if ESP32_BROWNOUT_DET_LVL_SEL_2
default 3 if ESP32_BROWNOUT_DET_LVL_SEL_3
default 4 if ESP32_BROWNOUT_DET_LVL_SEL_4
default 5 if ESP32_BROWNOUT_DET_LVL_SEL_5
default 6 if ESP32_BROWNOUT_DET_LVL_SEL_6
default 7 if ESP32_BROWNOUT_DET_LVL_SEL_7
#Reduce PHY TX power when brownout reset
config REDUCE_PHY_TX_POWER
config ESP32_REDUCE_PHY_TX_POWER
bool "Reduce PHY TX power when brownout reset"
depends on BROWNOUT_DET
depends on ESP32_BROWNOUT_DET
default y
help
When brownout reset occurs, reduce PHY TX power to keep the code running
@ -742,9 +472,9 @@ menu "ESP32-specific"
bool "None"
endchoice
choice ESP32_RTC_CLOCK_SOURCE
choice ESP32_RTC_CLK_SRC
prompt "RTC clock source"
default ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
default ESP32_RTC_CLK_SRC_INT_RC
help
Choose which clock is used as RTC clock source.
@ -765,19 +495,19 @@ menu "ESP32-specific"
deep sleep current (by 5uA) but has better frequency stability than
the internal 150kHz oscillator. It does not require external components.
config ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
config ESP32_RTC_CLK_SRC_INT_RC
bool "Internal 150kHz RC oscillator"
config ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
config ESP32_RTC_CLK_SRC_EXT_CRYS
bool "External 32kHz crystal"
config ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC
config ESP32_RTC_CLK_SRC_EXT_OSC
bool "External 32kHz oscillator at 32K_XP pin"
config ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256
config ESP32_RTC_CLK_SRC_INT_8MD256
bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)"
endchoice
config ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
config ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
bool "Additional current for external 32kHz crystal"
depends on ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
depends on ESP32_RTC_CLK_SRC_EXT_CRYS
default "n"
help
Choose which additional current is used for rtc external crystal.
@ -790,10 +520,10 @@ menu "ESP32-specific"
config ESP32_RTC_CLK_CAL_CYCLES
int "Number of cycles for RTC_SLOW_CLK calibration"
default 3000 if ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
default 1024 if ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
range 0 27000 if ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL || ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC || ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256 # NOERROR
range 0 32766 if ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
default 3000 if ESP32_RTC_CLK_SRC_EXT_CRYS
default 1024 if ESP32_RTC_CLK_SRC_INT_RC
range 0 27000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256
range 0 32766 if ESP32_RTC_CLK_SRC_INT_RC
help
When the startup code initializes RTC_SLOW_CLK, it can perform
calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
@ -812,7 +542,7 @@ menu "ESP32-specific"
config ESP32_RTC_XTAL_BOOTSTRAP_CYCLES
int "Bootstrap cycles for external 32kHz crystal"
depends on ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
depends on ESP32_RTC_CLK_SRC_EXT_CRYS
default 5
range 0 32768
help
@ -875,7 +605,7 @@ menu "ESP32-specific"
default 40 if ESP32_XTAL_FREQ_40
default 26 if ESP32_XTAL_FREQ_26
config DISABLE_BASIC_ROM_CONSOLE
config ESP32_DISABLE_BASIC_ROM_CONSOLE
bool "Permanently disable BASIC ROM Console"
default n
help
@ -887,7 +617,7 @@ menu "ESP32-specific"
(Enabling secure boot also disables the BASIC ROM Console by default.)
config NO_BLOBS
config ESP32_NO_BLOBS
bool "No Binary Blobs"
depends on !BT_ENABLED
default n
@ -895,18 +625,7 @@ menu "ESP32-specific"
If enabled, this disables the linking of binary libraries in the application build. Note
that after enabling this Wi-Fi/Bluetooth will not work.
config ESP_TIMER_PROFILING
bool "Enable esp_timer profiling features"
default n
help
If enabled, esp_timer_dump will dump information such as number of times
the timer was started, number of times the timer has triggered, and the
total time it took for the callback to run.
This option has some effect on timer performance and the amount of memory
used for timer storage, and should only be used for debugging/testing
purposes.
config COMPATIBLE_PRE_V2_1_BOOTLOADERS
config ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS
bool "App compatible with bootloaders before IDF v2.1"
default n
help
@ -922,16 +641,6 @@ menu "ESP32-specific"
Enabling this setting adds approximately 1KB to the app's IRAM usage.
config ESP_ERR_TO_NAME_LOOKUP
bool "Enable lookup of error code strings"
default "y"
help
Functions esp_err_to_name() and esp_err_to_name_r() return string
representations of error codes from a pre-generated lookup table.
This option can be used to turn off the use of the look-up table in
order to save memory but this comes at the price of sacrificing
distinguishable (meaningful) output string representations.
config ESP32_RTCDATA_IN_FAST_MEM
bool "Place RTC_DATA_ATTR and RTC_RODATA_ATTR variables into RTC fast memory segment"
default n

6
components/esp32/brownout.c
View File

@ -25,11 +25,11 @@
#include "driver/rtc_cntl.h"
#include "freertos/FreeRTOS.h"
#ifdef CONFIG_BROWNOUT_DET_LVL
#define BROWNOUT_DET_LVL CONFIG_BROWNOUT_DET_LVL
#ifdef CONFIG_ESP32_BROWNOUT_DET_LVL
#define BROWNOUT_DET_LVL CONFIG_ESP32_BROWNOUT_DET_LVL
#else
#define BROWNOUT_DET_LVL 0
#endif //CONFIG_BROWNOUT_DET_LVL
#endif //CONFIG_ESP32_BROWNOUT_DET_LVL
static void rtc_brownout_isr_handler()
{

18
components/esp32/clk.c
View File

@ -74,7 +74,7 @@ void esp_clk_init(void)
rtc_config_t cfg = RTC_CONFIG_DEFAULT();
rtc_init(cfg);
#ifdef CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS
#ifdef CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS
/* Check the bootloader set the XTAL frequency.
Bootloaders pre-v2.1 don't do this.
@ -85,7 +85,7 @@ void esp_clk_init(void)
bootloader_clock_configure();
}
#else
/* If this assertion fails, either upgrade the bootloader or enable CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS */
/* If this assertion fails, either upgrade the bootloader or enable CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS */
assert(rtc_clk_xtal_freq_get() != RTC_XTAL_FREQ_AUTO);
#endif
@ -103,11 +103,11 @@ void esp_clk_init(void)
rtc_wdt_protect_on();
#endif
#if defined(CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL)
#if defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS)
select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
#elif defined(CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC)
#elif defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC)
select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
#elif defined(CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256)
#elif defined(CONFIG_ESP32_RTC_CLK_SRC_INT_8MD256)
select_rtc_slow_clk(SLOW_CLK_8MD256);
#else
select_rtc_slow_clk(RTC_SLOW_FREQ_RTC);
@ -131,7 +131,7 @@ void esp_clk_init(void)
// Wait for UART TX to finish, otherwise some UART output will be lost
// when switching APB frequency
uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
rtc_clk_cpu_freq_set_config(&new_config);
@ -273,13 +273,13 @@ void esp_perip_clk_init(void)
//Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
common_perip_clk |= DPORT_I2S0_CLK_EN |
#if CONFIG_CONSOLE_UART_NUM != 0
#if CONFIG_ESP_CONSOLE_UART_NUM != 0
DPORT_UART_CLK_EN |
#endif
#if CONFIG_CONSOLE_UART_NUM != 1
#if CONFIG_ESP_CONSOLE_UART_NUM != 1
DPORT_UART1_CLK_EN |
#endif
#if CONFIG_CONSOLE_UART_NUM != 2
#if CONFIG_ESP_CONSOLE_UART_NUM != 2
DPORT_UART2_CLK_EN |
#endif
DPORT_SPI2_CLK_EN |

50
components/esp32/cpu_start.c
View File

@ -185,7 +185,7 @@ void IRAM_ATTR call_start_cpu0()
#ifndef CONFIG_APP_EXCLUDE_PROJECT_VER_VAR
ESP_EARLY_LOGI(TAG, "App version: %s", app_desc->version);
#endif
#ifdef CONFIG_APP_SECURE_VERSION
#ifdef CONFIG_BOOTLOADER_APP_SECURE_VERSION
ESP_EARLY_LOGI(TAG, "Secure version: %d", app_desc->secure_version);
#endif
#ifdef CONFIG_APP_COMPILE_TIME_DATE
@ -273,13 +273,13 @@ void IRAM_ATTR call_start_cpu1()
cpu_configure_region_protection();
cpu_init_memctl();
#if CONFIG_CONSOLE_UART_NONE
#if CONFIG_ESP_CONSOLE_UART_NONE
ets_install_putc1(NULL);
ets_install_putc2(NULL);
#else // CONFIG_CONSOLE_UART_NONE
#else // CONFIG_ESP_CONSOLE_UART_NONE
uartAttach();
ets_install_uart_printf();
uart_tx_switch(CONFIG_CONSOLE_UART_NUM);
uart_tx_switch(CONFIG_ESP_CONSOLE_UART_NUM);
#endif
wdt_reset_cpu1_info_enable();
@ -331,28 +331,28 @@ void start_cpu0_default(void)
esp_perip_clk_init();
intr_matrix_clear();
#ifndef CONFIG_CONSOLE_UART_NONE
#ifndef CONFIG_ESP_CONSOLE_UART_NONE
#ifdef CONFIG_PM_ENABLE
const int uart_clk_freq = REF_CLK_FREQ;
/* When DFS is enabled, use REFTICK as UART clock source */
CLEAR_PERI_REG_MASK(UART_CONF0_REG(CONFIG_CONSOLE_UART_NUM), UART_TICK_REF_ALWAYS_ON);
CLEAR_PERI_REG_MASK(UART_CONF0_REG(CONFIG_ESP_CONSOLE_UART_NUM), UART_TICK_REF_ALWAYS_ON);
#else
const int uart_clk_freq = APB_CLK_FREQ;
#endif // CONFIG_PM_DFS_ENABLE
uart_div_modify(CONFIG_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_CONSOLE_UART_BAUDRATE);
#endif // CONFIG_CONSOLE_UART_NONE
uart_div_modify(CONFIG_ESP_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_ESP_CONSOLE_UART_BAUDRATE);
#endif // CONFIG_ESP_CONSOLE_UART_NONE
#if CONFIG_BROWNOUT_DET
#if CONFIG_ESP32_BROWNOUT_DET
esp_brownout_init();
#endif
#if CONFIG_DISABLE_BASIC_ROM_CONSOLE
#if CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE
esp_efuse_disable_basic_rom_console();
#endif
rtc_gpio_force_hold_dis_all();
esp_vfs_dev_uart_register();
esp_reent_init(_GLOBAL_REENT);
#ifndef CONFIG_CONSOLE_UART_NONE
const char* default_uart_dev = "/dev/uart/" STRINGIFY(CONFIG_CONSOLE_UART_NUM);
#ifndef CONFIG_ESP_CONSOLE_UART_NONE
const char* default_uart_dev = "/dev/uart/" STRINGIFY(CONFIG_ESP_CONSOLE_UART_NUM);
_GLOBAL_REENT->_stdin = fopen(default_uart_dev, "r");
_GLOBAL_REENT->_stdout = fopen(default_uart_dev, "w");
_GLOBAL_REENT->_stderr = fopen(default_uart_dev, "w");
@ -377,7 +377,7 @@ void start_cpu0_default(void)
assert(err == ESP_OK && "Failed to init pthread module!");
do_global_ctors();
#if CONFIG_INT_WDT
#if CONFIG_ESP_INT_WDT
esp_int_wdt_init();
//Initialize the interrupt watch dog for CPU0.
esp_int_wdt_cpu_init();
@ -411,7 +411,7 @@ void start_cpu0_default(void)
}
#endif
#if CONFIG_SW_COEXIST_ENABLE
#if CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE
esp_coex_adapter_register(&g_coex_adapter_funcs);
#endif
@ -438,7 +438,7 @@ void start_cpu1_default(void)
esp_err_t err = esp_apptrace_init();
assert(err == ESP_OK && "Failed to init apptrace module on APP CPU!");
#endif
#if CONFIG_INT_WDT
#if CONFIG_ESP_INT_WDT
//Initialize the interrupt watch dog for CPU1.
esp_int_wdt_cpu_init();
#endif
@ -454,16 +454,16 @@ void start_cpu1_default(void)
}
#endif //!CONFIG_FREERTOS_UNICORE
#ifdef CONFIG_CXX_EXCEPTIONS
#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS
size_t __cxx_eh_arena_size_get()
{
return CONFIG_CXX_EXCEPTIONS_EMG_POOL_SIZE;
return CONFIG_COMPILER_CXX_EXCEPTIONS_EMG_POOL_SIZE;
}
#endif
static void do_global_ctors(void)
{
#ifdef CONFIG_CXX_EXCEPTIONS
#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS
static struct object ob;
__register_frame_info( __eh_frame, &ob );
#endif
@ -495,21 +495,21 @@ static void main_task(void* args)
#endif
//Initialize task wdt if configured to do so
#ifdef CONFIG_TASK_WDT_PANIC
ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_TASK_WDT_TIMEOUT_S, true));
#elif CONFIG_TASK_WDT
ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_TASK_WDT_TIMEOUT_S, false));
#ifdef CONFIG_ESP_TASK_WDT_PANIC
ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, true));
#elif CONFIG_ESP_TASK_WDT
ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, false));
#endif
//Add IDLE 0 to task wdt
#ifdef CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0
#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0);
if(idle_0 != NULL){
ESP_ERROR_CHECK(esp_task_wdt_add(idle_0));
}
#endif
//Add IDLE 1 to task wdt
#ifdef CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1
#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU(1);
if(idle_1 != NULL){
ESP_ERROR_CHECK(esp_task_wdt_add(idle_1));
@ -520,7 +520,7 @@ static void main_task(void* args)
#ifndef CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE
rtc_wdt_disable();
#endif
#ifdef CONFIG_EFUSE_SECURE_VERSION_EMULATE
#ifdef CONFIG_BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE
const esp_partition_t *efuse_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_EFUSE_EM, NULL);
if (efuse_partition) {
esp_efuse_init(efuse_partition->address, efuse_partition->size);

2
components/esp32/dport_panic_highint_hdl.S
View File

@ -86,7 +86,7 @@ xt_highint4:
movi a0, PANIC_RSN_CACHEERR
j 9f
1:
#if CONFIG_INT_WDT_CHECK_CPU1
#if CONFIG_ESP_INT_WDT_CHECK_CPU1
/* Check if the cause is the app cpu failing to tick.*/
movi a0, int_wdt_app_cpu_ticked
l32i a0, a0, 0

28
components/esp32/esp_adapter.c
View File

@ -54,12 +54,12 @@ extern void esp_dport_access_stall_other_cpu_start_wrap(void);
extern void esp_dport_access_stall_other_cpu_end_wrap(void);
/*
If CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST is enabled. Prefer to allocate a chunk of memory in SPIRAM firstly.
If CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is enabled. Prefer to allocate a chunk of memory in SPIRAM firstly.
If failed, try to allocate it in internal memory then.
*/
IRAM_ATTR void *wifi_malloc( size_t size )
{
#if CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
#if CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP
return heap_caps_malloc_prefer(size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL);
#else
return malloc(size);
@ -67,12 +67,12 @@ IRAM_ATTR void *wifi_malloc( size_t size )
}
/*
If CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST is enabled. Prefer to allocate a chunk of memory in SPIRAM firstly.
If CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is enabled. Prefer to allocate a chunk of memory in SPIRAM firstly.
If failed, try to allocate it in internal memory then.
*/
IRAM_ATTR void *wifi_realloc( void *ptr, size_t size )
{
#if CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
#if CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP
return heap_caps_realloc_prefer(ptr, size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL);
#else
return realloc(ptr, size);
@ -80,12 +80,12 @@ IRAM_ATTR void *wifi_realloc( void *ptr, size_t size )
}
/*
If CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST is enabled. Prefer to allocate a chunk of memory in SPIRAM firstly.
If CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is enabled. Prefer to allocate a chunk of memory in SPIRAM firstly.
If failed, try to allocate it in internal memory then.
*/
IRAM_ATTR void *wifi_calloc( size_t n, size_t size )
{
#if CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
#if CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP
return heap_caps_calloc_prefer(n, size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL);
#else
return calloc(n, size);
@ -396,7 +396,7 @@ static void sc_ack_send_wrapper(void *param)
static uint32_t coex_status_get_wrapper(void)
{
#if CONFIG_SW_COEXIST_ENABLE
#if CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE
return coex_status_get();
#else
return 0;
@ -405,7 +405,7 @@ static uint32_t coex_status_get_wrapper(void)
static int coex_wifi_request_wrapper(uint32_t event, uint32_t latency, uint32_t duration)
{
#if CONFIG_SW_COEXIST_ENABLE
#if CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE
return coex_wifi_request(event, latency, duration);
#else
return 0;
@ -414,7 +414,7 @@ static int coex_wifi_request_wrapper(uint32_t event, uint32_t latency, uint32_t
static int coex_wifi_release_wrapper(uint32_t event)
{
#if CONFIG_SW_COEXIST_ENABLE
#if CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE
return coex_wifi_release(event);
#else
return 0;
@ -423,7 +423,7 @@ static int coex_wifi_release_wrapper(uint32_t event)
int IRAM_ATTR coex_bt_request_wrapper(uint32_t event, uint32_t latency, uint32_t duration)
{
#if CONFIG_SW_COEXIST_ENABLE
#if CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE
return coex_bt_request(event, latency, duration);
#else
return 0;
@ -432,7 +432,7 @@ int IRAM_ATTR coex_bt_request_wrapper(uint32_t event, uint32_t latency, uint32_t
int IRAM_ATTR coex_bt_release_wrapper(uint32_t event)
{
#if CONFIG_SW_COEXIST_ENABLE
#if CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE
return coex_bt_release(event);
#else
return 0;
@ -441,7 +441,7 @@ int IRAM_ATTR coex_bt_release_wrapper(uint32_t event)
int coex_register_bt_cb_wrapper(coex_func_cb_t cb)
{
#if CONFIG_SW_COEXIST_ENABLE
#if CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE
return coex_register_bt_cb(cb);
#else
return 0;
@ -450,7 +450,7 @@ int coex_register_bt_cb_wrapper(coex_func_cb_t cb)
uint32_t IRAM_ATTR coex_bb_reset_lock_wrapper(void)
{
#if CONFIG_SW_COEXIST_ENABLE
#if CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE
return coex_bb_reset_lock();
#else
return 0;
@ -459,7 +459,7 @@ uint32_t IRAM_ATTR coex_bb_reset_lock_wrapper(void)
void IRAM_ATTR coex_bb_reset_unlock_wrapper(uint32_t restore)
{
#if CONFIG_SW_COEXIST_ENABLE
#if CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE
coex_bb_reset_unlock(restore);
#endif
}

16
components/esp32/gdbstub.c
View File

@ -273,9 +273,9 @@ static int sendPacket(const char * text) {
return ST_OK;
}
#if CONFIG_GDBSTUB_SUPPORT_TASKS
#if CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
#define STUB_TASKS_NUM CONFIG_GDBSTUB_MAX_TASKS
#define STUB_TASKS_NUM CONFIG_ESP_GDBSTUB_MAX_TASKS
//Remember the exception frame that caused panic since it's not saved in TCB
static XtExcFrame paniced_frame;
@ -365,7 +365,7 @@ static int findCurrentTaskIndex() {
return curTaskIndex;
}
#endif // CONFIG_GDBSTUB_SUPPORT_TASKS
#endif // CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
//Handle a command as received from GDB.
static int gdbHandleCommand(unsigned char *cmd, int len) {
@ -392,7 +392,7 @@ static int gdbHandleCommand(unsigned char *cmd, int len) {
gdbPacketEnd();
} else if (cmd[0]=='?') { //Reply with stop reason
sendReason();
#if CONFIG_GDBSTUB_SUPPORT_TASKS
#if CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
} else if (handlerState != HANDLER_TASK_SUPPORT_DISABLED) {
if (cmd[0]=='H') { //Continue with task
if (cmd[1]=='g' || cmd[1]=='c') {
@ -473,7 +473,7 @@ static int gdbHandleCommand(unsigned char *cmd, int len) {
}
return sendPacket(NULL);
}
#endif // CONFIG_GDBSTUB_SUPPORT_TASKS
#endif // CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
} else {
//We don't recognize or support whatever GDB just sent us.
return sendPacket(NULL);
@ -532,7 +532,7 @@ static int gdbReadCommand() {
void esp_gdbstub_panic_handler(XtExcFrame *frame) {
#if CONFIG_GDBSTUB_SUPPORT_TASKS
#if CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
if (handlerState == HANDLER_STARTED) {
//We have re-entered GDB Stub. Try disabling task support.
handlerState = HANDLER_TASK_SUPPORT_DISABLED;
@ -542,9 +542,9 @@ void esp_gdbstub_panic_handler(XtExcFrame *frame) {
memcpy(&paniced_frame, frame, sizeof(paniced_frame));
dumpHwToRegfile(&paniced_frame);
}
#else // CONFIG_GDBSTUB_SUPPORT_TASKS
#else // CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
dumpHwToRegfile(frame);
#endif // CONFIG_GDBSTUB_SUPPORT_TASKS
#endif // CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
//Make sure txd/rxd are enabled
gpio_pullup_dis(1);

4
components/esp32/include/esp_sleep.h
View File

@ -95,7 +95,7 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source);
* source is used.
* @return
* - ESP_OK on success
* - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT) is enabled.
* - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT) is enabled.
* - ESP_ERR_INVALID_STATE if ULP co-processor is not enabled or if wakeup triggers conflict
*/
esp_err_t esp_sleep_enable_ulp_wakeup();
@ -122,7 +122,7 @@ esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us);
*
* @return
* - ESP_OK on success
* - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT) is enabled.
* - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT) is enabled.
* - ESP_ERR_INVALID_STATE if wakeup triggers conflict
*/
esp_err_t esp_sleep_enable_touchpad_wakeup();

12
components/esp32/int_wdt.c
View File

@ -32,14 +32,14 @@
#include "driver/periph_ctrl.h"
#include "esp_int_wdt.h"
#if CONFIG_INT_WDT
#if CONFIG_ESP_INT_WDT
#define WDT_INT_NUM 24
//Take care: the tick hook can also be called before esp_int_wdt_init() is called.
#if CONFIG_INT_WDT_CHECK_CPU1
#if CONFIG_ESP_INT_WDT_CHECK_CPU1
//Not static; the ISR assembly checks this.
bool int_wdt_app_cpu_ticked=false;
@ -50,8 +50,8 @@ static void IRAM_ATTR tick_hook(void) {
//Only feed wdt if app cpu also ticked.
if (int_wdt_app_cpu_ticked) {
TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
TIMERG1.wdt_config2=CONFIG_INT_WDT_TIMEOUT_MS*2; //Set timeout before interrupt
TIMERG1.wdt_config3=CONFIG_INT_WDT_TIMEOUT_MS*4; //Set timeout before reset
TIMERG1.wdt_config2=CONFIG_ESP_INT_WDT_TIMEOUT_MS*2; //Set timeout before interrupt
TIMERG1.wdt_config3=CONFIG_ESP_INT_WDT_TIMEOUT_MS*4; //Set timeout before reset
TIMERG1.wdt_feed=1;
TIMERG1.wdt_wprotect=0;
int_wdt_app_cpu_ticked=false;
@ -62,8 +62,8 @@ static void IRAM_ATTR tick_hook(void) {
static void IRAM_ATTR tick_hook(void) {
if (xPortGetCoreID()!=0) return;
TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
TIMERG1.wdt_config2=CONFIG_INT_WDT_TIMEOUT_MS*2; //Set timeout before interrupt
TIMERG1.wdt_config3=CONFIG_INT_WDT_TIMEOUT_MS*4; //Set timeout before reset
TIMERG1.wdt_config2=CONFIG_ESP_INT_WDT_TIMEOUT_MS*2; //Set timeout before interrupt
TIMERG1.wdt_config3=CONFIG_ESP_INT_WDT_TIMEOUT_MS*4; //Set timeout before reset
TIMERG1.wdt_feed=1;
TIMERG1.wdt_wprotect=0;
}

6
components/esp32/ld/esp32.ld
View File

@ -69,8 +69,8 @@ MEMORY
Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
*/
rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
len = 0x1000 - CONFIG_ULP_COPROC_RESERVE_MEM
rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32_ULP_COPROC_RESERVE_MEM,
len = 0x1000 - CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
/* external memory ,including data and text */
extern_ram_seg(RWX) : org = 0x3F800000,
@ -78,7 +78,7 @@ MEMORY
}
/* Heap ends at top of dram0_0_seg */
_heap_end = 0x40000000 - CONFIG_TRACEMEM_RESERVE_DRAM;
_heap_end = 0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM;
_data_seg_org = ORIGIN(rtc_data_seg);

22
components/esp32/panic.c
View File

@ -67,8 +67,8 @@
//printf may be broken, so we fix our own printing fns...
static void panicPutChar(char c)
{
while (((READ_PERI_REG(UART_STATUS_REG(CONFIG_CONSOLE_UART_NUM)) >> UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT) >= 126) ;
WRITE_PERI_REG(UART_FIFO_REG(CONFIG_CONSOLE_UART_NUM), c);
while (((READ_PERI_REG(UART_STATUS_REG(CONFIG_ESP_CONSOLE_UART_NUM)) >> UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT) >= 126) ;
WRITE_PERI_REG(UART_FIFO_REG(CONFIG_ESP_CONSOLE_UART_NUM), c);
}
static void panicPutStr(const char *c)
@ -144,9 +144,9 @@ static __attribute__((noreturn)) inline void invoke_abort()
abort_called = true;
#if CONFIG_ESP32_APPTRACE_ENABLE
#if CONFIG_SYSVIEW_ENABLE
SEGGER_RTT_ESP32_FlushNoLock(CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
SEGGER_RTT_ESP32_FlushNoLock(CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
#else
esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH,
esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_THRESH,
APPTRACE_ONPANIC_HOST_FLUSH_TMO);
#endif
#endif
@ -315,9 +315,9 @@ void panicHandler(XtExcFrame *frame)
}
#if CONFIG_ESP32_APPTRACE_ENABLE
#if CONFIG_SYSVIEW_ENABLE
SEGGER_RTT_ESP32_FlushNoLock(CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
SEGGER_RTT_ESP32_FlushNoLock(CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
#else
esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH,
esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_THRESH,
APPTRACE_ONPANIC_HOST_FLUSH_TMO);
#endif
#endif
@ -348,9 +348,9 @@ void xt_unhandled_exception(XtExcFrame *frame)
panicPutStr(". Setting bp and returning..\r\n");
#if CONFIG_ESP32_APPTRACE_ENABLE
#if CONFIG_SYSVIEW_ENABLE
SEGGER_RTT_ESP32_FlushNoLock(CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
SEGGER_RTT_ESP32_FlushNoLock(CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
#else
esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH,
esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_THRESH,
APPTRACE_ONPANIC_HOST_FLUSH_TMO);
#endif
#endif
@ -434,7 +434,7 @@ static void esp_panic_dig_reset() __attribute__((noreturn));
static void esp_panic_dig_reset()
{
// make sure all the panic handler output is sent from UART FIFO
uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
// switch to XTAL (otherwise we will keep running from the PLL)
rtc_clk_cpu_freq_set_xtal();
// reset the digital part
@ -590,9 +590,9 @@ static __attribute__((noreturn)) void commonErrorHandler(XtExcFrame *frame)
#if CONFIG_ESP32_APPTRACE_ENABLE
disableAllWdts();
#if CONFIG_SYSVIEW_ENABLE
SEGGER_RTT_ESP32_FlushNoLock(CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
SEGGER_RTT_ESP32_FlushNoLock(CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
#else
esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH,
esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_THRESH,
APPTRACE_ONPANIC_HOST_FLUSH_TMO);
#endif
reconfigureAllWdts();

38
components/esp32/sdkconfig.rename Normal file
View File

@ -0,0 +1,38 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
# ESP32-specific
CONFIG_SPIRAM_SUPPORT CONFIG_ESP32_SPIRAM_SUPPORT
CONFIG_MEMMAP_TRACEMEM CONFIG_ESP32_MEMMAP_TRACEMEM
CONFIG_MEMMAP_TRACEMEM_TWOBANKS CONFIG_ESP32_MEMMAP_TRACEMEM_TWOBANKS
CONFIG_TRACEMEM_RESERVE_DRAM CONFIG_ESP32_TRACEMEM_RESERVE_DRAM
CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES
CONFIG_TWO_UNIVERSAL_MAC_ADDRESS CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
CONFIG_ESP32_RTC_CLOCK_SOURCE CONFIG_ESP32_RTC_CLK_SRC
CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC CONFIG_ESP32_RTC_CLK_SRC_INT_RC
CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC
CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256 CONFIG_ESP32_RTC_CLK_SRC_INT_8MD256
CONFIG_DISABLE_BASIC_ROM_CONSOLE CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE
CONFIG_NO_BLOBS CONFIG_ESP32_NO_BLOBS
CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS
CONFIG_ULP_COPROC_ENABLED CONFIG_ESP32_ULP_COPROC_ENABLED
CONFIG_ULP_COPROC_RESERVE_MEM CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
CONFIG_BROWNOUT_DET CONFIG_ESP32_BROWNOUT_DET
CONFIG_BROWNOUT_DET_LVL_SEL CONFIG_ESP32_BROWNOUT_DET_LVL_SEL
CONFIG_BROWNOUT_DET_LVL_SEL_0 CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_0
CONFIG_BROWNOUT_DET_LVL_SEL_1 CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_1
CONFIG_BROWNOUT_DET_LVL_SEL_2 CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_2
CONFIG_BROWNOUT_DET_LVL_SEL_3 CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_3
CONFIG_BROWNOUT_DET_LVL_SEL_4 CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_4
CONFIG_BROWNOUT_DET_LVL_SEL_5 CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_5
CONFIG_BROWNOUT_DET_LVL_SEL_6 CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_6
CONFIG_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_7
CONFIG_BROWNOUT_DET_LVL CONFIG_ESP32_BROWNOUT_DET_LVL
CONFIG_REDUCE_PHY_TX_POWER CONFIG_ESP32_REDUCE_PHY_TX_POWER
# SPI RAM config
CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP
CONFIG_PICO_PSRAM_CS_IO CONFIG_SPIRAM_PICO_PSRAM_CS_IO

18
components/esp32/sleep_modes.c
View File

@ -48,13 +48,13 @@
// Extra time it takes to enter and exit light sleep and deep sleep
// For deep sleep, this is until the wake stub runs (not the app).
#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
#ifdef CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
#define LIGHT_SLEEP_TIME_OVERHEAD_US (650 + 30 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
#define DEEP_SLEEP_TIME_OVERHEAD_US (650 + 100 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
#else
#define LIGHT_SLEEP_TIME_OVERHEAD_US (250 + 30 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
#define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
#endif // CONFIG_ESP32_RTC_CLOCK_SOURCE
#endif // CONFIG_ESP32_RTC_CLK_SRC
// Minimal amount of time we can sleep for
#define LIGHT_SLEEP_MIN_TIME_US 200
@ -305,7 +305,7 @@ esp_err_t esp_light_sleep_start()
const uint32_t flash_enable_time_us = VDD_SDIO_POWERUP_TO_FLASH_READ_US
+ CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY;
#ifndef CONFIG_SPIRAM_SUPPORT
#ifndef CONFIG_ESP32_SPIRAM_SUPPORT
const uint32_t vddsdio_pd_sleep_duration = MAX(FLASH_PD_MIN_SLEEP_TIME_US,
flash_enable_time_us + LIGHT_SLEEP_TIME_OVERHEAD_US + LIGHT_SLEEP_MIN_TIME_US);
@ -313,7 +313,7 @@ esp_err_t esp_light_sleep_start()
pd_flags |= RTC_SLEEP_PD_VDDSDIO;
s_config.sleep_time_adjustment += flash_enable_time_us;
}
#endif //CONFIG_SPIRAM_SUPPORT
#endif //CONFIG_ESP32_SPIRAM_SUPPORT
rtc_vddsdio_config_t vddsdio_config = rtc_vddsdio_get_config();
@ -390,7 +390,7 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source)
} else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_UART, (RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN))) {
s_config.wakeup_triggers &= ~(RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN);
}
#ifdef CONFIG_ULP_COPROC_ENABLED
#ifdef CONFIG_ESP32_ULP_COPROC_ENABLED
else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_ULP, RTC_ULP_TRIG_EN)) {
s_config.wakeup_triggers &= ~RTC_ULP_TRIG_EN;
}
@ -404,10 +404,10 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source)
esp_err_t esp_sleep_enable_ulp_wakeup()
{
#ifdef CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
#ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
return ESP_ERR_NOT_SUPPORTED;
#endif
#ifdef CONFIG_ULP_COPROC_ENABLED
#ifdef CONFIG_ESP32_ULP_COPROC_ENABLED
if(s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) {
ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
return ESP_ERR_INVALID_STATE;
@ -440,7 +440,7 @@ static void timer_wakeup_prepare()
esp_err_t esp_sleep_enable_touchpad_wakeup()
{
#ifdef CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
#ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
return ESP_ERR_NOT_SUPPORTED;
#endif
if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN)) {
@ -705,7 +705,7 @@ static uint32_t get_power_down_flags()
if ((s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) == 0) {
// If enabled EXT1 only and enable the additional current by touch, should be keep RTC_PERIPH power on.
#if ((defined CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL) && (defined CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT))
#if ((defined CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS) && (defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT))
pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
#endif
}

2
components/esp32/spiram.c
View File

@ -46,7 +46,7 @@ we add more types of external RAM memory, this can be made into a more intellige
#endif
#endif
#if CONFIG_SPIRAM_SUPPORT
#if CONFIG_ESP32_SPIRAM_SUPPORT
static const char* TAG = "spiram";

6
components/esp32/spiram_psram.c
View File

@ -36,7 +36,7 @@
#include "driver/spi_common.h"
#include "driver/periph_ctrl.h"
#if CONFIG_SPIRAM_SUPPORT
#if CONFIG_ESP32_SPIRAM_SUPPORT
#include "soc/rtc.h"
//Commands for PSRAM chip
@ -118,7 +118,7 @@ typedef enum {
#define PICO_FLASH_SPIHD_SD2_IO 11
#define PICO_PSRAM_CLK_IO 6
#define PICO_PSRAM_CS_IO CONFIG_PICO_PSRAM_CS_IO
#define PICO_PSRAM_CS_IO CONFIG_SPIRAM_PICO_PSRAM_CS_IO
#define PICO_PSRAM_SPIQ_SD0_IO 17
#define PICO_PSRAM_SPID_SD1_IO 8
#define PICO_PSRAM_SPIWP_SD3_IO 7
@ -836,4 +836,4 @@ static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psra
CLEAR_PERI_REG_MASK(SPI_PIN_REG(0), SPI_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
}
#endif // CONFIG_SPIRAM_SUPPORT
#endif // CONFIG_ESP32_SPIRAM_SUPPORT

6
components/esp32/test/test_4mpsram.c
View File

@ -6,7 +6,7 @@
static const char TAG[] = "test_psram";
#ifdef CONFIG_SPIRAM_SUPPORT
#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
static void test_psram_content()
{
const int test_size = 2048;
@ -40,7 +40,7 @@ static void test_psram_content()
TEST_CASE("can use spi when not being used by psram", "[psram_4m]")
{
spi_host_device_t host;
#if !CONFIG_SPIRAM_SUPPORT || !CONFIG_SPIRAM_SPEED_80M || CONFIG_SPIRAM_BANKSWITCH_ENABLE
#if !CONFIG_ESP32_SPIRAM_SUPPORT || !CONFIG_SPIRAM_SPEED_80M || CONFIG_SPIRAM_BANKSWITCH_ENABLE
//currently all 8M psram don't need more SPI peripherals
host = -1;
#elif CONFIG_SPIRAM_OCCUPY_HSPI_HOST
@ -66,7 +66,7 @@ TEST_CASE("can use spi when not being used by psram", "[psram_4m]")
TEST_ASSERT(claim_vspi==true);
}
#ifdef CONFIG_SPIRAM_SUPPORT
#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
test_psram_content();
#endif
}

4
components/esp32/test/test_dport.c
View File

@ -107,8 +107,8 @@ TEST_CASE("access DPORT and APB at same time", "[esp32]")
void run_tasks_with_change_freq_cpu(int cpu_freq_mhz)
{
const int uart_num = CONFIG_CONSOLE_UART_NUM;
const int uart_baud = CONFIG_CONSOLE_UART_BAUDRATE;
const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM;
const int uart_baud = CONFIG_ESP_CONSOLE_UART_BAUDRATE;
dport_test_result = false;
apb_test_result = false;
rtc_cpu_freq_config_t old_config;

2
components/esp32/test/test_pm.c
View File

@ -122,7 +122,7 @@ TEST_CASE("Automatic light occurs when tasks are suspended", "[pm]")
TEST_CASE("Can wake up from automatic light sleep by GPIO", "[pm]")
{
assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 16 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 16 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
/* Set up GPIO used to wake up RTC */
const int ext1_wakeup_gpio = 25;

6
components/esp32/test/test_sleep.c
View File

@ -125,7 +125,7 @@ TEST_CASE("light sleep stress test with periodic esp_timer", "[deepsleep]")
}
#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
#ifdef CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
#define MAX_SLEEP_TIME_ERROR_US 200
#else
#define MAX_SLEEP_TIME_ERROR_US 100
@ -176,8 +176,8 @@ TEST_CASE("light sleep and frequency switching", "[deepsleep]")
{
#ifndef CONFIG_PM_ENABLE
const int uart_clk_freq = REF_CLK_FREQ;
CLEAR_PERI_REG_MASK(UART_CONF0_REG(CONFIG_CONSOLE_UART_NUM), UART_TICK_REF_ALWAYS_ON);
uart_div_modify(CONFIG_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_CONSOLE_UART_BAUDRATE);
CLEAR_PERI_REG_MASK(UART_CONF0_REG(CONFIG_ESP_CONSOLE_UART_NUM), UART_TICK_REF_ALWAYS_ON);
uart_div_modify(CONFIG_ESP_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_ESP_CONSOLE_UART_BAUDRATE);
#endif
rtc_cpu_freq_config_t config_xtal, config_default;

4
components/esp32/test/test_spiram_cache_flush.c
View File

@ -23,7 +23,7 @@ This code tests the interaction between PSRAM and SPI flash routines.
#include "esp_partition.h"
#include "test_utils.h"
#if CONFIG_SPIRAM_SUPPORT
#if CONFIG_ESP32_SPIRAM_SUPPORT
#if CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC
#define USE_CAPS_ALLOC 1
@ -181,4 +181,4 @@ IRAM_ATTR TEST_CASE("Spiram memcmp weirdness at 80MHz", "[spiram]") {
#endif
}
#endif // CONFIG_SPIRAM_SUPPORT
#endif // CONFIG_ESP32_SPIRAM_SUPPORT

2
components/esp32/test/test_stack_check.c
View File

@ -1,6 +1,6 @@
#include "unity.h"
#if CONFIG_STACK_CHECK
#if CONFIG_COMPILER_STACK_CHECK
static void recur_and_smash()
{

2
components/esp32/test/test_stack_check_cxx.cpp
View File

@ -1,6 +1,6 @@
#include "unity.h"
#if CONFIG_STACK_CHECK
#if CONFIG_COMPILER_STACK_CHECK
static void recur_and_smash_cxx()
{

219
components/esp_common/Kconfig Normal file
View File

@ -0,0 +1,219 @@
menu "Common ESP-related"
config ESP_TIMER_PROFILING
bool "Enable esp_timer profiling features"
default n
help
If enabled, esp_timer_dump will dump information such as number of times the timer was started, number of
times the timer has triggered, and the total time it took for the callback to run. This option has some
effect on timer performance and the amount of memory used for timer storage, and should only be used for
debugging/testing purposes.
config ESP_ERR_TO_NAME_LOOKUP
bool "Enable lookup of error code strings"
default "y"
help
Functions esp_err_to_name() and esp_err_to_name_r() return string representations of error codes from a
pre-generated lookup table. This option can be used to turn off the use of the look-up table in order to
save memory but this comes at the price of sacrificing distinguishable (meaningful) output string
representations.
config ESP_SYSTEM_EVENT_QUEUE_SIZE
int "System event queue size"
default 32
help
Config system event queue size in different application.
config ESP_SYSTEM_EVENT_TASK_STACK_SIZE
int "Event loop task stack size"
default 2304
help
Config system event task stack size in different application.
config ESP_MAIN_TASK_STACK_SIZE
int "Main task stack size"
default 3584
help
Configure the "main task" stack size. This is the stack of the task
which calls app_main(). If app_main() returns then this task is deleted
and its stack memory is freed.
config ESP_IPC_TASK_STACK_SIZE
int "Inter-Processor Call (IPC) task stack size"
default 1024
range 512 65536 if !ESP32_APPTRACE_ENABLE
range 2048 65536 if ESP32_APPTRACE_ENABLE
help
Configure the IPC tasks stack size. One IPC task runs on each core
(in dual core mode), and allows for cross-core function calls.
See IPC documentation for more details.
The default stack size should be enough for most common use cases.
It can be shrunk if you are sure that you do not use any custom
IPC functionality.
config ESP_TIMER_TASK_STACK_SIZE
int "High-resolution timer task stack size"
default 3584
range 2048 65536
help
Configure the stack size of esp_timer/ets_timer task. This task is used
to dispatch callbacks of timers created using ets_timer and esp_timer
APIs. If you are seing stack overflow errors in timer task, increase
this value.
Note that this is not the same as FreeRTOS timer task. To configure
FreeRTOS timer task size, see "FreeRTOS timer task stack size" option
in "FreeRTOS" menu.
choice ESP_CONSOLE_UART
prompt "UART for console output"
default ESP_CONSOLE_UART_DEFAULT
help
Select whether to use UART for console output (through stdout and stderr).
- Default is to use UART0 on pins GPIO1(TX) and GPIO3(RX).
- If "Custom" is selected, UART0 or UART1 can be chosen,
and any pins can be selected.
- If "None" is selected, there will be no console output on any UART, except
for initial output from ROM bootloader. This output can be further suppressed by
bootstrapping GPIO13 pin to low logic level.
config ESP_CONSOLE_UART_DEFAULT
bool "Default: UART0, TX=GPIO1, RX=GPIO3"
config ESP_CONSOLE_UART_CUSTOM
bool "Custom"
config ESP_CONSOLE_UART_NONE
bool "None"
endchoice
choice ESP_CONSOLE_UART_NUM
prompt "UART peripheral to use for console output (0-1)"
depends on ESP_CONSOLE_UART_CUSTOM
default ESP_CONSOLE_UART_CUSTOM_NUM_0
help
Due of a ROM bug, UART2 is not supported for console output
via ets_printf.
config ESP_CONSOLE_UART_CUSTOM_NUM_0
bool "UART0"
config ESP_CONSOLE_UART_CUSTOM_NUM_1
bool "UART1"
endchoice
config ESP_CONSOLE_UART_NUM
int
default 0 if ESP_CONSOLE_UART_DEFAULT || ESP_CONSOLE_UART_NONE
default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0
default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1
config ESP_CONSOLE_UART_TX_GPIO
int "UART TX on GPIO#"
depends on ESP_CONSOLE_UART_CUSTOM
range 0 33
default 19
config ESP_CONSOLE_UART_RX_GPIO
int "UART RX on GPIO#"
depends on ESP_CONSOLE_UART_CUSTOM
range 0 39
default 21
config ESP_CONSOLE_UART_BAUDRATE
int "UART console baud rate"
depends on !ESP_CONSOLE_UART_NONE
default 115200
range 1200 4000000
config ESP_GDBSTUB_SUPPORT_TASKS
bool "GDBStub: enable listing FreeRTOS tasks"
default y
depends on ESP32_PANIC_GDBSTUB
help
If enabled, GDBStub can supply the list of FreeRTOS tasks to GDB.
Thread list can be queried from GDB using 'info threads' command.
Note that if GDB task lists were corrupted, this feature may not work.
If GDBStub fails, try disabling this feature.
config ESP_GDBSTUB_MAX_TASKS
int "GDBStub: maximum number of tasks supported"
default 32
depends on ESP_GDBSTUB_SUPPORT_TASKS
help
Set the number of tasks which GDB Stub will support.
config ESP_INT_WDT
bool "Interrupt watchdog"
default y
help
This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time,
either because a task turned off interrupts and did not turn them on for a long time, or because an
interrupt handler did not return. It will try to invoke the panic handler first and failing that
reset the SoC.
config ESP_INT_WDT_TIMEOUT_MS
int "Interrupt watchdog timeout (ms)"
depends on ESP_INT_WDT
default 300 if !ESP32_SPIRAM_SUPPORT
default 800 if ESP32_SPIRAM_SUPPORT
range 10 10000
help
The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate.
config ESP_INT_WDT_CHECK_CPU1
bool "Also watch CPU1 tick interrupt"
depends on ESP_INT_WDT && !FREERTOS_UNICORE
default y
help
Also detect if interrupts on CPU 1 are disabled for too long.
config ESP_TASK_WDT
bool "Initialize Task Watchdog Timer on startup"
default y
help
The Task Watchdog Timer can be used to make sure individual tasks are still
running. Enabling this option will cause the Task Watchdog Timer to be
initialized automatically at startup. The Task Watchdog timer can be
initialized after startup as well (see Task Watchdog Timer API Reference)
config ESP_TASK_WDT_PANIC
bool "Invoke panic handler on Task Watchdog timeout"
depends on ESP_TASK_WDT
default n
help
If this option is enabled, the Task Watchdog Timer will be configured to
trigger the panic handler when it times out. This can also be configured
at run time (see Task Watchdog Timer API Reference)
config ESP_TASK_WDT_TIMEOUT_S
int "Task Watchdog timeout period (seconds)"
depends on ESP_TASK_WDT
range 1 60
default 5
help
Timeout period configuration for the Task Watchdog Timer in seconds.
This is also configurable at run time (see Task Watchdog Timer API Reference)
config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
bool "Watch CPU0 Idle Task"
depends on ESP_TASK_WDT
default y
help
If this option is enabled, the Task Watchdog Timer will watch the CPU0
Idle Task. Having the Task Watchdog watch the Idle Task allows for detection
of CPU starvation as the Idle Task not being called is usually a symptom of
CPU starvation. Starvation of the Idle Task is detrimental as FreeRTOS household
tasks depend on the Idle Task getting some runtime every now and then.
config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
bool "Watch CPU1 Idle Task"
depends on ESP_TASK_WDT && !FREERTOS_UNICORE
default y
help
If this option is enabled, the Task Wtachdog Timer will wach the CPU1
Idle Task.
endmenu # Common ESP-related

2
components/esp_common/include/esp_err.h
View File

@ -105,7 +105,7 @@ void _esp_error_check_failed_without_abort(esp_err_t rc, const char *file, int l
esp_err_t __err_rc = (x); \
(void) sizeof(__err_rc); \
} while(0)
#elif defined(CONFIG_OPTIMIZATION_ASSERTIONS_SILENT)
#elif defined(CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT)
#define ESP_ERROR_CHECK(x) do { \
esp_err_t __err_rc = (x); \
if (__err_rc != ESP_OK) { \

2
components/esp_common/include/esp_system.h
View File

@ -37,7 +37,7 @@ typedef enum {
/** @cond */
#define TWO_UNIVERSAL_MAC_ADDR 2
#define FOUR_UNIVERSAL_MAC_ADDR 4
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES
/** @endcond */
/**

8
components/esp_common/include/esp_task.h
View File

@ -47,12 +47,12 @@
/* idf task */
#define ESP_TASK_TIMER_PRIO (ESP_TASK_PRIO_MAX - 3)
#define ESP_TASK_TIMER_STACK (CONFIG_TIMER_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
#define ESP_TASK_TIMER_STACK (CONFIG_ESP_TIMER_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
#define ESP_TASKD_EVENT_PRIO (ESP_TASK_PRIO_MAX - 5)
#define ESP_TASKD_EVENT_STACK (CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
#define ESP_TASKD_EVENT_STACK (CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
#define ESP_TASK_TCPIP_PRIO (ESP_TASK_PRIO_MAX - 7)
#define ESP_TASK_TCPIP_STACK (CONFIG_TCPIP_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
#define ESP_TASK_TCPIP_STACK (CONFIG_LWIP_TCPIP_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
#define ESP_TASK_MAIN_PRIO (ESP_TASK_PRIO_MIN + 1)
#define ESP_TASK_MAIN_STACK (CONFIG_MAIN_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
#define ESP_TASK_MAIN_STACK (CONFIG_ESP_MAIN_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
#endif

28
components/esp_common/sdkconfig.rename Normal file
View File

@ -0,0 +1,28 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_SYSTEM_EVENT_QUEUE_SIZE CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE
CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE
CONFIG_MAIN_TASK_STACK_SIZE CONFIG_ESP_MAIN_TASK_STACK_SIZE
CONFIG_IPC_TASK_STACK_SIZE CONFIG_ESP_IPC_TASK_STACK_SIZE
CONFIG_TIMER_TASK_STACK_SIZE CONFIG_ESP_TIMER_TASK_STACK_SIZE
CONFIG_CONSOLE_UART CONFIG_ESP_CONSOLE_UART
CONFIG_CONSOLE_UART_DEFAULT CONFIG_ESP_CONSOLE_UART_DEFAULT
CONFIG_CONSOLE_UART_CUSTOM CONFIG_ESP_CONSOLE_UART_CUSTOM
CONFIG_CONSOLE_UART_NONE CONFIG_ESP_CONSOLE_UART_NONE
CONFIG_CONSOLE_UART_NUM CONFIG_ESP_CONSOLE_UART_NUM
CONFIG_CONSOLE_UART_CUSTOM_NUM_0 CONFIG_ESP_CONSOLE_UART_CUSTOM_NUM_0
CONFIG_CONSOLE_UART_CUSTOM_NUM_1 CONFIG_ESP_CONSOLE_UART_CUSTOM_NUM_1
CONFIG_CONSOLE_UART_TX_GPIO CONFIG_ESP_CONSOLE_UART_TX_GPIO
CONFIG_CONSOLE_UART_RX_GPIO CONFIG_ESP_CONSOLE_UART_RX_GPIO
CONFIG_CONSOLE_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE
CONFIG_GDBSTUB_SUPPORT_TASKS CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
CONFIG_GDBSTUB_MAX_TASKS CONFIG_ESP_GDBSTUB_MAX_TASKS
CONFIG_INT_WDT CONFIG_ESP_INT_WDT
CONFIG_INT_WDT_TIMEOUT_MS CONFIG_ESP_INT_WDT_TIMEOUT_MS
CONFIG_INT_WDT_CHECK_CPU1 CONFIG_ESP_INT_WDT_CHECK_CPU1
CONFIG_TASK_WDT CONFIG_ESP_TASK_WDT
CONFIG_TASK_WDT_PANIC CONFIG_ESP_TASK_WDT_PANIC
CONFIG_TASK_WDT_TIMEOUT_S CONFIG_ESP_TASK_WDT_TIMEOUT_S
CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1

2
components/esp_common/src/ipc.c
View File

@ -92,7 +92,7 @@ static void esp_ipc_init()
for (int i = 0; i < portNUM_PROCESSORS; ++i) {
snprintf(task_name, sizeof(task_name), "ipc%d", i);
s_ipc_sem[i] = xSemaphoreCreateBinary();
portBASE_TYPE res = xTaskCreatePinnedToCore(ipc_task, task_name, CONFIG_IPC_TASK_STACK_SIZE, (void*) i,
portBASE_TYPE res = xTaskCreatePinnedToCore(ipc_task, task_name, CONFIG_ESP_IPC_TASK_STACK_SIZE, (void*) i,
configMAX_PRIORITIES - 1, NULL, i);
assert(res == pdTRUE);
}

2
components/esp_common/src/stack_check.c
View File

@ -15,7 +15,7 @@
#include "sdkconfig.h"
#include "esp_system.h"
#if CONFIG_STACK_CHECK
#if CONFIG_COMPILER_STACK_CHECK
#define LOG_LOCAL_LEVEL CONFIG_LOG_DEFAULT_LEVEL
#include "esp_log.h"

4
components/esp_event/CMakeLists.txt
View File

@ -15,7 +15,7 @@ set(COMPONENT_ADD_LDFRAGMENTS linker.lf)
register_component()
if(GCC_NOT_5_2_0 AND CONFIG_EVENT_LOOP_PROFILING)
if(GCC_NOT_5_2_0 AND CONFIG_ESP_EVENT_LOOP_PROFILING)
# uses C11 atomic feature
set_source_files_properties(esp_event.c PROPERTIES COMPILE_FLAGS -std=gnu11)
endif()
endif()

8
components/esp_event/Kconfig
View File

@ -1,6 +1,6 @@
menu "Event Loop Library"
config EVENT_LOOP_PROFILING
config ESP_EVENT_LOOP_PROFILING
bool "Enable event loop profiling"
default n
help
@ -8,16 +8,16 @@ menu "Event Loop Library"
to/recieved by an event loop, number of callbacks involved, number of events dropped to to a full event
loop queue, run time of event handlers, and number of times/run time of each event handler.
config POST_EVENTS_FROM_ISR
config ESP_EVENT_POST_FROM_ISR
bool "Support posting events from ISRs"
default y
help
Enable posting events from interrupt handlers.
config POST_EVENTS_FROM_IRAM_ISR
config ESP_EVENT_POST_FROM_IRAM_ISR
bool "Support posting events from ISRs placed in IRAM"
default y
depends on POST_EVENTS_FROM_ISR
depends on ESP_EVENT_POST_FROM_ISR
help
Enable posting events from interrupt handlers placed in IRAM. Enabling this option places API functions
esp_event_post and esp_event_post_to in IRAM.

2
components/esp_event/component.mk
View File

@ -5,7 +5,7 @@ COMPONENT_ADD_INCLUDEDIRS := include
COMPONENT_PRIV_INCLUDEDIRS := private_include
COMPONENT_SRCDIRS := .
ifdef CONFIG_EVENT_LOOP_PROFILING
ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
PROFILING_ENABLED := 1
else
PROFILING_ENABLED := 0

4
components/esp_event/default_event_loop.c
View File

@ -55,7 +55,7 @@ esp_err_t esp_event_post(esp_event_base_t event_base, int32_t event_id,
}
#if CONFIG_POST_EVENTS_FROM_ISR
#if CONFIG_ESP_EVENT_POST_FROM_ISR
esp_err_t esp_event_isr_post(esp_event_base_t event_base, int32_t event_id,
void* event_data, size_t event_data_size, BaseType_t* task_unblocked)
{
@ -76,7 +76,7 @@ esp_err_t esp_event_loop_create_default()
}
esp_event_loop_args_t loop_args = {
.queue_size = CONFIG_SYSTEM_EVENT_QUEUE_SIZE,
.queue_size = CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE,
.task_name = "sys_evt",
.task_stack_size = ESP_TASKD_EVENT_STACK,
.task_priority = ESP_TASKD_EVENT_PRIO,

42
components/esp_event/esp_event.c
View File

@ -23,13 +23,13 @@
#include "esp_event_internal.h"
#include "esp_event_private.h"
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
#include "esp_timer.h"
#endif
/* ---------------------------- Definitions --------------------------------- */
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
// LOOP @<address, name> rx:<recieved events no.> dr:<dropped events no.>
#define LOOP_DUMP_FORMAT "LOOP @%p,%s rx:%u dr:%u\n"
// handler @<address> ev:<base, id> inv:<times invoked> time:<runtime>
@ -47,7 +47,7 @@
static const char* TAG = "event";
static const char* esp_event_any_base = "any";
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
static SLIST_HEAD(esp_event_loop_instance_list_t, esp_event_loop_instance) s_event_loops =
SLIST_HEAD_INITIALIZER(s_event_loops);
@ -57,7 +57,7 @@ static portMUX_TYPE s_event_loops_spinlock = portMUX_INITIALIZER_UNLOCKED;
/* ------------------------- Static Functions ------------------------------- */
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
static int esp_event_dump_prepare()
@ -126,18 +126,18 @@ static void handler_execute(esp_event_loop_instance_t* loop, esp_event_handler_i
{
ESP_LOGD(TAG, "running post %s:%d with handler %p on loop %p", post.base, post.id, handler->handler, loop);
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
int64_t start, diff;
start = esp_timer_get_time();
#endif
// Execute the handler
#if CONFIG_POST_EVENTS_FROM_ISR
#if CONFIG_ESP_EVENT_POST_FROM_ISR
(*(handler->handler))(handler->arg, post.base, post.id, post.data_allocd ? post.data.ptr : &post.data.val);
#else
(*(handler->handler))(handler->arg, post.base, post.id, post.data);
#endif
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
diff = esp_timer_get_time() - start;
xSemaphoreTake(loop->profiling_mutex, portMAX_DELAY);
@ -379,7 +379,7 @@ static void loop_node_remove_all_handler(esp_event_loop_node_t* loop_node)
static void inline __attribute__((always_inline)) post_instance_delete(esp_event_post_instance_t* post)
{
#if CONFIG_POST_EVENTS_FROM_ISR
#if CONFIG_ESP_EVENT_POST_FROM_ISR
if (post->data_allocd && post->data.ptr) {
free(post->data.ptr);
}
@ -418,7 +418,7 @@ esp_err_t esp_event_loop_create(const esp_event_loop_args_t* event_loop_args, es
goto on_err;
}
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
loop->profiling_mutex = xSemaphoreCreateMutex();
if (loop->profiling_mutex == NULL) {
ESP_LOGE(TAG, "create event loop profiling mutex failed");
@ -450,7 +450,7 @@ esp_err_t esp_event_loop_create(const esp_event_loop_args_t* event_loop_args, es
loop->running_task = NULL;
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
portENTER_CRITICAL(&s_event_loops_spinlock);
SLIST_INSERT_HEAD(&s_event_loops, loop, next);
portEXIT_CRITICAL(&s_event_loops_spinlock);
@ -471,7 +471,7 @@ on_err:
vSemaphoreDelete(loop->mutex);
}
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
if(loop->profiling_mutex != NULL) {
vSemaphoreDelete(loop->profiling_mutex);
}
@ -582,13 +582,13 @@ esp_err_t esp_event_loop_delete(esp_event_loop_handle_t event_loop)
esp_event_loop_instance_t* loop = (esp_event_loop_instance_t*) event_loop;
SemaphoreHandle_t loop_mutex = loop->mutex;
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
SemaphoreHandle_t loop_profiling_mutex = loop->profiling_mutex;
#endif
xSemaphoreTakeRecursive(loop->mutex, portMAX_DELAY);
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
xSemaphoreTakeRecursive(loop->profiling_mutex, portMAX_DELAY);
portENTER_CRITICAL(&s_event_loops_spinlock);
SLIST_REMOVE(&s_event_loops, loop, esp_event_loop_instance, next);
@ -619,7 +619,7 @@ esp_err_t esp_event_loop_delete(esp_event_loop_handle_t event_loop)
free(loop);
// Free loop mutex before deleting
xSemaphoreGiveRecursive(loop_mutex);
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
xSemaphoreGiveRecursive(loop_profiling_mutex);
vSemaphoreDelete(loop_profiling_mutex);
#endif
@ -751,7 +751,7 @@ esp_err_t esp_event_post_to(esp_event_loop_handle_t event_loop, esp_event_base_t
}
memcpy(event_data_copy, event_data, event_data_size);
#if CONFIG_POST_EVENTS_FROM_ISR
#if CONFIG_ESP_EVENT_POST_FROM_ISR
post.data.ptr = event_data_copy;
post.data_allocd = true;
#else
@ -790,20 +790,20 @@ esp_err_t esp_event_post_to(esp_event_loop_handle_t event_loop, esp_event_base_t
if (result != pdTRUE) {
post_instance_delete(&post);
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
atomic_fetch_add(&loop->events_dropped, 1);
#endif
return ESP_ERR_TIMEOUT;
}
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
atomic_fetch_add(&loop->events_recieved, 1);
#endif
return ESP_OK;
}
#if CONFIG_POST_EVENTS_FROM_ISR
#if CONFIG_ESP_EVENT_POST_FROM_ISR
esp_err_t esp_event_isr_post_to(esp_event_loop_handle_t event_loop, esp_event_base_t event_base, int32_t event_id,
void* event_data, size_t event_data_size, BaseType_t* task_unblocked)
{
@ -837,13 +837,13 @@ esp_err_t esp_event_isr_post_to(esp_event_loop_handle_t event_loop, esp_event_ba
if (result != pdTRUE) {
post_instance_delete(&post);
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
atomic_fetch_add(&loop->events_dropped, 1);
#endif
return ESP_FAIL;
}
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
atomic_fetch_add(&loop->events_recieved, 1);
#endif
@ -853,7 +853,7 @@ esp_err_t esp_event_isr_post_to(esp_event_loop_handle_t event_loop, esp_event_ba
esp_err_t esp_event_dump(FILE* file)
{
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
assert(file);
esp_event_loop_instance_t* loop_it;

14
components/esp_event/include/esp_event.h
View File

@ -270,7 +270,7 @@ esp_err_t esp_event_post_to(esp_event_loop_handle_t event_loop,
size_t event_data_size,
TickType_t ticks_to_wait);
#if CONFIG_POST_EVENTS_FROM_ISR
#if CONFIG_ESP_EVENT_POST_FROM_ISR
/**
* @brief Special variant of esp_event_post for posting events from interrupt handlers.
*
@ -282,9 +282,9 @@ esp_err_t esp_event_post_to(esp_event_loop_handle_t event_loop,
* higher priority than currently running task has been unblocked by the posted event;
* a context switch should be requested before the interrupt is existed.
*
* @note this function is only available when CONFIG_POST_EVENTS_FROM_ISR is enabled
* @note this function is only available when CONFIG_ESP_EVENT_POST_FROM_ISR is enabled
* @note when this function is called from an interrupt handler placed in IRAM, this function should
* be placed in IRAM as well by enabling CONFIG_POST_EVENTS_FROM_IRAM_ISR
* be placed in IRAM as well by enabling CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR
*
* @return
* - ESP_OK: Success
@ -310,9 +310,9 @@ esp_err_t esp_event_isr_post(esp_event_base_t event_base,
* higher priority than currently running task has been unblocked by the posted event;
* a context switch should be requested before the interrupt is existed.
*
* @note this function is only available when CONFIG_POST_EVENTS_FROM_ISR is enabled
* @note this function is only available when CONFIG_ESP_EVENT_POST_FROM_ISR is enabled
* @note when this function is called from an interrupt handler placed in IRAM, this function should
* be placed in IRAM as well by enabling CONFIG_POST_EVENTS_FROM_IRAM_ISR
* be placed in IRAM as well by enabling CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR
*
* @return
* - ESP_OK: Success
@ -366,7 +366,7 @@ esp_err_t esp_event_isr_post_to(esp_event_loop_handle_t event_loop,
*
* @param[in] file the file stream to output to
*
* @note this function is a noop when CONFIG_EVENT_LOOP_PROFILING is disabled
* @note this function is a noop when CONFIG_ESP_EVENT_LOOP_PROFILING is disabled
*
* @return
* - ESP_OK: Success
@ -379,4 +379,4 @@ esp_err_t esp_event_dump(FILE* file);
} // extern "C"
#endif
#endif // #ifndef ESP_EVENT_H_
#endif // #ifndef ESP_EVENT_H_

4
components/esp_event/linker.lf
View File

@ -1,6 +1,6 @@
if POST_EVENTS_FROM_IRAM_ISR = y:
if ESP_EVENT_POST_FROM_IRAM_ISR = y:
[mapping:esp_event]
archive: libesp_event.a
entries:
esp_event:esp_event_isr_post_to (noflash)
default_event_loop:esp_event_isr_post (noflash)
default_event_loop:esp_event_isr_post (noflash)

10
components/esp_event/private_include/esp_event_internal.h
View File

@ -28,7 +28,7 @@ typedef SLIST_HEAD(base_nodes, base_node) base_nodes_t;
typedef struct esp_event_handler_instance {
esp_event_handler_t handler; /**< event handler function*/
void* arg; /**< event handler argument */
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
uint32_t invoked; /**< number of times this handler has been invoked */
int64_t time; /**< total runtime of this handler across all calls */
#endif
@ -77,7 +77,7 @@ typedef struct esp_event_loop_instance {
SemaphoreHandle_t mutex; /**< mutex for updating the events linked list */
esp_event_loop_nodes_t loop_nodes; /**< set of linked lists containing the
registered handlers for the loop */
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
atomic_uint_least32_t events_recieved; /**< number of events successfully posted to the loop */
atomic_uint_least32_t events_dropped; /**< number of events dropped due to queue being full */
SemaphoreHandle_t profiling_mutex; /**< mutex used for profiliing */
@ -85,7 +85,7 @@ typedef struct esp_event_loop_instance {
#endif
} esp_event_loop_instance_t;
#if CONFIG_POST_EVENTS_FROM_ISR
#if CONFIG_ESP_EVENT_POST_FROM_ISR
typedef union esp_event_post_data {
uint32_t val;
void *ptr;
@ -96,7 +96,7 @@ typedef void* esp_event_post_data_t;
/// Event posted to the event queue
typedef struct esp_event_post_instance {
#if CONFIG_POST_EVENTS_FROM_ISR
#if CONFIG_ESP_EVENT_POST_FROM_ISR
bool data_allocd; /**< indicates whether data is alloc'd */
#endif
esp_event_base_t base; /**< the event base */
@ -108,4 +108,4 @@ typedef struct esp_event_post_instance {
} // extern "C"
#endif
#endif // #ifndef ESP_EVENT_INTERNAL_H_
#endif // #ifndef ESP_EVENT_INTERNAL_H_

6
components/esp_event/sdkconfig.rename Normal file
View File

@ -0,0 +1,6 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_EVENT_LOOP_PROFILING CONFIG_ESP_EVENT_LOOP_PROFILING
CONFIG_POST_EVENTS_FROM_ISR CONFIG_ESP_EVENT_POST_FROM_ISR
CONFIG_POST_EVENTS_FROM_IRAM_ISR CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR

32
components/esp_event/test/test_event.c
View File

@ -42,7 +42,7 @@ static const char* TAG = "test_event";
#define TEST_TEARDOWN() \
test_teardown(); \
vTaskDelay(pdMS_TO_TICKS(CONFIG_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER)); \
vTaskDelay(pdMS_TO_TICKS(CONFIG_ESP_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER)); \
TEST_ASSERT_EQUAL(free_mem_before, heap_caps_get_free_size(MALLOC_CAP_DEFAULT));
typedef struct {
@ -118,7 +118,7 @@ static BaseType_t test_event_get_core()
static esp_event_loop_args_t test_event_get_default_loop_args()
{
esp_event_loop_args_t loop_config = {
.queue_size = CONFIG_SYSTEM_EVENT_QUEUE_SIZE,
.queue_size = CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE,
.task_name = "loop",
.task_priority = s_test_priority,
.task_stack_size = 2048,
@ -276,7 +276,7 @@ static void test_teardown()
#define TIMER_SCALE (TIMER_BASE_CLK / TIMER_DIVIDER) // convert counter value to seconds
#define TIMER_INTERVAL0_SEC (2.0) // sample test interval for the first timer
#if CONFIG_POST_EVENTS_FROM_ISR
#if CONFIG_ESP_EVENT_POST_FROM_ISR
static void test_handler_post_from_isr(void* event_handler_arg, esp_event_base_t event_base, int32_t event_id, void* event_data)
{
SemaphoreHandle_t *sem = (SemaphoreHandle_t*) event_handler_arg;
@ -287,7 +287,7 @@ static void test_handler_post_from_isr(void* event_handler_arg, esp_event_base_t
}
#endif
#if CONFIG_POST_EVENTS_FROM_ISR
#if CONFIG_ESP_EVENT_POST_FROM_ISR
void IRAM_ATTR test_event_on_timer_alarm(void* para)
{
/* Retrieve the interrupt status and the counter value
@ -313,7 +313,7 @@ void IRAM_ATTR test_event_on_timer_alarm(void* para)
portYIELD_FROM_ISR();
}
}
#endif //CONFIG_POST_EVENTS_FROM_ISR
#endif //CONFIG_ESP_EVENT_POST_FROM_ISR
TEST_CASE("can create and delete event loops", "[event]")
{
@ -850,17 +850,17 @@ static void performance_test(bool dedicated_task)
TEST_TEARDOWN();
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
ESP_LOGI(TAG, "events dispatched/second with profiling enabled: %d", average);
// Enabling profiling will slow down event dispatch, so the set threshold
// is not valid when it is enabled.
#else
#ifndef CONFIG_SPIRAM_SUPPORT
#ifndef CONFIG_ESP32_SPIRAM_SUPPORT
TEST_PERFORMANCE_GREATER_THAN(EVENT_DISPATCH, "%d", average);
#else
TEST_PERFORMANCE_GREATER_THAN(EVENT_DISPATCH_PSRAM, "%d", average);
#endif // CONFIG_SPIRAM_SUPPORT
#endif // CONFIG_EVENT_LOOP_PROFILING
#endif // CONFIG_ESP32_SPIRAM_SUPPORT
#endif // CONFIG_ESP_EVENT_LOOP_PROFILING
}
TEST_CASE("performance test - dedicated task", "[event]")
@ -912,11 +912,11 @@ TEST_CASE("can post to loop from handler - dedicated task", "[event]")
}
TEST_ASSERT_EQUAL(ESP_ERR_TIMEOUT, esp_event_post_to(loop_w_task, s_test_base1, TEST_EVENT_BASE1_EV2, NULL, 0,
pdMS_TO_TICKS(CONFIG_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER)));
pdMS_TO_TICKS(CONFIG_ESP_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER)));
xSemaphoreGive(arg.mutex);
vTaskDelay(pdMS_TO_TICKS(CONFIG_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER));
vTaskDelay(pdMS_TO_TICKS(CONFIG_ESP_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER));
TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_delete(loop_w_task));
@ -964,15 +964,15 @@ TEST_CASE("can post to loop from handler - no dedicated task", "[event]")
TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop_wo_task, s_test_base1, TEST_EVENT_BASE1_EV1, &loop_wo_task, sizeof(&loop_wo_task), portMAX_DELAY));
vTaskDelay(pdMS_TO_TICKS(CONFIG_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER));
vTaskDelay(pdMS_TO_TICKS(CONFIG_ESP_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER));
// For loop without tasks, posting is more restrictive. Posting should wait until execution of handler finishes
TEST_ASSERT_EQUAL(ESP_ERR_TIMEOUT, esp_event_post_to(loop_wo_task, s_test_base1, TEST_EVENT_BASE1_EV2, NULL, 0,
pdMS_TO_TICKS(CONFIG_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER)));
pdMS_TO_TICKS(CONFIG_ESP_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER)));
xSemaphoreGive(arg.mutex);
vTaskDelay(pdMS_TO_TICKS(CONFIG_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER));
vTaskDelay(pdMS_TO_TICKS(CONFIG_ESP_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER));
vTaskDelete(mtask);
@ -1148,7 +1148,7 @@ TEST_CASE("events are dispatched in the order they are registered", "[event]")
TEST_TEARDOWN();
}
#if CONFIG_POST_EVENTS_FROM_ISR
#if CONFIG_ESP_EVENT_POST_FROM_ISR
TEST_CASE("can post events from interrupt handler", "[event]")
{
SemaphoreHandle_t sem = xSemaphoreCreateBinary();
@ -1186,7 +1186,7 @@ TEST_CASE("can post events from interrupt handler", "[event]")
}
#endif
#ifdef CONFIG_EVENT_LOOP_PROFILING
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
TEST_CASE("can dump event loop profile", "[event]")
{
/* this test aims to verify that dumping event loop statistics succeed */

6
components/esp_wifi/CMakeLists.txt
View File

@ -11,14 +11,14 @@ set(COMPONENT_PRIV_INCLUDEDIRS)
set(COMPONENT_REQUIRES)
set(COMPONENT_PRIV_REQUIRES "wpa_supplicant" "nvs_flash")
if(NOT CONFIG_NO_BLOBS)
if(NOT CONFIG_ESP32_NO_BLOBS)
set(COMPONENT_ADD_LDFRAGMENTS "linker.lf")
endif()
register_component()
target_link_libraries(${COMPONENT_LIB} "-L ${CMAKE_CURRENT_SOURCE_DIR}/lib_${IDF_TARGET}")
if(NOT CONFIG_NO_BLOBS)
if(NOT CONFIG_ESP32_NO_BLOBS)
target_link_libraries(${COMPONENT_LIB} "-L ${CMAKE_CURRENT_SOURCE_DIR}/lib_${IDF_TARGET}")
target_link_libraries(${COMPONENT_LIB} coexist core espnow mesh net80211 phy pp rtc smartconfig wpa2 wpa wps)
endif()
@ -43,4 +43,4 @@ if(CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION)
add_dependencies(app phy_init_data)
esptool_py_flash_project_args(phy ${phy_partition_offset} ${phy_init_data_bin} FLASH_IN_PROJECT)
endif()
endif()

40
components/esp_wifi/Kconfig
View File

@ -1,7 +1,7 @@
menu Wi-Fi
config SW_COEXIST_ENABLE
config ESP32_WIFI_SW_COEXIST_ENABLE
bool "Software controls WiFi/Bluetooth coexistence"
depends on BT_ENABLED
default y
@ -12,10 +12,10 @@ menu Wi-Fi
If only Bluetooth is used, it is recommended to disable this option to reduce binary file
size.
choice SW_COEXIST_PREFERENCE
choice ESP32_WIFI_SW_COEXIST_PREFERENCE
prompt "WiFi/Bluetooth coexistence performance preference"
depends on SW_COEXIST_ENABLE
default SW_COEXIST_PREFERENCE_BALANCE
depends on ESP32_WIFI_SW_COEXIST_ENABLE
default ESP32_WIFI_SW_COEXIST_PREFERENCE_BALANCE
help
Choose Bluetooth/WiFi/Balance for different preference.
If choose WiFi, it will make WiFi performance better. Such, keep WiFi Audio more fluent.
@ -25,30 +25,30 @@ menu Wi-Fi
choose balance, the A2DP audio can play fluently, too.
Except config preference in menuconfig, you can also call esp_coex_preference_set() dynamically.
config SW_COEXIST_PREFERENCE_WIFI
config ESP32_WIFI_SW_COEXIST_PREFERENCE_WIFI
bool "WiFi"
config SW_COEXIST_PREFERENCE_BT
config ESP32_WIFI_SW_COEXIST_PREFERENCE_BT
bool "Bluetooth(include BR/EDR and BLE)"
config SW_COEXIST_PREFERENCE_BALANCE
config ESP32_WIFI_SW_COEXIST_PREFERENCE_BALANCE
bool "Balance"
endchoice
config SW_COEXIST_PREFERENCE_VALUE
config ESP32_WIFI_SW_COEXIST_PREFERENCE_VALUE
int
depends on SW_COEXIST_ENABLE
default 0 if SW_COEXIST_PREFERENCE_WIFI
default 1 if SW_COEXIST_PREFERENCE_BT
default 2 if SW_COEXIST_PREFERENCE_BALANCE
depends on ESP32_WIFI_SW_COEXIST_ENABLE
default 0 if ESP32_WIFI_SW_COEXIST_PREFERENCE_WIFI
default 1 if ESP32_WIFI_SW_COEXIST_PREFERENCE_BT
default 2 if ESP32_WIFI_SW_COEXIST_PREFERENCE_BALANCE
config ESP32_WIFI_STATIC_RX_BUFFER_NUM
int "Max number of WiFi static RX buffers"
range 2 25 if !WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
range 8 25 if WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
default 10 if !WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
default 16 if WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
range 2 25 if !SPIRAM_TRY_ALLOCATE_WIFI_LWIP
range 8 25 if SPIRAM_TRY_ALLOCATE_WIFI_LWIP
default 10 if !SPIRAM_TRY_ALLOCATE_WIFI_LWIP
default 16 if SPIRAM_TRY_ALLOCATE_WIFI_LWIP
help
Set the number of WiFi static RX buffers. Each buffer takes approximately 1.6KB of RAM.
The static rx buffers are allocated when esp_wifi_init is called, they are not freed
@ -170,10 +170,10 @@ menu Wi-Fi
config ESP32_WIFI_RX_BA_WIN
int "WiFi AMPDU RX BA window size"
depends on ESP32_WIFI_AMPDU_RX_ENABLED
range 2 32 if !WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
range 16 32 if WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
default 6 if !WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
default 16 if WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
range 2 32 if !SPIRAM_TRY_ALLOCATE_WIFI_LWIP
range 16 32 if SPIRAM_TRY_ALLOCATE_WIFI_LWIP
default 6 if !SPIRAM_TRY_ALLOCATE_WIFI_LWIP
default 16 if SPIRAM_TRY_ALLOCATE_WIFI_LWIP
help
Set the size of WiFi Block Ack RX window. Generally a bigger value means higher throughput and better
compatibility but more memory. Most of time we should NOT change the default value unless special

2
components/esp_wifi/component.mk
View File

@ -5,7 +5,7 @@
COMPONENT_ADD_INCLUDEDIRS := include
COMPONENT_SRCDIRS := src
ifndef CONFIG_NO_BLOBS
ifndef CONFIG_ESP32_NO_BLOBS
LIBS := core rtc net80211 pp wpa smartconfig coexist wps wpa2 espnow phy mesh
COMPONENT_ADD_LDFLAGS += -L$(COMPONENT_PATH)/lib_$(IDF_TARGET) \
$(addprefix -l,$(LIBS))

9
components/esp_wifi/sdkconfig.rename Normal file
View File

@ -0,0 +1,9 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_SW_COEXIST_ENABLE CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE
CONFIG_SW_COEXIST_PREFERENCE CONFIG_ESP32_WIFI_SW_COEXIST_PREFERENCE
CONFIG_SW_COEXIST_PREFERENCE_WIFI CONFIG_ESP32_WIFI_SW_COEXIST_PREFERENCE_WIFI
CONFIG_SW_COEXIST_PREFERENCE_BT CONFIG_ESP32_WIFI_SW_COEXIST_PREFERENCE_BT
CONFIG_SW_COEXIST_PREFERENCE_BALANCE CONFIG_ESP32_WIFI_SW_COEXIST_PREFERENCE_BALANCE
CONFIG_SW_COEXIST_PREFERENCE_VALUE CONFIG_ESP32_WIFI_SW_COEXIST_PREFERENCE_VALUE

20
components/esp_wifi/src/phy_init.c
View File

@ -165,12 +165,12 @@ esp_err_t esp_phy_rf_init(const esp_phy_init_data_t* init_data, esp_phy_calibrat
}
}
#if CONFIG_SW_COEXIST_ENABLE
#if CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE
if ((module == PHY_BT_MODULE) || (module == PHY_WIFI_MODULE)){
uint32_t phy_bt_wifi_mask = BIT(PHY_BT_MODULE) | BIT(PHY_WIFI_MODULE);
if ((s_module_phy_rf_init & phy_bt_wifi_mask) == phy_bt_wifi_mask) { //both wifi & bt enabled
coex_init();
coex_preference_set(CONFIG_SW_COEXIST_PREFERENCE_VALUE);
coex_preference_set(CONFIG_ESP32_WIFI_SW_COEXIST_PREFERENCE_VALUE);
coex_resume();
}
}
@ -197,7 +197,7 @@ esp_err_t esp_phy_rf_deinit(phy_rf_module_t module)
s_module_phy_rf_init &= ~BIT(module);
esp_err_t status = ESP_OK;
#if CONFIG_SW_COEXIST_ENABLE
#if CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE
if ((module == PHY_BT_MODULE) || (module == PHY_WIFI_MODULE)){
if (is_both_wifi_bt_enabled == true) {
coex_deinit();
@ -246,7 +246,7 @@ esp_err_t esp_phy_rf_deinit(phy_rf_module_t module)
esp_err_t esp_modem_sleep_enter(modem_sleep_module_t module)
{
#if CONFIG_SW_COEXIST_ENABLE
#if CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE
uint32_t phy_bt_wifi_mask = BIT(PHY_BT_MODULE) | BIT(PHY_WIFI_MODULE);
#endif
@ -262,7 +262,7 @@ esp_err_t esp_modem_sleep_enter(modem_sleep_module_t module)
else {
_lock_acquire(&s_modem_sleep_lock);
s_modem_sleep_module_enter |= BIT(module);
#if CONFIG_SW_COEXIST_ENABLE
#if CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE
_lock_acquire(&s_phy_rf_init_lock);
if (((s_module_phy_rf_init & phy_bt_wifi_mask) == phy_bt_wifi_mask) //both wifi & bt enabled
&& (s_modem_sleep_module_enter & (MODEM_BT_MASK | MODEM_WIFI_MASK)) != 0){
@ -283,7 +283,7 @@ esp_err_t esp_modem_sleep_enter(modem_sleep_module_t module)
esp_err_t esp_modem_sleep_exit(modem_sleep_module_t module)
{
#if CONFIG_SW_COEXIST_ENABLE
#if CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE
uint32_t phy_bt_wifi_mask = BIT(PHY_BT_MODULE) | BIT(PHY_WIFI_MODULE);
#endif
@ -305,7 +305,7 @@ esp_err_t esp_modem_sleep_exit(modem_sleep_module_t module)
s_is_modem_sleep_en = false;
}
}
#if CONFIG_SW_COEXIST_ENABLE
#if CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE
_lock_acquire(&s_phy_rf_init_lock);
if (((s_module_phy_rf_init & phy_bt_wifi_mask) == phy_bt_wifi_mask) //both wifi & bt enabled
&& (s_modem_sleep_module_enter & (MODEM_BT_MASK | MODEM_WIFI_MASK)) == 0){
@ -582,7 +582,7 @@ static esp_err_t store_cal_data_to_nvs_handle(nvs_handle handle,
return err;
}
#if CONFIG_REDUCE_PHY_TX_POWER
#if CONFIG_ESP32_REDUCE_PHY_TX_POWER
static void esp_phy_reduce_tx_power(esp_phy_init_data_t* init_data)
{
uint8_t i;
@ -603,7 +603,7 @@ void esp_phy_load_cal_and_init(phy_rf_module_t module)
abort();
}
#if CONFIG_REDUCE_PHY_TX_POWER
#if CONFIG_ESP32_REDUCE_PHY_TX_POWER
const esp_phy_init_data_t* phy_init_data = esp_phy_get_init_data();
if (phy_init_data == NULL) {
ESP_LOGE(TAG, "failed to obtain PHY init data");
@ -653,7 +653,7 @@ void esp_phy_load_cal_and_init(phy_rf_module_t module)
esp_phy_rf_init(init_data, PHY_RF_CAL_FULL, cal_data, module);
#endif
#if CONFIG_REDUCE_PHY_TX_POWER
#if CONFIG_ESP32_REDUCE_PHY_TX_POWER
esp_phy_release_init_data(phy_init_data);
free(init_data);
#else

58
components/esptool_py/Kconfig.projbuild
View File

@ -54,20 +54,20 @@ menu "Serial flasher config"
decompress it on the fly before flashing it. For most payloads, this should result in a
speed increase.
choice FLASHMODE
choice ESPTOOLPY_FLASHMODE
prompt "Flash SPI mode"
default FLASHMODE_DIO
default ESPTOOLPY_FLASHMODE_DIO
help
Mode the flash chip is flashed in, as well as the default mode for the
binary to run in.
config FLASHMODE_QIO
config ESPTOOLPY_FLASHMODE_QIO
bool "QIO"
config FLASHMODE_QOUT
config ESPTOOLPY_FLASHMODE_QOUT
bool "QOUT"
config FLASHMODE_DIO
config ESPTOOLPY_FLASHMODE_DIO
bool "DIO"
config FLASHMODE_DOUT
config ESPTOOLPY_FLASHMODE_DOUT
bool "DOUT"
endchoice
@ -76,10 +76,10 @@ menu "Serial flasher config"
# itself to quad mode during initialisation
config ESPTOOLPY_FLASHMODE
string
default "dio" if FLASHMODE_QIO
default "dio" if FLASHMODE_QOUT
default "dio" if FLASHMODE_DIO
default "dout" if FLASHMODE_DOUT
default "dio" if ESPTOOLPY_FLASHMODE_QIO
default "dio" if ESPTOOLPY_FLASHMODE_QOUT
default "dio" if ESPTOOLPY_FLASHMODE_DIO
default "dout" if ESPTOOLPY_FLASHMODE_DOUT
choice ESPTOOLPY_FLASHFREQ
prompt "Flash SPI speed"
@ -180,44 +180,44 @@ menu "Serial flasher config"
default "hard_reset" if ESPTOOLPY_AFTER_RESET
default "no_reset" if ESPTOOLPY_AFTER_NORESET
choice MONITOR_BAUD
choice ESPTOOLPY_MONITOR_BAUD
prompt "'make monitor' baud rate"
default MONITOR_BAUD_115200B
default ESPTOOLPY_MONITOR_BAUD_115200B
help
Baud rate to use when running 'make monitor' to view serial output
from a running chip.
Can override by setting the MONITORBAUD environment variable.
config MONITOR_BAUD_9600B
config ESPTOOLPY_MONITOR_BAUD_9600B
bool "9600 bps"
config MONITOR_BAUD_57600B
config ESPTOOLPY_MONITOR_BAUD_57600B
bool "57600 bps"
config MONITOR_BAUD_115200B
config ESPTOOLPY_MONITOR_BAUD_115200B
bool "115200 bps"
config MONITOR_BAUD_230400B
config ESPTOOLPY_MONITOR_BAUD_230400B
bool "230400 bps"
config MONITOR_BAUD_921600B
config ESPTOOLPY_MONITOR_BAUD_921600B
bool "921600 bps"
config MONITOR_BAUD_2MB
config ESPTOOLPY_MONITOR_BAUD_2MB
bool "2 Mbps"
config MONITOR_BAUD_OTHER
config ESPTOOLPY_MONITOR_BAUD_OTHER
bool "Custom baud rate"
endchoice
config MONITOR_BAUD_OTHER_VAL
int "Custom baud rate value" if MONITOR_BAUD_OTHER
config ESPTOOLPY_MONITOR_BAUD_OTHER_VAL
int "Custom baud rate value" if ESPTOOLPY_MONITOR_BAUD_OTHER
default 115200
config MONITOR_BAUD
config ESPTOOLPY_MONITOR_BAUD
int
default 9600 if MONITOR_BAUD_9600B
default 57600 if MONITOR_BAUD_57600B
default 115200 if MONITOR_BAUD_115200B
default 230400 if MONITOR_BAUD_230400B
default 921600 if MONITOR_BAUD_921600B
default 2000000 if MONITOR_BAUD_2MB
default MONITOR_BAUD_OTHER_VAL if MONITOR_BAUD_OTHER
default 9600 if ESPTOOLPY_MONITOR_BAUD_9600B
default 57600 if ESPTOOLPY_MONITOR_BAUD_57600B
default 115200 if ESPTOOLPY_MONITOR_BAUD_115200B
default 230400 if ESPTOOLPY_MONITOR_BAUD_230400B
default 921600 if ESPTOOLPY_MONITOR_BAUD_921600B
default 2000000 if ESPTOOLPY_MONITOR_BAUD_2MB
default ESPTOOLPY_MONITOR_BAUD_OTHER_VAL if ESPTOOLPY_MONITOR_BAUD_OTHER
endmenu

2
components/esptool_py/Makefile.projbuild
View File

@ -81,7 +81,7 @@ erase_flash: | check_python_dependencies
@echo "Erasing entire flash..."
$(ESPTOOLPY_SERIAL) erase_flash
MONITORBAUD ?= $(CONFIG_MONITOR_BAUD)
MONITORBAUD ?= $(CONFIG_ESPTOOLPY_MONITOR_BAUD)
MONITOR_PYTHON := $(PYTHON)

4
components/esptool_py/project_include.cmake
View File

@ -13,7 +13,7 @@ set(ESPFLASHSIZE ${CONFIG_ESPTOOLPY_FLASHSIZE})
set(ESPTOOLPY_BEFORE "${CONFIG_ESPTOOLPY_BEFORE}")
set(ESPTOOLPY_AFTER "${CONFIG_ESPTOOLPY_AFTER}")
if(CONFIG_SECURE_BOOT_ENABLED OR CONFIG_FLASH_ENCRYPTION_ENABLED)
if(CONFIG_SECURE_BOOT_ENABLED OR CONFIG_SECURE_FLASH_ENC_ENABLED)
# If security enabled then override post flash option
set(ESPTOOLPY_AFTER "no_reset")
endif()
@ -191,4 +191,4 @@ function(esptool_py_flash_project_args entry offset image)
list(APPEND flash_project_args_json "\"${offset}\" : \"${image}\"")
set_property(TARGET flash_project_args_target PROPERTY FLASH_PROJECT_ARGS_JSON "${flash_project_args_json}")
endif()
endfunction()
endfunction()

17
components/esptool_py/sdkconfig.rename Normal file
View File

@ -0,0 +1,17 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_FLASHMODE_QIO CONFIG_ESPTOOLPY_FLASHMODE_QIO
CONFIG_FLASHMODE_QOUT CONFIG_ESPTOOLPY_FLASHMODE_QOUT
CONFIG_FLASHMODE_DIO CONFIG_ESPTOOLPY_FLASHMODE_DIO
CONFIG_FLASHMODE_DOUT CONFIG_ESPTOOLPY_FLASHMODE_DOUT
CONFIG_MONITOR_BAUD CONFIG_ESPTOOLPY_MONITOR_BAUD
CONFIG_MONITOR_BAUD_9600B CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B
CONFIG_MONITOR_BAUD_57600B CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B
CONFIG_MONITOR_BAUD_115200B CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B
CONFIG_MONITOR_BAUD_230400B CONFIG_ESPTOOLPY_MONITOR_BAUD_230400B
CONFIG_MONITOR_BAUD_921600B CONFIG_ESPTOOLPY_MONITOR_BAUD_921600B
CONFIG_MONITOR_BAUD_2MB CONFIG_ESPTOOLPY_MONITOR_BAUD_2MB
CONFIG_MONITOR_BAUD_OTHER CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER
CONFIG_MONITOR_BAUD_OTHER_VAL CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL

12
components/ethernet/Kconfig
View File

@ -1,6 +1,6 @@
menu Ethernet
config DMA_RX_BUF_NUM
config ETH_DMA_RX_BUF_NUM
int "Number of DMA RX buffers"
range 3 20
default 10
@ -10,7 +10,7 @@ menu Ethernet
More buffers will increase throughput.
If flow ctrl is enabled, make sure this number is larger than 9.
config DMA_TX_BUF_NUM
config ETH_DMA_TX_BUF_NUM
int "Number of DMA TX buffers"
range 3 20
default 10
@ -19,7 +19,7 @@ menu Ethernet
These buffers are allocated dynamically.
More buffers will increase throughput.
config EMAC_L2_TO_L3_RX_BUF_MODE
config ETH_EMAC_L2_TO_L3_RX_BUF_MODE
bool "Enable received buffers be copied to Layer3 from Layer2"
default y
help
@ -30,7 +30,7 @@ menu Ethernet
If this option is not selected, IP layer only uses the pointers to the DMA buffers owned by Ethernet MAC.
When Ethernet MAC doesn't have any available buffers left, it will drop the incoming packets.
config EMAC_CHECK_LINK_PERIOD_MS
config ETH_CHECK_LINK_STATUS_PERIOD_MS
int "Period (ms) of checking Ethernet linkup status"
range 1000 5000
default 2000
@ -38,14 +38,14 @@ menu Ethernet
The emac driver uses an internal timer to check the Ethernet linkup status.
Here you should choose a valid interval time.
config EMAC_TASK_PRIORITY
config ETH_EMAC_TASK_PRIORITY
int "EMAC_TASK_PRIORITY"
default 20
range 3 22
help
Priority of Ethernet MAC task.
config EMAC_TASK_STACK_SIZE
config ETH_EMAC_TASK_STACK_SIZE
int "Stack Size of EMAC Task"
default 3072
range 2000 8000

8
components/ethernet/emac_common.h
View File

@ -102,10 +102,10 @@ struct emac_close_cmd {
int8_t err;
};
#define DMA_RX_BUF_NUM CONFIG_DMA_RX_BUF_NUM
#define DMA_TX_BUF_NUM CONFIG_DMA_TX_BUF_NUM
#define EMAC_TASK_PRIORITY CONFIG_EMAC_TASK_PRIORITY
#define EMAC_TASK_STACK_SIZE CONFIG_EMAC_TASK_STACK_SIZE
#define DMA_RX_BUF_NUM CONFIG_ETH_DMA_RX_BUF_NUM
#define DMA_TX_BUF_NUM CONFIG_ETH_DMA_TX_BUF_NUM
#define EMAC_TASK_PRIORITY CONFIG_ETH_EMAC_TASK_PRIORITY
#define EMAC_TASK_STACK_SIZE CONFIG_ETH_EMAC_TASK_STACK_SIZE
#define DMA_RX_BUF_SIZE 1600
#define DMA_TX_BUF_SIZE 1600

8
components/ethernet/emac_main.c
View File

@ -467,7 +467,7 @@ static uint32_t IRAM_ATTR emac_get_rxbuf_count_in_intr(void)
return cnt;
}
#if CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE
#if CONFIG_ETH_EMAC_L2_TO_L3_RX_BUF_MODE
static void emac_process_rx(void)
{
if (emac_config.emac_status == EMAC_RUNTIME_STOP) {
@ -649,7 +649,7 @@ static void emac_check_phy_init(void)
} else {
REG_CLR_BIT(EMAC_GMACCONFIG_REG, EMAC_EMACFESPEED);
}
#if CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE
#if CONFIG_ETH_EMAC_L2_TO_L3_RX_BUF_MODE
emac_disable_flowctrl();
emac_config.emac_flow_ctrl_partner_support = false;
#else
@ -768,7 +768,7 @@ void emac_link_check_func(void *pv_parameters)
static bool emac_link_check_timer_init(void)
{
emac_timer = xTimerCreate("emac_timer",
(CONFIG_EMAC_CHECK_LINK_PERIOD_MS / portTICK_PERIOD_MS),
(CONFIG_ETH_CHECK_LINK_STATUS_PERIOD_MS / portTICK_PERIOD_MS),
pdTRUE,
NULL,
emac_link_check_func);
@ -1116,7 +1116,7 @@ esp_err_t esp_eth_init_internal(eth_config_t *config)
periph_module_enable(PERIPH_EMAC_MODULE);
if (emac_config.clock_mode != ETH_CLOCK_GPIO0_IN) {
#if CONFIG_SPIRAM_SUPPORT
#if CONFIG_ESP32_SPIRAM_SUPPORT
if (esp_spiram_is_initialized()) {
ESP_LOGE(TAG, "GPIO16 and GPIO17 has been occupied by PSRAM, Only ETH_CLOCK_GPIO_IN is supported!");
ret = ESP_FAIL;

9
components/ethernet/sdkconfig.rename Normal file
View File

@ -0,0 +1,9 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_DMA_RX_BUF_NUM CONFIG_ETH_DMA_RX_BUF_NUM
CONFIG_DMA_TX_BUF_NUM CONFIG_ETH_DMA_TX_BUF_NUM
CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE CONFIG_ETH_EMAC_L2_TO_L3_RX_BUF_MODE
CONFIG_EMAC_CHECK_LINK_PERIOD_MS CONFIG_ETH_CHECK_LINK_STATUS_PERIOD_MS
CONFIG_EMAC_TASK_PRIORITY CONFIG_ETH_EMAC_TASK_PRIORITY
CONFIG_EMAC_TASK_STACK_SIZE CONFIG_ETH_EMAC_TASK_STACK_SIZE

34
components/freemodbus/Kconfig
View File

@ -1,6 +1,6 @@
menu "Modbus configuration"
config MB_MASTER_TIMEOUT_MS_RESPOND
config FMB_MASTER_TIMEOUT_MS_RESPOND
int "Slave respond timeout (Milliseconds)"
default 150
range 50 400
@ -9,7 +9,7 @@ menu "Modbus configuration"
If master sends a frame which is not broadcast, it has to wait sometime for slave response.
if slave is not respond in this time, the master will process timeout error.
config MB_MASTER_DELAY_MS_CONVERT
config FMB_MASTER_DELAY_MS_CONVERT
int "Slave conversion delay (Milliseconds)"
default 200
range 50 400
@ -18,7 +18,7 @@ menu "Modbus configuration"
If master sends a broadcast frame, it has to wait conversion time to delay,
then master can send next frame.
config MB_QUEUE_LENGTH
config FMB_QUEUE_LENGTH
int "Modbus serial task queue length"
range 0 200
default 20
@ -26,7 +26,7 @@ menu "Modbus configuration"
Modbus serial driver queue length. It is used by event queue task.
See the serial driver API for more information.
config MB_SERIAL_TASK_STACK_SIZE
config FMB_SERIAL_TASK_STACK_SIZE
int "Modbus serial task stack size"
range 768 8192
default 2048
@ -34,7 +34,7 @@ menu "Modbus configuration"
Modbus serial task stack size for event queue task.
It may be adjusted when debugging is enabled (for example).
config MB_SERIAL_BUF_SIZE
config FMB_SERIAL_BUF_SIZE
int "Modbus serial task RX/TX buffer size"
range 0 2048
default 256
@ -43,33 +43,33 @@ menu "Modbus configuration"
This buffer is used for modbus frame transfer. The Modbus protocol maximum
frame size is 256 bytes. Bigger size can be used for non standard implementations.
config MB_SERIAL_TASK_PRIO
config FMB_SERIAL_TASK_PRIO
int "Modbus serial task priority"
range 3 10
default 10
help
Modbus UART driver event task priority.
The priority of Modbus controller task is equal to (CONFIG_MB_SERIAL_TASK_PRIO - 1).
The priority of Modbus controller task is equal to (CONFIG_FMB_SERIAL_TASK_PRIO - 1).
config MB_CONTROLLER_SLAVE_ID_SUPPORT
config FMB_CONTROLLER_SLAVE_ID_SUPPORT
bool "Modbus controller slave ID support"
default n
help
Modbus slave ID support enable.
When enabled the Modbus <Report Slave ID> command is supported by stack.
config MB_CONTROLLER_SLAVE_ID
config FMB_CONTROLLER_SLAVE_ID
hex "Modbus controller slave ID"
range 0 4294967295
default 0x00112233
depends on MB_CONTROLLER_SLAVE_ID_SUPPORT
depends on FMB_CONTROLLER_SLAVE_ID_SUPPORT
help
Modbus slave ID value to identify modbus device
in the network using <Report Slave ID> command.
Most significant byte of ID is used as short device ID and
other three bytes used as long ID.
config MB_CONTROLLER_NOTIFY_TIMEOUT
config FMB_CONTROLLER_NOTIFY_TIMEOUT
int "Modbus controller notification timeout (ms)"
range 0 200
default 20
@ -77,7 +77,7 @@ menu "Modbus configuration"
Modbus controller notification timeout in milliseconds.
This timeout is used to send notification about accessed parameters.
config MB_CONTROLLER_NOTIFY_QUEUE_SIZE
config FMB_CONTROLLER_NOTIFY_QUEUE_SIZE
int "Modbus controller notification queue size"
range 0 200
default 20
@ -85,7 +85,7 @@ menu "Modbus configuration"
Modbus controller notification queue size.
The notification queue is used to get information about accessed parameters.
config MB_CONTROLLER_STACK_SIZE
config FMB_CONTROLLER_STACK_SIZE
int "Modbus controller stack size"
range 0 8192
default 4096
@ -93,7 +93,7 @@ menu "Modbus configuration"
Modbus controller task stack size. The Stack size may be adjusted when
debug mode is used which requires more stack size (for example).
config MB_EVENT_QUEUE_TIMEOUT
config FMB_EVENT_QUEUE_TIMEOUT
int "Modbus stack event queue timeout (ms)"
range 0 500
default 20
@ -101,21 +101,21 @@ menu "Modbus configuration"
Modbus stack event queue timeout in milliseconds. This may help to optimize
Modbus stack event processing time.
config MB_TIMER_PORT_ENABLED
config FMB_TIMER_PORT_ENABLED
bool "Modbus slave stack use timer for 3.5T symbol time measurement"
default y
help
If this option is set the Modbus stack uses timer for T3.5 time measurement.
Else the internal UART TOUT timeout is used for 3.5T symbol time measurement.
config MB_TIMER_GROUP
config FMB_TIMER_GROUP
int "Modbus Timer group number"
range 0 1
default 0
help
Modbus Timer group number that is used for timeout measurement.
config MB_TIMER_INDEX
config FMB_TIMER_INDEX
int "Modbus Timer index in the group"
range 0 1
default 0

8
components/freemodbus/common/esp_modbus_slave.c
View File

@ -21,14 +21,14 @@
#include "esp_modbus_callbacks.h" // for modbus callbacks function pointers declaration
#include "mbc_serial_slave.h" // for create function of serial port
#ifdef CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT
#ifdef CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT
#define MB_ID_BYTE0(id) ((uint8_t)(id))
#define MB_ID_BYTE1(id) ((uint8_t)(((uint16_t)(id) >> 8) & 0xFF))
#define MB_ID_BYTE2(id) ((uint8_t)(((uint32_t)(id) >> 16) & 0xFF))
#define MB_ID_BYTE3(id) ((uint8_t)(((uint32_t)(id) >> 24) & 0xFF))
#define MB_CONTROLLER_SLAVE_ID (CONFIG_MB_CONTROLLER_SLAVE_ID)
#define MB_CONTROLLER_SLAVE_ID (CONFIG_FMB_CONTROLLER_SLAVE_ID)
#define MB_SLAVE_ID_SHORT (MB_ID_BYTE3(MB_CONTROLLER_SLAVE_ID))
// Slave ID constant
@ -127,7 +127,7 @@ esp_err_t mbc_slave_start()
MB_SLAVE_CHECK((slave_interface_ptr->start != NULL),
ESP_ERR_INVALID_STATE,
"Slave interface is not correctly initialized.");
#ifdef CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT
#ifdef CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT
// Set the slave ID if the KConfig option is selected
eMBErrorCode status = eMBSetSlaveID(MB_SLAVE_ID_SHORT, TRUE, (UCHAR*)mb_slave_id, sizeof(mb_slave_id));
MB_SLAVE_CHECK((status == MB_ENOERR), ESP_ERR_INVALID_STATE, "mb stack set slave ID failure.");
@ -252,4 +252,4 @@ eMBErrorCode eMBRegInputCB(UCHAR * pucRegBuffer, USHORT usAddress,
"Slave interface is not correctly initialized.");
error = slave_interface_ptr->slave_reg_cb_input(pucRegBuffer, usAddress, usNRegs);
return error;
}
}

4
components/freemodbus/common/include/esp_modbus_common.h
View File

@ -18,8 +18,8 @@
#include "driver/uart.h" // for UART types
#define MB_CONTROLLER_STACK_SIZE (CONFIG_MB_CONTROLLER_STACK_SIZE) // Stack size for Modbus controller
#define MB_CONTROLLER_PRIORITY (CONFIG_MB_SERIAL_TASK_PRIO - 1) // priority of MB controller task
#define MB_CONTROLLER_STACK_SIZE (CONFIG_FMB_CONTROLLER_STACK_SIZE) // Stack size for Modbus controller
#define MB_CONTROLLER_PRIORITY (CONFIG_FMB_SERIAL_TASK_PRIO - 1) // priority of MB controller task
// Default port defines
#define MB_DEVICE_ADDRESS (1) // Default slave device address in Modbus

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