mirror of
https://github.com/espressif/esp-idf.git
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feat(bluetooth/controller): adopting new HCI layer code and support UHCI function on ESP32-C6 and ESP32-H2
This commit is contained in:
zwl
Zhao Wei Liang
parent
1390711c27
commit
e761c1de8f
@ -2,19 +2,37 @@
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menu "HCI Config"
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choice BT_LE_HCI_INTERFACE
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prompt "Select HCI interface"
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prompt "HCI mode"
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default BT_LE_HCI_INTERFACE_USE_RAM
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config BT_LE_HCI_INTERFACE_USE_RAM
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bool "ram"
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bool "VHCI"
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help
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Use RAM as HCI interface
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config BT_LE_HCI_INTERFACE_USE_UART
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bool "uart"
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bool "UART(H4)"
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help
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Use UART as HCI interface
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endchoice
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choice BT_LE_UART_HCI_MODE_CHOICE
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prompt "UART HCI mode"
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depends on BT_LE_HCI_INTERFACE_USE_UART
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default BT_LE_UART_HCI_NO_DMA_MODE
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help
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Specify UART HCI mode: DMA or No DMA
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config BT_LE_UART_HCI_DMA_MODE
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bool "UHCI(UART with DMA)(EXPERIMENTAL)"
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help
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UART HCI Mode with DMA functionality.
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config BT_LE_UART_HCI_NO_DMA_MODE
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bool "UART(NO DMA)"
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help
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UART HCI Mode without DMA functionality.
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endchoice
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config BT_LE_HCI_UART_PORT
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int "HCI UART port"
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depends on BT_LE_HCI_INTERFACE_USE_UART
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@ -73,12 +91,40 @@ menu "HCI Config"
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UART_PARITY_ODD
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endchoice
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config BT_LE_HCI_UART_TASK_STACK_SIZE
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int "HCI uart task stack size"
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depends on BT_LE_HCI_INTERFACE_USE_UART
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default 1000
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config BT_LE_HCI_UART_RX_BUFFER_SIZE
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int "The size of rx ring buffer memory"
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depends on BT_LE_UART_HCI_NO_DMA_MODE
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default 512
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help
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Set the size of uart task stack
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The size of rx ring buffer memory
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config BT_LE_HCI_UART_TX_BUFFER_SIZE
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int "The size of tx ring buffer memory"
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depends on BT_LE_UART_HCI_NO_DMA_MODE
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default 256
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help
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The size of tx ring buffer memory
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config BT_LE_HCI_TRANS_TASK_STACK_SIZE
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int "HCI transport task stack size"
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depends on !BT_LE_HCI_INTERFACE_USE_RAM
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default 1024
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help
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This configures stack size of hci transport task
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config BT_LE_HCI_TRANS_RX_MEM_NUM
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int "The amount of rx memory received at the same time"
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depends on BT_LE_UART_HCI_DMA_MODE
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default 3
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help
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The amount of rx memory received at the same time
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config BT_LE_HCI_LLDESCS_POOL_NUM
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int "The amount of lldecs memory for driver dma mode"
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depends on BT_LE_UART_HCI_DMA_MODE
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default 20
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help
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The amount of lldecs memory for driver dma mode
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endmenu
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config BT_LE_CONTROLLER_NPL_OS_PORTING_SUPPORT
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@ -30,7 +30,7 @@
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#endif // CONFIG_ESP_COEX_ENABLED
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#include "nimble/nimble_npl_os.h"
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#include "ble_hci_trans.h"
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#include "esp_hci_transport.h"
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#include "os/endian.h"
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#include "esp_bt.h"
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@ -41,7 +41,6 @@
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#include "esp_phy_init.h"
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#endif
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#include "esp_private/periph_ctrl.h"
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#include "hci_uart.h"
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#include "bt_osi_mem.h"
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#if SOC_PM_RETENTION_HAS_CLOCK_BUG
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@ -52,10 +51,6 @@
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#include "esp_private/sleep_modem.h"
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#endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
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#ifdef CONFIG_BT_BLUEDROID_ENABLED
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#include "hci/hci_hal.h"
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#endif // CONFIG_BT_BLUEDROID_ENABLED
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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@ -71,16 +66,11 @@
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#define OSI_COEX_VERSION 0x00010006
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#define OSI_COEX_MAGIC_VALUE 0xFADEBEAD
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#define EXT_FUNC_VERSION 0x20221122
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#define EXT_FUNC_VERSION 0x20240422
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#define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5
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#define BT_ASSERT_PRINT ets_printf
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#ifdef CONFIG_BT_BLUEDROID_ENABLED
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/* ACL_DATA_MBUF_LEADINGSPCAE: The leadingspace in user info header for ACL data */
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#define ACL_DATA_MBUF_LEADINGSPCAE 4
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#endif // CONFIG_BT_BLUEDROID_ENABLED
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/* Types definition
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************************************************************************
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*/
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@ -99,12 +89,6 @@ struct ext_funcs_t {
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int (*_esp_intr_free)(void **ret_handle);
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void *(* _malloc)(size_t size);
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void (*_free)(void *p);
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void (*_hal_uart_start_tx)(int);
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int (*_hal_uart_init_cbs)(int, hci_uart_tx_char, hci_uart_tx_done, hci_uart_rx_char, void *);
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int (*_hal_uart_config)(int, int32_t, uint8_t, uint8_t, uart_parity_t, uart_hw_flowcontrol_t);
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int (*_hal_uart_close)(int);
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void (*_hal_uart_blocking_tx)(int, uint8_t);
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int (*_hal_uart_init)(int, void *);
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int (* _task_create)(void *task_func, const char *name, uint32_t stack_depth, void *param,
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uint32_t prio, void *task_handle, uint32_t core_id);
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void (* _task_delete)(void *task_handle);
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@ -181,16 +165,6 @@ static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status);
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static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth,
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void *param, uint32_t prio, void *task_handle, uint32_t core_id);
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static void task_delete_wrapper(void *task_handle);
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#if CONFIG_BT_LE_HCI_INTERFACE_USE_UART
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static void hci_uart_start_tx_wrapper(int uart_no);
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static int hci_uart_init_cbs_wrapper(int uart_no, hci_uart_tx_char tx_func,
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hci_uart_tx_done tx_done, hci_uart_rx_char rx_func, void *arg);
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static int hci_uart_config_wrapper(int uart_no, int32_t speed, uint8_t databits, uint8_t stopbits,
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uart_parity_t parity, uart_hw_flowcontrol_t flow_ctl);
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static int hci_uart_close_wrapper(int uart_no);
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static void hci_uart_blocking_tx_wrapper(int port, uint8_t data);
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static int hci_uart_init_wrapper(int uart_no, void *cfg);
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#endif // CONFIG_BT_LE_HCI_INTERFACE_USE_UART
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static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
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void *arg, void **ret_handle_in);
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static int esp_intr_free_wrapper(void **ret_handle);
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@ -208,7 +182,6 @@ static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, b
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*/
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/* Static variable declare */
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static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
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#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
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const static uint32_t log_bufs_size[] = {CONFIG_BT_LE_LOG_CTRL_BUF1_SIZE, CONFIG_BT_LE_LOG_HCI_BUF_SIZE, CONFIG_BT_LE_LOG_CTRL_BUF2_SIZE};
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#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
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@ -238,14 +211,6 @@ struct ext_funcs_t ext_funcs_ro = {
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._esp_intr_free = esp_intr_free_wrapper,
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._malloc = bt_osi_mem_malloc_internal,
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._free = bt_osi_mem_free,
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#if CONFIG_BT_LE_HCI_INTERFACE_USE_UART
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._hal_uart_start_tx = hci_uart_start_tx_wrapper,
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._hal_uart_init_cbs = hci_uart_init_cbs_wrapper,
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._hal_uart_config = hci_uart_config_wrapper,
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._hal_uart_close = hci_uart_close_wrapper,
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._hal_uart_blocking_tx = hci_uart_blocking_tx_wrapper,
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._hal_uart_init = hci_uart_init_wrapper,
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#endif //CONFIG_BT_LE_HCI_INTERFACE_USE_UART
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._task_create = task_create_wrapper,
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._task_delete = task_delete_wrapper,
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._osi_assert = osi_assert_wrapper,
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@ -290,75 +255,6 @@ static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status)
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#endif // CONFIG_SW_COEXIST_ENABLE
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}
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#ifdef CONFIG_BT_BLUEDROID_ENABLED
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bool esp_vhci_host_check_send_available(void)
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{
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if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
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return false;
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}
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return true;
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}
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static struct os_mbuf *ble_hs_mbuf_gen_pkt(uint16_t leading_space)
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{
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struct os_mbuf *om;
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int rc;
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om = os_msys_get_pkthdr(0, 0);
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if (om == NULL) {
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return NULL;
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}
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if (om->om_omp->omp_databuf_len < leading_space) {
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rc = os_mbuf_free_chain(om);
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assert(rc == 0);
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return NULL;
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}
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om->om_data += leading_space;
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return om;
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}
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struct os_mbuf *ble_hs_mbuf_acl_pkt(void)
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{
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return ble_hs_mbuf_gen_pkt(4 + 1);
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}
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void esp_vhci_host_send_packet(uint8_t *data, uint16_t len)
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{
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if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
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return;
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}
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if (*(data) == DATA_TYPE_COMMAND) {
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struct ble_hci_cmd *cmd = NULL;
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cmd = (struct ble_hci_cmd *) ble_hci_trans_buf_alloc(BLE_HCI_TRANS_BUF_CMD);
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assert(cmd);
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memcpy((uint8_t *)cmd, data + 1, len - 1);
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ble_hci_trans_hs_cmd_tx((uint8_t *)cmd);
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}
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if (*(data) == DATA_TYPE_ACL) {
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struct os_mbuf *om = os_msys_get_pkthdr(len, ACL_DATA_MBUF_LEADINGSPCAE);
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assert(om);
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assert(os_mbuf_append(om, &data[1], len - 1) == 0);
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ble_hci_trans_hs_acl_tx(om);
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}
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}
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esp_err_t esp_vhci_host_register_callback(const esp_vhci_host_callback_t *callback)
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{
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if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
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return ESP_FAIL;
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}
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ble_hci_trans_cfg_hs(ble_hs_hci_rx_evt, NULL, ble_hs_rx_data, NULL);
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return ESP_OK;
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}
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#endif // CONFIG_BT_BLUEDROID_ENABLED
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static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth,
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void *param, uint32_t prio, void *task_handle, uint32_t core_id)
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{
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@ -390,56 +286,6 @@ static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer
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return rc;
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}
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#ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART
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static void hci_uart_start_tx_wrapper(int uart_no)
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{
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hci_uart_start_tx(uart_no);
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}
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static int hci_uart_init_cbs_wrapper(int uart_no, hci_uart_tx_char tx_func,
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hci_uart_tx_done tx_done, hci_uart_rx_char rx_func, void *arg)
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{
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int rc = -1;
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rc = hci_uart_init_cbs(uart_no, tx_func, tx_done, rx_func, arg);
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return rc;
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}
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static int hci_uart_config_wrapper(int port_num, int32_t baud_rate, uint8_t data_bits,
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uint8_t stop_bits, uart_parity_t parity,
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uart_hw_flowcontrol_t flow_ctl)
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{
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int rc = -1;
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rc = hci_uart_config(port_num, baud_rate, data_bits, stop_bits, parity, flow_ctl);
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return rc;
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}
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static int hci_uart_close_wrapper(int uart_no)
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{
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int rc = -1;
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rc = hci_uart_close(uart_no);
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return rc;
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}
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static void hci_uart_blocking_tx_wrapper(int port, uint8_t data)
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{
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//This function is nowhere to use.
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}
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static int hci_uart_init_wrapper(int uart_no, void *cfg)
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{
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//This function is nowhere to use.
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return 0;
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}
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#endif //CONFIG_BT_LE_HCI_INTERFACE_USE_UART
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static int ble_hci_unregistered_hook(void*, void*)
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{
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ESP_LOGD(NIMBLE_PORT_LOG_TAG,"%s ble hci rx_evt is not registered.",__func__);
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return 0;
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}
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static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
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void *arg, void **ret_handle_in)
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{
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@ -718,6 +564,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
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esp_err_t ret = ESP_OK;
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ble_npl_count_info_t npl_info;
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uint32_t slow_clk_freq = 0;
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uint8_t hci_transport_mode;
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memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
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@ -862,11 +709,23 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
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ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED;
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ble_hci_trans_cfg_hs((ble_hci_trans_rx_cmd_fn *)ble_hci_unregistered_hook,NULL,
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(ble_hci_trans_rx_acl_fn *)ble_hci_unregistered_hook,NULL);
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return ESP_OK;
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#if CONFIG_BT_LE_HCI_INTERFACE_USE_RAM
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hci_transport_mode = HCI_TRANSPORT_VHCI;
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#elif CONFIG_BT_LE_HCI_INTERFACE_USE_UART
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hci_transport_mode = HCI_TRANSPORT_UART_NO_DMA;
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#if CONFIG_BT_LE_UART_HCI_DMA_MODE
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hci_transport_mode = HCI_TRANSPORT_UART_UHCI;
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#endif // CONFIG_BT_LE_UART_HCI_DMA_MODE
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#endif // CONFIG_BT_LE_HCI_INTERFACE_USE_RAM
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ret = hci_transport_init(hci_transport_mode);
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if (ret) {
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ESP_LOGW(NIMBLE_PORT_LOG_TAG, "hci transport init failed %d", ret);
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goto free_controller;
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}
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return ESP_OK;
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free_controller:
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hci_transport_deinit();
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controller_sleep_deinit();
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os_msys_deinit();
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r_ble_controller_deinit();
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@ -897,6 +756,7 @@ esp_err_t esp_bt_controller_deinit(void)
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return ESP_FAIL;
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}
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hci_transport_deinit();
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controller_sleep_deinit();
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os_msys_deinit();
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -129,6 +129,21 @@ extern "C" {
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#else
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#define DEFAULT_BT_LE_50_FEATURE_SUPPORT (0)
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#endif
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#if defined (CONFIG_BT_LE_HCI_UART_FLOWCTRL)
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#define DEFAULT_BT_LE_HCI_UART_FLOW_CTRL (CONFIG_BT_LE_HCI_UART_FLOWCTRL)
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#if DEFAULT_BT_LE_HCI_UART_FLOW_CTRL
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#define DEFAULT_BT_LE_HCI_UART_CTS_PIN (CONFIG_BT_LE_HCI_UART_CTS_PIN)
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#define DEFAULT_BT_LE_HCI_UART_RTS_PIN (CONFIG_BT_LE_HCI_UART_RTS_PIN)
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#else
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#define DEFAULT_BT_LE_HCI_UART_CTS_PIN (-1)
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#define DEFAULT_BT_LE_HCI_UART_RTS_PIN (-1)
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#endif
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#else
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#define DEFAULT_BT_LE_HCI_UART_FLOW_CTRL (0)
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#define DEFAULT_BT_LE_HCI_UART_CTS_PIN (-1)
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#define DEFAULT_BT_LE_HCI_UART_RTS_PIN (-1)
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#endif
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#endif
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#define DEFAULT_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF CONFIG_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF
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@ -169,8 +184,6 @@ extern "C" {
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#define DEFAULT_BT_LE_HCI_UART_DATA_BITS (UART_DATA_8_BITS)
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#define DEFAULT_BT_LE_HCI_UART_STOP_BITS (UART_STOP_BITS_1)
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#define DEFAULT_BT_LE_HCI_UART_PARITY (0)
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#define DEFAULT_BT_LE_HCI_UART_TASK_STACK_SIZE (CONFIG_BT_LE_HCI_UART_TASK_STACK_SIZE)
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#define DEFAULT_BT_LE_HCI_UART_FLOW_CTRL (0)
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#else
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#define DEFAULT_BT_LE_HCI_UART_TX_PIN (0)
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#define DEFAULT_BT_LE_HCI_UART_RX_PIN (0)
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@ -179,8 +192,6 @@ extern "C" {
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#define DEFAULT_BT_LE_HCI_UART_DATA_BITS (0)
|
||||
#define DEFAULT_BT_LE_HCI_UART_STOP_BITS (0)
|
||||
#define DEFAULT_BT_LE_HCI_UART_PARITY (0)
|
||||
#define DEFAULT_BT_LE_HCI_UART_TASK_STACK_SIZE (0)
|
||||
#define DEFAULT_BT_LE_HCI_UART_FLOW_CTRL (0)
|
||||
#endif
|
||||
|
||||
/* Unchanged configuration */
|
||||
|
||||
@ -2,19 +2,37 @@
|
||||
menu "HCI Config"
|
||||
|
||||
choice BT_LE_HCI_INTERFACE
|
||||
prompt "Select HCI interface"
|
||||
prompt "HCI mode"
|
||||
default BT_LE_HCI_INTERFACE_USE_RAM
|
||||
|
||||
config BT_LE_HCI_INTERFACE_USE_RAM
|
||||
bool "ram"
|
||||
bool "VHCI"
|
||||
help
|
||||
Use RAM as HCI interface
|
||||
config BT_LE_HCI_INTERFACE_USE_UART
|
||||
bool "uart"
|
||||
bool "UART(H4)"
|
||||
help
|
||||
Use UART as HCI interface
|
||||
endchoice
|
||||
|
||||
choice BT_LE_UART_HCI_MODE_CHOICE
|
||||
prompt "UART HCI mode"
|
||||
depends on BT_LE_HCI_INTERFACE_USE_UART
|
||||
default BT_LE_UART_HCI_NO_DMA_MODE
|
||||
help
|
||||
Specify UART HCI mode: DMA or No DMA
|
||||
|
||||
config BT_LE_UART_HCI_DMA_MODE
|
||||
bool "UHCI(UART with DMA)(EXPERIMENTAL)"
|
||||
help
|
||||
UART HCI Mode with DMA functionality.
|
||||
|
||||
config BT_LE_UART_HCI_NO_DMA_MODE
|
||||
bool "UART(NO DMA)"
|
||||
help
|
||||
UART HCI Mode without DMA functionality.
|
||||
endchoice
|
||||
|
||||
config BT_LE_HCI_UART_PORT
|
||||
int "HCI UART port"
|
||||
depends on BT_LE_HCI_INTERFACE_USE_UART
|
||||
@ -73,12 +91,40 @@ menu "HCI Config"
|
||||
UART_PARITY_ODD
|
||||
endchoice
|
||||
|
||||
config BT_LE_HCI_UART_TASK_STACK_SIZE
|
||||
int "HCI uart task stack size"
|
||||
depends on BT_LE_HCI_INTERFACE_USE_UART
|
||||
default 1000
|
||||
config BT_LE_HCI_UART_RX_BUFFER_SIZE
|
||||
int "The size of rx ring buffer memory"
|
||||
depends on BT_LE_UART_HCI_NO_DMA_MODE
|
||||
default 512
|
||||
help
|
||||
Set the size of uart task stack
|
||||
The size of rx ring buffer memory
|
||||
|
||||
config BT_LE_HCI_UART_TX_BUFFER_SIZE
|
||||
int "The size of tx ring buffer memory"
|
||||
depends on BT_LE_UART_HCI_NO_DMA_MODE
|
||||
default 256
|
||||
help
|
||||
The size of tx ring buffer memory
|
||||
|
||||
config BT_LE_HCI_TRANS_TASK_STACK_SIZE
|
||||
int "HCI transport task stack size"
|
||||
depends on !BT_LE_HCI_INTERFACE_USE_RAM
|
||||
default 1024
|
||||
help
|
||||
This configures stack size of hci transport task
|
||||
|
||||
config BT_LE_HCI_TRANS_RX_MEM_NUM
|
||||
int "The amount of rx memory received at the same time"
|
||||
depends on BT_LE_UART_HCI_DMA_MODE
|
||||
default 3
|
||||
help
|
||||
The amount of rx memory received at the same time
|
||||
|
||||
config BT_LE_HCI_LLDESCS_POOL_NUM
|
||||
int "The amount of lldecs memory for driver dma mode"
|
||||
depends on BT_LE_UART_HCI_DMA_MODE
|
||||
default 20
|
||||
help
|
||||
The amount of lldecs memory for driver dma mode
|
||||
endmenu
|
||||
|
||||
config BT_LE_CONTROLLER_NPL_OS_PORTING_SUPPORT
|
||||
|
||||
@ -30,7 +30,7 @@
|
||||
#endif // CONFIG_ESP_COEX_ENABLED
|
||||
|
||||
#include "nimble/nimble_npl_os.h"
|
||||
#include "ble_hci_trans.h"
|
||||
#include "esp_hci_transport.h"
|
||||
#include "os/endian.h"
|
||||
|
||||
#include "esp_bt.h"
|
||||
@ -39,7 +39,6 @@
|
||||
#include "esp_pm.h"
|
||||
#include "esp_phy_init.h"
|
||||
#include "esp_private/periph_ctrl.h"
|
||||
#include "hci_uart.h"
|
||||
#include "bt_osi_mem.h"
|
||||
|
||||
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
||||
@ -47,10 +46,6 @@
|
||||
#include "esp_private/sleep_retention.h"
|
||||
#endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
||||
|
||||
#ifdef CONFIG_BT_BLUEDROID_ENABLED
|
||||
#include "hci/hci_hal.h"
|
||||
#endif // CONFIG_BT_BLUEDROID_ENABLED
|
||||
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
|
||||
@ -64,16 +59,11 @@
|
||||
#define OSI_COEX_VERSION 0x00010006
|
||||
#define OSI_COEX_MAGIC_VALUE 0xFADEBEAD
|
||||
|
||||
#define EXT_FUNC_VERSION 0x20221122
|
||||
#define EXT_FUNC_VERSION 0x20240422
|
||||
#define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5
|
||||
|
||||
#define BT_ASSERT_PRINT ets_printf
|
||||
|
||||
#ifdef CONFIG_BT_BLUEDROID_ENABLED
|
||||
/* ACL_DATA_MBUF_LEADINGSPCAE: The leadingspace in user info header for ACL data */
|
||||
#define ACL_DATA_MBUF_LEADINGSPCAE 4
|
||||
#endif // CONFIG_BT_BLUEDROID_ENABLED
|
||||
|
||||
/* Types definition
|
||||
************************************************************************
|
||||
*/
|
||||
@ -92,12 +82,6 @@ struct ext_funcs_t {
|
||||
int (*_esp_intr_free)(void **ret_handle);
|
||||
void *(* _malloc)(size_t size);
|
||||
void (*_free)(void *p);
|
||||
void (*_hal_uart_start_tx)(int);
|
||||
int (*_hal_uart_init_cbs)(int, hci_uart_tx_char, hci_uart_tx_done, hci_uart_rx_char, void *);
|
||||
int (*_hal_uart_config)(int, int32_t, uint8_t, uint8_t, uart_parity_t, uart_hw_flowcontrol_t);
|
||||
int (*_hal_uart_close)(int);
|
||||
void (*_hal_uart_blocking_tx)(int, uint8_t);
|
||||
int (*_hal_uart_init)(int, void *);
|
||||
int (* _task_create)(void *task_func, const char *name, uint32_t stack_depth, void *param,
|
||||
uint32_t prio, void *task_handle, uint32_t core_id);
|
||||
void (* _task_delete)(void *task_handle);
|
||||
@ -173,16 +157,6 @@ static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status);
|
||||
static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth,
|
||||
void *param, uint32_t prio, void *task_handle, uint32_t core_id);
|
||||
static void task_delete_wrapper(void *task_handle);
|
||||
#if CONFIG_BT_LE_HCI_INTERFACE_USE_UART
|
||||
static void hci_uart_start_tx_wrapper(int uart_no);
|
||||
static int hci_uart_init_cbs_wrapper(int uart_no, hci_uart_tx_char tx_func,
|
||||
hci_uart_tx_done tx_done, hci_uart_rx_char rx_func, void *arg);
|
||||
static int hci_uart_config_wrapper(int uart_no, int32_t speed, uint8_t databits, uint8_t stopbits,
|
||||
uart_parity_t parity, uart_hw_flowcontrol_t flow_ctl);
|
||||
static int hci_uart_close_wrapper(int uart_no);
|
||||
static void hci_uart_blocking_tx_wrapper(int port, uint8_t data);
|
||||
static int hci_uart_init_wrapper(int uart_no, void *cfg);
|
||||
#endif // CONFIG_BT_LE_HCI_INTERFACE_USE_UART
|
||||
static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
|
||||
void *arg, void **ret_handle_in);
|
||||
static int esp_intr_free_wrapper(void **ret_handle);
|
||||
@ -200,7 +174,6 @@ static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, b
|
||||
*/
|
||||
/* Static variable declare */
|
||||
static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
|
||||
|
||||
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||
const static uint32_t log_bufs_size[] = {CONFIG_BT_LE_LOG_CTRL_BUF1_SIZE, CONFIG_BT_LE_LOG_HCI_BUF_SIZE, CONFIG_BT_LE_LOG_CTRL_BUF2_SIZE};
|
||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||
@ -230,14 +203,6 @@ struct ext_funcs_t ext_funcs_ro = {
|
||||
._esp_intr_free = esp_intr_free_wrapper,
|
||||
._malloc = bt_osi_mem_malloc_internal,
|
||||
._free = bt_osi_mem_free,
|
||||
#if CONFIG_BT_LE_HCI_INTERFACE_USE_UART
|
||||
._hal_uart_start_tx = hci_uart_start_tx_wrapper,
|
||||
._hal_uart_init_cbs = hci_uart_init_cbs_wrapper,
|
||||
._hal_uart_config = hci_uart_config_wrapper,
|
||||
._hal_uart_close = hci_uart_close_wrapper,
|
||||
._hal_uart_blocking_tx = hci_uart_blocking_tx_wrapper,
|
||||
._hal_uart_init = hci_uart_init_wrapper,
|
||||
#endif //CONFIG_BT_LE_HCI_INTERFACE_USE_UART
|
||||
._task_create = task_create_wrapper,
|
||||
._task_delete = task_delete_wrapper,
|
||||
._osi_assert = osi_assert_wrapper,
|
||||
@ -282,75 +247,6 @@ static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status)
|
||||
#endif // CONFIG_SW_COEXIST_ENABLE
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BT_BLUEDROID_ENABLED
|
||||
bool esp_vhci_host_check_send_available(void)
|
||||
{
|
||||
if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static struct os_mbuf *ble_hs_mbuf_gen_pkt(uint16_t leading_space)
|
||||
{
|
||||
struct os_mbuf *om;
|
||||
int rc;
|
||||
|
||||
om = os_msys_get_pkthdr(0, 0);
|
||||
if (om == NULL) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (om->om_omp->omp_databuf_len < leading_space) {
|
||||
rc = os_mbuf_free_chain(om);
|
||||
assert(rc == 0);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
om->om_data += leading_space;
|
||||
|
||||
return om;
|
||||
}
|
||||
|
||||
struct os_mbuf *ble_hs_mbuf_acl_pkt(void)
|
||||
{
|
||||
return ble_hs_mbuf_gen_pkt(4 + 1);
|
||||
}
|
||||
|
||||
void esp_vhci_host_send_packet(uint8_t *data, uint16_t len)
|
||||
{
|
||||
if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (*(data) == DATA_TYPE_COMMAND) {
|
||||
struct ble_hci_cmd *cmd = NULL;
|
||||
cmd = (struct ble_hci_cmd *) ble_hci_trans_buf_alloc(BLE_HCI_TRANS_BUF_CMD);
|
||||
assert(cmd);
|
||||
memcpy((uint8_t *)cmd, data + 1, len - 1);
|
||||
ble_hci_trans_hs_cmd_tx((uint8_t *)cmd);
|
||||
}
|
||||
|
||||
if (*(data) == DATA_TYPE_ACL) {
|
||||
struct os_mbuf *om = os_msys_get_pkthdr(len, ACL_DATA_MBUF_LEADINGSPCAE);
|
||||
assert(om);
|
||||
assert(os_mbuf_append(om, &data[1], len - 1) == 0);
|
||||
ble_hci_trans_hs_acl_tx(om);
|
||||
}
|
||||
}
|
||||
|
||||
esp_err_t esp_vhci_host_register_callback(const esp_vhci_host_callback_t *callback)
|
||||
{
|
||||
if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
|
||||
return ESP_FAIL;
|
||||
}
|
||||
|
||||
ble_hci_trans_cfg_hs(ble_hs_hci_rx_evt, NULL, ble_hs_rx_data, NULL);
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
#endif // CONFIG_BT_BLUEDROID_ENABLED
|
||||
|
||||
static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth,
|
||||
void *param, uint32_t prio, void *task_handle, uint32_t core_id)
|
||||
{
|
||||
@ -382,56 +278,6 @@ static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer
|
||||
return rc;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART
|
||||
static void hci_uart_start_tx_wrapper(int uart_no)
|
||||
{
|
||||
hci_uart_start_tx(uart_no);
|
||||
}
|
||||
|
||||
static int hci_uart_init_cbs_wrapper(int uart_no, hci_uart_tx_char tx_func,
|
||||
hci_uart_tx_done tx_done, hci_uart_rx_char rx_func, void *arg)
|
||||
{
|
||||
int rc = -1;
|
||||
rc = hci_uart_init_cbs(uart_no, tx_func, tx_done, rx_func, arg);
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
static int hci_uart_config_wrapper(int port_num, int32_t baud_rate, uint8_t data_bits,
|
||||
uint8_t stop_bits, uart_parity_t parity,
|
||||
uart_hw_flowcontrol_t flow_ctl)
|
||||
{
|
||||
int rc = -1;
|
||||
rc = hci_uart_config(port_num, baud_rate, data_bits, stop_bits, parity, flow_ctl);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int hci_uart_close_wrapper(int uart_no)
|
||||
{
|
||||
int rc = -1;
|
||||
rc = hci_uart_close(uart_no);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void hci_uart_blocking_tx_wrapper(int port, uint8_t data)
|
||||
{
|
||||
//This function is nowhere to use.
|
||||
}
|
||||
|
||||
static int hci_uart_init_wrapper(int uart_no, void *cfg)
|
||||
{
|
||||
//This function is nowhere to use.
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif //CONFIG_BT_LE_HCI_INTERFACE_USE_UART
|
||||
|
||||
static int ble_hci_unregistered_hook(void*, void*)
|
||||
{
|
||||
ESP_LOGD(NIMBLE_PORT_LOG_TAG,"%s ble hci rx_evt is not registered.",__func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
|
||||
void *arg, void **ret_handle_in)
|
||||
{
|
||||
@ -689,6 +535,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
||||
esp_err_t ret = ESP_OK;
|
||||
ble_npl_count_info_t npl_info;
|
||||
uint32_t slow_clk_freq = 0;
|
||||
uint8_t hci_transport_mode;
|
||||
|
||||
memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
|
||||
if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) {
|
||||
@ -831,11 +678,23 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
||||
|
||||
ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED;
|
||||
|
||||
ble_hci_trans_cfg_hs((ble_hci_trans_rx_cmd_fn *)ble_hci_unregistered_hook,NULL,
|
||||
(ble_hci_trans_rx_acl_fn *)ble_hci_unregistered_hook,NULL);
|
||||
return ESP_OK;
|
||||
#if CONFIG_BT_LE_HCI_INTERFACE_USE_RAM
|
||||
hci_transport_mode = HCI_TRANSPORT_VHCI;
|
||||
#elif CONFIG_BT_LE_HCI_INTERFACE_USE_UART
|
||||
hci_transport_mode = HCI_TRANSPORT_UART_NO_DMA;
|
||||
#if CONFIG_BT_LE_UART_HCI_DMA_MODE
|
||||
hci_transport_mode = HCI_TRANSPORT_UART_UHCI;
|
||||
#endif // CONFIG_BT_LE_UART_HCI_DMA_MODE
|
||||
#endif // CONFIG_BT_LE_HCI_INTERFACE_USE_RAM
|
||||
ret = hci_transport_init(hci_transport_mode);
|
||||
if (ret) {
|
||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "hci transport init failed %d", ret);
|
||||
goto free_controller;
|
||||
}
|
||||
|
||||
return ESP_OK;
|
||||
free_controller:
|
||||
hci_transport_deinit();
|
||||
controller_sleep_deinit();
|
||||
os_msys_deinit();
|
||||
r_ble_controller_deinit();
|
||||
@ -865,6 +724,7 @@ esp_err_t esp_bt_controller_deinit(void)
|
||||
return ESP_FAIL;
|
||||
}
|
||||
|
||||
hci_transport_deinit();
|
||||
controller_sleep_deinit();
|
||||
|
||||
os_msys_deinit();
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -124,12 +124,26 @@ extern "C" {
|
||||
#else
|
||||
#define DEFAULT_BT_LE_POWER_CONTROL_ENABLED (0)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BT_LE_50_FEATURE_SUPPORT)
|
||||
#define DEFAULT_BT_LE_50_FEATURE_SUPPORT (1)
|
||||
#else
|
||||
#define DEFAULT_BT_LE_50_FEATURE_SUPPORT (0)
|
||||
#endif
|
||||
|
||||
#if defined (CONFIG_BT_LE_HCI_UART_FLOWCTRL)
|
||||
#define DEFAULT_BT_LE_HCI_UART_FLOW_CTRL (CONFIG_BT_LE_HCI_UART_FLOWCTRL)
|
||||
#if DEFAULT_BT_LE_HCI_UART_FLOW_CTRL
|
||||
#define DEFAULT_BT_LE_HCI_UART_CTS_PIN (CONFIG_BT_LE_HCI_UART_CTS_PIN)
|
||||
#define DEFAULT_BT_LE_HCI_UART_RTS_PIN (CONFIG_BT_LE_HCI_UART_RTS_PIN)
|
||||
#else
|
||||
#define DEFAULT_BT_LE_HCI_UART_CTS_PIN (-1)
|
||||
#define DEFAULT_BT_LE_HCI_UART_RTS_PIN (-1)
|
||||
#endif
|
||||
#else
|
||||
#define DEFAULT_BT_LE_HCI_UART_FLOW_CTRL (0)
|
||||
#define DEFAULT_BT_LE_HCI_UART_CTS_PIN (-1)
|
||||
#define DEFAULT_BT_LE_HCI_UART_RTS_PIN (-1)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define DEFAULT_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF CONFIG_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF
|
||||
@ -170,8 +184,6 @@ extern "C" {
|
||||
#define DEFAULT_BT_LE_HCI_UART_DATA_BITS (UART_DATA_8_BITS)
|
||||
#define DEFAULT_BT_LE_HCI_UART_STOP_BITS (UART_STOP_BITS_1)
|
||||
#define DEFAULT_BT_LE_HCI_UART_PARITY (0)
|
||||
#define DEFAULT_BT_LE_HCI_UART_TASK_STACK_SIZE (CONFIG_BT_LE_HCI_UART_TASK_STACK_SIZE)
|
||||
#define DEFAULT_BT_LE_HCI_UART_FLOW_CTRL (0)
|
||||
#else
|
||||
#define DEFAULT_BT_LE_HCI_UART_TX_PIN (0)
|
||||
#define DEFAULT_BT_LE_HCI_UART_RX_PIN (0)
|
||||
@ -180,8 +192,6 @@ extern "C" {
|
||||
#define DEFAULT_BT_LE_HCI_UART_DATA_BITS (0)
|
||||
#define DEFAULT_BT_LE_HCI_UART_STOP_BITS (0)
|
||||
#define DEFAULT_BT_LE_HCI_UART_PARITY (0)
|
||||
#define DEFAULT_BT_LE_HCI_UART_TASK_STACK_SIZE (0)
|
||||
#define DEFAULT_BT_LE_HCI_UART_FLOW_CTRL (0)
|
||||
#endif
|
||||
|
||||
/* Unchanged configuration */
|
||||
|
||||
@ -1 +1 @@
|
||||
Subproject commit 4a63b2963a8a75958db680df4ace64bbd3d6c618
|
||||
Subproject commit 2085541b6e9963640e4090401faaf2061758d847
|
||||
@ -1 +1 @@
|
||||
Subproject commit 96b48749e249d0752f196007b008212cb8b28e07
|
||||
Subproject commit 9e29a8b39fe81ac82064dc4525e56e0faa9e1b8a
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -155,7 +155,7 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type
|
||||
*/
|
||||
esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle);
|
||||
|
||||
#define CONFIG_VERSION 0x20231124
|
||||
#define CONFIG_VERSION 0x20240422
|
||||
#define CONFIG_MAGIC 0x5A5AA5A5
|
||||
|
||||
/**
|
||||
@ -196,13 +196,6 @@ typedef struct {
|
||||
uint8_t controller_run_cpu; /*!< CPU core on which the controller runs */
|
||||
uint8_t enable_qa_test; /*!< Enable quality assurance (QA) testing */
|
||||
uint8_t enable_bqb_test; /*!< Enable Bluetooth Qualification Test (BQB) testing */
|
||||
uint8_t enable_uart_hci; /*!< Enable UART HCI (Host Controller Interface) */
|
||||
uint8_t ble_hci_uart_port; /*!< UART port number for Bluetooth HCI */
|
||||
uint32_t ble_hci_uart_baud; /*!< Baud rate for Bluetooth HCI UART */
|
||||
uint8_t ble_hci_uart_data_bits; /*!< Number of data bits for Bluetooth HCI UART */
|
||||
uint8_t ble_hci_uart_stop_bits; /*!< Number of stop bits for Bluetooth HCI UART */
|
||||
uint8_t ble_hci_uart_flow_ctrl; /*!< Flow control settings for Bluetooth HCI UART */
|
||||
uint8_t ble_hci_uart_uart_parity; /*!< Parity settings for Bluetooth HCI UART */
|
||||
uint8_t enable_tx_cca; /*!< Enable Transmit Clear Channel Assessment (TX CCA) */
|
||||
uint8_t cca_rssi_thresh; /*!< RSSI threshold for Transmit Clear Channel Assessment (CCA) */
|
||||
uint8_t sleep_en; /*!< Enable sleep mode */
|
||||
@ -253,13 +246,6 @@ typedef struct {
|
||||
.controller_run_cpu = 0, \
|
||||
.enable_qa_test = RUN_QA_TEST, \
|
||||
.enable_bqb_test = RUN_BQB_TEST, \
|
||||
.enable_uart_hci = HCI_UART_EN, \
|
||||
.ble_hci_uart_port = DEFAULT_BT_LE_HCI_UART_PORT, \
|
||||
.ble_hci_uart_baud = DEFAULT_BT_LE_HCI_UART_BAUD, \
|
||||
.ble_hci_uart_data_bits = DEFAULT_BT_LE_HCI_UART_DATA_BITS, \
|
||||
.ble_hci_uart_stop_bits = DEFAULT_BT_LE_HCI_UART_STOP_BITS, \
|
||||
.ble_hci_uart_flow_ctrl = DEFAULT_BT_LE_HCI_UART_FLOW_CTRL, \
|
||||
.ble_hci_uart_uart_parity = DEFAULT_BT_LE_HCI_UART_PARITY, \
|
||||
.enable_tx_cca = DEFAULT_BT_LE_TX_CCA_ENABLED, \
|
||||
.cca_rssi_thresh = 256 - DEFAULT_BT_LE_CCA_RSSI_THRESH, \
|
||||
.sleep_en = NIMBLE_SLEEP_ENABLE, \
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -160,7 +160,7 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type
|
||||
*/
|
||||
esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle);
|
||||
|
||||
#define CONFIG_VERSION 0x20231124
|
||||
#define CONFIG_VERSION 0x20240422
|
||||
#define CONFIG_MAGIC 0x5A5AA5A5
|
||||
|
||||
/**
|
||||
@ -201,13 +201,6 @@ typedef struct {
|
||||
uint8_t controller_run_cpu; /*!< CPU number on which the Bluetooth controller task runs */
|
||||
uint8_t enable_qa_test; /*!< Enable for QA test */
|
||||
uint8_t enable_bqb_test; /*!< Enable for BQB test */
|
||||
uint8_t enable_uart_hci; /*!< Enable UART for HCI (Host Controller Interface) */
|
||||
uint8_t ble_hci_uart_port; /*!< Port of UART for HCI */
|
||||
uint32_t ble_hci_uart_baud; /*!< Baudrate of UART for HCI */
|
||||
uint8_t ble_hci_uart_data_bits; /*!< Data bits of UART for HCI */
|
||||
uint8_t ble_hci_uart_stop_bits; /*!< Stop bits of UART for HCI */
|
||||
uint8_t ble_hci_uart_flow_ctrl; /*!< Flow control of UART for HCI */
|
||||
uint8_t ble_hci_uart_uart_parity; /*!< UART parity */
|
||||
uint8_t enable_tx_cca; /*!< Enable Clear Channel Assessment (CCA) when transmitting */
|
||||
uint8_t cca_rssi_thresh; /*!< RSSI threshold for CCA */
|
||||
uint8_t sleep_en; /*!< Enable sleep functionality */
|
||||
@ -258,13 +251,6 @@ typedef struct {
|
||||
.controller_run_cpu = 0, \
|
||||
.enable_qa_test = RUN_QA_TEST, \
|
||||
.enable_bqb_test = RUN_BQB_TEST, \
|
||||
.enable_uart_hci = HCI_UART_EN, \
|
||||
.ble_hci_uart_port = DEFAULT_BT_LE_HCI_UART_PORT, \
|
||||
.ble_hci_uart_baud = DEFAULT_BT_LE_HCI_UART_BAUD, \
|
||||
.ble_hci_uart_data_bits = DEFAULT_BT_LE_HCI_UART_DATA_BITS, \
|
||||
.ble_hci_uart_stop_bits = DEFAULT_BT_LE_HCI_UART_STOP_BITS, \
|
||||
.ble_hci_uart_flow_ctrl = DEFAULT_BT_LE_HCI_UART_FLOW_CTRL, \
|
||||
.ble_hci_uart_uart_parity = DEFAULT_BT_LE_HCI_UART_PARITY, \
|
||||
.enable_tx_cca = DEFAULT_BT_LE_TX_CCA_ENABLED, \
|
||||
.cca_rssi_thresh = 256 - DEFAULT_BT_LE_CCA_RSSI_THRESH, \
|
||||
.sleep_en = NIMBLE_SLEEP_ENABLE, \
|
||||
|
||||
133
components/hal/esp32c6/include/hal/uhci_ll.h
Normal file
133
components/hal/esp32c6/include/hal/uhci_ll.h
Normal file
@ -0,0 +1,133 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
#include <stdio.h>
|
||||
#include "hal/uhci_types.h"
|
||||
#include "soc/uhci_struct.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
|
||||
|
||||
typedef enum {
|
||||
UHCI_RX_BREAK_CHR_EOF = 0x1,
|
||||
UHCI_RX_IDLE_EOF = 0x2,
|
||||
UHCI_RX_LEN_EOF = 0x4,
|
||||
UHCI_RX_EOF_MAX = 0x7,
|
||||
} uhci_rxeof_cfg_t;
|
||||
|
||||
static inline void uhci_ll_init(uhci_dev_t *hw)
|
||||
{
|
||||
typeof(hw->conf0) conf0_reg;
|
||||
hw->conf0.clk_en = 1;
|
||||
conf0_reg.val = 0;
|
||||
conf0_reg.clk_en = 1;
|
||||
hw->conf0.val = conf0_reg.val;
|
||||
hw->conf1.val = 0;
|
||||
}
|
||||
|
||||
static inline void uhci_ll_attach_uart_port(uhci_dev_t *hw, int uart_num)
|
||||
{
|
||||
hw->conf0.uart0_ce = (uart_num == 0)? 1: 0;
|
||||
hw->conf0.uart1_ce = (uart_num == 1)? 1: 0;
|
||||
}
|
||||
|
||||
static inline void uhci_ll_set_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_char)
|
||||
{
|
||||
if (seper_char->sub_chr_en) {
|
||||
typeof(hw->esc_conf0) esc_conf0_reg;
|
||||
esc_conf0_reg.val = hw->esc_conf0.val;
|
||||
|
||||
esc_conf0_reg.seper_char = seper_char->seper_chr;
|
||||
esc_conf0_reg.seper_esc_char0 = seper_char->sub_chr1;
|
||||
esc_conf0_reg.seper_esc_char1 = seper_char->sub_chr2;
|
||||
hw->esc_conf0.val = esc_conf0_reg.val;
|
||||
hw->escape_conf.tx_c0_esc_en = 1;
|
||||
hw->escape_conf.rx_c0_esc_en = 1;
|
||||
} else {
|
||||
hw->escape_conf.tx_c0_esc_en = 0;
|
||||
hw->escape_conf.rx_c0_esc_en = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void uhci_ll_get_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_chr)
|
||||
{
|
||||
(void)hw;
|
||||
(void)seper_chr;
|
||||
}
|
||||
|
||||
static inline void uhci_ll_set_swflow_ctrl_sub_chr(uhci_dev_t *hw, uhci_swflow_ctrl_sub_chr_t *sub_ctr)
|
||||
{
|
||||
typeof(hw->escape_conf) escape_conf_reg;
|
||||
escape_conf_reg.val = hw->escape_conf.val;
|
||||
|
||||
if (sub_ctr->flow_en == 1) {
|
||||
typeof(hw->esc_conf2) esc_conf2_reg;
|
||||
esc_conf2_reg.val = hw->esc_conf2.val;
|
||||
typeof(hw->esc_conf3) esc_conf3_reg;
|
||||
esc_conf3_reg.val = hw->esc_conf3.val;
|
||||
|
||||
esc_conf2_reg.esc_seq1 = sub_ctr->xon_chr;
|
||||
esc_conf2_reg.esc_seq1_char0 = sub_ctr->xon_sub1;
|
||||
esc_conf2_reg.esc_seq1_char1 = sub_ctr->xon_sub2;
|
||||
esc_conf3_reg.esc_seq2 = sub_ctr->xoff_chr;
|
||||
esc_conf3_reg.esc_seq2_char0 = sub_ctr->xoff_sub1;
|
||||
esc_conf3_reg.esc_seq2_char1 = sub_ctr->xoff_sub2;
|
||||
escape_conf_reg.tx_11_esc_en = 1;
|
||||
escape_conf_reg.tx_13_esc_en = 1;
|
||||
escape_conf_reg.rx_11_esc_en = 1;
|
||||
escape_conf_reg.rx_13_esc_en = 1;
|
||||
hw->esc_conf2.val = esc_conf2_reg.val;
|
||||
hw->esc_conf3.val = esc_conf3_reg.val;
|
||||
} else {
|
||||
escape_conf_reg.tx_11_esc_en = 0;
|
||||
escape_conf_reg.tx_13_esc_en = 0;
|
||||
escape_conf_reg.rx_11_esc_en = 0;
|
||||
escape_conf_reg.rx_13_esc_en = 0;
|
||||
}
|
||||
hw->escape_conf.val = escape_conf_reg.val;
|
||||
}
|
||||
|
||||
static inline void uhci_ll_enable_intr(uhci_dev_t *hw, uint32_t intr_mask)
|
||||
{
|
||||
hw->int_ena.val |= intr_mask;
|
||||
}
|
||||
|
||||
static inline void uhci_ll_disable_intr(uhci_dev_t *hw, uint32_t intr_mask)
|
||||
{
|
||||
hw->int_ena.val &= (~intr_mask);
|
||||
}
|
||||
|
||||
static inline void uhci_ll_clear_intr(uhci_dev_t *hw, uint32_t intr_mask)
|
||||
{
|
||||
hw->int_clr.val = intr_mask;
|
||||
}
|
||||
|
||||
static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw)
|
||||
{
|
||||
return hw->int_st.val;
|
||||
}
|
||||
|
||||
|
||||
static inline void uhci_ll_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
|
||||
{
|
||||
if (eof_mode & UHCI_RX_BREAK_CHR_EOF) {
|
||||
hw->conf0.uart_rx_brk_eof_en = 1;
|
||||
}
|
||||
if (eof_mode & UHCI_RX_IDLE_EOF) {
|
||||
hw->conf0.uart_idle_eof_en = 1;
|
||||
}
|
||||
if (eof_mode & UHCI_RX_LEN_EOF) {
|
||||
hw->conf0.len_eof_en = 1;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
133
components/hal/esp32h2/include/hal/uhci_ll.h
Normal file
133
components/hal/esp32h2/include/hal/uhci_ll.h
Normal file
@ -0,0 +1,133 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
#include <stdio.h>
|
||||
#include "hal/uhci_types.h"
|
||||
#include "soc/uhci_struct.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
|
||||
|
||||
typedef enum {
|
||||
UHCI_RX_BREAK_CHR_EOF = 0x1,
|
||||
UHCI_RX_IDLE_EOF = 0x2,
|
||||
UHCI_RX_LEN_EOF = 0x4,
|
||||
UHCI_RX_EOF_MAX = 0x7,
|
||||
} uhci_rxeof_cfg_t;
|
||||
|
||||
static inline void uhci_ll_init(uhci_dev_t *hw)
|
||||
{
|
||||
typeof(hw->conf0) conf0_reg;
|
||||
hw->conf0.clk_en = 1;
|
||||
conf0_reg.val = 0;
|
||||
conf0_reg.clk_en = 1;
|
||||
hw->conf0.val = conf0_reg.val;
|
||||
hw->conf1.val = 0;
|
||||
}
|
||||
|
||||
static inline void uhci_ll_attach_uart_port(uhci_dev_t *hw, int uart_num)
|
||||
{
|
||||
hw->conf0.uart0_ce = (uart_num == 0)? 1: 0;
|
||||
hw->conf0.uart1_ce = (uart_num == 1)? 1: 0;
|
||||
}
|
||||
|
||||
static inline void uhci_ll_set_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_char)
|
||||
{
|
||||
if (seper_char->sub_chr_en) {
|
||||
typeof(hw->esc_conf0) esc_conf0_reg;
|
||||
esc_conf0_reg.val = hw->esc_conf0.val;
|
||||
|
||||
esc_conf0_reg.seper_char = seper_char->seper_chr;
|
||||
esc_conf0_reg.seper_esc_char0 = seper_char->sub_chr1;
|
||||
esc_conf0_reg.seper_esc_char1 = seper_char->sub_chr2;
|
||||
hw->esc_conf0.val = esc_conf0_reg.val;
|
||||
hw->escape_conf.tx_c0_esc_en = 1;
|
||||
hw->escape_conf.rx_c0_esc_en = 1;
|
||||
} else {
|
||||
hw->escape_conf.tx_c0_esc_en = 0;
|
||||
hw->escape_conf.rx_c0_esc_en = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void uhci_ll_get_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_chr)
|
||||
{
|
||||
(void)hw;
|
||||
(void)seper_chr;
|
||||
}
|
||||
|
||||
static inline void uhci_ll_set_swflow_ctrl_sub_chr(uhci_dev_t *hw, uhci_swflow_ctrl_sub_chr_t *sub_ctr)
|
||||
{
|
||||
typeof(hw->escape_conf) escape_conf_reg;
|
||||
escape_conf_reg.val = hw->escape_conf.val;
|
||||
|
||||
if (sub_ctr->flow_en == 1) {
|
||||
typeof(hw->esc_conf2) esc_conf2_reg;
|
||||
esc_conf2_reg.val = hw->esc_conf2.val;
|
||||
typeof(hw->esc_conf3) esc_conf3_reg;
|
||||
esc_conf3_reg.val = hw->esc_conf3.val;
|
||||
|
||||
esc_conf2_reg.esc_seq1 = sub_ctr->xon_chr;
|
||||
esc_conf2_reg.esc_seq1_char0 = sub_ctr->xon_sub1;
|
||||
esc_conf2_reg.esc_seq1_char1 = sub_ctr->xon_sub2;
|
||||
esc_conf3_reg.esc_seq2 = sub_ctr->xoff_chr;
|
||||
esc_conf3_reg.esc_seq2_char0 = sub_ctr->xoff_sub1;
|
||||
esc_conf3_reg.esc_seq2_char1 = sub_ctr->xoff_sub2;
|
||||
escape_conf_reg.tx_11_esc_en = 1;
|
||||
escape_conf_reg.tx_13_esc_en = 1;
|
||||
escape_conf_reg.rx_11_esc_en = 1;
|
||||
escape_conf_reg.rx_13_esc_en = 1;
|
||||
hw->esc_conf2.val = esc_conf2_reg.val;
|
||||
hw->esc_conf3.val = esc_conf3_reg.val;
|
||||
} else {
|
||||
escape_conf_reg.tx_11_esc_en = 0;
|
||||
escape_conf_reg.tx_13_esc_en = 0;
|
||||
escape_conf_reg.rx_11_esc_en = 0;
|
||||
escape_conf_reg.rx_13_esc_en = 0;
|
||||
}
|
||||
hw->escape_conf.val = escape_conf_reg.val;
|
||||
}
|
||||
|
||||
static inline void uhci_ll_enable_intr(uhci_dev_t *hw, uint32_t intr_mask)
|
||||
{
|
||||
hw->int_ena.val |= intr_mask;
|
||||
}
|
||||
|
||||
static inline void uhci_ll_disable_intr(uhci_dev_t *hw, uint32_t intr_mask)
|
||||
{
|
||||
hw->int_ena.val &= (~intr_mask);
|
||||
}
|
||||
|
||||
static inline void uhci_ll_clear_intr(uhci_dev_t *hw, uint32_t intr_mask)
|
||||
{
|
||||
hw->int_clr.val = intr_mask;
|
||||
}
|
||||
|
||||
static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw)
|
||||
{
|
||||
return hw->int_st.val;
|
||||
}
|
||||
|
||||
|
||||
static inline void uhci_ll_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
|
||||
{
|
||||
if (eof_mode & UHCI_RX_BREAK_CHR_EOF) {
|
||||
hw->conf0.uart_rx_brk_eof_en = 1;
|
||||
}
|
||||
if (eof_mode & UHCI_RX_IDLE_EOF) {
|
||||
hw->conf0.uart_idle_eof_en = 1;
|
||||
}
|
||||
if (eof_mode & UHCI_RX_LEN_EOF) {
|
||||
hw->conf0.len_eof_en = 1;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user