Merge branch 'bugfix/renable_unit_tests_v4.3' into 'release/v4.3'

ci: enable previously disabled unit tests (v4.3)

See merge request espressif/esp-idf!13775

components/driver/test/test_spi_master.c

@@ -1050,7 +1050,6 @@ TEST_CASE("SPI master hd dma TX without RX test", "[spi]")
 #endif  //#if !DISABLED_FOR_TARGETS(ESP32C3)
 
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C3)
 /********************************************************************************
  *      Test SPI transaction interval
  ********************************************************************************/
@@ -1058,8 +1057,8 @@ TEST_CASE("SPI master hd dma TX without RX test", "[spi]")
 #ifndef CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE
 
 #define RECORD_TIME_PREPARE() uint32_t __t1, __t2
-#define RECORD_TIME_START()   do {__t1 = xthal_get_ccount();}while(0)
+#define RECORD_TIME_START()   do {__t1 = esp_cpu_get_ccount();}while(0)
-#define RECORD_TIME_END(p_time) do{__t2 = xthal_get_ccount(); *p_time = (__t2-__t1);}while(0)
+#define RECORD_TIME_END(p_time) do{__t2 = esp_cpu_get_ccount(); *p_time = (__t2-__t1);}while(0)
 #ifdef CONFIG_IDF_TARGET_ESP32
 #define GET_US_BY_CCOUNT(t) ((double)t/CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
 #elif CONFIG_IDF_TARGET_ESP32S2
@@ -1203,5 +1202,3 @@ TEST_CASE("spi_speed","[spi]")
     master_free_device_bus(spi);
 }
 #endif // CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE
-
-#endif // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C3)

components/driver/test/test_spi_sio.c

@@ -24,7 +24,8 @@
 
 #include "hal/spi_ll.h"
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C3)
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
+#if !DISABLED_FOR_TARGETS(ESP32C3)  //There is only one GPSPI controller, so single-board test is disabled.
 
 /********************************************************************************
  *      Test SIO
@@ -101,6 +102,8 @@ TEST_CASE("local test sio", "[spi]")
     spi_slave_free(TEST_SLAVE_HOST);
     master_free_device_bus(spi);
 }
+#endif //!DISABLED_FOR_TARGETS(ESP32C3)  //There is only one GPSPI controller, so single-board test is disabled.
+
 
 #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3)
 //These tests are ESP32 only due to lack of runners

components/esp_pm/test/test_pm.c

@@ -26,6 +26,8 @@
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/clk.h"
 #include "esp32s3/ulp.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/clk.h"
 #endif
 
 TEST_CASE("Can dump power management lock stats", "[pm]")
@@ -44,6 +46,8 @@ static void switch_freq(int mhz)
     esp_pm_config_esp32s2_t pm_config = {
 #elif CONFIG_IDF_TARGET_ESP32S3
     esp_pm_config_esp32s3_t pm_config = {
+#elif CONFIG_IDF_TARGET_ESP32C3
+    esp_pm_config_esp32c3_t pm_config = {
 #endif
         .max_freq_mhz = mhz,
         .min_freq_mhz = MIN(mhz, xtal_freq),
@@ -56,22 +60,21 @@ static void switch_freq(int mhz)
     }
 }
 
+#if CONFIG_IDF_TARGET_ESP32C3
+static const int test_freqs[] = {40, 160, 80, 40, 80, 10, 80, 20, 40};
+#else
+static const int test_freqs[] = {240, 40, 160, 240, 80, 40, 240, 40, 80, 10, 80, 20, 40};
+#endif
+
+
 TEST_CASE("Can switch frequency using esp_pm_configure", "[pm]")
 {
     int orig_freq_mhz = esp_clk_cpu_freq() / MHZ;
-    switch_freq(240);
+
-    switch_freq(40);
+    for (int i = 0; i < sizeof(test_freqs)/sizeof(int); i++) {
-    switch_freq(160);
+        switch_freq(test_freqs[i]);
-    switch_freq(240);
+    }
-    switch_freq(80);
+
-    switch_freq(40);
-    switch_freq(240);
-    switch_freq(40);
-    switch_freq(80);
-    switch_freq(10);
-    switch_freq(80);
-    switch_freq(20);
-    switch_freq(40);
     switch_freq(orig_freq_mhz);
 }
 
@@ -88,6 +91,8 @@ static void light_sleep_enable(void)
     esp_pm_config_esp32s2_t pm_config = {
 #elif CONFIG_IDF_TARGET_ESP32S3
     esp_pm_config_esp32s3_t pm_config = {
+#elif CONFIG_IDF_TARGET_ESP32C3
+    esp_pm_config_esp32c3_t pm_config = {
 #endif
         .max_freq_mhz = cur_freq_mhz,
         .min_freq_mhz = xtal_freq,
@@ -106,6 +111,8 @@ static void light_sleep_disable(void)
     esp_pm_config_esp32s2_t pm_config = {
 #elif CONFIG_IDF_TARGET_ESP32S3
     esp_pm_config_esp32s3_t pm_config = {
+#elif CONFIG_IDF_TARGET_ESP32C3
+    esp_pm_config_esp32c3_t pm_config = {
 #endif
         .max_freq_mhz = cur_freq_mhz,
         .min_freq_mhz = cur_freq_mhz,
@@ -154,6 +161,9 @@ TEST_CASE("Automatic light occurs when tasks are suspended", "[pm]")
 }
 
 #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3)
+#if !DISABLED_FOR_TARGETS(ESP32C3)
+// No ULP on C3
+
 // Fix failure on ESP32 when running alone; passes when the previous test is run before this one
 TEST_CASE("Can wake up from automatic light sleep by GPIO", "[pm][ignore]")
 {
@@ -227,7 +237,9 @@ TEST_CASE("Can wake up from automatic light sleep by GPIO", "[pm][ignore]")
 
     light_sleep_disable();
 }
-#endif
+#endif //!DISABLED_FOR_TARGETS(ESP32C3)
+#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3)
+
 typedef struct {
     int delay_us;
     int result;

components/esp_rom/test/test_miniz.c

@@ -10,6 +10,7 @@
 #ifdef CONFIG_SPIRAM
 
 #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32)
+// miniz unit test can't pass on ESP32 non-ECO3 version IDF-1807
 
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/miniz.h"

components/esp_system/port/soc/esp32s2/clk.c

@@ -35,6 +35,7 @@
 #include "driver/periph_ctrl.h"
 #include "bootloader_clock.h"
 #include "soc/syscon_reg.h"
+#include "hal/clk_gate_ll.h"
 
 static const char *TAG = "clk";
 
@@ -313,6 +314,8 @@ __attribute__((weak)) void esp_perip_clk_init(void)
     DPORT_CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_8M);
     DPORT_SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_RTC_SLOW);
 
+    periph_ll_reset(PERIPH_SYSTIMER_MODULE);
+
     /* Enable RNG clock. */
     periph_module_enable(PERIPH_RNG_MODULE);
 }

components/esp_system/test/test_sleep.c

@@ -20,7 +20,7 @@
 #include "esp_rom_sys.h"
 #include "esp_timer.h"
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C3, ESP32S3)
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
 
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/clk.h"
@@ -66,7 +66,6 @@ TEST_CASE("wake up from deep sleep using timer", "[deepsleep][reset=DEEPSLEEP_RE
     esp_deep_sleep_start();
 }
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3)
 TEST_CASE("light sleep followed by deep sleep", "[deepsleep][reset=DEEPSLEEP_RESET]")
 {
     esp_sleep_enable_timer_wakeup(1000000);
@@ -85,7 +84,6 @@ TEST_CASE("wake up from light sleep using timer", "[deepsleep]")
                (tv_stop.tv_usec - tv_start.tv_usec) * 1e-3f;
     TEST_ASSERT_INT32_WITHIN(500, 2000, (int) dt);
 }
-#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3)
 
 static void test_light_sleep(void* arg)
 {
@@ -194,7 +192,12 @@ TEST_CASE("light sleep duration is correct", "[deepsleep][ignore]")
 TEST_CASE("light sleep and frequency switching", "[deepsleep]")
 {
 #ifndef CONFIG_PM_ENABLE
-    uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), UART_SCLK_REF_TICK);
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+    uart_sclk_t clk_source = UART_SCLK_REF_TICK;
+#else
+    uart_sclk_t clk_source = UART_SCLK_XTAL;
+#endif
+    uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), clk_source);
     uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE);
 #endif
 
@@ -350,6 +353,8 @@ TEST_CASE_MULTIPLE_STAGES("can set sleep wake stub from stack in RTC RAM", "[dee
 
 #endif // CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
 
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
+
 TEST_CASE("wake up using ext0 (13 high)", "[deepsleep][ignore]")
 {
     ESP_ERROR_CHECK(rtc_gpio_init(GPIO_NUM_13));
@@ -420,7 +425,9 @@ __attribute__((unused)) static uint32_t get_cause(void)
     return wakeup_cause;
 }
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3)
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
+// Fails on S2 IDF-2903
+
 // This test case verifies deactivation of trigger for wake up sources
 TEST_CASE("disable source trigger behavior", "[deepsleep]")
 {
@@ -493,7 +500,9 @@ TEST_CASE("disable source trigger behavior", "[deepsleep]")
     // Disable ext0 wakeup source, as this might interfere with other tests
     ESP_ERROR_CHECK(esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_EXT0));
 }
-#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3)
+#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
+
+#endif //SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
 
 static RTC_DATA_ATTR struct timeval start;
 static void trigger_deepsleep(void)
@@ -530,7 +539,7 @@ static void check_time_deepsleep(void)
 
 TEST_CASE_MULTIPLE_STAGES("check a time after wakeup from deep sleep", "[deepsleep][reset=DEEPSLEEP_RESET]", trigger_deepsleep, check_time_deepsleep);
 
-#endif // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C3, ESP32S3)
+#endif // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
 
 #if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
 static void gpio_deepsleep_wakeup_config(void)

components/esp_timer/test/test_esp_timer_light_sleep.c

@@ -9,8 +9,7 @@
 #include "esp_sleep.h"
 
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C3) // IDF-1780 ESP32-S3 Deep sleep and light sleep
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) // IDF-1780 ESP32-S3 Deep sleep and light sleep
-// TODO ESP32-C3 IDF-2571
 
 static void timer_cb1(void *arg)
 {
@@ -50,4 +49,4 @@ TEST_CASE("Test the periodic timer does not handle lost events during light slee
     TEST_ESP_OK(esp_timer_delete(periodic_timer));
 }
 
-#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C3)
+#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)

components/newlib/port/esp_time_impl.c

@@ -51,7 +51,7 @@
 // Offset between FRC timer and the RTC.
 // Initialized after reset or light sleep.
 #if defined(CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER) && defined(CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER)
-uint64_t s_microseconds_offset;
+uint64_t s_microseconds_offset = 0;
 #endif
 
 #ifndef CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER

examples/system/esp_event/default_event_loop/example_test.py

@@ -81,7 +81,7 @@ def _test_iteration_events(dut):
     print('Deleted task event source')
 
 
-@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32'])
+@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32', 'esp32c3'])
 def test_default_event_loop_example(env, extra_data):
     dut = env.get_dut('default_event_loop', 'examples/system/esp_event/default_event_loop')
 

examples/system/light_sleep/README.md

@@ -1,5 +1,3 @@
-| Supported Targets | ESP32 | ESP32-S2 |
-| ----------------- | ----- | -------- |
 # Light Sleep Example
 
 (See the README.md file in the upper level 'examples' directory for more information about examples.)

examples/system/light_sleep/example_test.py

@@ -7,12 +7,12 @@ import ttfw_idf
 
 ENTERING_SLEEP_STR = 'Entering light sleep'
 EXIT_SLEEP_REGEX = re.compile(r'Returned from light sleep, reason: (\w+), t=(\d+) ms, slept for (\d+) ms')
-WAITING_FOR_GPIO_STR = 'Waiting for GPIO0 to go high...'
+WAITING_FOR_GPIO_STR = re.compile(r'Waiting for GPIO\d to go high...')
 
 WAKEUP_INTERVAL_MS = 2000
 
 
-@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32'])
+@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32', 'esp32c3'])
 def test_examples_system_light_sleep(env, extra_data):
     dut = env.get_dut('light_sleep_example', 'examples/system/light_sleep')
     dut.start_app()

examples/system/light_sleep/main/light_sleep_example_main.c

@@ -29,7 +29,7 @@
 #define BUTTON_GPIO_NUM_DEFAULT     0
 #endif
 
-/* "Boot" button on GPIO0 is active low */
+/* "Boot" button is active low */
 #define BUTTON_WAKEUP_LEVEL_DEFAULT     0
 
 void app_main(void)

tools/unit-test-app/configs/pm_c3

@@ -0,0 +1,4 @@
+CONFIG_IDF_TARGET="esp32c3"
+TEST_COMPONENTS=esp_pm
+CONFIG_PM_ENABLE=y
+CONFIG_FREERTOS_USE_TICKLESS_IDLE=y