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feat(driver_spi): add esp32c61 spi master, slave, slave_hd support

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This commit is contained in:
wanckl 2024-08-19 10:17:37 +08:00 committed by Wan Lei
parent b70f41ca7a
commit e6e7b23917
34 changed files with 260 additions and 155 deletions
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4
components/esp_driver_sdspi/test_apps/sdspi/README.md
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@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

17
components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h
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@ -75,12 +75,19 @@
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 12 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 12
#elif CONFIG_IDF_TARGET_ESP32C5 #elif CONFIG_IDF_TARGET_ESP32C5
//TODO: IDF-10002 update after chips back and PLL setup
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000 #define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 1000 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 24
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 1000 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 1000 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 22
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 1000 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 12
#elif CONFIG_IDF_TARGET_ESP32C61
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 17
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 29
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 14
#else #else
#pragma message "`spi_performance.h` is not updated with your target"
#endif #endif

4
components/esp_driver_spi/test_apps/master/README.md
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@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

7
components/esp_driver_spi/test_apps/master/main/test_spi_master.c
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@ -80,6 +80,7 @@ static void check_spi_pre_n_for(int clk, int pre, int n)
#define TEST_CLK_TIMES 8 #define TEST_CLK_TIMES 8
uint32_t clk_param_80m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 16, 50}, {333333, 4, 60}, {800000, 2, 50}, {900000, 2, 44}, {8000000, 1, 10}, {20000000, 1, 4}, {26000000, 1, 3} }; uint32_t clk_param_80m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 16, 50}, {333333, 4, 60}, {800000, 2, 50}, {900000, 2, 44}, {8000000, 1, 10}, {20000000, 1, 4}, {26000000, 1, 3} };
uint32_t clk_param_48m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 8, 60}, {333333, 3, 48}, {800000, 1, 60}, {5000000, 1, 10}, {12000000, 1, 4}, {18000000, 1, 3}, {26000000, 1, 2} }; uint32_t clk_param_48m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 8, 60}, {333333, 3, 48}, {800000, 1, 60}, {5000000, 1, 10}, {12000000, 1, 4}, {18000000, 1, 3}, {26000000, 1, 2} };
uint32_t clk_param_160m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 16, 50}, {333333, 4, 60}, {800000, 2, 50}, {900000, 2, 44}, {8000000, 1, 10}, {20000000, 1, 4}, {26000000, 1, 3} };
#if SPI_LL_SUPPORT_CLK_SRC_PRE_DIV #if SPI_LL_SUPPORT_CLK_SRC_PRE_DIV
uint32_t clk_param_40m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 4, 50}, {333333, 1, 60}, {800000, 1, 25}, {2000000, 1, 10}, {5000000, 1, 4}, {12000000, 1, 2}, {18000000, 1, 1} }; uint32_t clk_param_40m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 4, 50}, {333333, 1, 60}, {800000, 1, 25}, {2000000, 1, 10}, {5000000, 1, 4}, {12000000, 1, 2}, {18000000, 1, 1} };
#else #else
@ -94,7 +95,11 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")
esp_clk_tree_src_get_freq_hz(SPI_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz); esp_clk_tree_src_get_freq_hz(SPI_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
printf("\nTest clock source SPI_CLK_SRC_DEFAULT = %ld\n", clock_source_hz); printf("\nTest clock source SPI_CLK_SRC_DEFAULT = %ld\n", clock_source_hz);
if ((80 * 1000 * 1000) == clock_source_hz) { if ((160 * 1000 * 1000) == clock_source_hz) {
for (int i = 0; i < TEST_CLK_TIMES; i++) {
check_spi_pre_n_for(clk_param_160m[i][0], clk_param_160m[i][1], clk_param_160m[i][2]);
}
} else if ((80 * 1000 * 1000) == clock_source_hz) {
for (int i = 0; i < TEST_CLK_TIMES; i++) { for (int i = 0; i < TEST_CLK_TIMES; i++) {
check_spi_pre_n_for(clk_param_80m[i][0], clk_param_80m[i][1], clk_param_80m[i][2]); check_spi_pre_n_for(clk_param_80m[i][0], clk_param_80m[i][1], clk_param_80m[i][2]);
} }

4
components/esp_driver_spi/test_apps/param/README.md
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@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

4
components/esp_driver_spi/test_apps/slave/README.md
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@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

4
components/esp_driver_spi/test_apps/slave_hd/README.md
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@ -1,2 +1,2 @@
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

4
components/esp_lcd/test_apps/spi_lcd/README.md
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@ -1,4 +1,4 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
This test app is used to test LCDs with SPI interface. This test app is used to test LCDs with SPI interface.

40
components/hal/esp32c61/include/hal/spi_ll.h
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@ -26,8 +26,6 @@
#include "hal/spi_types.h" #include "hal/spi_types.h"
#include "soc/pcr_struct.h" #include "soc/pcr_struct.h"
// TODO: [ESP32C61] IDF-9299, inherit from c6
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
@ -44,6 +42,8 @@ extern "C" {
#define SPI_LL_DMA_MAX_BIT_LEN (1 << 18) //reg len: 18 bits #define SPI_LL_DMA_MAX_BIT_LEN (1 << 18) //reg len: 18 bits
#define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words #define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words
#define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized #define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized
#define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV 1 //clock source have divider before peripheral
#define SPI_LL_CLK_SRC_PRE_DIV_MAX 256//div1(8bit)
/** /**
* The data structure holding calculated clock configuration. Since the * The data structure holding calculated clock configuration. Since the
@ -167,6 +167,24 @@ static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_s
} }
} }
/**
* Config clock source integrate pre_div before it enter GPSPI peripheral
*
* @note 1. For timing turning(e.g. input_delay) feature available, should be (mst_div >= 2)
* 2. From peripheral limitation: (sour_freq/hs_div <= 160M) and (sour_freq/hs_div/mst_div <= 80M)
*
* @param hw Beginning address of the peripheral registers.
* @param hs_div Timing turning clock divider: (hs_clk_o = sour_freq/hs_div)
* @param mst_div Functional output clock divider: (mst_clk_o = sour_freq/hs_div/mst_div)
*/
__attribute__((always_inline))
static inline void spi_ll_clk_source_pre_div(spi_dev_t *hw, uint8_t hs_div, uint8_t mst_div)
{
// In IDF master driver 'mst_div' will be const 2 and 'hs_div' is actually pre_div temporally
(void) hs_div;
PCR.spi2_clkm_conf.spi2_clkm_div_num = mst_div - 1;
}
/** /**
* Initialize SPI peripheral (master). * Initialize SPI peripheral (master).
* *
@ -309,7 +327,7 @@ static inline void spi_ll_slave_reset(spi_dev_t *hw)
/** /**
* Reset SPI CPU TX FIFO * Reset SPI CPU TX FIFO
* *
* On ESP32C3, this function is not seperated * On ESP32C61, this function is not separated
* *
* @param hw Beginning address of the peripheral registers. * @param hw Beginning address of the peripheral registers.
*/ */
@ -322,7 +340,7 @@ static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw)
/** /**
* Reset SPI CPU RX FIFO * Reset SPI CPU RX FIFO
* *
* On ESP32C3, this function is not seperated * On ESP32C61, this function is not separated
* *
* @param hw Beginning address of the peripheral registers. * @param hw Beginning address of the peripheral registers.
*/ */
@ -707,7 +725,7 @@ static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, const spi_ll_cl
* Get the frequency of given dividers. Don't use in app. * Get the frequency of given dividers. Don't use in app.
* *
* @param fapb APB clock of the system. * @param fapb APB clock of the system.
* @param pre Pre devider. * @param pre Pre divider.
* @param n Main divider. * @param n Main divider.
* *
* @return Frequency of given dividers. * @return Frequency of given dividers.
@ -718,10 +736,10 @@ static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n)
} }
/** /**
* Calculate the nearest frequency avaliable for master. * Calculate the nearest frequency available for master.
* *
* @param fapb APB clock of the system. * @param fapb APB clock of the system.
* @param hz Frequncy desired. * @param hz Frequency desired.
* @param duty_cycle Duty cycle desired. * @param duty_cycle Duty cycle desired.
* @param out_reg Output address to store the calculated clock configurations for the return frequency. * @param out_reg Output address to store the calculated clock configurations for the return frequency.
* *
@ -801,7 +819,7 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_
* *
* @param hw Beginning address of the peripheral registers. * @param hw Beginning address of the peripheral registers.
* @param fapb APB clock of the system. * @param fapb APB clock of the system.
* @param hz Frequncy desired. * @param hz Frequency desired.
* @param duty_cycle Duty cycle desired. * @param duty_cycle Duty cycle desired.
* *
* @return Actual frequency that is used. * @return Actual frequency that is used.
@ -855,7 +873,7 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold)
/** /**
* Set the delay of SPI clocks before the first SPI clock after the CS active edge. * Set the delay of SPI clocks before the first SPI clock after the CS active edge.
* *
* Note ESP32 doesn't support to use this feature when command/address phases * Note ESP32C61 doesn't support to use this feature when command/address phases
* are used in full duplex mode. * are used in full duplex mode.
* *
* @param hw Beginning address of the peripheral registers. * @param hw Beginning address of the peripheral registers.
@ -905,7 +923,7 @@ static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen)
*/ */
static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen) static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen)
{ {
//This is not used in esp32c3 //This is not used in esp32c61
} }
/** /**
@ -916,7 +934,7 @@ static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen)
*/ */
static inline void spi_ll_slave_set_tx_bitlen(spi_dev_t *hw, size_t bitlen) static inline void spi_ll_slave_set_tx_bitlen(spi_dev_t *hw, size_t bitlen)
{ {
//This is not used in esp32c3 //This is not used in esp32c61
} }
/** /**

28
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
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@ -51,6 +51,10 @@ config SOC_RTC_MEM_SUPPORTED
bool bool
default y default y
config SOC_GPSPI_SUPPORTED
bool
default y
config SOC_I2C_SUPPORTED config SOC_I2C_SUPPORTED
bool bool
default y default y
@ -439,6 +443,30 @@ config SOC_SPI_MAX_CS_NUM
int int
default 6 default 6
config SOC_SPI_MAX_PRE_DIVIDER
int
default 16
config SOC_SPI_MAXIMUM_BUFFER_SIZE
int
default 64
config SOC_SPI_SUPPORT_SLAVE_HD_VER2
bool
default y
config SOC_SPI_SUPPORT_CLK_XTAL
bool
default y
config SOC_SPI_SUPPORT_CLK_PLL
bool
default y
config SOC_SPI_SUPPORT_CLK_RC_FAST
bool
default y
config SOC_MEMSPI_IS_INDEPENDENT config SOC_MEMSPI_IS_INDEPENDENT
bool bool
default y default y

6
components/soc/esp32c61/include/soc/clk_tree_defs.h
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@ -246,16 +246,16 @@ typedef enum {
/** /**
* @brief Array initializer for all supported clock sources of SPI * @brief Array initializer for all supported clock sources of SPI
*/ */
#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} #define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/** /**
* @brief Type of SPI clock source. * @brief Type of SPI clock source.
*/ */
typedef enum { typedef enum {
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */ SPI_CLK_SRC_PLL_F160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as SPI source clock */
SPI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */
SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */ SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */ SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */
SPI_CLK_SRC_DEFAULT = SPI_CLK_SRC_PLL_F160M, /*!< Select PLL_160M as default SPI source clock */
} soc_periph_spi_clk_src_t; } soc_periph_spi_clk_src_t;
//////////////////////////////////////////////////GPIO Glitch Filter//////////////////////////////////////////////////// //////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////

30
components/soc/esp32c61/include/soc/soc_caps.h
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@ -36,7 +36,7 @@
#define SOC_RTC_FAST_MEM_SUPPORTED 1 #define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1 //TODO: [ESP32C61] IDF-9274 #define SOC_RTC_MEM_SUPPORTED 1 //TODO: [ESP32C61] IDF-9274
// \#define SOC_I2S_SUPPORTED 1 //TODO: [ESP32C61] IDF-9312, IDF-9313 // \#define SOC_I2S_SUPPORTED 1 //TODO: [ESP32C61] IDF-9312, IDF-9313
// \#define SOC_GPSPI_SUPPORTED 1 //TODO: [ESP32C61] IDF-9299, IDF-9300, IDF-9301 #define SOC_GPSPI_SUPPORTED 1
#define SOC_I2C_SUPPORTED 1 #define SOC_I2C_SUPPORTED 1
#define SOC_LEDC_SUPPORTED 1 #define SOC_LEDC_SUPPORTED 1
#define SOC_SYSTIMER_SUPPORTED 1 //TODO: [ESP32C61] IDF-9307, IDF-9308 #define SOC_SYSTIMER_SUPPORTED 1 //TODO: [ESP32C61] IDF-9307, IDF-9308
@ -296,26 +296,20 @@
#define SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE (1) #define SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE (1)
/*-------------------------- SPI CAPS ----------------------------------------*/ /*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2 #define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 6 #define SOC_SPI_PERIPH_CS_NUM(i) 6
#define SOC_SPI_MAX_CS_NUM 6 #define SOC_SPI_MAX_CS_NUM 6
#define SOC_SPI_MAX_PRE_DIVIDER 16
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
// #define SOC_SPI_MAX_PRE_DIVIDER 16 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
// #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 #define SOC_SPI_SUPPORT_CLK_XTAL 1
#define SOC_SPI_SUPPORT_CLK_PLL 1
#define SOC_SPI_SUPPORT_CLK_RC_FAST 1
// #define SOC_SPI_SUPPORT_DDRCLK 1 // Peripheral supports DIO, DOUT, QIO, or QOUT
// #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 // host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
// #define SOC_SPI_SUPPORT_CD_SIG 1
// #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
// #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 // TODO : [ESP32C61] IDF-9301
// #define SOC_SPI_SUPPORT_CLK_XTAL 1
// #define SOC_SPI_SUPPORT_CLK_PLL_F80M 1
// #define SOC_SPI_SUPPORT_CLK_RC_FAST 1
// // Peripheral supports DIO, DOUT, QIO, or QOUT
// // host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
#define SOC_MEMSPI_IS_INDEPENDENT 1 #define SOC_MEMSPI_IS_INDEPENDENT 1
/*-------------------------- SPI MEM CAPS ---------------------------------------*/ /*-------------------------- SPI MEM CAPS ---------------------------------------*/

20
components/soc/esp32c61/include/soc/spi_pins.h
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@ -4,9 +4,6 @@
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#ifndef _SOC_SPI_PINS_H_
#define _SOC_SPI_PINS_H_
#define SPI_FUNC_NUM 0 #define SPI_FUNC_NUM 0
#define SPI_IOMUX_PIN_NUM_CS 24 #define SPI_IOMUX_PIN_NUM_CS 24
#define SPI_IOMUX_PIN_NUM_CLK 29 #define SPI_IOMUX_PIN_NUM_CLK 29
@ -15,12 +12,11 @@
#define SPI_IOMUX_PIN_NUM_WP 26 #define SPI_IOMUX_PIN_NUM_WP 26
#define SPI_IOMUX_PIN_NUM_HD 28 #define SPI_IOMUX_PIN_NUM_HD 28
#define SPI2_FUNC_NUM 2 // GPSPI2 IOMUX PINs
#define SPI2_IOMUX_PIN_NUM_MISO 2 #define SPI2_FUNC_NUM 2
#define SPI2_IOMUX_PIN_NUM_HD 4 #define SPI2_IOMUX_PIN_NUM_MISO 2
#define SPI2_IOMUX_PIN_NUM_WP 5 #define SPI2_IOMUX_PIN_NUM_HD 3
#define SPI2_IOMUX_PIN_NUM_CLK 6 #define SPI2_IOMUX_PIN_NUM_WP 4
#define SPI2_IOMUX_PIN_NUM_MOSI 7 #define SPI2_IOMUX_PIN_NUM_CLK 6
#define SPI2_IOMUX_PIN_NUM_CS 16 #define SPI2_IOMUX_PIN_NUM_MOSI 7
#define SPI2_IOMUX_PIN_NUM_CS 8
#endif

64
components/soc/esp32c61/spi_periph.c Normal file
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@ -0,0 +1,64 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stddef.h>
#include "soc/spi_periph.h"
/*
Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
{
// MSPI has dedicated iomux pins
.spiclk_out = -1,
.spiclk_in = -1,
.spid_out = -1,
.spiq_out = -1,
.spiwp_out = -1,
.spihd_out = -1,
.spid_in = -1,
.spiq_in = -1,
.spiwp_in = -1,
.spihd_in = -1,
.spics_out = {-1},
.spics_in = -1,
.spiclk_iomux_pin = -1,
.spid_iomux_pin = -1,
.spiq_iomux_pin = -1,
.spiwp_iomux_pin = -1,
.spihd_iomux_pin = -1,
.spics0_iomux_pin = -1,
.irq = -1,
.irq_dma = -1,
.module = -1,
.hw = NULL,
.func = -1,
}, {
.spiclk_out = FSPICLK_OUT_IDX,
.spiclk_in = FSPICLK_IN_IDX,
.spid_out = FSPID_OUT_IDX,
.spiq_out = FSPIQ_OUT_IDX,
.spiwp_out = FSPIWP_OUT_IDX,
.spihd_out = FSPIHD_OUT_IDX,
.spid_in = FSPID_IN_IDX,
.spiq_in = FSPIQ_IN_IDX,
.spiwp_in = FSPIWP_IN_IDX,
.spihd_in = FSPIHD_IN_IDX,
.spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX, FSPICS3_OUT_IDX, FSPICS4_OUT_IDX, FSPICS5_OUT_IDX},
.spics_in = FSPICS0_IN_IDX,
.spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK,
.spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI,
.spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO,
.spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP,
.spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD,
.spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
.irq = ETS_GPSPI2_INTR_SOURCE,
.irq_dma = -1,
.module = -1,
.hw = &GPSPI2,
.func = SPI2_FUNC_NUM,
},
};

4
docs/docs_not_updated/esp32c5.txt
View File

@ -65,7 +65,6 @@ api-reference/storage/nvs_partition_parse.rst
api-reference/peripherals/sdspi_share.rst api-reference/peripherals/sdspi_share.rst
api-reference/peripherals/twai.rst api-reference/peripherals/twai.rst
api-reference/peripherals/sdspi_host.rst api-reference/peripherals/sdspi_host.rst
api-reference/peripherals/spi_slave.rst
api-reference/peripherals/gptimer.rst api-reference/peripherals/gptimer.rst
api-reference/peripherals/touch_element.rst api-reference/peripherals/touch_element.rst
api-reference/peripherals/lcd.rst api-reference/peripherals/lcd.rst
@ -78,9 +77,7 @@ api-reference/peripherals/spi_flash/spi_flash_idf_vs_rom.rst
api-reference/peripherals/spi_flash/index.rst api-reference/peripherals/spi_flash/index.rst
api-reference/peripherals/touch_pad.rst api-reference/peripherals/touch_pad.rst
api-reference/peripherals/adc_calibration.rst api-reference/peripherals/adc_calibration.rst
api-reference/peripherals/spi_slave_hd.rst
api-reference/peripherals/sd_pullup_requirements.rst api-reference/peripherals/sd_pullup_requirements.rst
api-reference/peripherals/spi_master.rst
api-reference/peripherals/index.rst api-reference/peripherals/index.rst
api-reference/peripherals/sdmmc_host.rst api-reference/peripherals/sdmmc_host.rst
api-reference/peripherals/ecdsa.rst api-reference/peripherals/ecdsa.rst
@ -136,7 +133,6 @@ api-reference/protocols/icmp_echo.rst
api-reference/protocols/esp_serial_slave_link.rst api-reference/protocols/esp_serial_slave_link.rst
api-reference/protocols/mqtt.rst api-reference/protocols/mqtt.rst
api-reference/protocols/esp_crt_bundle.rst api-reference/protocols/esp_crt_bundle.rst
api-reference/protocols/esp_spi_slave_protocol.rst
api-reference/protocols/modbus.rst api-reference/protocols/modbus.rst
api-reference/protocols/esp_tls.rst api-reference/protocols/esp_tls.rst
api-reference/protocols/mdns.rst api-reference/protocols/mdns.rst

4
docs/docs_not_updated/esp32c61.txt
View File

@ -89,7 +89,6 @@ api-reference/peripherals/usb_device.rst
api-reference/peripherals/gpio.rst api-reference/peripherals/gpio.rst
api-reference/peripherals/sdspi_host.rst api-reference/peripherals/sdspi_host.rst
api-reference/peripherals/dac.rst api-reference/peripherals/dac.rst
api-reference/peripherals/spi_slave.rst
api-reference/peripherals/etm.rst api-reference/peripherals/etm.rst
api-reference/peripherals/i2s.rst api-reference/peripherals/i2s.rst
api-reference/peripherals/touch_element.rst api-reference/peripherals/touch_element.rst
@ -111,11 +110,9 @@ api-reference/peripherals/lcd/dsi_lcd.rst
api-reference/peripherals/lcd/index.rst api-reference/peripherals/lcd/index.rst
api-reference/peripherals/lcd/rgb_lcd.rst api-reference/peripherals/lcd/rgb_lcd.rst
api-reference/peripherals/adc_calibration.rst api-reference/peripherals/adc_calibration.rst
api-reference/peripherals/spi_slave_hd.rst
api-reference/peripherals/parlio.rst api-reference/peripherals/parlio.rst
api-reference/peripherals/ds.rst api-reference/peripherals/ds.rst
api-reference/peripherals/sd_pullup_requirements.rst api-reference/peripherals/sd_pullup_requirements.rst
api-reference/peripherals/spi_master.rst
api-reference/peripherals/index.rst api-reference/peripherals/index.rst
api-reference/peripherals/sdmmc_host.rst api-reference/peripherals/sdmmc_host.rst
api-reference/peripherals/ecdsa.rst api-reference/peripherals/ecdsa.rst
@ -223,7 +220,6 @@ api-reference/protocols/esp_local_ctrl.rst
api-reference/protocols/esp_crt_bundle.rst api-reference/protocols/esp_crt_bundle.rst
api-reference/protocols/esp_http_client.rst api-reference/protocols/esp_http_client.rst
api-reference/protocols/esp_https_server.rst api-reference/protocols/esp_https_server.rst
api-reference/protocols/esp_spi_slave_protocol.rst
api-reference/protocols/modbus.rst api-reference/protocols/modbus.rst
api-reference/protocols/esp_tls.rst api-reference/protocols/esp_tls.rst
api-reference/protocols/mdns.rst api-reference/protocols/mdns.rst

20
docs/en/api-reference/peripherals/spi_master.rst
View File

@ -473,12 +473,12 @@ GPIO Matrix and IO_MUX
.. only:: not esp32 .. only:: not esp32
{IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7", esp32c5="10"} {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7" , esp32c5="10", esp32c61="8"}
{IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9", esp32c5="6"} {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9" , esp32c5="6", esp32c61="6"}
{IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8", esp32c5="7"} {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8" , esp32c5="7", esp32c61="7"}
{IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10", esp32c5="2"} {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10", esp32c5="2", esp32c61="2"}
{IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3", esp32p4="6", esp32c5="4"} {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3", esp32p4="6" , esp32c5="4", esp32c61="3"}
{IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2", esp32p4="11", esp32c5="5"} {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2", esp32p4="11", esp32c5="5", esp32c61="4"}
Most of the chip's peripheral signals have a direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it. Most of the chip's peripheral signals have a direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it.
@ -524,10 +524,10 @@ The main parameter that determines the transfer speed for large transactions is
Transaction Duration Transaction Duration
^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^
{IDF_TARGET_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58"} {IDF_TARGET_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58", esp32p4="44", esp32c5="24", esp32c61="32"}
{IDF_TARGET_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9", esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28"} {IDF_TARGET_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9", esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28", esp32p4="27", esp32c5="15", esp32c61="17"}
{IDF_TARGET_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54"} {IDF_TARGET_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54", esp32p4="26", esp32c5="22", esp32c61="29"}
{IDF_TARGET_TRANS_TIME_POLL_CPU:default="N/A", esp32="8", esp32s2="8", esp32c3="9", esp32s3="9", esp32c2="15", esp32c6="15", esp32h2="24"} {IDF_TARGET_TRANS_TIME_POLL_CPU:default="N/A", esp32="8", esp32s2="8", esp32c3="9", esp32s3="9", esp32c2="15", esp32c6="15", esp32h2="24", esp32p4="12", esp32c5="12", esp32c61="14"}
Transaction duration includes setting up SPI peripheral registers, copying data to FIFOs or setting up DMA links, and the time for SPI transactions. Transaction duration includes setting up SPI peripheral registers, copying data to FIFOs or setting up DMA links, and the time for SPI transactions.

12
docs/en/api-reference/peripherals/spi_slave.rst
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@ -141,12 +141,12 @@ GPIO Matrix and IO_MUX
.. only:: not esp32 .. only:: not esp32
{IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7"} {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7" , esp32c5="10", esp32c61="8"}
{IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9"} {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9" , esp32c5="6", esp32c61="6"}
{IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8"} {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8" , esp32c5="7", esp32c61="7"}
{IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10"} {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10", esp32c5="2", esp32c61="2"}
{IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3", esp32p4="6"} {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3", esp32p4="6" , esp32c5="4", esp32c61="3"}
{IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2", esp32p4="11"} {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2", esp32p4="11", esp32c5="5", esp32c61="4"}
Most of chip's peripheral signals have direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it. Most of chip's peripheral signals have direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it.

30
docs/en/api-reference/protocols/esp_spi_slave_protocol.rst
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@ -14,21 +14,21 @@ ESP SPI Slave HD (Half Duplex) Mode Protocol
SPI Slave Capabilities of Espressif Chips SPI Slave Capabilities of Espressif Chips
----------------------------------------- -----------------------------------------
+------------------+-------+----------+----------+----------+----------+----------+----------+----------+ +------------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
| | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 | ESP32-C2 | ESP32-C6 | ESP32-H2 | ESP32-P4 | | | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 | ESP32-C2 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-C5 | ESP32-C61 |
+------------------+-------+----------+----------+----------+----------+----------+----------+----------+ +------------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
| SPI Slave HD | N | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | | SPI Slave HD | N | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) |
+------------------+-------+----------+----------+----------+----------+----------+----------+----------+ +------------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
| Tohost intr | | N | N | N | N | N | N | N | | Tohost intr | | N | N | N | N | N | N | N | N | N |
+------------------+-------+----------+----------+----------+----------+----------+----------+----------+ +------------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
| Frhost intr | | 2 \* | 2 \* | 2 \* | 2 \* | 2 \* | 2 \* | 2 \* | | Frhost intr | | 2 \* | 2 \* | 2 \* | 2 \* | 2 \* | 2 \* | 2 \* | 2 \* | 2 \* |
+------------------+-------+----------+----------+----------+----------+----------+----------+----------+ +------------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
| TX DMA | | Y | Y | Y | Y | Y | Y | Y | | TX DMA | | Y | Y | Y | Y | Y | Y | Y | Y | Y |
+------------------+-------+----------+----------+----------+----------+----------+----------+----------+ +------------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
| RX DMA | | Y | Y | Y | Y | Y | Y | Y | | RX DMA | | Y | Y | Y | Y | Y | Y | Y | Y | Y |
+------------------+-------+----------+----------+----------+----------+----------+----------+----------+ +------------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
| Shared registers | | 72 | 64 | 64 | 64 | 64 | 64 | 64 | | Shared registers | | 72 | 64 | 64 | 64 | 64 | 64 | 64 | 64 | 64 |
+------------------+-------+----------+----------+----------+----------+----------+----------+----------+ +------------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
Introduction Introduction
------------ ------------

20
docs/zh_CN/api-reference/peripherals/spi_master.rst
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@ -473,12 +473,12 @@ GPIO 矩阵与 IO_MUX 管脚
.. only:: not esp32 .. only:: not esp32
{IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7", esp32c5="10"} {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7" , esp32c5="10", esp32c61="8"}
{IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9", esp32c5="6"} {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9" , esp32c5="6", esp32c61="6"}
{IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8", esp32c5="7"} {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8" , esp32c5="7", esp32c61="7"}
{IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10", esp32c5="2"} {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10", esp32c5="2", esp32c61="2"}
{IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3", esp32p4="6", esp32c5="4"} {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3", esp32p4="6" , esp32c5="4", esp32c61="3"}
{IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2", esp32p4="11", esp32c5="5"} {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2", esp32p4="11", esp32c5="5", esp32c61="4"}
芯片的大多数外围信号都与之专用的 IO_MUX 管脚连接，但这些信号也可以通过较不直接的 GPIO 矩阵路由到任何其他可用的管脚。只要有一个信号是通过 GPIO 矩阵路由的，那么所有的信号都将通过它路由。 芯片的大多数外围信号都与之专用的 IO_MUX 管脚连接，但这些信号也可以通过较不直接的 GPIO 矩阵路由到任何其他可用的管脚。只要有一个信号是通过 GPIO 矩阵路由的，那么所有的信号都将通过它路由。
@ -524,10 +524,10 @@ GPIO 矩阵与 IO_MUX 管脚
传输事务持续时间 传输事务持续时间
^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^
{IDF_TARGET_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58"} {IDF_TARGET_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58", esp32p4="44", esp32c5="24", esp32c61="32"}
{IDF_TARGET_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9", esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28"} {IDF_TARGET_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9", esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28", esp32p4="27", esp32c5="15", esp32c61="17"}
{IDF_TARGET_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54"} {IDF_TARGET_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54", esp32p4="26", esp32c5="22", esp32c61="29"}
{IDF_TARGET_TRANS_TIME_POLL_CPU:default="N/A", esp32="8", esp32s2="8", esp32c3="9", esp32s3="9", esp32c2="15", esp32c6="15", esp32h2="24"} {IDF_TARGET_TRANS_TIME_POLL_CPU:default="N/A", esp32="8", esp32s2="8", esp32c3="9", esp32s3="9", esp32c2="15", esp32c6="15", esp32h2="24", esp32p4="12", esp32c5="12", esp32c61="14"}
传输事务持续时间包括设置 SPI 外设寄存器，将数据复制到 FIFO 或设置 DMA 链接，以及 SPI 传输事务时间。 传输事务持续时间包括设置 SPI 外设寄存器，将数据复制到 FIFO 或设置 DMA 链接，以及 SPI 传输事务时间。

12
docs/zh_CN/api-reference/peripherals/spi_slave.rst
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@ -141,12 +141,12 @@ GPIO 交换矩阵和 IO_MUX
.. only:: not esp32 .. only:: not esp32
{IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7"} {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7" , esp32c5="10", esp32c61="8"}
{IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9"} {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9" , esp32c5="6", esp32c61="6"}
{IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8"} {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8" , esp32c5="7", esp32c61="7"}
{IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10"} {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10", esp32c5="2", esp32c61="2"}
{IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3", esp32p4="6"} {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3", esp32p4="6" , esp32c5="4", esp32c61="3"}
{IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2", esp32p4="11"} {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2", esp32p4="11", esp32c5="5", esp32c61="4"}
{IDF_TARGET_NAME} 的大多数外设信号都直接连接到其专用的 IO_MUX 管脚。不过，也可以使用 GPIO 交换矩阵，将信号路由到任何可用的其他管脚。如果通过 GPIO 交换矩阵路由了至少一个信号，则所有信号都将通过 GPIO 交换矩阵路由。 {IDF_TARGET_NAME} 的大多数外设信号都直接连接到其专用的 IO_MUX 管脚。不过，也可以使用 GPIO 交换矩阵，将信号路由到任何可用的其他管脚。如果通过 GPIO 交换矩阵路由了至少一个信号，则所有信号都将通过 GPIO 交换矩阵路由。

30
docs/zh_CN/api-reference/protocols/esp_spi_slave_protocol.rst
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@ -14,21 +14,21 @@ ESP SPI 从机 HD（半双工）模式协议
乐鑫芯片的 SPI 从机功能支持概况 乐鑫芯片的 SPI 从机功能支持概况
--------------------------------- ---------------------------------
+-------------+-------+----------+----------+----------+----------+----------+----------+----------+ +-------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
| | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 | ESP32-C2 | ESP32-C6 | ESP32-H2 | ESP32-P4 | | | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 | ESP32-C2 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-C5 | ESP32-C61 |
+-------------+-------+----------+----------+----------+----------+----------+----------+----------+ +-------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
| SPI 从机 HD | N | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | | SPI 从机 HD | N | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) |
+-------------+-------+----------+----------+----------+----------+----------+----------+----------+ +-------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
| Tohost intr | | N | N | N | N | N | N | N | | Tohost intr | | N | N | N | N | N | N | N | N | N |
+-------------+-------+----------+----------+----------+----------+----------+----------+----------+ +-------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
| Frhost intr | | 2 * | 2 * | 2 * | 2 * | 2 * | 2 * | 2 \* | | Frhost intr | | 2 * | 2 * | 2 * | 2 * | 2 * | 2 * | 2 \* | 2 \* | 2 \* |
+-------------+-------+----------+----------+----------+----------+----------+----------+----------+ +-------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
| TX DMA | | Y | Y | Y | Y | Y | Y | Y | | TX DMA | | Y | Y | Y | Y | Y | Y | Y | Y | Y |
+-------------+-------+----------+----------+----------+----------+----------+----------+----------+ +-------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
| RX DMA | | Y | Y | Y | Y | Y | Y | Y | | RX DMA | | Y | Y | Y | Y | Y | Y | Y | Y | Y |
+-------------+-------+----------+----------+----------+----------+----------+----------+----------+ +-------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
| 共享寄存器 | | 72 | 64 | 64 | 64 | 64 | 64 | 64 | | 共享寄存器 | | 72 | 64 | 64 | 64 | 64 | 64 | 64 | 64 | 64 |
+-------------+-------+----------+----------+----------+----------+----------+----------+----------+ +-------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
概述 概述
---- ----

4
examples/get-started/blink/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
# Blink Example # Blink Example

1
examples/get-started/blink/sdkconfig.defaults.esp32c61 Normal file
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@ -0,0 +1 @@
CONFIG_BLINK_LED_STRIP=y

4
examples/peripherals/lcd/spi_lcd_touch/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
# SPI LCD and Touch Panel Example # SPI LCD and Touch Panel Example

4
examples/peripherals/lcd/tjpgd/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
## LCD tjpgd example ## LCD tjpgd example

6
examples/peripherals/spi_master/hd_eeprom/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
## SPI master half duplex EEPROM example ## SPI master half duplex EEPROM example
@ -24,4 +24,4 @@ For different chip and host used, the connections may be different. Here show a
### Notes ### Notes
If you meet timeout issues, please check your connections. If you meet timeout issues, please check your connections.

4
examples/peripherals/spi_master/lcd/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
# SPI Host Driver Example # SPI Host Driver Example

4
examples/peripherals/spi_slave/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
## SPI slave example ## SPI slave example

4
examples/peripherals/spi_slave_hd/append_mode/master/README.md
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@ -1,4 +1,4 @@
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
See README.md in the parent directory See README.md in the parent directory

4
examples/peripherals/spi_slave_hd/append_mode/slave/README.md
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@ -1,4 +1,4 @@
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
See README.md in the parent directory See README.md in the parent directory

4
examples/peripherals/spi_slave_hd/segment_mode/seg_master/README.md
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@ -1,4 +1,4 @@
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
See README.md in the parent directory See README.md in the parent directory

4
examples/peripherals/spi_slave_hd/segment_mode/seg_slave/README.md
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@ -1,2 +1,2 @@
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

4
examples/storage/sd_card/sdspi/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
# SD Card example (SDSPI) # SD Card example (SDSPI)