From b72d7592905bf3345bbd3166f12e8612cc222b2d Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Tue, 31 Jan 2023 15:09:24 +0800 Subject: [PATCH] uart: Add support for esp32h2 --- components/driver/uart.c | 51 +---- .../esp_hw_support/port/esp32h2/clk_tree.c | 3 + components/hal/esp32c2/include/hal/uart_ll.h | 2 +- components/hal/esp32c6/include/hal/uart_ll.h | 13 +- components/hal/esp32h2/include/hal/uart_ll.h | 201 ++++++++---------- components/soc/esp32c2/include/soc/soc.h | 1 - components/soc/esp32c3/include/soc/soc.h | 1 - components/soc/esp32c6/include/soc/soc.h | 1 - components/soc/esp32c6/include/soc/soc_caps.h | 6 +- .../soc/esp32c6/include/soc/uart_channel.h | 9 +- components/soc/esp32c6/include/soc/uart_reg.h | 77 +------ .../soc/esp32c6/include/soc/uart_struct.h | 54 +---- .../esp32h2/include/soc/Kconfig.soc_caps.in | 6 +- components/soc/esp32h2/include/soc/soc.h | 1 - components/soc/esp32h2/include/soc/soc_caps.h | 9 +- .../soc/esp32h2/include/soc/uart_channel.h | 9 +- components/soc/esp32h2/include/soc/uart_reg.h | 35 +-- .../soc/esp32h2/include/soc/uart_struct.h | 54 +---- components/soc/esp32h4/include/soc/soc.h | 1 - components/soc/esp32s3/include/soc/soc.h | 1 - docs/docs_not_updated/esp32h2.txt | 1 - .../uart/nmea0183_parser/README.md | 2 +- .../uart/uart_async_rxtxtasks/README.md | 4 +- examples/peripherals/uart/uart_echo/README.md | 4 +- .../peripherals/uart/uart_events/README.md | 2 +- .../peripherals/uart/uart_select/README.md | 4 +- 26 files changed, 129 insertions(+), 423 deletions(-) diff --git a/components/driver/uart.c b/components/driver/uart.c index 326b6869d8..1141cea455 100644 --- a/components/driver/uart.c +++ b/components/driver/uart.c @@ -24,7 +24,7 @@ #include "driver/gpio.h" #include "driver/uart_select.h" #include "esp_private/periph_ctrl.h" -#include "esp_private/esp_clk.h" +#include "clk_tree.h" #include "sdkconfig.h" #include "esp_rom_gpio.h" #include "clk_ctrl_os.h" @@ -200,50 +200,9 @@ static void uart_module_disable(uart_port_t uart_num) UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); } -esp_err_t uart_get_sclk_freq(uart_sclk_t sclk, uint32_t* out_freq_hz) +esp_err_t uart_get_sclk_freq(uart_sclk_t sclk, uint32_t *out_freq_hz) { - uint32_t freq; - switch (sclk) { -#if SOC_UART_SUPPORT_APB_CLK - case UART_SCLK_APB: - freq = esp_clk_apb_freq(); - break; -#endif -#if SOC_UART_SUPPORT_AHB_CLK - case UART_SCLK_AHB: - freq = APB_CLK_FREQ; //This only exist on H4. Fix this when H2 MP is supported. - break; -#endif -#if SOC_UART_SUPPORT_PLL_F40M_CLK - case UART_SCLK_PLL_F40M: - freq = 40 * MHZ; - break; -#endif -#if SOC_UART_SUPPORT_REF_TICK - case UART_SCLK_REF_TICK: - freq = REF_CLK_FREQ; - break; -#endif -#if SOC_UART_SUPPORT_RTC_CLK - case UART_SCLK_RTC: - freq = RTC_CLK_FREQ; - break; -#endif -#if SOC_UART_SUPPORT_XTAL_CLK - case UART_SCLK_XTAL: - freq = esp_clk_xtal_freq(); - break; -#endif -#if SOC_UART_SUPPORT_PLL_F80M_CLK - case UART_SCLK_PLL_F80M: - freq = UART_LL_PLL_DIV_FREQ; - break; -#endif - default: - return ESP_ERR_INVALID_ARG; - } - *out_freq_hz = freq; - return ESP_OK; + return clk_tree_src_get_freq_hz((soc_module_clk_t)sclk, CLK_TREE_SRC_FREQ_PRECISION_CACHED, out_freq_hz); } esp_err_t uart_set_word_length(uart_port_t uart_num, uart_word_length_t data_bit) @@ -586,11 +545,11 @@ esp_err_t uart_enable_pattern_det_baud_intr(uart_port_t uart_num, char pattern_c at_cmd.char_num = chr_num; #if CONFIG_IDF_TARGET_ESP32 - int apb_clk_freq = 0; + uint32_t apb_clk_freq = 0; uint32_t uart_baud = 0; uint32_t uart_div = 0; uart_get_baudrate(uart_num, &uart_baud); - apb_clk_freq = esp_clk_apb_freq(); + clk_tree_src_get_freq_hz((soc_module_clk_t)UART_SCLK_APB, CLK_TREE_SRC_FREQ_PRECISION_EXACT, &apb_clk_freq); uart_div = apb_clk_freq / uart_baud; at_cmd.gap_tout = chr_tout * uart_div; diff --git a/components/esp_hw_support/port/esp32h2/clk_tree.c b/components/esp_hw_support/port/esp32h2/clk_tree.c index a186ae2bd9..7f330a7270 100644 --- a/components/esp_hw_support/port/esp32h2/clk_tree.c +++ b/components/esp_hw_support/port/esp32h2/clk_tree.c @@ -28,6 +28,9 @@ uint32_t *freq_value) case SOC_MOD_CLK_PLL_F96M: clk_src_freq = 96 * MHZ; break; + case SOC_MOD_CLK_PLL_F48M: + clk_src_freq = 48 * MHZ; + break; case SOC_MOD_CLK_RC_FAST: clk_src_freq = SOC_CLK_RC_FAST_FREQ_APPROX; break; diff --git a/components/hal/esp32c2/include/hal/uart_ll.h b/components/hal/esp32c2/include/hal/uart_ll.h index 68168cd031..c0ea4a2e4f 100644 --- a/components/hal/esp32c2/include/hal/uart_ll.h +++ b/components/hal/esp32c2/include/hal/uart_ll.h @@ -98,7 +98,7 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) * @brief Set the UART source clock. * * @param hw Beginning address of the peripheral registers. - * @param source_clk The UART source clock. The source clock can be APB clock, RTC clock or XTAL clock. + * @param source_clk The UART source clock. The source clock can be PLL_F40M clock, RTC clock or XTAL clock. * If the source clock is RTC/XTAL, the UART can still work when the APB changes. * * @return None. diff --git a/components/hal/esp32c6/include/hal/uart_ll.h b/components/hal/esp32c6/include/hal/uart_ll.h index 20f9729049..918bba5812 100644 --- a/components/hal/esp32c6/include/hal/uart_ll.h +++ b/components/hal/esp32c6/include/hal/uart_ll.h @@ -31,8 +31,6 @@ extern "C" { #define UART_LL_FSM_IDLE (0x0) #define UART_LL_FSM_TX_WAIT_SEND (0xf) -#define UART_LL_PLL_DIV_FREQ (80000000) // 80 MHz - #define UART_LL_PCR_REG_U32_SET(hw, reg_suffix, field_suffix, val) \ if ((hw) == &UART0) { \ HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart0_##reg_suffix, uart0_##field_suffix, (val)) \ @@ -88,7 +86,6 @@ typedef enum { */ static inline void uart_ll_update(uart_dev_t *hw) { - // TODO: set a timeout ?? hw->reg_update.reg_update = 1; while (hw->reg_update.reg_update); } @@ -103,7 +100,7 @@ static inline void uart_ll_update(uart_dev_t *hw) */ static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) { - hw->clk_conf.rst_core = core_rst_en; + UART_LL_PCR_REG_SET(hw, conf, rst_en, core_rst_en); } /** @@ -134,8 +131,8 @@ static inline void uart_ll_sclk_disable(uart_dev_t *hw) * @brief Set the UART source clock. * * @param hw Beginning address of the peripheral registers. - * @param source_clk The UART source clock. The source clock can be APB clock, RTC clock or XTAL clock. - * If the source clock is RTC/XTAL, the UART can still work when the APB changes. + * @param source_clk The UART source clock. The source clock can be PLL_F80M clock, RTC clock or XTAL clock. + * All clock sources can remain at their original frequencies during DFS. * * @return None. */ @@ -198,7 +195,7 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t // The baud rate configuration register is divided into // an integer part and a fractional part. hw->clkdiv_sync.clkdiv_int = clk_div >> 4; - hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; + hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1); #undef DIV_UP uart_ll_update(hw); @@ -303,7 +300,7 @@ static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd * * @param hw Beginning address of the peripheral registers. * @param buf The data buffer. - * @param wr_len The data length needs to be writen. + * @param wr_len The data length needs to be written. * * @return None */ diff --git a/components/hal/esp32h2/include/hal/uart_ll.h b/components/hal/esp32h2/include/hal/uart_ll.h index e1ab6fa015..1bb0ae0ba7 100644 --- a/components/hal/esp32h2/include/hal/uart_ll.h +++ b/components/hal/esp32h2/include/hal/uart_ll.h @@ -14,6 +14,7 @@ #include "hal/uart_types.h" #include "soc/uart_periph.h" #include "soc/uart_struct.h" +#include "soc/pcr_struct.h" #ifdef __cplusplus extern "C" { @@ -30,6 +31,28 @@ extern "C" { #define UART_LL_FSM_IDLE (0x0) #define UART_LL_FSM_TX_WAIT_SEND (0xf) +#define UART_LL_PCR_REG_U32_SET(hw, reg_suffix, field_suffix, val) \ + if ((hw) == &UART0) { \ + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart0_##reg_suffix, uart0_##field_suffix, (val)) \ + } else { \ + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart1_##reg_suffix, uart1_##field_suffix, (val)) \ + } + +#define UART_LL_PCR_REG_U32_GET(hw, reg_suffix, field_suffix) \ + (((hw) == &UART0) ? \ + HAL_FORCE_READ_U32_REG_FIELD(PCR.uart0_##reg_suffix, uart0_##field_suffix) : \ + HAL_FORCE_READ_U32_REG_FIELD(PCR.uart1_##reg_suffix, uart1_##field_suffix)) + +#define UART_LL_PCR_REG_SET(hw, reg_suffix, field_suffix, val) \ + if ((hw) == &UART0) { \ + PCR.uart0_##reg_suffix.uart0_##field_suffix = (val); \ + } else { \ + PCR.uart1_##reg_suffix.uart1_##field_suffix = (val); \ + } + +#define UART_LL_PCR_REG_GET(hw, reg_suffix, field_suffix) \ + (((hw) == &UART0) ? PCR.uart0_##reg_suffix.uart0_##field_suffix : PCR.uart1_##reg_suffix.uart1_##field_suffix) + // Define UART interrupts typedef enum { UART_INTR_RXFIFO_FULL = (0x1 << 0), @@ -51,19 +74,20 @@ typedef enum { UART_INTR_RS485_FRM_ERR = (0x1 << 16), UART_INTR_RS485_CLASH = (0x1 << 17), UART_INTR_CMD_CHAR_DET = (0x1 << 18), - // UART_INTR_WAKEUP = (0x1 << 19), // TODO: IDF-5338 + // UART_INTR_WAKEUP = (0x1 << 19), // TODO: IDF-6267 } uart_intr_t; -static inline void uart_ll_update(int uart_no) // TODO: IDF-5338 should use uart_dev_t *hw +/** + * @brief Sync the update to UART core clock domain + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +static inline void uart_ll_update(uart_dev_t *hw) { - // TODO: set a timeout ?? - while(1) { - int update = GET_PERI_REG_BITS2(UART_REG_UPDATE_REG(uart_no), UART_REG_UPDATE_V, UART_REG_UPDATE_S); - if (!update) { - break; - } - } - SET_PERI_REG_MASK(UART_REG_UPDATE_REG(uart_no), UART_REG_UPDATE_M); + hw->reg_update.reg_update = 1; + while (hw->reg_update.reg_update); } /** @@ -76,7 +100,7 @@ static inline void uart_ll_update(int uart_no) // TODO: IDF-5338 should use uart */ static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) { - hw->clk_conf.rst_core = core_rst_en; + UART_LL_PCR_REG_SET(hw, conf, rst_en, core_rst_en); } /** @@ -88,9 +112,7 @@ static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) */ static inline void uart_ll_sclk_enable(uart_dev_t *hw) { - hw->clk_conf.sclk_en = 1; - hw->clk_conf.rx_sclk_en = 1; - hw->clk_conf.tx_sclk_en = 1; + UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 1); } /** @@ -102,17 +124,15 @@ static inline void uart_ll_sclk_enable(uart_dev_t *hw) */ static inline void uart_ll_sclk_disable(uart_dev_t *hw) { - hw->clk_conf.sclk_en = 0; - hw->clk_conf.rx_sclk_en = 0; - hw->clk_conf.tx_sclk_en = 0; + UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 0); } /** * @brief Set the UART source clock. * * @param hw Beginning address of the peripheral registers. - * @param source_clk The UART source clock. The source clock can be APB clock, RTC clock or XTAL clock. - * If the source clock is RTC/XTAL, the UART can still work when the APB changes. + * @param source_clk The UART source clock. The source clock can be PLL_F48M clock, RTC clock or XTAL clock. + * All clock sources can remain at their original frequencies during DFS. * * @return None. */ @@ -121,13 +141,13 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk) switch (source_clk) { default: case UART_SCLK_PLL_F48M: - hw->clk_conf.sclk_sel = 1; + UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 1); break; case UART_SCLK_RTC: - hw->clk_conf.sclk_sel = 2; + UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 2); break; case UART_SCLK_XTAL: - hw->clk_conf.sclk_sel = 3; + UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 3); break; } } @@ -142,7 +162,7 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk) */ static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk) { - switch (hw->clk_conf.sclk_sel) { + switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) { default: case 1: *source_clk = UART_SCLK_PLL_F48M; @@ -175,10 +195,10 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t // The baud rate configuration register is divided into // an integer part and a fractional part. hw->clkdiv_sync.clkdiv_int = clk_div >> 4; - hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1); + hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; + UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1); #undef DIV_UP - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); } /** @@ -191,8 +211,9 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t */ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) { - typeof(hw->clkdiv_sync) div_reg = hw->clkdiv_sync; - return ((sclk_freq << 4)) / (((div_reg.clkdiv_int << 4) | div_reg.clkdiv_frag) * (HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1)); + typeof(hw->clkdiv_sync) div_reg; + div_reg.val = hw->clkdiv_sync.val; + return ((sclk_freq << 4)) / (((div_reg.clkdiv_int << 4) | div_reg.clkdiv_frag) * (UART_LL_PCR_REG_U32_GET(hw, sclk_conf, sclk_div_num) + 1)); } /** @@ -270,7 +291,7 @@ static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) { for (int i = 0; i < (int)rd_len; i++) { - buf[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->fifo, rxfifo_rd_byte); + buf[i] = hw->fifo.rxfifo_rd_byte; } } @@ -279,14 +300,14 @@ static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd * * @param hw Beginning address of the peripheral registers. * @param buf The data buffer. - * @param wr_len The data length needs to be writen. + * @param wr_len The data length needs to be written. * * @return None */ static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len) { for (int i = 0; i < (int)wr_len; i++) { - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->fifo, rxfifo_rd_byte, buf[i]); + hw->fifo.rxfifo_rd_byte = buf[i]; } } @@ -300,9 +321,9 @@ static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint static inline void uart_ll_rxfifo_rst(uart_dev_t *hw) { hw->conf0_sync.rxfifo_rst = 1; - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); hw->conf0_sync.rxfifo_rst = 0; - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); } /** @@ -315,9 +336,9 @@ static inline void uart_ll_rxfifo_rst(uart_dev_t *hw) static inline void uart_ll_txfifo_rst(uart_dev_t *hw) { hw->conf0_sync.txfifo_rst = 1; - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); hw->conf0_sync.txfifo_rst = 0; - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); } /** @@ -355,7 +376,7 @@ static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit) { hw->conf0_sync.stop_bit_num = stop_bit; - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); } /** @@ -368,7 +389,7 @@ static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_b */ static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit) { - *stop_bit = hw->conf0_sync.stop_bit_num; + *stop_bit = (uart_stop_bits_t)hw->conf0_sync.stop_bit_num; } /** @@ -385,7 +406,7 @@ static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode) hw->conf0_sync.parity = parity_mode & 0x1; } hw->conf0_sync.parity_en = (parity_mode >> 1) & 0x1; - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); } /** @@ -399,7 +420,7 @@ static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode) static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode) { if (hw->conf0_sync.parity_en) { - *parity_mode = 0X2 | hw->conf0_sync.parity; + *parity_mode = (uart_parity_t)(0x2 | hw->conf0_sync.parity); } else { *parity_mode = UART_PARITY_DISABLE; } @@ -445,7 +466,7 @@ static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_t static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr) { hw->idle_conf_sync.rx_idle_thrhd = rx_idle_thr; - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); } /** @@ -459,7 +480,7 @@ static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr) static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num) { hw->idle_conf_sync.tx_idle_num = idle_num; - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); } /** @@ -474,13 +495,11 @@ static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) { if (break_num > 0) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf_sync, tx_brk_num, break_num); - uart_ll_update(0); // TODO: IDF-5338 hw->conf0_sync.txd_brk = 1; - uart_ll_update(0); // TODO: IDF-5338 } else { hw->conf0_sync.txd_brk = 0; - uart_ll_update(0); // TODO: IDF-5338 } + uart_ll_update(hw); } /** @@ -497,20 +516,16 @@ static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_ //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set. if (flow_ctrl & UART_HW_FLOWCTRL_RTS) { hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs; - uart_ll_update(0); // TODO: IDF-5338 hw->hwfc_conf_sync.rx_flow_en = 1; - uart_ll_update(0); // TODO: IDF-5338 } else { hw->hwfc_conf_sync.rx_flow_en = 0; - uart_ll_update(0); // TODO: IDF-5338 } if (flow_ctrl & UART_HW_FLOWCTRL_CTS) { hw->conf0_sync.tx_flow_en = 1; - uart_ll_update(0); // TODO: IDF-5338 } else { hw->conf0_sync.tx_flow_en = 0; - uart_ll_update(0); // TODO: IDF-5338 } + uart_ll_update(hw); } /** @@ -525,10 +540,10 @@ static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_ { *flow_ctrl = UART_HW_FLOWCTRL_DISABLE; if (hw->hwfc_conf_sync.rx_flow_en) { - *flow_ctrl |= UART_HW_FLOWCTRL_RTS; + *flow_ctrl = (uart_hw_flowcontrol_t)((unsigned int)(*flow_ctrl) | (unsigned int)UART_HW_FLOWCTRL_RTS); } if (hw->conf0_sync.tx_flow_en) { - *flow_ctrl |= UART_HW_FLOWCTRL_CTS; + *flow_ctrl = (uart_hw_flowcontrol_t)((unsigned int)(*flow_ctrl) | (unsigned int)UART_HW_FLOWCTRL_CTS); } } @@ -545,21 +560,16 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t * { if (sw_flow_ctrl_en) { hw->swfc_conf0_sync.xonoff_del = 1; - uart_ll_update(0); // TODO: IDF-5338 hw->swfc_conf0_sync.sw_flow_con_en = 1; - uart_ll_update(0); // TODO: IDF-5338 hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd; hw->swfc_conf1.xoff_threshold = flow_ctrl->xoff_thrd; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char); - uart_ll_update(0); // TODO: IDF-5338 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char); - uart_ll_update(0); // TODO: IDF-5338 } else { hw->swfc_conf0_sync.sw_flow_con_en = 0; - uart_ll_update(0); // TODO: IDF-5338 hw->swfc_conf0_sync.xonoff_del = 0; - uart_ll_update(0); // TODO: IDF-5338 } + uart_ll_update(hw); } /** @@ -578,15 +588,11 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t * static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, data, cmd_char->cmd_char); - uart_ll_update(0); // TODO: IDF-5338 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, char_num, cmd_char->char_num); - uart_ll_update(0); // TODO: IDF-5338 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt_sync, post_idle_num, cmd_char->post_idle); - uart_ll_update(0); // TODO: IDF-5338 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt_sync, pre_idle_num, cmd_char->pre_idle); - uart_ll_update(0); // TODO: IDF-5338 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout_sync, rx_gap_tout, cmd_char->gap_tout); - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); } /** @@ -600,7 +606,7 @@ static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_ch static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit) { hw->conf0_sync.bit_num = data_bit; - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); } /** @@ -614,7 +620,7 @@ static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t d static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level) { hw->conf0_sync.sw_rts = level & 0x1; - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); } /** @@ -654,13 +660,10 @@ static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd) static inline void uart_ll_set_mode_normal(uart_dev_t *hw) { hw->rs485_conf_sync.rs485_en = 0; - uart_ll_update(0); // TODO: IDF-5338 hw->rs485_conf_sync.rs485tx_rx_en = 0; - uart_ll_update(0); // TODO: IDF-5338 hw->rs485_conf_sync.rs485rxby_tx_en = 0; - uart_ll_update(0); // TODO: IDF-5338 hw->conf0_sync.irda_en = 0; - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); } /** @@ -674,19 +677,13 @@ static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw) { // Application software control, remove echo hw->rs485_conf_sync.rs485rxby_tx_en = 1; - uart_ll_update(0); // TODO: IDF-5338 hw->conf0_sync.irda_en = 0; - uart_ll_update(0); // TODO: IDF-5338 hw->conf0_sync.sw_rts = 0; - uart_ll_update(0); // TODO: IDF-5338 hw->conf0_sync.irda_en = 0; - uart_ll_update(0); // TODO: IDF-5338 hw->rs485_conf_sync.dl0_en = 1; - uart_ll_update(0); // TODO: IDF-5338 hw->rs485_conf_sync.dl1_en = 1; - uart_ll_update(0); // TODO: IDF-5338 hw->rs485_conf_sync.rs485_en = 1; - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); } /** @@ -700,22 +697,16 @@ static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw) { // Enable receiver, sw_rts = 1 generates low level on RTS pin hw->conf0_sync.sw_rts = 1; - uart_ll_update(0); // TODO: IDF-5338 // Half duplex mode hw->rs485_conf_sync.rs485tx_rx_en = 0; - uart_ll_update(0); // TODO: IDF-5338 // Setting this bit will allow data to be transmitted while receiving data(full-duplex mode). // But note that this full-duplex mode has no conflict detection function hw->rs485_conf_sync.rs485rxby_tx_en = 0; - uart_ll_update(0); // TODO: IDF-5338 hw->conf0_sync.irda_en = 0; - uart_ll_update(0); // TODO: IDF-5338 hw->rs485_conf_sync.dl0_en = 1; - uart_ll_update(0); // TODO: IDF-5338 hw->rs485_conf_sync.dl1_en = 1; - uart_ll_update(0); // TODO: IDF-5338 hw->rs485_conf_sync.rs485_en = 1; - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); } /** @@ -728,21 +719,15 @@ static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw) static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw) { hw->conf0_sync.irda_en = 0; - uart_ll_update(0); // TODO: IDF-5338 // Enable full-duplex mode hw->rs485_conf_sync.rs485tx_rx_en = 1; - uart_ll_update(0); // TODO: IDF-5338 // Transmitter should send data when the receiver is busy, hw->rs485_conf_sync.rs485rxby_tx_en = 1; - uart_ll_update(0); // TODO: IDF-5338 hw->rs485_conf_sync.dl0_en = 1; - uart_ll_update(0); // TODO: IDF-5338 hw->rs485_conf_sync.dl1_en = 1; - uart_ll_update(0); // TODO: IDF-5338 hw->conf0_sync.sw_rts = 0; - uart_ll_update(0); // TODO: IDF-5338 hw->rs485_conf_sync.rs485_en = 1; - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); } /** @@ -755,15 +740,11 @@ static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw) static inline void uart_ll_set_mode_irda(uart_dev_t *hw) { hw->rs485_conf_sync.rs485_en = 0; - uart_ll_update(0); // TODO: IDF-5338 hw->rs485_conf_sync.rs485tx_rx_en = 0; - uart_ll_update(0); // TODO: IDF-5338 hw->rs485_conf_sync.rs485rxby_tx_en = 0; - uart_ll_update(0); // TODO: IDF-5338 hw->conf0_sync.sw_rts = 0; - uart_ll_update(0); // TODO: IDF-5338 hw->conf0_sync.irda_en = 1; - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); } /** @@ -808,9 +789,7 @@ static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num) { *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, data); - uart_ll_update(0); // TODO: IDF-5338 *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, char_num); - uart_ll_update(0); // TODO: IDF-5338 } /** @@ -835,7 +814,7 @@ static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw) */ static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit) { - *data_bit = hw->conf0_sync.bit_num; + *data_bit = (uart_word_length_t)hw->conf0_sync.bit_num; } /** @@ -885,15 +864,16 @@ static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw) static inline void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en) { hw->conf0_sync.loopback = loop_back_en; + uart_ll_update(hw); } static inline void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) { hw->swfc_conf0_sync.force_xon = 1; - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); if(!always_on) { hw->swfc_conf0_sync.force_xon = 0; - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); } } @@ -908,20 +888,22 @@ static inline void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) */ static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask) { - typeof(hw->conf0_sync) conf0_reg = hw->conf0_sync; + typeof(hw->conf0_sync) conf0_reg; + conf0_reg.val = hw->conf0_sync.val; conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0; conf0_reg.irda_rx_inv = (inv_mask & UART_SIGNAL_IRDA_RX_INV) ? 1 : 0; conf0_reg.rxd_inv = (inv_mask & UART_SIGNAL_RXD_INV) ? 1 : 0; conf0_reg.txd_inv = (inv_mask & UART_SIGNAL_TXD_INV) ? 1 : 0; hw->conf0_sync.val = conf0_reg.val; - uart_ll_update(0); // TODO: IDF-5338 - typeof(hw->conf1) conf1_reg = hw->conf1; + typeof(hw->conf1) conf1_reg; + conf1_reg.val = hw->conf1.val; conf1_reg.rts_inv = (inv_mask & UART_SIGNAL_RTS_INV) ? 1 : 0; conf1_reg.dtr_inv = (inv_mask & UART_SIGNAL_DTR_INV) ? 1 : 0; conf1_reg.cts_inv = (inv_mask & UART_SIGNAL_CTS_INV) ? 1 : 0; conf1_reg.dsr_inv = (inv_mask & UART_SIGNAL_DSR_INV) ? 1 : 0; hw->conf1.val = conf1_reg.val; + uart_ll_update(hw); } /** @@ -937,13 +919,11 @@ static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) uint16_t tout_val = tout_thrd; if(tout_thrd > 0) { hw->tout_conf_sync.rx_tout_thrhd = tout_val; - uart_ll_update(0); // TODO: IDF-5338 hw->tout_conf_sync.rx_tout_en = 1; - uart_ll_update(0); // TODO: IDF-5338 } else { hw->tout_conf_sync.rx_tout_en = 0; - uart_ll_update(0); // TODO: IDF-5338 } + uart_ll_update(hw); } /** @@ -983,7 +963,7 @@ static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable) { hw->conf0_sync.autobaud_en = enable ? 1 : 0; - uart_ll_update(0); // TODO: IDF-5338 + uart_ll_update(hw); } /** @@ -1046,10 +1026,8 @@ static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw) static inline void uart_ll_force_xoff(uart_port_t uart_num) { REG_CLR_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_FORCE_XON); - uart_ll_update(0); // TODO: IDF-5338 REG_SET_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XOFF); - uart_ll_update(0); // TODO: IDF-5338 - // REG_SET_BIT(UART_ID_REG(uart_num), UART_UPDATE); + uart_ll_update(UART_LL_GET_HW(uart_num)); } /** @@ -1062,12 +1040,9 @@ static inline void uart_ll_force_xoff(uart_port_t uart_num) static inline void uart_ll_force_xon(uart_port_t uart_num) { REG_CLR_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_FORCE_XOFF); - uart_ll_update(0); // TODO: IDF-5338 REG_SET_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_FORCE_XON); - uart_ll_update(0); // TODO: IDF-5338 REG_CLR_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XON); - uart_ll_update(0); // TODO: IDF-5338 - // REG_SET_BIT(UART_ID_REG(uart_num), UART_UPDATE); + uart_ll_update(UART_LL_GET_HW(uart_num)); } /** diff --git a/components/soc/esp32c2/include/soc/soc.h b/components/soc/esp32c2/include/soc/soc.h index f482342ec6..07349b1ed3 100644 --- a/components/soc/esp32c2/include/soc/soc.h +++ b/components/soc/esp32c2/include/soc/soc.h @@ -146,7 +146,6 @@ #define CPU_CLK_FREQ APB_CLK_FREQ #define APB_CLK_FREQ ( 40*1000000 ) #define REF_CLK_FREQ ( 1000000 ) -#define RTC_CLK_FREQ (20*1000000) #define UART_CLK_FREQ APB_CLK_FREQ #define WDT_CLK_FREQ APB_CLK_FREQ #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 4 diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index 1ca46adf8f..932611d1e5 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -139,7 +139,6 @@ #define CPU_CLK_FREQ APB_CLK_FREQ #define APB_CLK_FREQ ( 80*1000000 ) #define REF_CLK_FREQ ( 1000000 ) -#define RTC_CLK_FREQ (20*1000000) #define XTAL_CLK_FREQ (40*1000000) #define UART_CLK_FREQ APB_CLK_FREQ #define WDT_CLK_FREQ APB_CLK_FREQ diff --git a/components/soc/esp32c6/include/soc/soc.h b/components/soc/esp32c6/include/soc/soc.h index 8adccb044b..8f8fde8730 100644 --- a/components/soc/esp32c6/include/soc/soc.h +++ b/components/soc/esp32c6/include/soc/soc.h @@ -143,7 +143,6 @@ #define APB_CLK_FREQ ( 40*1000000 ) #define MODEM_APB_CLK_FREQ ( 80*1000000 ) #define REF_CLK_FREQ ( 1000000 ) -#define RTC_CLK_FREQ (20*1000000) #define XTAL_CLK_FREQ (40*1000000) #define GPIO_MATRIX_DELAY_NS 0 //}} diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index c54be95933..b7d3b9fafb 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -401,16 +401,16 @@ /*-------------------------- MEMPROT CAPS ------------------------------------*/ -// TODO: IDF-5338 (Copy from esp32c3, need check) + /*-------------------------- UART CAPS ---------------------------------------*/ // ESP32-C6 has 2 UARTs #define SOC_UART_NUM (2) #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ -#define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_DIV as the clock source */ +#define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */ #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ #define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ -#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ // TODO: Test UART wakeup while supporting sleep +#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) diff --git a/components/soc/esp32c6/include/soc/uart_channel.h b/components/soc/esp32c6/include/soc/uart_channel.h index 507f020603..9d9fb454fd 100644 --- a/components/soc/esp32c6/include/soc/uart_channel.h +++ b/components/soc/esp32c6/include/soc/uart_channel.h @@ -1,13 +1,12 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C3. +// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C6. -#ifndef _SOC_UART_CHANNEL_H -#define _SOC_UART_CHANNEL_H +#pragma once //UART channels #define UART_GPIO16_DIRECT_CHANNEL UART_NUM_0 @@ -17,5 +16,3 @@ #define UART_TXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL #define UART_RXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL - -#endif diff --git a/components/soc/esp32c6/include/soc/uart_reg.h b/components/soc/esp32c6/include/soc/uart_reg.h index 958b2e51df..abac8d92b1 100644 --- a/components/soc/esp32c6/include/soc/uart_reg.h +++ b/components/soc/esp32c6/include/soc/uart_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -1471,81 +1471,6 @@ extern "C" { #define UART_RXD_EDGE_CNT_V 0x000003FFU #define UART_RXD_EDGE_CNT_S 0 -/** UART_CLK_CONF_REG register - * UART core clock configuration - */ -#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88) -/** UART_SCLK_DIV_B : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor. - */ -#define UART_SCLK_DIV_B 0x0000003FU -#define UART_SCLK_DIV_B_M (UART_SCLK_DIV_B_V << UART_SCLK_DIV_B_S) -#define UART_SCLK_DIV_B_V 0x0000003FU -#define UART_SCLK_DIV_B_S 0 -/** UART_SCLK_DIV_A : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor. - */ -#define UART_SCLK_DIV_A 0x0000003FU -#define UART_SCLK_DIV_A_M (UART_SCLK_DIV_A_V << UART_SCLK_DIV_A_S) -#define UART_SCLK_DIV_A_V 0x0000003FU -#define UART_SCLK_DIV_A_S 6 -/** UART_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; - * The integral part of the frequency divider factor. - */ -#define UART_SCLK_DIV_NUM 0x000000FFU -#define UART_SCLK_DIV_NUM_M (UART_SCLK_DIV_NUM_V << UART_SCLK_DIV_NUM_S) -#define UART_SCLK_DIV_NUM_V 0x000000FFU -#define UART_SCLK_DIV_NUM_S 12 -/** UART_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; - * UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. - */ -#define UART_SCLK_SEL 0x00000003U -#define UART_SCLK_SEL_M (UART_SCLK_SEL_V << UART_SCLK_SEL_S) -#define UART_SCLK_SEL_V 0x00000003U -#define UART_SCLK_SEL_S 20 -/** UART_SCLK_EN : R/W; bitpos: [22]; default: 1; - * Set this bit to enable UART Tx/Rx clock. - */ -#define UART_SCLK_EN (BIT(22)) -#define UART_SCLK_EN_M (UART_SCLK_EN_V << UART_SCLK_EN_S) -#define UART_SCLK_EN_V 0x00000001U -#define UART_SCLK_EN_S 22 -/** UART_RST_CORE : R/W; bitpos: [23]; default: 0; - * Write 1 then write 0 to this bit to reset UART Tx/Rx. - */ -#define UART_RST_CORE (BIT(23)) -#define UART_RST_CORE_M (UART_RST_CORE_V << UART_RST_CORE_S) -#define UART_RST_CORE_V 0x00000001U -#define UART_RST_CORE_S 23 -/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; - * Set this bit to enable UART Tx clock. - */ -#define UART_TX_SCLK_EN (BIT(24)) -#define UART_TX_SCLK_EN_M (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S) -#define UART_TX_SCLK_EN_V 0x00000001U -#define UART_TX_SCLK_EN_S 24 -/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; - * Set this bit to enable UART Rx clock. - */ -#define UART_RX_SCLK_EN (BIT(25)) -#define UART_RX_SCLK_EN_M (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S) -#define UART_RX_SCLK_EN_V 0x00000001U -#define UART_RX_SCLK_EN_S 25 -/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0; - * Write 1 then write 0 to this bit to reset UART Tx. - */ -#define UART_TX_RST_CORE (BIT(26)) -#define UART_TX_RST_CORE_M (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S) -#define UART_TX_RST_CORE_V 0x00000001U -#define UART_TX_RST_CORE_S 26 -/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0; - * Write 1 then write 0 to this bit to reset UART Rx. - */ -#define UART_RX_RST_CORE (BIT(27)) -#define UART_RX_RST_CORE_M (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S) -#define UART_RX_RST_CORE_V 0x00000001U -#define UART_RX_RST_CORE_S 27 - /** UART_DATE_REG register * UART Version register */ diff --git a/components/soc/esp32c6/include/soc/uart_struct.h b/components/soc/esp32c6/include/soc/uart_struct.h index 2315f5c1ad..467f86ff5a 100644 --- a/components/soc/esp32c6/include/soc/uart_struct.h +++ b/components/soc/esp32c6/include/soc/uart_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -875,56 +875,6 @@ typedef union { uint32_t val; } uart_rs485_conf_sync_reg_t; -/** Type of clk_conf register - * UART core clock configuration - */ -typedef union { - struct { - /** sclk_div_b : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor. - */ - uint32_t sclk_div_b:6; - /** sclk_div_a : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor. - */ - uint32_t sclk_div_a:6; - /** sclk_div_num : R/W; bitpos: [19:12]; default: 1; - * The integral part of the frequency divider factor. - */ - uint32_t sclk_div_num:8; - /** sclk_sel : R/W; bitpos: [21:20]; default: 3; - * UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. - */ - uint32_t sclk_sel:2; - /** sclk_en : R/W; bitpos: [22]; default: 1; - * Set this bit to enable UART Tx/Rx clock. - */ - uint32_t sclk_en:1; - /** rst_core : R/W; bitpos: [23]; default: 0; - * Write 1 then write 0 to this bit to reset UART Tx/Rx. - */ - uint32_t rst_core:1; - /** tx_sclk_en : R/W; bitpos: [24]; default: 1; - * Set this bit to enable UART Tx clock. - */ - uint32_t tx_sclk_en:1; - /** rx_sclk_en : R/W; bitpos: [25]; default: 1; - * Set this bit to enable UART Rx clock. - */ - uint32_t rx_sclk_en:1; - /** tx_rst_core : R/W; bitpos: [26]; default: 0; - * Write 1 then write 0 to this bit to reset UART Tx. - */ - uint32_t tx_rst_core:1; - /** rx_rst_core : R/W; bitpos: [27]; default: 0; - * Write 1 then write 0 to this bit to reset UART Rx. - */ - uint32_t rx_rst_core:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} uart_clk_conf_reg_t; - /** Group: Status Register */ /** Type of status register @@ -1273,7 +1223,7 @@ typedef struct uart_dev_s { volatile uart_lowpulse_reg_t lowpulse; volatile uart_highpulse_reg_t highpulse; volatile uart_rxd_cnt_reg_t rxd_cnt; - volatile uart_clk_conf_reg_t clk_conf; + uint32_t reserved_088; volatile uart_date_reg_t date; volatile uart_afifo_status_reg_t afifo_status; uint32_t reserved_094; diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 51aac11cad..2a4854bb53 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -788,14 +788,10 @@ config SOC_UART_BITRATE_MAX default 5000000 config SOC_UART_SUPPORT_RTC_CLK - bool - default n - -config SOC_UART_SUPPORT_XTAL_CLK bool default y -config SOC_UART_REQUIRE_CORE_RESET +config SOC_UART_SUPPORT_XTAL_CLK bool default y diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index 7bda5f0ce2..28063eb22d 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -140,7 +140,6 @@ #define CPU_CLK_FREQ APB_CLK_FREQ #define APB_CLK_FREQ ( 32*1000000 ) #define REF_CLK_FREQ ( 1000000 ) -#define RTC_CLK_FREQ (20*1000000) #define XTAL_CLK_FREQ (32*1000000) #define UART_CLK_FREQ APB_CLK_FREQ #define WDT_CLK_FREQ APB_CLK_FREQ diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 4c93e5689d..d32d86b7aa 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -380,18 +380,15 @@ #define SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE 16 #define SOC_MEMPROT_MEM_ALIGN_SIZE 512 -// TODO: IDF-6249 (Copy from esp32c6, need check) /*-------------------------- UART CAPS ---------------------------------------*/ // ESP32-H2 has 2 UARTs #define SOC_UART_NUM (2) #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ -// #define SOC_UART_SUPPORT_APB_CLK (1) /*!< Support APB as the clock source */ -#define SOC_UART_SUPPORT_RTC_CLK (0) /*!< Support RTC clock as the clock source */ // TODO: IDF-6249 -#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ -// #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ // TODO: IDF-6249 -#define SOC_UART_REQUIRE_CORE_RESET (1) +#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ +#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ +// #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ // TODO: IDF-6267 // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) diff --git a/components/soc/esp32h2/include/soc/uart_channel.h b/components/soc/esp32h2/include/soc/uart_channel.h index 9977264f21..037dd9c71d 100644 --- a/components/soc/esp32h2/include/soc/uart_channel.h +++ b/components/soc/esp32h2/include/soc/uart_channel.h @@ -1,13 +1,12 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C3. +// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32H2. -#ifndef _SOC_UART_CHANNEL_H -#define _SOC_UART_CHANNEL_H +#pragma once //UART channels #define UART_GPIO24_DIRECT_CHANNEL UART_NUM_0 @@ -17,5 +16,3 @@ #define UART_TXD_GPIO24_DIRECT_CHANNEL UART_GPIO24_DIRECT_CHANNEL #define UART_RXD_GPIO23_DIRECT_CHANNEL UART_GPIO23_DIRECT_CHANNEL - -#endif diff --git a/components/soc/esp32h2/include/soc/uart_reg.h b/components/soc/esp32h2/include/soc/uart_reg.h index 164b55603f..5c8d8c01f9 100644 --- a/components/soc/esp32h2/include/soc/uart_reg.h +++ b/components/soc/esp32h2/include/soc/uart_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -1471,39 +1471,6 @@ extern "C" { #define UART_RXD_EDGE_CNT_V 0x000003FFU #define UART_RXD_EDGE_CNT_S 0 -/** UART_CLK_CONF_REG(i) register - * UART core clock configuration - */ -#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88) -/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; - * Set this bit to enable UART Tx clock. - */ -#define UART_TX_SCLK_EN (BIT(24)) -#define UART_TX_SCLK_EN_M (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S) -#define UART_TX_SCLK_EN_V 0x00000001U -#define UART_TX_SCLK_EN_S 24 -/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; - * Set this bit to enable UART Rx clock. - */ -#define UART_RX_SCLK_EN (BIT(25)) -#define UART_RX_SCLK_EN_M (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S) -#define UART_RX_SCLK_EN_V 0x00000001U -#define UART_RX_SCLK_EN_S 25 -/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0; - * Write 1 then write 0 to this bit to reset UART Tx. - */ -#define UART_TX_RST_CORE (BIT(26)) -#define UART_TX_RST_CORE_M (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S) -#define UART_TX_RST_CORE_V 0x00000001U -#define UART_TX_RST_CORE_S 26 -/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0; - * Write 1 then write 0 to this bit to reset UART Rx. - */ -#define UART_RX_RST_CORE (BIT(27)) -#define UART_RX_RST_CORE_M (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S) -#define UART_RX_RST_CORE_V 0x00000001U -#define UART_RX_RST_CORE_S 27 - /** UART_DATE_REG(i) register * UART Version register */ diff --git a/components/soc/esp32h2/include/soc/uart_struct.h b/components/soc/esp32h2/include/soc/uart_struct.h index 2315f5c1ad..467f86ff5a 100644 --- a/components/soc/esp32h2/include/soc/uart_struct.h +++ b/components/soc/esp32h2/include/soc/uart_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -875,56 +875,6 @@ typedef union { uint32_t val; } uart_rs485_conf_sync_reg_t; -/** Type of clk_conf register - * UART core clock configuration - */ -typedef union { - struct { - /** sclk_div_b : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor. - */ - uint32_t sclk_div_b:6; - /** sclk_div_a : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor. - */ - uint32_t sclk_div_a:6; - /** sclk_div_num : R/W; bitpos: [19:12]; default: 1; - * The integral part of the frequency divider factor. - */ - uint32_t sclk_div_num:8; - /** sclk_sel : R/W; bitpos: [21:20]; default: 3; - * UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. - */ - uint32_t sclk_sel:2; - /** sclk_en : R/W; bitpos: [22]; default: 1; - * Set this bit to enable UART Tx/Rx clock. - */ - uint32_t sclk_en:1; - /** rst_core : R/W; bitpos: [23]; default: 0; - * Write 1 then write 0 to this bit to reset UART Tx/Rx. - */ - uint32_t rst_core:1; - /** tx_sclk_en : R/W; bitpos: [24]; default: 1; - * Set this bit to enable UART Tx clock. - */ - uint32_t tx_sclk_en:1; - /** rx_sclk_en : R/W; bitpos: [25]; default: 1; - * Set this bit to enable UART Rx clock. - */ - uint32_t rx_sclk_en:1; - /** tx_rst_core : R/W; bitpos: [26]; default: 0; - * Write 1 then write 0 to this bit to reset UART Tx. - */ - uint32_t tx_rst_core:1; - /** rx_rst_core : R/W; bitpos: [27]; default: 0; - * Write 1 then write 0 to this bit to reset UART Rx. - */ - uint32_t rx_rst_core:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} uart_clk_conf_reg_t; - /** Group: Status Register */ /** Type of status register @@ -1273,7 +1223,7 @@ typedef struct uart_dev_s { volatile uart_lowpulse_reg_t lowpulse; volatile uart_highpulse_reg_t highpulse; volatile uart_rxd_cnt_reg_t rxd_cnt; - volatile uart_clk_conf_reg_t clk_conf; + uint32_t reserved_088; volatile uart_date_reg_t date; volatile uart_afifo_status_reg_t afifo_status; uint32_t reserved_094; diff --git a/components/soc/esp32h4/include/soc/soc.h b/components/soc/esp32h4/include/soc/soc.h index 5c45de2447..520a09e0d9 100644 --- a/components/soc/esp32h4/include/soc/soc.h +++ b/components/soc/esp32h4/include/soc/soc.h @@ -143,7 +143,6 @@ #define APB_CLK_FREQ ( 48*1000000 ) //ESP32H4-TODO: IDF-3786 #endif #define REF_CLK_FREQ ( 1000000 ) -#define RTC_CLK_FREQ (17.5*1000000) #define XTAL_CLK_FREQ (32*1000000) #define UART_CLK_FREQ APB_CLK_FREQ #define WDT_CLK_FREQ APB_CLK_FREQ diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index 340ecb6521..4247786637 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -155,7 +155,6 @@ #define CPU_CLK_FREQ APB_CLK_FREQ #define APB_CLK_FREQ (80*1000000) #define REF_CLK_FREQ (1000000) -#define RTC_CLK_FREQ (20*1000000) #define XTAL_CLK_FREQ (40*1000000) #define UART_CLK_FREQ APB_CLK_FREQ #define WDT_CLK_FREQ APB_CLK_FREQ diff --git a/docs/docs_not_updated/esp32h2.txt b/docs/docs_not_updated/esp32h2.txt index c5a20b2e78..ed7f009e9e 100644 --- a/docs/docs_not_updated/esp32h2.txt +++ b/docs/docs_not_updated/esp32h2.txt @@ -102,7 +102,6 @@ api-reference/peripherals/sd_pullup_requirements api-reference/peripherals/spi_master api-reference/peripherals/index api-reference/peripherals/sdmmc_host -api-reference/peripherals/uart api-reference/kconfig api-reference/network/esp_openthread api-reference/network/esp_eth diff --git a/examples/peripherals/uart/nmea0183_parser/README.md b/examples/peripherals/uart/nmea0183_parser/README.md index ab8c38a900..22bf4e36c9 100644 --- a/examples/peripherals/uart/nmea0183_parser/README.md +++ b/examples/peripherals/uart/nmea0183_parser/README.md @@ -24,7 +24,7 @@ Usually, modules will also output some vendor specific statements which common n ### Hardware Required -To run this example, you need an ESP32, ESP32-S or ESP32-C series dev board (e.g. ESP32-WROVER Kit). For test purpose, you also need a GPS module. Here we take the [ATGM332D-5N](http://www.icofchina.com/pro/mokuai/2016-08-01/5.html) as an example to show how to parse the NMEA statements and output common information such as UTC time, latitude, longitude, altitude, speed and so on. +To run this example, you need a dev board that is based on Espressif SoC (e.g. ESP32-WROVER Kit). For test purpose, you also need a GPS module. Here we take the [ATGM332D-5N](http://www.icofchina.com/pro/mokuai/2016-08-01/5.html) as an example to show how to parse the NMEA statements and output common information such as UTC time, latitude, longitude, altitude, speed and so on. #### Pin Assignment: diff --git a/examples/peripherals/uart/uart_async_rxtxtasks/README.md b/examples/peripherals/uart/uart_async_rxtxtasks/README.md index 8e829577ed..38061afb55 100644 --- a/examples/peripherals/uart/uart_async_rxtxtasks/README.md +++ b/examples/peripherals/uart/uart_async_rxtxtasks/README.md @@ -16,8 +16,8 @@ The example starts two FreeRTOS tasks: ### Hardware Required -The example can be run on any commonly available ESP32, ESP32-S and ESP32-C series based development board. You will need a USB cable to connect the -development board to a computer, and a simple one-wire cable for shorting two pins of the board. +The example can be run on any commonly available development board, that is based on the Espressif SoC. You will need a +USB cable to connect the development board to a computer, and a simple one-wire cable for shorting two pins of the board. ### Setup the Hardware diff --git a/examples/peripherals/uart/uart_echo/README.md b/examples/peripherals/uart/uart_echo/README.md index 808c58c66a..baecc8db24 100644 --- a/examples/peripherals/uart/uart_echo/README.md +++ b/examples/peripherals/uart/uart_echo/README.md @@ -12,8 +12,8 @@ configured UART. ### Hardware Required -The example can be run on any ESP32, ESP32-S and ESP32-C series based development board connected to a computer with a single USB cable for flashing and -monitoring. The external interface should have 3.3V outputs. You may use e.g. 3.3V compatible USB-to-Serial dongle. +The example can be run on any development board, that is based on the Espressif SoC. The board shall be connected to a computer with a single USB cable for flashing and monitoring. The external interface should have 3.3V outputs. You may +use e.g. 3.3V compatible USB-to-Serial dongle. ### Setup the Hardware diff --git a/examples/peripherals/uart/uart_events/README.md b/examples/peripherals/uart/uart_events/README.md index 753f464b89..97cf5def2b 100644 --- a/examples/peripherals/uart/uart_events/README.md +++ b/examples/peripherals/uart/uart_events/README.md @@ -12,7 +12,7 @@ and echoes it back to the monitoring console. ### Hardware Required -The example can be used with any ESP32, ESP32-S and ESP32-C series based development board connected to a computer with a USB cable. +The example can be run on any development board, that is based on the Espressif SoC. The board shall be connected to a computer with a single USB cable for flashing and monitoring. ### Configure the project diff --git a/examples/peripherals/uart/uart_select/README.md b/examples/peripherals/uart/uart_select/README.md index e65094b925..4914731761 100644 --- a/examples/peripherals/uart/uart_select/README.md +++ b/examples/peripherals/uart/uart_select/README.md @@ -23,8 +23,8 @@ For a more comprehensive example please refer to `system/select`. ### Hardware Required -The example can be run on any ESP32, ESP32-S and ESP32-C series based development board connected to a computer with a single USB cable for communication -through UART. +The example can be run on any development board, that is based on the Espressif SoC. The board shall be connected to a +computer with a single USB cable for communication through UART. ### Configure the project