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fix(soc): fix the pms reg headers base addr

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laokaiyao 2024-05-20 22:41:32 +08:00 committed by Kevin (Lao Kaiyao)
parent 4db2236626
commit e4224be406
5 changed files with 170 additions and 170 deletions
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260
components/soc/esp32p4/include/soc/dma_pms_reg.h
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14
components/soc/esp32p4/include/soc/hp2lp_peri_pms_reg.h
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@ -14,7 +14,7 @@ extern "C" {
/** PMS_HP2LP_PERI_PMS_DATE_REG register
* Version control register
*/
#define PMS_HP2LP_PERI_PMS_DATE_REG (DR_REG_PMS_BASE + 0x0)
#define PMS_HP2LP_PERI_PMS_DATE_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x0)
/** PMS_HP2LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294790;
* Version control register
*/
@ -26,7 +26,7 @@ extern "C" {
/** PMS_HP2LP_PERI_PMS_CLK_EN_REG register
* Clock gating register
*/
#define PMS_HP2LP_PERI_PMS_CLK_EN_REG (DR_REG_PMS_BASE + 0x4)
#define PMS_HP2LP_PERI_PMS_CLK_EN_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x4)
/** PMS_HP2LP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: Enable automatic clock gating
@ -40,7 +40,7 @@ extern "C" {
/** PMS_HP_CORE0_MM_PMS_REG0_REG register
* Permission control register0 for HP CPU0 in machine mode
*/
#define PMS_HP_CORE0_MM_PMS_REG0_REG (DR_REG_PMS_BASE + 0x8)
#define PMS_HP_CORE0_MM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x8)
/** PMS_HP_CORE0_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP System
* Registers.
@ -267,7 +267,7 @@ extern "C" {
/** PMS_HP_CORE0_UM_PMS_REG0_REG register
* Permission control register0 for HP CPU0 in user mode
*/
#define PMS_HP_CORE0_UM_PMS_REG0_REG (DR_REG_PMS_BASE + 0xc)
#define PMS_HP_CORE0_UM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0xc)
/** PMS_HP_CORE0_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP System
* Registers.
@ -492,7 +492,7 @@ extern "C" {
/** PMS_HP_CORE1_MM_PMS_REG0_REG register
* Permission control register0 for HP CPU1 in machine mode
*/
#define PMS_HP_CORE1_MM_PMS_REG0_REG (DR_REG_PMS_BASE + 0x10)
#define PMS_HP_CORE1_MM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x10)
/** PMS_HP_CORE1_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP System
* Registers.
@ -719,7 +719,7 @@ extern "C" {
/** PMS_HP_CORE1_UM_PMS_REG0_REG register
* Permission control register0 for HP CPU1 in user mode
*/
#define PMS_HP_CORE1_UM_PMS_REG0_REG (DR_REG_PMS_BASE + 0x14)
#define PMS_HP_CORE1_UM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x14)
/** PMS_HP_CORE1_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP System
* Registers.
@ -944,7 +944,7 @@ extern "C" {
/** PMS_REGDMA_LP_PERI_PMS_REG register
* LP Peripheral Permission register for REGDMA
*/
#define PMS_REGDMA_LP_PERI_PMS_REG (DR_REG_PMS_BASE + 0x18)
#define PMS_REGDMA_LP_PERI_PMS_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x18)
/** PMS_REGDMA_PERI_LP_SRAM_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether REGDMA has permission to access LP SRAM.
* 0: Not allowed

38
components/soc/esp32p4/include/soc/hp_peri_pms_reg.h
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@ -14,7 +14,7 @@ extern "C" {
/** PMS_HP_PERI_PMS_DATE_REG register
* Version control register
*/
#define PMS_HP_PERI_PMS_DATE_REG (DR_REG_PMS_BASE + 0x0)
#define PMS_HP_PERI_PMS_DATE_REG (DR_REG_HP_PERI_PMS_BASE + 0x0)
/** PMS_HP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294537;
* Version control register.
*/
@ -26,7 +26,7 @@ extern "C" {
/** PMS_HP_PERI_PMS_CLK_EN_REG register
* Clock gating register
*/
#define PMS_HP_PERI_PMS_CLK_EN_REG (DR_REG_PMS_BASE + 0x4)
#define PMS_HP_PERI_PMS_CLK_EN_REG (DR_REG_HP_PERI_PMS_BASE + 0x4)
/** PMS_HP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: Enable automatic clock gating
@ -40,7 +40,7 @@ extern "C" {
/** PMS_CORE0_MM_HP_PERI_PMS_REG0_REG register
* Permission control register0 for HP CPU0 in machine mode
*/
#define PMS_CORE0_MM_HP_PERI_PMS_REG0_REG (DR_REG_PMS_BASE + 0x8)
#define PMS_CORE0_MM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x8)
/** PMS_CORE0_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access external RAM
* without going through cache.
@ -140,7 +140,7 @@ extern "C" {
/** PMS_CORE0_MM_HP_PERI_PMS_REG1_REG register
* Permission control register1 for HP CPU0 in machine mode
*/
#define PMS_CORE0_MM_HP_PERI_PMS_REG1_REG (DR_REG_PMS_BASE + 0xc)
#define PMS_CORE0_MM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0xc)
/** PMS_CORE0_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access HP high-speed
* USB 2.0 OTG.
@ -421,7 +421,7 @@ extern "C" {
/** PMS_CORE0_MM_HP_PERI_PMS_REG2_REG register
* Permission control register2 for HP CPU0 in machine mode
*/
#define PMS_CORE0_MM_HP_PERI_PMS_REG2_REG (DR_REG_PMS_BASE + 0x10)
#define PMS_CORE0_MM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x10)
/** PMS_CORE0_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access HP MCPWM0.
* 0: Not allowed
@ -702,7 +702,7 @@ extern "C" {
/** PMS_CORE0_MM_HP_PERI_PMS_REG3_REG register
* Permission control register3 for HP CPU0 in machine mode
*/
#define PMS_CORE0_MM_HP_PERI_PMS_REG3_REG (DR_REG_PMS_BASE + 0x14)
#define PMS_CORE0_MM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x14)
/** PMS_CORE0_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access HP GPIO Matrix.
* 0: Not allowed
@ -754,7 +754,7 @@ extern "C" {
/** PMS_CORE0_UM_HP_PERI_PMS_REG0_REG register
* Permission control register0 for HP CPU0 in user mode
*/
#define PMS_CORE0_UM_HP_PERI_PMS_REG0_REG (DR_REG_PMS_BASE + 0x18)
#define PMS_CORE0_UM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x18)
/** PMS_CORE0_UM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access external RAM
* without going through cache.
@ -853,7 +853,7 @@ extern "C" {
/** PMS_CORE0_UM_HP_PERI_PMS_REG1_REG register
* Permission control register1 for HP CPU0 in user mode
*/
#define PMS_CORE0_UM_HP_PERI_PMS_REG1_REG (DR_REG_PMS_BASE + 0x1c)
#define PMS_CORE0_UM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0x1c)
/** PMS_CORE0_UM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access HP high-speed USB
* 2.0 OTG.
@ -1128,7 +1128,7 @@ extern "C" {
/** PMS_CORE0_UM_HP_PERI_PMS_REG2_REG register
* Permission control register2 for HP CPU0 in user mode
*/
#define PMS_CORE0_UM_HP_PERI_PMS_REG2_REG (DR_REG_PMS_BASE + 0x20)
#define PMS_CORE0_UM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x20)
/** PMS_CORE0_UM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access HP MCPWM0.
* 0: Not allowed
@ -1407,7 +1407,7 @@ extern "C" {
/** PMS_CORE0_UM_HP_PERI_PMS_REG3_REG register
* Permission control register3 for HP CPU0 in user mode
*/
#define PMS_CORE0_UM_HP_PERI_PMS_REG3_REG (DR_REG_PMS_BASE + 0x24)
#define PMS_CORE0_UM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x24)
/** PMS_CORE0_UM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access HP GPIO Matrix.
* 0: Not allowed
@ -1458,7 +1458,7 @@ extern "C" {
/** PMS_CORE1_MM_HP_PERI_PMS_REG0_REG register
* Permission control register0 for HP CPU1 in machine mode
*/
#define PMS_CORE1_MM_HP_PERI_PMS_REG0_REG (DR_REG_PMS_BASE + 0x28)
#define PMS_CORE1_MM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x28)
/** PMS_CORE1_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access external RAM
* without going through cache.
@ -1558,7 +1558,7 @@ extern "C" {
/** PMS_CORE1_MM_HP_PERI_PMS_REG1_REG register
* Permission control register1 for HP CPU1 in machine mode
*/
#define PMS_CORE1_MM_HP_PERI_PMS_REG1_REG (DR_REG_PMS_BASE + 0x2c)
#define PMS_CORE1_MM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0x2c)
/** PMS_CORE1_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access HP high-speed
* USB 2.0 OTG.
@ -1839,7 +1839,7 @@ extern "C" {
/** PMS_CORE1_MM_HP_PERI_PMS_REG2_REG register
* Permission control register2 for HP CPU1 in machine mode
*/
#define PMS_CORE1_MM_HP_PERI_PMS_REG2_REG (DR_REG_PMS_BASE + 0x30)
#define PMS_CORE1_MM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x30)
/** PMS_CORE1_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access HP MCPWM0.
* 0: Not allowed
@ -2120,7 +2120,7 @@ extern "C" {
/** PMS_CORE1_MM_HP_PERI_PMS_REG3_REG register
* Permission control register3 for HP CPU1 in machine mode
*/
#define PMS_CORE1_MM_HP_PERI_PMS_REG3_REG (DR_REG_PMS_BASE + 0x34)
#define PMS_CORE1_MM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x34)
/** PMS_CORE1_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access HP GPIO Matrix.
* 0: Not allowed
@ -2172,7 +2172,7 @@ extern "C" {
/** PMS_CORE1_UM_HP_PERI_PMS_REG0_REG register
* Permission control register0 for HP CPU1 in user mode
*/
#define PMS_CORE1_UM_HP_PERI_PMS_REG0_REG (DR_REG_PMS_BASE + 0x38)
#define PMS_CORE1_UM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x38)
/** PMS_CORE1_UM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access external RAM
* without going through cache.
@ -2271,7 +2271,7 @@ extern "C" {
/** PMS_CORE1_UM_HP_PERI_PMS_REG1_REG register
* Permission control register1 for HP CPU1 in user mode
*/
#define PMS_CORE1_UM_HP_PERI_PMS_REG1_REG (DR_REG_PMS_BASE + 0x3c)
#define PMS_CORE1_UM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0x3c)
/** PMS_CORE1_UM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access HP high-speed USB
* 2.0 OTG.
@ -2546,7 +2546,7 @@ extern "C" {
/** PMS_CORE1_UM_HP_PERI_PMS_REG2_REG register
* Permission control register2 for HP CPU1 in user mode
*/
#define PMS_CORE1_UM_HP_PERI_PMS_REG2_REG (DR_REG_PMS_BASE + 0x40)
#define PMS_CORE1_UM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x40)
/** PMS_CORE1_UM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access HP MCPWM0.
* 0: Not allowed
@ -2825,7 +2825,7 @@ extern "C" {
/** PMS_CORE1_UM_HP_PERI_PMS_REG3_REG register
* Permission control register3 for HP CPU1 in user mode
*/
#define PMS_CORE1_UM_HP_PERI_PMS_REG3_REG (DR_REG_PMS_BASE + 0x44)
#define PMS_CORE1_UM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x44)
/** PMS_CORE1_UM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access HP GPIO Matrix.
* 0: Not allowed
@ -2876,7 +2876,7 @@ extern "C" {
/** PMS_REGDMA_PERI_PMS_REG register
* Permission register for REGDMA
*/
#define PMS_REGDMA_PERI_PMS_REG (DR_REG_PMS_BASE + 0x48)
#define PMS_REGDMA_PERI_PMS_REG (DR_REG_HP_PERI_PMS_BASE + 0x48)
/** PMS_REGDMA_PERI_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether REGDMA has permission to access all HP peripheral (including CPU
* peripherals).

12
components/soc/esp32p4/include/soc/lp2hp_peri_pms_reg.h
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@ -14,7 +14,7 @@ extern "C" {
/** PMS_LP2HP_PERI_PMS_DATE_REG register
* Version control register
*/
#define PMS_LP2HP_PERI_PMS_DATE_REG (DR_REG_PMS_BASE + 0x0)
#define PMS_LP2HP_PERI_PMS_DATE_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x0)
/** PMS_LP2HP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294790;
* Version control register.
*/
@ -26,7 +26,7 @@ extern "C" {
/** PMS_LP2HP_PERI_PMS_CLK_EN_REG register
* Clock gating register
*/
#define PMS_LP2HP_PERI_PMS_CLK_EN_REG (DR_REG_PMS_BASE + 0x4)
#define PMS_LP2HP_PERI_PMS_CLK_EN_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x4)
/** PMS_LP2HP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: Enable automatic clock gating.
@ -40,7 +40,7 @@ extern "C" {
/** PMS_LP_MM_PMS_REG0_REG register
* Permission control register0 for the LP CPU in machine mode
*/
#define PMS_LP_MM_PMS_REG0_REG (DR_REG_PMS_BASE + 0x8)
#define PMS_LP_MM_PMS_REG0_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x8)
/** PMS_LP_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access external RAM
* without going through cache.
@ -141,7 +141,7 @@ extern "C" {
/** PMS_LP_MM_PMS_REG1_REG register
* Permission control register1 for the LP CPU in machine mode
*/
#define PMS_LP_MM_PMS_REG1_REG (DR_REG_PMS_BASE + 0x30)
#define PMS_LP_MM_PMS_REG1_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x30)
/** PMS_LP_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP
* high-speed USB 2.0 OTG.
@ -422,7 +422,7 @@ extern "C" {
/** PMS_LP_MM_PMS_REG2_REG register
* Permission control register2 for the LP CPU in machine mode
*/
#define PMS_LP_MM_PMS_REG2_REG (DR_REG_PMS_BASE + 0xa4)
#define PMS_LP_MM_PMS_REG2_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0xa4)
/** PMS_LP_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP MCPWM0.
* 0: Not allowed
@ -703,7 +703,7 @@ extern "C" {
/** PMS_LP_MM_PMS_REG3_REG register
* Permission control register3 for the LP CPU in machine mode
*/
#define PMS_LP_MM_PMS_REG3_REG (DR_REG_PMS_BASE + 0x11c)
#define PMS_LP_MM_PMS_REG3_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x11c)
/** PMS_LP_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP GPIO
* Matrix.

16
components/soc/esp32p4/include/soc/lp_peri_pms_reg.h
View File

@ -14,7 +14,7 @@ extern "C" {
/** PMS_LP_PERI_PMS_DATE_REG register
* Version control register
*/
#define PMS_LP_PERI_PMS_DATE_REG (DR_REG_PMS_BASE + 0x0)
#define PMS_LP_PERI_PMS_DATE_REG (DR_REG_LP_PERI_PMS_BASE + 0x0)
/** PMS_LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294537;
* Version control register
*/
@ -26,7 +26,7 @@ extern "C" {
/** PMS_LP_PERI_PMS_CLK_EN_REG register
* Clock gating register
*/
#define PMS_LP_PERI_PMS_CLK_EN_REG (DR_REG_PMS_BASE + 0x4)
#define PMS_LP_PERI_PMS_CLK_EN_REG (DR_REG_LP_PERI_PMS_BASE + 0x4)
/** PMS_LP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: Enable automatic clock gating
@ -40,7 +40,7 @@ extern "C" {
/** PMS_LP_MM_LP_PERI_PMS_REG0_REG register
* Permission control register0 for LP CPU in machine mode
*/
#define PMS_LP_MM_LP_PERI_PMS_REG0_REG (DR_REG_PMS_BASE + 0x8)
#define PMS_LP_MM_LP_PERI_PMS_REG0_REG (DR_REG_LP_PERI_PMS_BASE + 0x8)
/** PMS_LP_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP system
* registers.
@ -272,7 +272,7 @@ extern "C" {
/** PMS_PERI_REGION0_LOW_REG register
* Region0 start address configuration register
*/
#define PMS_PERI_REGION0_LOW_REG (DR_REG_PMS_BASE + 0xc)
#define PMS_PERI_REGION0_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0xc)
/** PMS_PERI_REGION0_LOW : R/W; bitpos: [31:2]; default: 0;
* Configures the high 30 bits of the start address of peripheral register's region0.
*/
@ -284,7 +284,7 @@ extern "C" {
/** PMS_PERI_REGION0_HIGH_REG register
* Region0 end address configuration register
*/
#define PMS_PERI_REGION0_HIGH_REG (DR_REG_PMS_BASE + 0x10)
#define PMS_PERI_REGION0_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x10)
/** PMS_PERI_REGION0_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* Configures the high 30 bits of the end address of peripheral register's region0.
*/
@ -296,7 +296,7 @@ extern "C" {
/** PMS_PERI_REGION1_LOW_REG register
* Region1 start address configuration register
*/
#define PMS_PERI_REGION1_LOW_REG (DR_REG_PMS_BASE + 0x14)
#define PMS_PERI_REGION1_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0x14)
/** PMS_PERI_REGION1_LOW : R/W; bitpos: [31:2]; default: 0;
* Configures the high 30 bits of the start address of peripheral register's region1.
*/
@ -308,7 +308,7 @@ extern "C" {
/** PMS_PERI_REGION1_HIGH_REG register
* Region1 end address configuration register
*/
#define PMS_PERI_REGION1_HIGH_REG (DR_REG_PMS_BASE + 0x18)
#define PMS_PERI_REGION1_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x18)
/** PMS_PERI_REGION1_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* Configures the high 30 bits of the end address of peripheral register's region1.
*/
@ -320,7 +320,7 @@ extern "C" {
/** PMS_PERI_REGION_PMS_REG register
* Permission register of region
*/
#define PMS_PERI_REGION_PMS_REG (DR_REG_PMS_BASE + 0x1c)
#define PMS_PERI_REGION_PMS_REG (DR_REG_LP_PERI_PMS_BASE + 0x1c)
/** PMS_LP_CORE_REGION_PMS : R/W; bitpos: [1:0]; default: 3;
* Configures whether LP core in machine mode has permission to access address region0
* and address region1. Bit0 corresponds to region0 and bit1 corresponds to region1.