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Code Issues Actions 2 Packages Projects Releases Wiki Activity

1. Update libbt

Browse Source 
2. Release the controller's .bss and .data memory
3. Modify the kconfig in nimble host
This commit is contained in:
Shen Weilong 2022-12-19 21:02:50 +08:00
parent 0f6373ca97
commit e41b35b089
6 changed files with 77 additions and 53 deletions
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85
components/bt/controller/esp32c6/bt.c
View File

@ -139,12 +139,12 @@ extern int ble_txpwr_get(esp_ble_enhanced_power_type_t power_type, uint16_t hand
extern int ble_get_npl_element_info(esp_bt_controller_config_t *cfg, ble_npl_count_info_t * npl_info);
extern uint32_t _bt_bss_start;
extern uint32_t _bt_bss_end;
extern uint32_t _nimble_bss_start;
extern uint32_t _nimble_bss_end;
extern uint32_t _nimble_data_start;
extern uint32_t _nimble_data_end;
extern uint32_t _bt_controller_bss_start;
extern uint32_t _bt_controller_bss_end;
extern uint32_t _bt_data_start;
extern uint32_t _bt_data_end;
extern uint32_t _bt_controller_data_start;
extern uint32_t _bt_controller_data_end;
/* Local Function Declaration
*********************************************************************
@ -786,33 +786,62 @@ esp_err_t esp_bt_mem_release(esp_bt_mode_t mode)
{
intptr_t mem_start, mem_end;
if (mode == ESP_BT_MODE_BLE) {
mem_start = (intptr_t)&_bt_bss_start;
mem_end = (intptr_t)&_bt_bss_end;
if (mem_start != mem_end) {
ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release BT BSS [0x%08x] - [0x%08x]", mem_start, mem_end);
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
}
if (mode & ESP_BT_MODE_BLE) {
/* If the addresses of btdm .bss and bt .bss are consecutive,
* they are registered in the system heap as a piece of memory
*/
if(_bt_bss_end == _bt_controller_bss_start) {
mem_start = (intptr_t)&_bt_bss_start;
mem_end = (intptr_t)&_bt_controller_bss_end;
if (mem_start != mem_end) {
ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release BSS [0x%08x] - [0x%08x], len %d",
mem_start, mem_end, mem_end - mem_start);
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
}
} else {
mem_start = (intptr_t)&_bt_bss_start;
mem_end = (intptr_t)&_bt_bss_end;
if (mem_start != mem_end) {
ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release BT BSS [0x%08x] - [0x%08x], len %d",
mem_start, mem_end, mem_end - mem_start);
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
}
mem_start = (intptr_t)&_bt_data_start;
mem_end = (intptr_t)&_bt_data_end;
if (mem_start != mem_end) {
ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release BT Data [0x%08x] - [0x%08x]", mem_start, mem_end);
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
mem_start = (intptr_t)&_bt_controller_bss_start;
mem_end = (intptr_t)&_bt_controller_bss_end;
if (mem_start != mem_end) {
ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release Controller BSS [0x%08x] - [0x%08x], len %d",
mem_start, mem_end, mem_end - mem_start);
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
}
}
/* If the addresses of btdm .data and bt .data are consecutive,
* they are registered in the system heap as a piece of memory
*/
if(_bt_data_end == _bt_controller_data_start) {
mem_start = (intptr_t)&_bt_data_start;
mem_end = (intptr_t)&_bt_controller_data_end;
if (mem_start != mem_end) {
ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release data [0x%08x] - [0x%08x], len %d",
mem_start, mem_end, mem_end - mem_start);
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
}
} else {
mem_start = (intptr_t)&_bt_data_start;
mem_end = (intptr_t)&_bt_data_end;
if (mem_start != mem_end) {
ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release BT Data [0x%08x] - [0x%08x], len %d",
mem_start, mem_end, mem_end - mem_start);
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
}
mem_start = (intptr_t)&_nimble_bss_start;
mem_end = (intptr_t)&_nimble_bss_end;
if (mem_start != mem_end) {
ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release NimBLE BSS [0x%08x] - [0x%08x]", mem_start, mem_end);
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
}
mem_start = (intptr_t)&_nimble_data_start;
mem_end = (intptr_t)&_nimble_data_end;
if (mem_start != mem_end) {
ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release NimBLE Data [0x%08x] - [0x%08x]", mem_start, mem_end);
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
mem_start = (intptr_t)&_bt_controller_data_start;
mem_end = (intptr_t)&_bt_controller_data_end;
if (mem_start != mem_end) {
ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release Controller Data [0x%08x] - [0x%08x], len %d",
mem_start, mem_end, mem_end - mem_start);
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
}
}
}

2
components/bt/controller/lib_esp32c6/esp32c6-bt-lib

@ -1 +1 @@
Subproject commit 8f6c402d19576bf720a18f350b39a0e83517f7aa
Subproject commit 5b6a490d2b2fa54f3603079000b833f749289283

27
components/bt/host/nimble/Kconfig.in
View File

@ -592,18 +592,12 @@ config BT_NIMBLE_MAX_PERIODIC_ADVERTISER_LIST
help
Set this option to set the upper limit for number of periodic advertiser list.
menuconfig BT_NIMBLE_53_FEATURE_SUPPORT
bool "Enable BLE 5.3 feature"
depends on BT_NIMBLE_ENABLED && SOC_ESP_NIMBLE_CONTROLLER && IDF_TARGET_NONE
config BT_NIMBLE_BLE_POWER_CONTROL
bool "Enable support for BLE Power Control"
depends on BT_NIMBLE_50_FEATURE_SUPPORT && IDF_TARGET_ESP32C6
default n
help
Enable BLE 5.3 feature
config BT_NIMBLE_SUBRATE
bool "Connection Subrate"
depends on BT_NIMBLE_53_FEATURE_SUPPORT
help
Enable support for Connection Subrate
Set this option to enable the Power Control feature
choice BT_NIMBLE_COEX_PHY_CODED_TX_RX_TLIM
prompt "Coexistence: limit on MAX Tx/Rx time for coded-PHY connection"
@ -624,17 +618,6 @@ choice BT_NIMBLE_COEX_PHY_CODED_TX_RX_TLIM
Disable the limitation on max tx/rx time for Coded-PHY connection
endchoice
menuconfig BT_NIMBLE_52_FEATURE_SUPPORT
bool "Enable BLE 5.2 Feature"
help
Enable this option to select 5.2 features
config BT_NIMBLE_BLE_POWER_CONTROL
bool "Enable support for BLE Power Control"
depends on BT_NIMBLE_52_FEATURE_SUPPORT && SOC_ESP_NIMBLE_CONTROLLER
help
Set this option to enable the Power Control feature
config BT_NIMBLE_COEX_PHY_CODED_TX_RX_TLIM_EFF
int
default 0 if !(ESP32_WIFI_SW_COEXIST_ENABLE && BT_NIMBLE_ENABLED)

6
components/bt/include/esp32c6/include/esp_bt.h
View File

@ -145,7 +145,7 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type
*/
esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle);
#define CONFIG_VERSION 0x20220824
#define CONFIG_VERSION 0x20221220
#define CONFIG_MAGIC 0x5A5AA5A5
/**
@ -203,7 +203,9 @@ typedef struct {
uint8_t cca_drop_mode;
int8_t cca_low_tx_pwr;
uint8_t main_xtal_freq;
uint8_t version_num;
uint8_t cpu_freq_mhz;
uint8_t ignore_wl_for_direct_adv;
uint32_t config_magic;
} esp_bt_controller_config_t;
@ -255,7 +257,9 @@ typedef struct {
.dis_scan_backoff = NIMBLE_DISABLE_SCAN_BACKOFF, \
.ble_scan_classify_filter_enable = 0, \
.main_xtal_freq = CONFIG_XTAL_FREQ, \
.version_num = 0, \
.cpu_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, \
.ignore_wl_for_direct_adv = 0, \
.config_magic = CONFIG_MAGIC, \
}

8
components/bt/linker.lf
View File

@ -39,6 +39,14 @@ entries:
bt_common -> dram0_bss ALIGN(4) ALIGN(4, post) SURROUND(btdm_common),
data -> dram0_data ALIGN(4) ALIGN(4, post) SURROUND(btdm_data)
[mapping:bt_controller]
archive: libble_app.a
entries:
* (bt_start_end);
bt_bss -> dram0_bss ALIGN(4) ALIGN(4, post) SURROUND(bt_controller_bss),
bt_common -> dram0_bss ALIGN(4) ALIGN(4, post) SURROUND(bt_controller_common),
data -> dram0_data ALIGN(4) ALIGN(4, post) SURROUND(bt_controller_data)
[mapping:nimble]
archive: libnimble.a
entries:

2
components/soc/esp32c6/include/soc/soc_caps.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/