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fix(mbedtls/aes): Fix incorrect dma alignment size

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This commit is contained in:
harshal.patil 2024-03-29 12:02:55 +05:30 committed by Gao Xu
parent 8e9b1501c0
commit e383616503
2 changed files with 8 additions and 6 deletions
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3
components/mbedtls/port/aes/dma/esp_aes_dma_core.c
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@ -278,9 +278,8 @@ static inline void *aes_dma_calloc(size_t num, size_t size, uint32_t caps, size_
void *ptr = NULL;
esp_dma_mem_info_t dma_mem_info = {
.extra_heap_caps = caps,
.dma_alignment_bytes = 4,
.dma_alignment_bytes = DMA_DESC_MEM_ALIGN_SIZE,
};
//TODO: IDF-9638
esp_dma_capable_calloc(num, size, &dma_mem_info, &ptr, actual_size);
return ptr;
}

11
components/mbedtls/port/include/esp_crypto_dma.h
View File

@ -7,9 +7,12 @@
#pragma once
#include "hal/dma_types.h"
#include "soc/gdma_channel.h"
#include "soc/soc_caps.h"
#if SOC_GDMA_SUPPORTED
#include "soc/gdma_channel.h"
#include "hal/gdma_ll.h"
#endif /* SOC_GDMA_SUPPORTED */
#ifdef __cplusplus
extern "C"
@ -22,17 +25,17 @@ extern "C"
#if (SOC_AES_GDMA) || (SOC_SHA_GDMA)
#if (SOC_GDMA_TRIG_PERIPH_AES0_BUS == SOC_GDMA_BUS_AHB) || (SOC_GDMA_TRIG_PERIPH_SHA0_BUS == SOC_GDMA_BUS_AHB)
#define DMA_DESC_MEM_ALIGN_SIZE 4
#define DMA_DESC_MEM_ALIGN_SIZE GDMA_LL_AHB_DESC_ALIGNMENT
typedef dma_descriptor_align4_t crypto_dma_desc_t;
#elif (SOC_GDMA_TRIG_PERIPH_AES0_BUS == SOC_GDMA_BUS_AXI) || (SOC_GDMA_TRIG_PERIPH_SHA0_BUS == SOC_GDMA_BUS_AXI)
#define DMA_DESC_MEM_ALIGN_SIZE 8
#define DMA_DESC_MEM_ALIGN_SIZE GDMA_LL_AXI_DESC_ALIGNMENT
typedef dma_descriptor_align8_t crypto_dma_desc_t;
#else
#error "As we support a shared crypto GDMA layer for the AES and the SHA peripheral, both the peripherals must use the same GDMA bus"
#endif /* (SOC_GDMA_TRIG_PERIPH_AES0_BUS == SOC_GDMA_BUS_AHB) || (SOC_GDMA_TRIG_PERIPH_AES0_BUS == SOC_GDMA_BUS_AHB) */
#elif (SOC_AES_CRYPTO_DMA) || (SOC_SHA_CRYPTO_DMA)
#define DMA_DESC_MEM_ALIGN_SIZE 4
#define DMA_DESC_MEM_ALIGN_SIZE GDMA_LL_AHB_DESC_ALIGNMENT
typedef dma_descriptor_align4_t crypto_dma_desc_t;
#endif /* (SOC_AES_GDMA) && (SOC_SHA_GDMA) */