mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
global: rename esp32s2beta to esp32s2
This commit is contained in:
morris
parent
95743f4ee6
commit
e30cd361a8
8
Kconfig
8
Kconfig
@ -24,22 +24,22 @@ mainmenu "Espressif IoT Development Framework Configuration"
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bool
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default "y" if IDF_TARGET="esp32"
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config IDF_TARGET_ESP32S2BETA
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config IDF_TARGET_ESP32S2
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bool
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default "y" if IDF_TARGET="esp32s2beta"
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default "y" if IDF_TARGET="esp32s2"
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select FREERTOS_UNICORE
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config IDF_FIRMWARE_CHIP_ID
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hex
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default 0x0000 if IDF_TARGET_ESP32
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default 0x0002 if IDF_TARGET_ESP32S2BETA
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default 0x0002 if IDF_TARGET_ESP32S2
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default 0xFFFF
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menu "SDK tool configuration"
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config SDK_TOOLPREFIX
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string "Compiler toolchain path/prefix"
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default "xtensa-esp32-elf-" if IDF_TARGET_ESP32
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default "xtensa-esp32s2-elf-" if IDF_TARGET_ESP32S2BETA
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default "xtensa-esp32s2-elf-" if IDF_TARGET_ESP32S2
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help
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The prefix/path that is used to call the toolchain. The default setting assumes
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a crosstool-ng gcc setup that is in your PATH.
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@ -158,7 +158,7 @@
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#include <sys/param.h>
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#include "soc/soc.h"
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#include "soc/dport_reg.h"
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#if CONFIG_IDF_TARGET_ESP32S2BETA
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#if CONFIG_IDF_TARGET_ESP32S2
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#include "soc/sensitive_reg.h"
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#endif
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#include "eri.h"
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@ -210,7 +210,7 @@ const static char *TAG = "esp_apptrace";
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#define TRACEMEM_MUX_BLK0_ONLY 1
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#define TRACEMEM_MUX_BLK1_ONLY 2
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#define TRACEMEM_MUX_PROBLK1_APPBLK0 3
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#elif CONFIG_IDF_TARGET_ESP32S2
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#define TRACEMEM_MUX_BLK0_NUM 19
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#define TRACEMEM_MUX_BLK1_NUM 20
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#define TRACEMEM_BLK_NUM2ADDR(_n_) (0x3FFB8000UL + 0x4000UL*((_n_)-4))
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@ -244,7 +244,7 @@ static volatile uint8_t *s_trax_blocks[] = {
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(volatile uint8_t *) 0x3FFFC000,
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(volatile uint8_t *) 0x3FFF8000
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};
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#elif CONFIG_IDF_TARGET_ESP32S2
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static volatile uint8_t *s_trax_blocks[] = {
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(volatile uint8_t *)TRACEMEM_BLK_NUM2ADDR(TRACEMEM_MUX_BLK0_NUM),
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(volatile uint8_t *)TRACEMEM_BLK_NUM2ADDR(TRACEMEM_MUX_BLK1_NUM)
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@ -435,7 +435,7 @@ static inline void esp_apptrace_trax_select_memory_block(int block_num)
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// select memory block to be exposed to the TRAX module (accessed by host)
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#if CONFIG_IDF_TARGET_ESP32
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DPORT_WRITE_PERI_REG(DPORT_TRACEMEM_MUX_MODE_REG, block_num ? TRACEMEM_MUX_BLK0_ONLY : TRACEMEM_MUX_BLK1_ONLY);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#elif CONFIG_IDF_TARGET_ESP32S2
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DPORT_WRITE_PERI_REG(DPORT_PMS_OCCUPY_3_REG, block_num ? BIT(TRACEMEM_MUX_BLK0_NUM-4) : BIT(TRACEMEM_MUX_BLK1_NUM-4));
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#endif
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}
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@ -18,8 +18,8 @@
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#include "sdkconfig.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/clk.h"
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#include "esp32s2beta/clk.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/clk.h"
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#endif
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///////////////////////////////////////////////////////////////////////////////
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@ -26,8 +26,8 @@
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#include "hal/timer_ll.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/libc_stubs.h"
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#include "esp32s2beta/rom/libc_stubs.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/libc_stubs.h"
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#endif
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#if CONFIG_APPTRACE_GCOV_ENABLE
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@ -66,9 +66,9 @@ Revision: $Rev: 3734 $
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/ets_sys.h"
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#include "esp32/clk.h"
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#include "esp32s2beta/rom/ets_sys.h"
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#include "esp32s2beta/clk.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/ets_sys.h"
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#include "esp32s2/clk.h"
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#endif
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#include "esp_app_trace.h"
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#include "esp_app_trace_util.h"
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@ -78,9 +78,9 @@ Revision: $Rev: 3734 $
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/ets_sys.h"
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#include "esp32/clk.h"
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#include "esp32s2beta/rom/ets_sys.h"
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#include "esp32s2beta/clk.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/ets_sys.h"
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#include "esp32s2/clk.h"
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#endif
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@ -140,7 +140,7 @@ extern const SEGGER_SYSVIEW_OS_API SYSVIEW_X_OS_TraceAPI;
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// CCOUNT is incremented at CPU frequency
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#if CONFIG_IDF_TARGET_ESP32
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#define SYSVIEW_TIMESTAMP_FREQ (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ * 1000000)
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#elif CONFIG_IDF_TARGET_ESP32S2
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#define SYSVIEW_TIMESTAMP_FREQ (CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ * 1000000)
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#endif
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#endif // TS_USE_CCOUNT
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@ -20,8 +20,8 @@
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/ets_sys.h"
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#include "esp32s2beta/rom/ets_sys.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/ets_sys.h"
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#endif
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#include "esp_app_trace.h"
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@ -10,9 +10,9 @@
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/spi_flash.h"
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#include "esp32/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#include "esp32s2beta/rom/spi_flash.h"
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#include "esp32s2beta/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/spi_flash.h"
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#include "esp32s2/rom/rtc.h"
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#endif
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#include "freertos/FreeRTOS.h"
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@ -206,11 +206,11 @@ menu "Bootloader config"
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depends on BOOTLOADER_APP_ANTI_ROLLBACK
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range 1 32 if IDF_TARGET_ESP32
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default 32 if IDF_TARGET_ESP32
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range 1 16 if IDF_TARGET_ESP32S2BETA
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default 16 if IDF_TARGET_ESP32S2BETA
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range 1 16 if IDF_TARGET_ESP32S2
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default 16 if IDF_TARGET_ESP32S2
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help
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The size of the efuse secure version field.
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Its length is limited to 32 bits for ESP32 and 16 bits for ESP32S2BETA.
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Its length is limited to 32 bits for ESP32 and 16 bits for ESP32-S2.
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This determines how many times the security version can be increased.
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config BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE
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@ -468,7 +468,7 @@ menu "Security features"
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choice SECURE_FLASH_ENCRYPTION_KEYSIZE
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bool "Size of generated AES-XTS key"
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default SECURE_FLASH_ENCRYPTION_AES128
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depends on IDF_TARGET_ESP32S2BETA && SECURE_FLASH_ENC_ENABLED
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depends on IDF_TARGET_ESP32S2 && SECURE_FLASH_ENC_ENABLED
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help
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Size of generated AES-XTS key.
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@ -12,7 +12,7 @@ set(srcs
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)
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if(IDF_TARGET STREQUAL "esp32")
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# Not supported on ESP32S2Beta yet
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# Not supported on ESP32S2 yet
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list(APPEND srcs "src/flash_encrypt.c")
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endif()
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@ -19,8 +19,8 @@ ifndef IS_BOOTLOADER_BUILD
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COMPONENT_OBJEXCLUDE := src/bootloader_init.o
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endif
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COMPONENT_OBJEXCLUDE += src/bootloader_flash_config_esp32s2beta.o \
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src/bootloader_efuse_esp32s2beta.o
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COMPONENT_OBJEXCLUDE += src/bootloader_flash_config_esp32s2.o \
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src/bootloader_efuse_esp32s2.o
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#
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# Secure boot signing key support
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@ -19,8 +19,8 @@
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// RESET_REASON is declared in rom/rtc.h
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#include "esp32s2beta/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/rtc.h"
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#endif
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#ifdef __cplusplus
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@ -52,7 +52,7 @@ static inline /** @cond */ IRAM_ATTR /** @endcond */ bool esp_flash_encryption_e
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uint32_t flash_crypt_cnt;
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#if CONFIG_IDF_TARGET_ESP32
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flash_crypt_cnt = REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_FLASH_CRYPT_CNT);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#elif CONFIG_IDF_TARGET_ESP32S2
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flash_crypt_cnt = REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_SPI_BOOT_CRYPT_CNT);
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#endif
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/* __builtin_parity is in flash, so we calculate parity inline */
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@ -18,8 +18,8 @@
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#include "soc/efuse_periph.h"
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#include "sdkconfig.h"
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#if CONFIG_IDF_TARGET_ESP32S2BETA
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#include "esp32s2beta/rom/efuse.h"
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#if CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/efuse.h"
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#endif
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#ifdef CONFIG_SECURE_BOOT_ENABLED
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@ -48,7 +48,7 @@ static inline bool esp_secure_boot_enabled(void)
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{
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#if CONFIG_IDF_TARGET_ESP32
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return REG_READ(EFUSE_BLK0_RDATA6_REG) & EFUSE_RD_ABS_DONE_0;
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#elif CONFIG_IDF_TARGET_ESP32S2
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return ets_efuse_secure_boot_enabled();
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#endif
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}
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@ -21,9 +21,9 @@
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#ifdef CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/uart.h"
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#include "esp32/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#include "esp32s2beta/rom/uart.h"
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#include "esp32s2beta/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/uart.h"
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#include "esp32s2/rom/rtc.h"
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#endif
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void bootloader_clock_configure(void)
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@ -55,7 +55,7 @@ void bootloader_clock_configure(void)
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#if CONFIG_IDF_TARGET_ESP32
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clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ;
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clk_cfg.cpu_freq_mhz = cpu_freq_mhz;
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#elif CONFIG_IDF_TARGET_ESP32S2
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clk_cfg.xtal_freq = RTC_XTAL_FREQ_40M;
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clk_cfg.cpu_freq = RTC_CPU_FREQ_80M;
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#endif
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@ -21,11 +21,11 @@
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#include "esp32/rom/spi_flash.h"
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#include "esp32/rom/crc.h"
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#include "esp32/rom/gpio.h"
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#include "esp32s2beta/rom/spi_flash.h"
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#include "esp32s2beta/rom/crc.h"
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#include "esp32s2beta/rom/ets_sys.h"
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#include "esp32s2beta/rom/gpio.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/spi_flash.h"
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#include "esp32s2/rom/crc.h"
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#include "esp32s2/rom/ets_sys.h"
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#include "esp32s2/rom/gpio.h"
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#endif
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#include "esp_flash_partitions.h"
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#include "bootloader_flash.h"
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@ -18,6 +18,6 @@
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uint8_t bootloader_common_get_chip_revision(void)
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{
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/* No other revisions for ESP32-S2beta */
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/* No other revisions for ESP32-S2 */
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return 0;
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}
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@ -17,8 +17,8 @@
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#include <esp_log.h>
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#include <esp_spi_flash.h> /* including in bootloader for error values */
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#include <esp_flash_encrypt.h>
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#if CONFIG_IDF_TARGET_ESP32S2BETA
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#include "esp32s2beta/rom/spi_flash.h"
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#if CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/spi_flash.h"
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#endif
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#ifndef BOOTLOADER_BUILD
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@ -72,7 +72,7 @@ esp_err_t bootloader_flash_write(size_t dest_addr, void *src, size_t size, bool
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if (write_encrypted) {
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#if CONFIG_IDF_TARGET_ESP32
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return spi_flash_write_encrypted(dest_addr, src, size);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#elif CONFIG_IDF_TARGET_ESP32S2
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return SPI_Encrypt_Write(dest_addr, src, size);
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#endif
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} else {
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@ -96,9 +96,9 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/spi_flash.h"
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#include "esp32/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#include "esp32s2beta/rom/spi_flash.h"
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#include "esp32s2beta/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/spi_flash.h"
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#include "esp32s2/rom/cache.h"
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#include "soc/cache_memory.h"
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#endif
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static const char *TAG = "bootloader_flash";
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@ -111,7 +111,7 @@ static const char *TAG = "bootloader_flash";
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#define MMU_SIZE (0x320000)
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#define MMU_BLOCK50_VADDR (MMU_BLOCK0_VADDR + MMU_SIZE)
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#define FLASH_READ_VADDR MMU_BLOCK50_VADDR
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#elif CONFIG_IDF_TARGET_ESP32S2
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/* Use first 63 blocks in MMU for bootloader_mmap,
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63th block for bootloader_flash_read
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*/
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@ -153,7 +153,7 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size)
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Read_Disable(0);
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Cache_Flush(0);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#elif CONFIG_IDF_TARGET_ESP32S2
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uint32_t autoload = Cache_Suspend_ICache();
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Cache_Invalidate_ICache_All();
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#endif
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@ -161,21 +161,21 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size)
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src_addr & MMU_FLASH_MASK, count, size, src_addr, src_addr_aligned );
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#if CONFIG_IDF_TARGET_ESP32
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int e = cache_flash_mmu_set(0, 0, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#elif CONFIG_IDF_TARGET_ESP32S2
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int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0);
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#endif
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if (e != 0) {
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ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Read_Enable(0);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#elif CONFIG_IDF_TARGET_ESP32S2
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Cache_Resume_ICache(autoload);
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#endif
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return NULL;
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}
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Read_Enable(0);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#elif CONFIG_IDF_TARGET_ESP32S2
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Cache_Resume_ICache(autoload);
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#endif
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@ -192,7 +192,7 @@ void bootloader_munmap(const void *mapping)
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Cache_Read_Disable(0);
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Cache_Flush(0);
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mmu_init(0);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#elif CONFIG_IDF_TARGET_ESP32S2
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//TODO, save the autoload value.
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Cache_Suspend_ICache();
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Cache_Invalidate_ICache_All();
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@ -222,13 +222,13 @@ static esp_err_t bootloader_flash_read_no_decrypt(size_t src_addr, void *dest, s
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Read_Disable(0);
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Cache_Flush(0);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#elif CONFIG_IDF_TARGET_ESP32S2
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uint32_t autoload = Cache_Suspend_ICache();
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#endif
|
||||
esp_rom_spiflash_result_t r = esp_rom_spiflash_read(src_addr, dest, size);
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
Cache_Read_Enable(0);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
Cache_Resume_ICache(autoload);
|
||||
#endif
|
||||
|
||||
@ -248,21 +248,21 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
Cache_Read_Disable(0);
|
||||
Cache_Flush(0);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
uint32_t autoload = Cache_Suspend_ICache();
|
||||
Cache_Invalidate_ICache_All();
|
||||
#endif
|
||||
ESP_LOGD(TAG, "mmu set block paddr=0x%08x (was 0x%08x)", map_at, current_read_mapping);
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
int e = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0);
|
||||
#endif
|
||||
if (e != 0) {
|
||||
ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
Cache_Read_Enable(0);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
Cache_Resume_ICache(autoload);
|
||||
#endif
|
||||
return ESP_FAIL;
|
||||
@ -270,7 +270,7 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
|
||||
current_read_mapping = map_at;
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
Cache_Read_Enable(0);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
Cache_Resume_ICache(autoload);
|
||||
#endif
|
||||
}
|
||||
@ -327,7 +327,7 @@ esp_err_t bootloader_flash_write(size_t dest_addr, void *src, size_t size, bool
|
||||
if (write_encrypted) {
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
return spi_to_esp_err(esp_rom_spiflash_write_encrypted(dest_addr, src, size));
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
// TODO: use the same ROM AP here
|
||||
return spi_to_esp_err(SPI_Encrypt_Write(dest_addr, src, size));
|
||||
#endif
|
||||
|
||||
@ -17,9 +17,9 @@
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp32s2beta/rom/gpio.h"
|
||||
#include "esp32s2beta/rom/spi_flash.h"
|
||||
#include "esp32s2beta/rom/efuse.h"
|
||||
#include "esp32s2/rom/gpio.h"
|
||||
#include "esp32s2/rom/spi_flash.h"
|
||||
#include "esp32s2/rom/efuse.h"
|
||||
#include "soc/gpio_periph.h"
|
||||
#include "soc/efuse_reg.h"
|
||||
#include "soc/spi_reg.h"
|
||||
@ -22,7 +22,7 @@
|
||||
#include "soc/i2s_periph.h"
|
||||
#include "esp_log.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
#if CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "soc/apb_saradc_reg.h"
|
||||
#endif
|
||||
|
||||
@ -62,7 +62,7 @@ void bootloader_fill_random(void *buffer, size_t length)
|
||||
random ^= REG_READ(WDEV_RND_REG);
|
||||
RSR(CCOUNT, now);
|
||||
} while (now - start < 80 * 32 * 2); /* extra factor of 2 is precautionary */
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
// ToDo: Get random from register
|
||||
random = 12345678;
|
||||
#endif
|
||||
@ -101,7 +101,7 @@ void bootloader_random_enable(void)
|
||||
#endif // BOOTLOADER_BUILD
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_START_TOP);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
/* Disable IO1 digital function for random function. */
|
||||
PIN_INPUT_DISABLE(PERIPHS_IO_MUX_GPIO1_U);
|
||||
PIN_PULLDWN_DIS(PERIPHS_IO_MUX_GPIO1_U);
|
||||
@ -126,7 +126,7 @@ void bootloader_random_enable(void)
|
||||
SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S);
|
||||
SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE);
|
||||
SET_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD);
|
||||
WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD);
|
||||
WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD);
|
||||
@ -145,7 +145,7 @@ void bootloader_random_enable(void)
|
||||
CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_SAR_SEL);
|
||||
SET_PERI_REG_BITS(I2S_SAMPLE_RATE_CONF_REG(0), I2S_RX_BCK_DIV_NUM, 20, I2S_RX_BCK_DIV_NUM_S);
|
||||
SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_TO_I2S);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
SET_PERI_REG_BITS(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 4, APB_SARADC_SAR_CLK_DIV_S);
|
||||
SET_PERI_REG_BITS(APB_SARADC_FSM_REG, APB_SARADC_RSTB_WAIT, 8, APB_SARADC_RSTB_WAIT_S); /* was 1 */
|
||||
SET_PERI_REG_BITS(APB_SARADC_CTRL_REG, APB_SARADC_WORK_MODE, 0, APB_SARADC_WORK_MODE_S);
|
||||
@ -184,7 +184,7 @@ void bootloader_random_disable(void)
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE);
|
||||
#endif
|
||||
|
||||
@ -194,7 +194,7 @@ void bootloader_random_disable(void)
|
||||
CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX
|
||||
| SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S);
|
||||
SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST);
|
||||
CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_SEL | APB_SARADC_DATA_TO_I2S);
|
||||
SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
|
||||
|
||||
@ -29,16 +29,16 @@
|
||||
#include "esp32/rom/uart.h"
|
||||
#include "esp32/rom/gpio.h"
|
||||
#include "esp32/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#include "esp32s2beta/rom/cache.h"
|
||||
#include "esp32s2beta/rom/efuse.h"
|
||||
#include "esp32s2beta/rom/ets_sys.h"
|
||||
#include "esp32s2beta/rom/spi_flash.h"
|
||||
#include "esp32s2beta/rom/crc.h"
|
||||
#include "esp32s2beta/rom/rtc.h"
|
||||
#include "esp32s2beta/rom/uart.h"
|
||||
#include "esp32s2beta/rom/gpio.h"
|
||||
#include "esp32s2beta/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/rom/cache.h"
|
||||
#include "esp32s2/rom/efuse.h"
|
||||
#include "esp32s2/rom/ets_sys.h"
|
||||
#include "esp32s2/rom/spi_flash.h"
|
||||
#include "esp32s2/rom/crc.h"
|
||||
#include "esp32s2/rom/rtc.h"
|
||||
#include "esp32s2/rom/uart.h"
|
||||
#include "esp32s2/rom/gpio.h"
|
||||
#include "esp32s2/rom/secure_boot.h"
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/cache_memory.h"
|
||||
#else
|
||||
@ -679,7 +679,7 @@ static void set_cache_and_start_app(
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
Cache_Read_Disable(0);
|
||||
Cache_Flush(0);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
uint32_t autoload = Cache_Suspend_ICache();
|
||||
Cache_Invalidate_ICache_All();
|
||||
#endif
|
||||
@ -691,7 +691,7 @@ static void set_cache_and_start_app(
|
||||
for (int i = 0; i < DPORT_FLASH_MMU_TABLE_SIZE; i++) {
|
||||
DPORT_PRO_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL;
|
||||
}
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
for (int i = 0; i < FLASH_MMU_TABLE_SIZE; i++) {
|
||||
FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL;
|
||||
}
|
||||
@ -702,7 +702,7 @@ static void set_cache_and_start_app(
|
||||
drom_addr & MMU_FLASH_MASK, drom_load_addr_aligned, drom_size, drom_page_count);
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
rc = cache_flash_mmu_set(0, 0, drom_load_addr_aligned, drom_addr & MMU_FLASH_MASK, 64, drom_page_count);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0);
|
||||
#endif
|
||||
ESP_LOGV(TAG, "rc=%d", rc);
|
||||
@ -716,7 +716,7 @@ static void set_cache_and_start_app(
|
||||
irom_addr & MMU_FLASH_MASK, irom_load_addr_aligned, irom_size, irom_page_count);
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
rc = cache_flash_mmu_set(0, 0, irom_load_addr_aligned, irom_addr & MMU_FLASH_MASK, 64, irom_page_count);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
uint32_t iram1_used = 0;
|
||||
if (irom_load_addr + irom_size > IRAM1_ADDRESS_LOW) {
|
||||
iram1_used = 1;
|
||||
@ -740,12 +740,12 @@ static void set_cache_and_start_app(
|
||||
(DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) |
|
||||
(DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 |
|
||||
DPORT_APP_CACHE_MASK_DRAM1 );
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
REG_CLR_BIT( EXTMEM_PRO_ICACHE_CTRL1_REG, (EXTMEM_PRO_ICACHE_MASK_IRAM0) | (EXTMEM_PRO_ICACHE_MASK_IRAM1 & 0) | EXTMEM_PRO_ICACHE_MASK_DROM0 );
|
||||
#endif
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
Cache_Read_Enable(0);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
Cache_Resume_ICache(autoload);
|
||||
#endif
|
||||
// Application will need to do Cache_Flush(1) and Cache_Read_Enable(1)
|
||||
|
||||
@ -17,19 +17,19 @@
|
||||
#include "soc/efuse_reg.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
#include "esp32s2beta/rom/efuse.h"
|
||||
#include "esp32s2beta/rom/gpio.h"
|
||||
#include "esp32s2beta/rom/spi_flash.h"
|
||||
#include "esp32s2/rom/efuse.h"
|
||||
#include "esp32s2/rom/gpio.h"
|
||||
#include "esp32s2/rom/spi_flash.h"
|
||||
|
||||
#include "bootloader_init.h"
|
||||
#include "bootloader_clock.h"
|
||||
#include "bootloader_flash_config.h"
|
||||
|
||||
#include "esp32s2beta/rom/cache.h"
|
||||
#include "esp32s2beta/rom/ets_sys.h"
|
||||
#include "esp32s2beta/rom/spi_flash.h"
|
||||
#include "esp32s2beta/rom/rtc.h"
|
||||
#include "esp32s2beta/rom/uart.h"
|
||||
#include "esp32s2/rom/cache.h"
|
||||
#include "esp32s2/rom/ets_sys.h"
|
||||
#include "esp32s2/rom/spi_flash.h"
|
||||
#include "esp32s2/rom/rtc.h"
|
||||
#include "esp32s2/rom/uart.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_image_format.h"
|
||||
@ -17,7 +17,7 @@
|
||||
#include <assert.h>
|
||||
#include <sys/param.h>
|
||||
|
||||
#include "esp32s2beta/rom/sha.h"
|
||||
#include "esp32s2/rom/sha.h"
|
||||
|
||||
static SHA_CTX ctx;
|
||||
|
||||
@ -22,9 +22,9 @@
|
||||
#include "esp_flash_partitions.h"
|
||||
#include "esp_secure_boot.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp32s2beta/rom/secure_boot.h"
|
||||
#include "esp32s2beta/rom/cache.h"
|
||||
#include "esp32s2beta/rom/efuse.h"
|
||||
#include "esp32s2/rom/secure_boot.h"
|
||||
#include "esp32s2/rom/cache.h"
|
||||
#include "esp32s2/rom/efuse.h"
|
||||
|
||||
static const char *TAG = "flash_encrypt";
|
||||
|
||||
@ -13,7 +13,7 @@
|
||||
// limitations under the License.
|
||||
#include "esp_secure_boot.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp32s2beta/rom/secure_boot.h"
|
||||
#include "esp32s2/rom/secure_boot.h"
|
||||
|
||||
#define TAG "secure_boot"
|
||||
|
||||
@ -17,7 +17,7 @@
|
||||
#include "bootloader_sha.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_image_format.h"
|
||||
#include "esp32s2beta/rom/secure_boot.h"
|
||||
#include "esp32s2/rom/secure_boot.h"
|
||||
|
||||
static const char* TAG = "secure_boot";
|
||||
|
||||
@ -26,9 +26,9 @@
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/rom/rtc.h"
|
||||
#include "esp32/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#include "esp32s2beta/rom/rtc.h"
|
||||
#include "esp32s2beta/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/rom/rtc.h"
|
||||
#include "esp32s2/rom/secure_boot.h"
|
||||
#endif
|
||||
|
||||
/* Checking signatures as part of verifying images is necessary:
|
||||
@ -204,7 +204,7 @@ static esp_err_t image_load(esp_image_load_mode_t mode, const esp_partition_pos_
|
||||
esptool.py may have rewritten the header - rely on esptool.py having verified the bootloader at flashing time, instead.)
|
||||
*/
|
||||
bool verify_sha;
|
||||
#if CONFIG_SECURE_BOOT_ENABLED && CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#if CONFIG_SECURE_BOOT_ENABLED && CONFIG_IDF_TARGET_ESP32S2
|
||||
verify_sha = true;
|
||||
#else // ESP32, or ESP32S2 without secure boot enabled
|
||||
verify_sha = (data->start_addr != ESP_BOOTLOADER_OFFSET);
|
||||
@ -638,7 +638,7 @@ static esp_err_t verify_secure_boot_signature(bootloader_sha256_handle_t sha_han
|
||||
bootloader_munmap(simple_hash);
|
||||
}
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
// Pad to 4096 byte sector boundary
|
||||
if (end % FLASH_SECTOR_SIZE != 0) {
|
||||
uint32_t pad_len = FLASH_SECTOR_SIZE - (end % FLASH_SECTOR_SIZE);
|
||||
@ -677,7 +677,7 @@ static esp_err_t verify_secure_boot_signature(bootloader_sha256_handle_t sha_han
|
||||
return ESP_ERR_IMAGE_INVALID;
|
||||
}
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
// Adjust image length result to include the appended signature
|
||||
data->image_len = end - data->start_addr + sizeof(ets_secure_boot_signature_t);
|
||||
#endif
|
||||
|
||||
@ -19,9 +19,9 @@
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/rom/spi_flash.h"
|
||||
#include "esp32/rom/efuse.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#include "esp32s2beta/rom/spi_flash.h"
|
||||
#include "esp32s2beta/rom/efuse.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/rom/spi_flash.h"
|
||||
#include "esp32s2/rom/efuse.h"
|
||||
#include "soc/spi_mem_struct.h"
|
||||
#endif
|
||||
#include "soc/spi_struct.h"
|
||||
@ -33,7 +33,7 @@
|
||||
/* SPI flash controller */
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#define SPIFLASH SPI1
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#define SPIFLASH SPIMEM1
|
||||
#endif
|
||||
|
||||
@ -141,7 +141,7 @@ uint32_t bootloader_read_flash_id(void)
|
||||
return id;
|
||||
}
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
#define FLASH_WRAP_CMD 0x77
|
||||
typedef enum {
|
||||
FLASH_WRAP_MODE_8B = 0,
|
||||
@ -212,7 +212,7 @@ void bootloader_enable_qio_mode(void)
|
||||
enable_qio_mode(chip_data[i].read_status_fn,
|
||||
chip_data[i].write_status_fn,
|
||||
chip_data[i].status_qio_bit);
|
||||
#if CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
spi_flash_wrap_set(FLASH_WRAP_MODE_DISABLE);
|
||||
#endif
|
||||
}
|
||||
@ -277,7 +277,7 @@ static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn,
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
esp_rom_spiflash_select_qio_pins(CONFIG_BOOTLOADER_SPI_WP_PIN, spiconfig);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
if (ets_efuse_get_wp_pad() <= MAX_PAD_GPIO_NUM) {
|
||||
esp_rom_spiflash_select_qio_pins(ets_efuse_get_wp_pad(), spiconfig);
|
||||
} else {
|
||||
@ -340,7 +340,7 @@ static uint32_t execute_flash_command(uint8_t command, uint32_t mosi_data, uint8
|
||||
uint32_t old_ctrl_reg = SPIFLASH.ctrl.val;
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
SPIFLASH.ctrl.val = SPI_WP_REG_M; // keep WP high while idle, otherwise leave DIO mode
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
SPIFLASH.ctrl.val = SPI_MEM_WP_REG_M; // keep WP high while idle, otherwise leave DIO mode
|
||||
#endif
|
||||
SPIFLASH.user.usr_dummy = 0;
|
||||
@ -352,13 +352,13 @@ static uint32_t execute_flash_command(uint8_t command, uint32_t mosi_data, uint8
|
||||
SPIFLASH.user.usr_miso = miso_len > 0;
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
SPIFLASH.miso_dlen.usr_miso_dbitlen = miso_len ? (miso_len - 1) : 0;
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
SPIFLASH.miso_dlen.usr_miso_bit_len = miso_len ? (miso_len - 1) : 0;
|
||||
#endif
|
||||
SPIFLASH.user.usr_mosi = mosi_len > 0;
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
SPIFLASH.mosi_dlen.usr_mosi_dbitlen = mosi_len ? (mosi_len - 1) : 0;
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
SPIFLASH.mosi_dlen.usr_mosi_bit_len = mosi_len ? (mosi_len - 1) : 0;
|
||||
#endif
|
||||
SPIFLASH.data_buf[0] = mosi_data;
|
||||
|
||||
@ -33,7 +33,7 @@ TEST_CASE("Verify bootloader image in flash", "[bootloader_support]")
|
||||
TEST_ASSERT_EQUAL(data.image_len, bootloader_length);
|
||||
}
|
||||
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
|
||||
TEST_CASE("Verify unit test app image", "[bootloader_support]")
|
||||
{
|
||||
esp_image_metadata_t data = { 0 };
|
||||
|
||||
@ -34,11 +34,11 @@ if(IDF_TARGET STREQUAL "esp32")
|
||||
list(APPEND includes "esp32/include")
|
||||
endif()
|
||||
|
||||
if(IDF_TARGET STREQUAL "esp32s2beta")
|
||||
list(APPEND srcs "esp32s2beta/rtc_tempsensor.c"
|
||||
"esp32s2beta/touch_sensor.c")
|
||||
if(IDF_TARGET STREQUAL "esp32s2")
|
||||
list(APPEND srcs "esp32s2/rtc_tempsensor.c"
|
||||
"esp32s2/touch_sensor.c")
|
||||
# currently only S2 beta has its own target-specific includes
|
||||
list(APPEND includes "esp32s2beta/include")
|
||||
list(APPEND includes "esp32s2/include")
|
||||
endif()
|
||||
|
||||
idf_component_register(SRCS "${srcs}"
|
||||
|
||||
@ -23,7 +23,7 @@
|
||||
#include "soc/sens_reg.h"
|
||||
#include "soc/sens_struct.h"
|
||||
#include "temp_sensor.h"
|
||||
#include "esp32s2beta/rom/ets_sys.h"
|
||||
#include "esp32s2/rom/ets_sys.h"
|
||||
|
||||
static const char *TAG = "tsens";
|
||||
|
||||
@ -28,7 +28,7 @@
|
||||
#include "driver/gpio.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
#include "esp32s2beta/rom/ets_sys.h"
|
||||
#include "esp32s2/rom/ets_sys.h"
|
||||
#include "hal/touch_sensor_types.h"
|
||||
#include "hal/touch_sensor_hal.h"
|
||||
|
||||
@ -49,7 +49,7 @@ typedef enum {
|
||||
ADC1_CHANNEL_7, /*!< ADC1 channel 7 is GPIO35 (ESP32), GPIO8 (ESP32-S2) */
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
ADC1_CHANNEL_MAX,
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
ADC1_CHANNEL_8, /*!< ADC1 channel 6 is GPIO9 (ESP32-S2)*/
|
||||
ADC1_CHANNEL_9, /*!< ADC1 channel 7 is GPIO10 (ESP32-S2) */
|
||||
ADC1_CHANNEL_MAX,
|
||||
|
||||
@ -24,8 +24,8 @@
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/rom/gpio.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#include "esp32s2beta/rom/gpio.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/rom/gpio.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS
|
||||
|
||||
@ -120,7 +120,7 @@ static uint32_t ledc_get_src_clk_freq(ledc_clk_cfg_t clk_cfg)
|
||||
src_clk_freq = LEDC_REF_CLK_HZ;
|
||||
} else if (clk_cfg == LEDC_USE_RTC8M_CLK) {
|
||||
src_clk_freq = s_ledc_slow_clk_8M;
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32S2
|
||||
} else if (clk_cfg == LEDC_USE_XTAL_CLK) {
|
||||
src_clk_freq = rtc_clk_xtal_freq_get() * 1000000;
|
||||
#endif
|
||||
|
||||
@ -66,7 +66,7 @@ static uint32_t get_clk_en_mask(periph_module_t periph)
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
case PERIPH_UART2_MODULE:
|
||||
return DPORT_UART2_CLK_EN;
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
case PERIPH_USB_MODULE:
|
||||
return DPORT_USB_CLK_EN;
|
||||
#endif
|
||||
@ -105,7 +105,7 @@ static uint32_t get_clk_en_mask(periph_module_t periph)
|
||||
return DPORT_SPI3_CLK_EN;
|
||||
case PERIPH_SPI_DMA_MODULE:
|
||||
return DPORT_SPI_DMA_CLK_EN;
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
case PERIPH_FSPI_MODULE:
|
||||
return DPORT_SPI2_CLK_EN;
|
||||
case PERIPH_HSPI_MODULE:
|
||||
@ -130,7 +130,7 @@ static uint32_t get_clk_en_mask(periph_module_t periph)
|
||||
case PERIPH_WIFI_MODULE:
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
return DPORT_WIFI_CLK_WIFI_EN_M;
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
return 0;
|
||||
#endif
|
||||
case PERIPH_BT_MODULE:
|
||||
@ -168,7 +168,7 @@ static uint32_t get_rst_en_mask(periph_module_t periph, bool enable)
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
case PERIPH_UART2_MODULE:
|
||||
return DPORT_UART2_RST;
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
case PERIPH_USB_MODULE:
|
||||
return DPORT_USB_RST;
|
||||
#endif
|
||||
@ -207,7 +207,7 @@ static uint32_t get_rst_en_mask(periph_module_t periph, bool enable)
|
||||
return DPORT_SPI3_RST;
|
||||
case PERIPH_SPI_DMA_MODULE:
|
||||
return DPORT_SPI_DMA_RST;
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
case PERIPH_FSPI_MODULE:
|
||||
return DPORT_SPI2_RST;
|
||||
case PERIPH_HSPI_MODULE:
|
||||
@ -290,7 +290,7 @@ static uint32_t get_clk_en_reg(periph_module_t periph)
|
||||
if (periph == PERIPH_AES_MODULE || periph == PERIPH_SHA_MODULE || periph == PERIPH_RSA_MODULE) {
|
||||
return DPORT_PERI_CLK_EN_REG;
|
||||
}
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
if(periph == PERIPH_SPI_SHARED_DMA_MODULE) {
|
||||
return DPORT_PERIP_CLK_EN1_REG;
|
||||
}
|
||||
@ -306,7 +306,7 @@ static uint32_t get_rst_en_reg(periph_module_t periph)
|
||||
if (periph == PERIPH_AES_MODULE || periph == PERIPH_SHA_MODULE || periph == PERIPH_RSA_MODULE) {
|
||||
return DPORT_PERI_RST_EN_REG;
|
||||
}
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
if(periph == PERIPH_SPI_SHARED_DMA_MODULE){
|
||||
return DPORT_PERIP_CLK_EN1_REG;
|
||||
}
|
||||
|
||||
@ -31,8 +31,8 @@
|
||||
#include "sdkconfig.h"
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#include "esp32s2beta/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/rom/ets_sys.h"
|
||||
#endif
|
||||
|
||||
#ifndef NDEBUG
|
||||
|
||||
@ -105,7 +105,7 @@ int spicommon_irqdma_source_for_host(spi_host_device_t host)
|
||||
|
||||
static inline uint32_t get_dma_periph(int dma_chan)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
if (dma_chan == 1) {
|
||||
return PERIPH_SPI2_DMA_MODULE;
|
||||
} else if (dma_chan==2) {
|
||||
@ -135,7 +135,7 @@ bool spicommon_dma_chan_claim (int dma_chan)
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
periph_module_enable(get_dma_periph(dma_chan));
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
if (dma_chan==1) {
|
||||
periph_module_enable(PERIPH_SPI2_DMA_MODULE);
|
||||
} else if (dma_chan==2) {
|
||||
@ -167,7 +167,7 @@ bool spicommon_dma_chan_free(int dma_chan)
|
||||
//disable the DMA only when all the channels are freed.
|
||||
periph_module_disable(get_dma_periph(dma_chan));
|
||||
}
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
if (dma_chan==1) {
|
||||
periph_module_disable(PERIPH_SPI2_DMA_MODULE);
|
||||
} else if (dma_chan==2) {
|
||||
@ -305,7 +305,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
|
||||
gpio_set_direction(bus_config->mosi_io_num, GPIO_MODE_INPUT);
|
||||
}
|
||||
gpio_matrix_in(bus_config->mosi_io_num, spi_periph_signal[host].spid_in, false);
|
||||
#if CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->mosi_io_num]);
|
||||
#endif
|
||||
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->mosi_io_num], FUNC_GPIO);
|
||||
@ -318,7 +318,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
|
||||
gpio_set_direction(bus_config->miso_io_num, GPIO_MODE_INPUT);
|
||||
}
|
||||
gpio_matrix_in(bus_config->miso_io_num, spi_periph_signal[host].spiq_in, false);
|
||||
#if CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->miso_io_num]);
|
||||
#endif
|
||||
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->miso_io_num], FUNC_GPIO);
|
||||
@ -327,7 +327,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
|
||||
gpio_set_direction(bus_config->quadwp_io_num, GPIO_MODE_INPUT_OUTPUT);
|
||||
gpio_matrix_out(bus_config->quadwp_io_num, spi_periph_signal[host].spiwp_out, false, false);
|
||||
gpio_matrix_in(bus_config->quadwp_io_num, spi_periph_signal[host].spiwp_in, false);
|
||||
#if CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num]);
|
||||
#endif
|
||||
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num], FUNC_GPIO);
|
||||
@ -336,7 +336,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
|
||||
gpio_set_direction(bus_config->quadhd_io_num, GPIO_MODE_INPUT_OUTPUT);
|
||||
gpio_matrix_out(bus_config->quadhd_io_num, spi_periph_signal[host].spihd_out, false, false);
|
||||
gpio_matrix_in(bus_config->quadhd_io_num, spi_periph_signal[host].spihd_in, false);
|
||||
#if CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num]);
|
||||
#endif
|
||||
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num], FUNC_GPIO);
|
||||
@ -349,7 +349,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
|
||||
gpio_set_direction(bus_config->sclk_io_num, GPIO_MODE_INPUT);
|
||||
}
|
||||
gpio_matrix_in(bus_config->sclk_io_num, spi_periph_signal[host].spiclk_in, false);
|
||||
#if CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->sclk_io_num]);
|
||||
#endif
|
||||
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->sclk_io_num], FUNC_GPIO);
|
||||
@ -388,7 +388,7 @@ void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num,
|
||||
gpio_iomux_in(cs_io_num, spi_periph_signal[host].spics_in);
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
gpio_iomux_out(cs_io_num, spi_periph_signal[host].func, false);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
gpio_iomux_out(cs_io_num, spi_periph_signal[host].func, false);
|
||||
#endif
|
||||
} else {
|
||||
|
||||
@ -220,7 +220,7 @@ esp_err_t spi_bus_initialize(spi_host_device_t host, const spi_bus_config_t *bus
|
||||
SPI_CHECK(host>=SPI_HOST && host<=VSPI_HOST, "invalid host", ESP_ERR_INVALID_ARG);
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32
|
||||
SPI_CHECK( dma_chan >= 0 && dma_chan <= 2, "invalid dma channel", ESP_ERR_INVALID_ARG );
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
SPI_CHECK( dma_chan == 0 || dma_chan == host, "invalid dma channel", ESP_ERR_INVALID_ARG );
|
||||
#endif
|
||||
SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH|ESP_INTR_FLAG_EDGE|ESP_INTR_FLAG_INTRDISABLED))==0, "intr flag not allowed", ESP_ERR_INVALID_ARG);
|
||||
|
||||
@ -105,7 +105,7 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b
|
||||
SPI_CHECK(VALID_HOST(host), "invalid host", ESP_ERR_INVALID_ARG);
|
||||
#if defined(CONFIG_IDF_TARGET_ESP32)
|
||||
SPI_CHECK( dma_chan >= 0 && dma_chan <= 2, "invalid dma channel", ESP_ERR_INVALID_ARG );
|
||||
#elif defined(CONFIG_IDF_TARGET_ESP32S2BETA)
|
||||
#elif defined(CONFIG_IDF_TARGET_ESP32S2)
|
||||
SPI_CHECK( dma_chan == 0 || dma_chan == host, "invalid dma channel", ESP_ERR_INVALID_ARG );
|
||||
#endif
|
||||
SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH|ESP_INTR_FLAG_EDGE|ESP_INTR_FLAG_INTRDISABLED))==0, "intr flag not allowed", ESP_ERR_INVALID_ARG);
|
||||
|
||||
@ -48,7 +48,7 @@
|
||||
#define ESP_SPI_SLAVE_TV (12.5*3.5)
|
||||
#define WIRE_DELAY 12.5
|
||||
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
|
||||
#define TEST_SPI_HOST FSPI_HOST
|
||||
#define TEST_SLAVE_HOST HSPI_HOST
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
#include "nvs_flash.h"
|
||||
#include "test_utils.h"
|
||||
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
|
||||
|
||||
static const char* TAG = "test_adc2";
|
||||
|
||||
|
||||
@ -16,8 +16,8 @@
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/rom/uart.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#include "esp32s2beta/rom/uart.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/rom/uart.h"
|
||||
#endif
|
||||
|
||||
#define WAKE_UP_IGNORE 1 // gpio_wakeup function development is not completed yet, set it deprecated.
|
||||
@ -25,7 +25,7 @@
|
||||
#define GPIO_OUTPUT_IO 18 // default output GPIO
|
||||
#define GPIO_INPUT_IO 19 // default input GPIO
|
||||
#define GPIO_OUTPUT_MAX GPIO_NUM_34
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
// ESP32_S2 DEVKIC uses IO19 and IO20 as USB functions, so it is necessary to avoid using IO19, otherwise GPIO io pull up/down function cannot pass
|
||||
#define GPIO_OUTPUT_IO 18 // default output GPIO
|
||||
#define GPIO_INPUT_IO 21 // default input GPIO
|
||||
@ -55,7 +55,7 @@ static gpio_config_t init_io(gpio_num_t num)
|
||||
return io_conf;
|
||||
}
|
||||
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
|
||||
//No runners
|
||||
// edge interrupt event
|
||||
static void gpio_isr_edge_handler(void* arg)
|
||||
@ -169,7 +169,7 @@ TEST_CASE("GPIO config parameters test", "[gpio]")
|
||||
io_config.mode = GPIO_MODE_OUTPUT;
|
||||
// ESP32 34-39 input only, once set as output should log something
|
||||
TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
io_config.pin_bit_mask = (uint64_t)1<<26;
|
||||
TEST_ESP_OK(gpio_config(&io_config));
|
||||
|
||||
@ -183,7 +183,7 @@ TEST_CASE("GPIO config parameters test", "[gpio]")
|
||||
|
||||
}
|
||||
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
|
||||
//No runners
|
||||
TEST_CASE("GPIO rising edge interrupt test", "[gpio][test_env=UT_T1_GPIO]")
|
||||
{
|
||||
@ -375,7 +375,7 @@ TEST_CASE("GPIO enable and disable interrupt test", "[gpio][test_env=UT_T1_GPIO]
|
||||
TEST_ASSERT(gpio_isr_handler_add(GPIO_INPUT_IO, gpio_isr_level_handler, (void*) GPIO_INPUT_IO) == ESP_ERR_INVALID_STATE);
|
||||
TEST_ASSERT(gpio_isr_handler_remove(GPIO_INPUT_IO) == ESP_ERR_INVALID_STATE);
|
||||
}
|
||||
#endif //DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#endif //DISABLED_FOR_TARGETS(ESP32S2)
|
||||
|
||||
// ESP32 Connect GPIO18 with GPIO19, ESP32-S2 Connect GPIO18 with GPIO21
|
||||
// use multimeter to test the voltage, so it is ignored in CI
|
||||
@ -408,7 +408,7 @@ TEST_CASE("GPIO set gpio output level test", "[gpio][ignore]")
|
||||
io_conf.mode = GPIO_MODE_OUTPUT;
|
||||
gpio_config(&io_conf);
|
||||
TEST_ASSERT(gpio_config(&io_conf) == ESP_ERR_INVALID_ARG);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
//ESP32-S2 IO46 are just used for input
|
||||
io_conf.pin_bit_mask = ((uint64_t)1<<46);
|
||||
io_conf.mode = GPIO_MODE_OUTPUT;
|
||||
@ -463,7 +463,7 @@ TEST_CASE("GPIO io pull up/down function", "[gpio]")
|
||||
TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(GPIO_INPUT_IO), 0, "gpio_pullup_dis error, it can pull up");
|
||||
}
|
||||
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
|
||||
//No runners
|
||||
TEST_CASE("GPIO output and input mode test", "[gpio][test_env=UT_T1_GPIO]")
|
||||
{
|
||||
@ -537,7 +537,7 @@ TEST_CASE("GPIO repeate call service and isr has no memory leak test","[gpio][te
|
||||
}
|
||||
TEST_ASSERT_INT32_WITHIN(size, esp_get_free_heap_size(), 100);
|
||||
}
|
||||
#endif //DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#endif //DISABLED_FOR_TARGETS(ESP32S2)
|
||||
|
||||
#if !WAKE_UP_IGNORE
|
||||
//this function development is not completed yet, set it ignored
|
||||
|
||||
@ -242,7 +242,7 @@ TEST_CASE("I2C driver memory leaking check", "[i2c]")
|
||||
TEST_ASSERT_INT_WITHIN(100, size, esp_get_free_heap_size());
|
||||
}
|
||||
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
|
||||
|
||||
// print the reading buffer
|
||||
static void disp_buf(uint8_t *buf, int len)
|
||||
@ -372,7 +372,7 @@ static void slave_write_buffer_test(void)
|
||||
|
||||
TEST_CASE_MULTIPLE_DEVICES("I2C master read slave test", "[i2c][test_env=UT_T2_I2C][timeout=150]", master_read_slave_test, slave_write_buffer_test);
|
||||
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA, ESP32)
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32)
|
||||
static void i2c_master_write_read_test(void)
|
||||
{
|
||||
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH);
|
||||
@ -513,8 +513,8 @@ static void i2c_slave_repeat_read(void)
|
||||
TEST_CASE_MULTIPLE_DEVICES("I2C repeat write test", "[i2c][test_env=UT_T2_I2C][timeout=150]", i2c_master_repeat_write, i2c_slave_repeat_read);
|
||||
|
||||
|
||||
#endif //DISABLED_FOR_TARGET(ESP32S2BETA, ESP32)
|
||||
#endif //DISABLED_FOR_TARGET(ESP32S2BETA)
|
||||
#endif //DISABLED_FOR_TARGET(ESP32S2, ESP32)
|
||||
#endif //DISABLED_FOR_TARGET(ESP32S2)
|
||||
|
||||
static volatile bool exit_flag;
|
||||
static bool test_read_func;
|
||||
|
||||
@ -21,7 +21,7 @@
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#define MASTER_WS_IO 25
|
||||
#define DATA_OUT_IO 22
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#define MASTER_WS_IO 28
|
||||
#define DATA_OUT_IO 20
|
||||
#endif
|
||||
@ -76,8 +76,8 @@ TEST_CASE("I2S basic driver install, uninstall, set pin test", "[i2s]")
|
||||
TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
|
||||
}
|
||||
|
||||
#if !DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
/* ESP32S2BETA has only single I2S port and hence following test cases are not applicable */
|
||||
#if !DISABLED_FOR_TARGETS(ESP32S2)
|
||||
/* ESP32S2 has only single I2S port and hence following test cases are not applicable */
|
||||
|
||||
TEST_CASE("I2S write and read test(master tx and slave rx)", "[i2s][test_env=UT_T1_I2S]")
|
||||
{
|
||||
|
||||
@ -138,7 +138,7 @@ TEST_CASE("LEDC error log channel and timer config", "[ledc][test_env=UT_T1_LEDC
|
||||
{
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32
|
||||
const ledc_mode_t test_speed_mode = LEDC_HIGH_SPEED_MODE;
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2
|
||||
const ledc_mode_t test_speed_mode = LEDC_LOW_SPEED_MODE;
|
||||
#endif
|
||||
//channel configuration test
|
||||
@ -236,7 +236,7 @@ TEST_CASE("LEDC normal channel and timer config", "[ledc][test_env=UT_T1_LEDC]")
|
||||
// use all kinds of speed mode, channel, timer combination to test all of possible configuration
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32
|
||||
ledc_mode_t speed_mode[LEDC_SPEED_MODE_MAX] = {LEDC_HIGH_SPEED_MODE, LEDC_LOW_SPEED_MODE};
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2
|
||||
ledc_mode_t speed_mode[LEDC_SPEED_MODE_MAX] = {LEDC_LOW_SPEED_MODE};
|
||||
#endif
|
||||
ledc_channel_t channel_type[8] = {LEDC_CHANNEL_0, LEDC_CHANNEL_1, LEDC_CHANNEL_2, LEDC_CHANNEL_3, LEDC_CHANNEL_4, LEDC_CHANNEL_5, LEDC_CHANNEL_6, LEDC_CHANNEL_7};
|
||||
@ -262,7 +262,7 @@ TEST_CASE("LEDC normal channel and timer config", "[ledc][test_env=UT_T1_LEDC]")
|
||||
// set it ignore: need to debug
|
||||
TEST_CASE("LEDC set and get frequency", "[ledc][test_env=UT_T1_LEDC][timeout=60][ignore]")
|
||||
{
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
|
||||
timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_0, LEDC_HIGH_SPEED_MODE);
|
||||
timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_1, LEDC_HIGH_SPEED_MODE);
|
||||
timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_2, LEDC_HIGH_SPEED_MODE);
|
||||
@ -281,7 +281,7 @@ TEST_CASE("LEDC set and get dut(with logic analyzer)", "[ledc][ignore]")
|
||||
ledc_timer_t timer_list[4] = {LEDC_TIMER_0, LEDC_TIMER_1, LEDC_TIMER_2, LEDC_TIMER_3};
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32
|
||||
ledc_mode_t speed_mode_list[LEDC_SPEED_MODE_MAX] = {LEDC_HIGH_SPEED_MODE, LEDC_LOW_SPEED_MODE};
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2
|
||||
ledc_mode_t speed_mode_list[LEDC_SPEED_MODE_MAX] = {LEDC_LOW_SPEED_MODE};
|
||||
#endif
|
||||
for(int i=0; i<LEDC_TIMER_MAX-1; i++) {
|
||||
@ -295,7 +295,7 @@ TEST_CASE("LEDC timer set", "[ledc][test_env=UT_T1_LEDC]")
|
||||
{
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32
|
||||
const ledc_mode_t test_speed_mode = LEDC_HIGH_SPEED_MODE;
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2
|
||||
const ledc_mode_t test_speed_mode = LEDC_LOW_SPEED_MODE;
|
||||
#endif
|
||||
ledc_channel_config_t ledc_ch_config = {
|
||||
@ -351,7 +351,7 @@ TEST_CASE("LEDC timer pause and resume", "[ledc][test_env=UT_T1_LEDC]")
|
||||
{
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32
|
||||
const ledc_mode_t test_speed_mode = LEDC_HIGH_SPEED_MODE;
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2
|
||||
const ledc_mode_t test_speed_mode = LEDC_LOW_SPEED_MODE;
|
||||
#endif
|
||||
int16_t count;
|
||||
@ -408,7 +408,7 @@ TEST_CASE("LEDC fade with time(logic analyzer)", "[ledc][test_env=UT_T1_LEDC]")
|
||||
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32
|
||||
const ledc_mode_t test_speed_mode = LEDC_HIGH_SPEED_MODE;
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2
|
||||
const ledc_mode_t test_speed_mode = LEDC_LOW_SPEED_MODE;
|
||||
#endif
|
||||
ledc_channel_config_t ledc_ch_config = {
|
||||
@ -456,7 +456,7 @@ TEST_CASE("LEDC fade with step(logic analyzer)", "[ledc][test_env=UT_T1_LEDC]")
|
||||
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32
|
||||
const ledc_mode_t test_speed_mode = LEDC_HIGH_SPEED_MODE;
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2
|
||||
const ledc_mode_t test_speed_mode = LEDC_LOW_SPEED_MODE;
|
||||
#endif
|
||||
ledc_channel_config_t ledc_ch_config = {
|
||||
@ -504,7 +504,7 @@ TEST_CASE("LEDC memory test", "[ledc][test_env=UT_T1_LEDC]")
|
||||
{
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32
|
||||
const ledc_mode_t test_speed_mode = LEDC_HIGH_SPEED_MODE;
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2
|
||||
const ledc_mode_t test_speed_mode = LEDC_LOW_SPEED_MODE;
|
||||
#endif
|
||||
ledc_channel_config_t ledc_ch_config = {
|
||||
|
||||
@ -23,7 +23,7 @@
|
||||
#include "soc/gpio_periph.h"
|
||||
#include "unity.h"
|
||||
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
|
||||
|
||||
#define PULSE_IO 18
|
||||
#define PCNT_INPUT_IO 4
|
||||
|
||||
@ -18,7 +18,7 @@
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rmt_periph.h"
|
||||
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
|
||||
//No runners
|
||||
static const char *TAG = "RMT.test";
|
||||
|
||||
@ -779,4 +779,4 @@ TEST_CASE("RMT loop_en test", "[rmt][test_env=UT_T1_RMT][ignore]")
|
||||
TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
|
||||
}
|
||||
|
||||
#endif //DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#endif //DISABLED_FOR_TARGETS(ESP32S2)
|
||||
@ -29,7 +29,7 @@
|
||||
// Wait timeout for uart driver
|
||||
#define PACKET_READ_TICS (1000 / portTICK_RATE_MS)
|
||||
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
|
||||
//No runners
|
||||
|
||||
// The table for fast CRC16 calculation
|
||||
|
||||
@ -947,7 +947,7 @@ TEST_CASE("SPI master variable dummy test", "[spi]")
|
||||
#define RECORD_TIME_END(p_time) do{__t2 = xthal_get_ccount(); *p_time = (__t2-__t1);}while(0)
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32
|
||||
#define GET_US_BY_CCOUNT(t) ((double)t/CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#define GET_US_BY_CCOUNT(t) ((double)t/CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ)
|
||||
#endif
|
||||
|
||||
|
||||
@ -209,10 +209,10 @@ static void local_test_loop(const void* arg1, void* arg2)
|
||||
}
|
||||
|
||||
/************ Timing Test ***********************************************/
|
||||
//TODO: esp32s2beta has better timing performance
|
||||
//TODO: esp32s2 has better timing performance
|
||||
static spitest_param_set_t timing_pgroup[] = {
|
||||
//signals are not fed to peripherals through iomux if the functions are not selected to iomux
|
||||
#if !DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#if !DISABLED_FOR_TARGETS(ESP32S2)
|
||||
{ .pset_name = "FULL_DUP, MASTER IOMUX",
|
||||
.freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
|
||||
.master_limit = SPI_MASTER_FREQ_13M,
|
||||
@ -239,7 +239,7 @@ static spitest_param_set_t timing_pgroup[] = {
|
||||
.slave_tv_ns = TV_INT_CONNECT_GPIO,
|
||||
},
|
||||
//signals are not fed to peripherals through iomux if the functions are not selected to iomux
|
||||
#if !DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#if !DISABLED_FOR_TARGETS(ESP32S2)
|
||||
{ .pset_name = "MISO_DUP, MASTER IOMUX",
|
||||
.freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
|
||||
.master_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
|
||||
@ -266,7 +266,7 @@ static spitest_param_set_t timing_pgroup[] = {
|
||||
.slave_tv_ns = TV_INT_CONNECT_GPIO,
|
||||
},
|
||||
//signals are not fed to peripherals through iomux if the functions are not selected to iomux
|
||||
#if !DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#if !DISABLED_FOR_TARGETS(ESP32S2)
|
||||
{ .pset_name = "MOSI_DUP, MASTER IOMUX",
|
||||
.freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
|
||||
//.freq_limit = ESP_SPI_SLAVE_MAX_READ_FREQ, //ESP_SPI_SLAVE_MAX_FREQ_SYNC,
|
||||
@ -496,7 +496,7 @@ static spitest_param_set_t mode_pgroup[] = {
|
||||
};
|
||||
TEST_SPI_LOCAL(MODE, mode_pgroup)
|
||||
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
|
||||
//These tests are ESP32 only due to lack of runners
|
||||
/********************************************************************************
|
||||
* Test By Master & Slave (2 boards)
|
||||
|
||||
@ -10,8 +10,8 @@
|
||||
#include "sdkconfig.h"
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#include "esp32s2beta/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/rom/ets_sys.h"
|
||||
#endif
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
@ -107,7 +107,7 @@ TEST_CASE("local test sio", "[spi]")
|
||||
master_free_device_bus(spi);
|
||||
}
|
||||
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
|
||||
//These tests are ESP32 only due to lack of runners
|
||||
/********************************************************************************
|
||||
* Test SIO Master & Slave
|
||||
|
||||
@ -30,8 +30,8 @@
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#include "esp32s2beta/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/rom/ets_sys.h"
|
||||
#endif
|
||||
#include "hal/touch_sensor_types.h"
|
||||
#include "hal/touch_sensor_hal.h"
|
||||
@ -47,7 +47,7 @@ static const char *TOUCH_TAG = "TOUCH_SENSOR";
|
||||
#define TOUCH_CHANNEL_CHECK(channel) do { \
|
||||
TOUCH_CHECK(channel < SOC_TOUCH_SENSOR_NUM && channel >= 0, "Touch channel error", ESP_ERR_INVALID_ARG); \
|
||||
} while (0);
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2
|
||||
#define TOUCH_CHANNEL_CHECK(channel) do { \
|
||||
TOUCH_CHECK(channel < SOC_TOUCH_SENSOR_NUM && channel >= 0, "Touch channel error", ESP_ERR_INVALID_ARG); \
|
||||
TOUCH_CHECK(channel != SOC_TOUCH_DENOISE_CHANNEL, "TOUCH0 is internal denoise channel", ESP_ERR_INVALID_ARG); \
|
||||
@ -199,7 +199,7 @@ esp_err_t touch_pad_set_thresh(touch_pad_t touch_num, uint16_t threshold)
|
||||
TOUCH_EXIT_CRITICAL();
|
||||
return ESP_OK;
|
||||
}
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2
|
||||
esp_err_t touch_pad_set_thresh(touch_pad_t touch_num, uint32_t threshold)
|
||||
{
|
||||
TOUCH_CHANNEL_CHECK(touch_num);
|
||||
@ -219,7 +219,7 @@ esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint16_t *threshold)
|
||||
touch_hal_get_threshold(touch_num, threshold);
|
||||
return ESP_OK;
|
||||
}
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2
|
||||
esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint32_t *threshold)
|
||||
{
|
||||
TOUCH_CHANNEL_CHECK(touch_num);
|
||||
|
||||
@ -32,8 +32,8 @@
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/clk.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#include "esp32s2beta/clk.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/clk.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_UART_ISR_IN_IRAM
|
||||
@ -481,7 +481,7 @@ esp_err_t uart_enable_pattern_det_baud_intr(uart_port_t uart_num, char pattern_c
|
||||
at_cmd.gap_tout = chr_tout * uart_div;
|
||||
at_cmd.pre_idle = pre_idle * uart_div;
|
||||
at_cmd.post_idle = post_idle * uart_div;
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
at_cmd.gap_tout = chr_tout;
|
||||
at_cmd.pre_idle = pre_idle;
|
||||
at_cmd.post_idle = post_idle;
|
||||
|
||||
@ -42,6 +42,6 @@ menu "eFuse Bit Manager"
|
||||
default 256 if EFUSE_CODE_SCHEME_COMPAT_NONE
|
||||
default 192 if EFUSE_CODE_SCHEME_COMPAT_3_4
|
||||
default 128 if EFUSE_CODE_SCHEME_COMPAT_REPEAT
|
||||
default 256 if IDF_TARGET_ESP32S2BETA
|
||||
default 256 if IDF_TARGET_ESP32S2
|
||||
|
||||
endmenu
|
||||
|
||||
@ -354,7 +354,7 @@ class FuseDefinition(object):
|
||||
if strval not in ["EFUSE_BLK0", "EFUSE_BLK1", "EFUSE_BLK2", "EFUSE_BLK3"]:
|
||||
raise InputError("Field 'efuse_block' should be one of EFUSE_BLK0..EFUSE_BLK3")
|
||||
|
||||
if idf_target == "esp32s2beta":
|
||||
if idf_target == "esp32s2":
|
||||
if strval not in ["EFUSE_BLK0", "EFUSE_BLK1", "EFUSE_BLK2", "EFUSE_BLK3", "EFUSE_BLK4",
|
||||
"EFUSE_BLK5", "EFUSE_BLK6", "EFUSE_BLK7", "EFUSE_BLK8", "EFUSE_BLK9",
|
||||
"EFUSE_BLK10"]:
|
||||
@ -463,7 +463,7 @@ def main():
|
||||
global idf_target
|
||||
|
||||
parser = argparse.ArgumentParser(description='ESP32 eFuse Manager')
|
||||
parser.add_argument('--idf_target', '-t', help='Target chip type', choices=['esp32','esp32s2beta'], default='esp32')
|
||||
parser.add_argument('--idf_target', '-t', help='Target chip type', choices=['esp32','esp32s2'], default='esp32')
|
||||
parser.add_argument('--quiet', '-q', help="Don't print non-critical status messages to stderr", action='store_true')
|
||||
parser.add_argument('--debug', help='Create header file with debug info', default=False, action="store_false")
|
||||
parser.add_argument('--info', help='Print info about range of used bits', default=False, action="store_true")
|
||||
|
||||
|
Can't render this file because it contains an unexpected character in line 7 and column 87.
|
@ -19,7 +19,7 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Type of eFuse blocks ESP32S2BETA
|
||||
* @brief Type of eFuse blocks ESP32S2
|
||||
*/
|
||||
typedef enum {
|
||||
EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */
|
||||
@ -24,8 +24,8 @@ extern "C" {
|
||||
#include "sdkconfig.h"
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/esp_efuse.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#include "esp32s2beta/esp_efuse.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/esp_efuse.h"
|
||||
#endif
|
||||
|
||||
#define ESP_ERR_EFUSE 0x1600 /*!< Base error code for efuse api. */
|
||||
|
||||
@ -25,8 +25,8 @@ extern "C" {
|
||||
#include "sdkconfig.h"
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/esp_efuse_utility.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#include "esp32s2beta/esp_efuse_utility.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/esp_efuse_utility.h"
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
||||
@ -17,7 +17,7 @@
|
||||
#include "esp_efuse_table.h"
|
||||
#include "stdlib.h"
|
||||
#include "esp_types.h"
|
||||
#include "esp32s2beta/rom/efuse.h"
|
||||
#include "esp32s2/rom/efuse.h"
|
||||
#include "assert.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp_log.h"
|
||||
@ -33,7 +33,7 @@ const static char *TAG = "efuse";
|
||||
uint8_t esp_efuse_get_chip_ver(void)
|
||||
{
|
||||
uint32_t chip_ver = 0;
|
||||
// TODO: ESP32S2BETA does not have this field
|
||||
// TODO: ESP32S2 does not have this field
|
||||
return chip_ver;
|
||||
}
|
||||
|
||||
@ -41,7 +41,7 @@ uint8_t esp_efuse_get_chip_ver(void)
|
||||
uint32_t esp_efuse_get_pkg_ver(void)
|
||||
{
|
||||
uint32_t pkg_ver = 0;
|
||||
// TODO: ESP32S2BETA does not have this field
|
||||
// TODO: ESP32S2 does not have this field
|
||||
return pkg_ver;
|
||||
}
|
||||
|
||||
@ -14,12 +14,12 @@
|
||||
|
||||
#include "esp_efuse_utility.h"
|
||||
#include "soc/efuse_periph.h"
|
||||
#include "esp32s2beta/clk.h"
|
||||
#include "esp32s2/clk.h"
|
||||
#include "esp_log.h"
|
||||
#include "assert.h"
|
||||
#include "sdkconfig.h"
|
||||
#include <sys/param.h>
|
||||
#include "esp32s2beta/rom/efuse.h"
|
||||
#include "esp32s2/rom/efuse.h"
|
||||
|
||||
static const char *TAG = "efuse";
|
||||
|
||||
@ -28,8 +28,8 @@
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/rom/efuse.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#include "esp32s2beta/rom/efuse.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/rom/efuse.h"
|
||||
#endif
|
||||
|
||||
// Permanently update values written to the efuse write registers
|
||||
|
||||
@ -34,7 +34,7 @@ static void test_read_blob(void)
|
||||
TEST_ASSERT_EQUAL_INT(sizeof(mac) * 8, esp_efuse_get_field_size(ESP_EFUSE_MAC_FACTORY));
|
||||
ESP_LOGI(TAG, "MAC: %02x:%02x:%02x:%02x:%02x:%02x", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
|
||||
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
|
||||
ESP_LOGI(TAG, "2. Check CRC by MAC");
|
||||
uint8_t crc;
|
||||
TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_MAC_FACTORY_CRC, &crc, 8));
|
||||
@ -510,7 +510,7 @@ TEST_CASE("Test esp_efuse_read_block esp_efuse_write_block functions", "[efuse]"
|
||||
printf("EFUSE_CODING_SCHEME_REPEAT\n");
|
||||
count_useful_reg = 4;
|
||||
}
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
if (coding_scheme == EFUSE_CODING_SCHEME_RS) {
|
||||
printf("EFUSE_CODING_SCHEME_RS\n");
|
||||
count_useful_reg = 8;
|
||||
@ -573,7 +573,7 @@ TEST_CASE("Test Bits are not empty. Write operation is forbidden", "[efuse]")
|
||||
printf("EFUSE_CODING_SCHEME_REPEAT\n");
|
||||
count_useful_reg = 4;
|
||||
}
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
if (coding_scheme == EFUSE_CODING_SCHEME_RS) {
|
||||
printf("EFUSE_CODING_SCHEME_RS\n");
|
||||
if (num_block == EFUSE_BLK1) {
|
||||
@ -741,7 +741,7 @@ TEST_CASE("Test a write/read protection", "[efuse]")
|
||||
test_rp(EFUSE_BLK1, ESP_EFUSE_RD_DIS_BLK1, true);
|
||||
test_rp(EFUSE_BLK2, ESP_EFUSE_RD_DIS_BLK2, false);
|
||||
test_rp(EFUSE_BLK3, ESP_EFUSE_RD_DIS_BLK3, false);
|
||||
#elif defined(CONFIG_IDF_TARGET_ESP32S2BETA)
|
||||
#elif defined(CONFIG_IDF_TARGET_ESP32S2)
|
||||
test_wp(EFUSE_BLK2, ESP_EFUSE_WR_DIS_SYS_DATA_PART1);
|
||||
test_wp(EFUSE_BLK3, ESP_EFUSE_WR_DIS_USER_DATA);
|
||||
|
||||
|
||||
@ -11,7 +11,7 @@ typedef struct {
|
||||
uint32_t encoded[8];
|
||||
} coding_scheme_test_t;
|
||||
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
|
||||
/* Randomly generated byte strings, encoded and written to ESP32
|
||||
using espefuse algorithm, then verified to have no encoding errors
|
||||
and correct readback.
|
||||
|
||||
@ -6,8 +6,8 @@
|
||||
#include <stdio.h>
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#include "esp32s2beta/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/rom/ets_sys.h"
|
||||
#endif
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
|
||||
@ -1,13 +1,13 @@
|
||||
idf_build_get_property(target IDF_TARGET)
|
||||
idf_build_get_property(sdkconfig_header SDKCONFIG_HEADER)
|
||||
if(NOT "${target}" STREQUAL "esp32s2beta")
|
||||
if(NOT "${target}" STREQUAL "esp32s2")
|
||||
return()
|
||||
endif()
|
||||
|
||||
if(BOOTLOADER_BUILD)
|
||||
# For bootloader, all we need from esp32s2beta is headers
|
||||
# For bootloader, all we need from esp32s2 is headers
|
||||
idf_component_register(INCLUDE_DIRS include)
|
||||
target_linker_script(${COMPONENT_LIB} INTERFACE "ld/esp32s2beta.peripherals.ld")
|
||||
target_linker_script(${COMPONENT_LIB} INTERFACE "ld/esp32s2.peripherals.ld")
|
||||
else()
|
||||
# Regular app build
|
||||
|
||||
@ -18,18 +18,18 @@ else()
|
||||
"crosscore_int.c"
|
||||
"dport_access.c"
|
||||
"dport_panic_highint_hdl.S"
|
||||
"esp_timer_esp32s2beta.c"
|
||||
"esp_timer_esp32s2.c"
|
||||
"hw_random.c"
|
||||
"int_wdt.c"
|
||||
"intr_alloc.c"
|
||||
"panic.c"
|
||||
"pm_esp32s2beta.c"
|
||||
"pm_esp32s2.c"
|
||||
"pm_trace.c"
|
||||
"reset_reason.c"
|
||||
"sleep_modes.c"
|
||||
"spiram.c"
|
||||
"spiram_psram.c"
|
||||
"system_api_esp32s2beta.c"
|
||||
"system_api_esp32s2.c"
|
||||
"task_wdt.c")
|
||||
set(include_dirs "include")
|
||||
|
||||
@ -41,25 +41,25 @@ else()
|
||||
app_trace app_update bootloader_support log mbedtls nvs_flash
|
||||
pthread spi_flash vfs espcoredump esp_common)
|
||||
|
||||
set(fragments linker.lf ld/esp32s2beta_fragments.lf)
|
||||
set(fragments linker.lf ld/esp32s2_fragments.lf)
|
||||
|
||||
idf_component_register(SRCS "${srcs}"
|
||||
INCLUDE_DIRS "${include_dirs}"
|
||||
LDFRAGMENTS "${fragments}"
|
||||
REQUIRES "${requires}"
|
||||
PRIV_REQUIRES "${priv_requires}"
|
||||
REQUIRED_IDF_TARGETS esp32s2beta)
|
||||
REQUIRED_IDF_TARGETS esp32s2)
|
||||
|
||||
target_linker_script(${COMPONENT_LIB} INTERFACE "${CMAKE_CURRENT_BINARY_DIR}/esp32s2beta_out.ld")
|
||||
target_linker_script(${COMPONENT_LIB} INTERFACE "${CMAKE_CURRENT_BINARY_DIR}/esp32s2_out.ld")
|
||||
|
||||
# Rely on user code to define app_main
|
||||
target_link_libraries(${COMPONENT_LIB} INTERFACE "-u app_main")
|
||||
|
||||
# Process the template file through the linker script generation mechanism, and use the output for linking the
|
||||
# final binary
|
||||
target_linker_script(${COMPONENT_LIB} INTERFACE "${CMAKE_CURRENT_LIST_DIR}/ld/esp32s2beta.project.ld.in" PROCESS "${CMAKE_CURRENT_BINARY_DIR}/ld/esp32s2beta.project.ld")
|
||||
target_linker_script(${COMPONENT_LIB} INTERFACE "${CMAKE_CURRENT_LIST_DIR}/ld/esp32s2.project.ld.in" PROCESS "${CMAKE_CURRENT_BINARY_DIR}/ld/esp32s2.project.ld")
|
||||
|
||||
target_linker_script(${COMPONENT_LIB} INTERFACE "ld/esp32s2beta.peripherals.ld")
|
||||
target_linker_script(${COMPONENT_LIB} INTERFACE "ld/esp32s2.peripherals.ld")
|
||||
target_link_libraries(${COMPONENT_LIB} PUBLIC gcc)
|
||||
target_link_libraries(${COMPONENT_LIB} INTERFACE "-u call_user_start_cpu0")
|
||||
|
||||
@ -69,17 +69,17 @@ else()
|
||||
target_link_libraries(${COMPONENT_LIB} INTERFACE "-u ld_include_panic_highint_hdl")
|
||||
|
||||
idf_build_get_property(config_dir CONFIG_DIR)
|
||||
# Preprocess esp32s2beta.ld linker script to include configuration, becomes esp32s2beta_out.ld
|
||||
# Preprocess esp32s2.ld linker script to include configuration, becomes esp32s2_out.ld
|
||||
set(LD_DIR ${CMAKE_CURRENT_SOURCE_DIR}/ld)
|
||||
add_custom_command(
|
||||
OUTPUT esp32s2beta_out.ld
|
||||
COMMAND "${CMAKE_C_COMPILER}" -C -P -x c -E -o esp32s2beta_out.ld -I ${config_dir} ${LD_DIR}/esp32s2beta.ld
|
||||
MAIN_DEPENDENCY ${LD_DIR}/esp32s2beta.ld ${sdkconfig_header}
|
||||
OUTPUT esp32s2_out.ld
|
||||
COMMAND "${CMAKE_C_COMPILER}" -C -P -x c -E -o esp32s2_out.ld -I ${config_dir} ${LD_DIR}/esp32s2.ld
|
||||
MAIN_DEPENDENCY ${LD_DIR}/esp32s2.ld ${sdkconfig_header}
|
||||
COMMENT "Generating linker script..."
|
||||
VERBATIM)
|
||||
|
||||
add_custom_target(esp32s2beta_linker_script DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/esp32s2beta_out.ld)
|
||||
add_dependencies(${COMPONENT_LIB} esp32s2beta_linker_script)
|
||||
add_custom_target(esp32s2_linker_script DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/esp32s2_out.ld)
|
||||
add_dependencies(${COMPONENT_LIB} esp32s2_linker_script)
|
||||
|
||||
# disable stack protection in files which are involved in initialization of that feature
|
||||
set_source_files_properties(
|
||||
@ -2,14 +2,14 @@ menu "ESP32S2-specific"
|
||||
# TODO: this component simply shouldn't be included
|
||||
# in the build at the CMake level, but this is currently
|
||||
# not working so we just hide all items here
|
||||
visible if IDF_TARGET_ESP32S2BETA
|
||||
visible if IDF_TARGET_ESP32S2
|
||||
|
||||
choice ESP32S2_BETA_CHIP_VERSION
|
||||
choice ESP32S2_CHIP_VERSION
|
||||
# TODO: remove once final S2 chip is supported
|
||||
prompt "ESP32-S2 Beta chip version"
|
||||
default ESP32S2_BETA_VERSION_A
|
||||
prompt "ESP32-S2 chip version"
|
||||
default ESP32S2_VERSION_A
|
||||
help
|
||||
There are three versions of ESP32-S2 beta chip with different Wi-Fi PHY: A, B and Marlin3.
|
||||
There are three versions of ESP32-S2 chip with different Wi-Fi PHY: A, B and Marlin3.
|
||||
|
||||
This setting must match the chip for Wi-Fi to work correctly. You can determine
|
||||
the chip version by reading the markings on top of the chip. It will be one of the
|
||||
@ -17,11 +17,11 @@ menu "ESP32S2-specific"
|
||||
|
||||
The Wi-Fi performance of Marlin3 is the best among the three versions of chip.
|
||||
|
||||
config ESP32S2_BETA_VERSION_A
|
||||
config ESP32S2_VERSION_A
|
||||
bool "Chip7.2.2-A"
|
||||
config ESP32S2_BETA_VERSION_B
|
||||
config ESP32S2_VERSION_B
|
||||
bool "Chip7.2.2-B"
|
||||
config ESP32S2_BETA_VERSION_MARLIN3
|
||||
config ESP32S2_VERSION_MARLIN3
|
||||
bool "Marlin3-B2 or Marlin3-B3"
|
||||
endchoice
|
||||
|
||||
@ -504,7 +504,7 @@ menu "Power Management"
|
||||
# TODO: this component simply shouldn't be included
|
||||
# in the build at the CMake level, but this is currently
|
||||
# not working so we just hide all items here
|
||||
visible if IDF_TARGET_ESP32S2BETA
|
||||
visible if IDF_TARGET_ESP32S2
|
||||
|
||||
config PM_ENABLE
|
||||
bool "Support for power management"
|
||||
1
components/esp32s2/Makefile.projbuild
Normal file
1
components/esp32s2/Makefile.projbuild
Normal file
@ -0,0 +1 @@
|
||||
# nothing here, esp32s2 is not suppoted in Make build system
|
||||
@ -20,7 +20,7 @@
|
||||
#include "soc/soc.h"
|
||||
#include "soc/cpu.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "esp32s2beta/rom/ets_sys.h"
|
||||
#include "esp32s2/rom/ets_sys.h"
|
||||
#include "esp_private/system_internal.h"
|
||||
#include "driver/rtc_cntl.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
@ -48,7 +48,7 @@ static void rtc_brownout_isr_handler(void *arg)
|
||||
|
||||
void esp_brownout_init(void)
|
||||
{
|
||||
// TODO: implement brownout threshold configuration for esp32s2beta - IDF-751
|
||||
// TODO: implement brownout threshold configuration for esp32s2 - IDF-751
|
||||
|
||||
ESP_ERROR_CHECK( rtc_isr_register(rtc_brownout_isr_handler, NULL, RTC_CNTL_BROWN_OUT_INT_ENA_M) );
|
||||
|
||||
@ -31,7 +31,7 @@
|
||||
#include "soc/dport_reg.h"
|
||||
#include "soc/periph_defs.h"
|
||||
#include "sdkconfig.h"
|
||||
#include "esp32s2beta/dport_access.h"
|
||||
#include "esp32s2/dport_access.h"
|
||||
|
||||
void esp_cache_err_int_init(void)
|
||||
{
|
||||
@ -19,11 +19,11 @@
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp32s2beta/clk.h"
|
||||
#include "esp32s2/clk.h"
|
||||
#include "esp_clk_internal.h"
|
||||
#include "esp32s2beta/rom/ets_sys.h"
|
||||
#include "esp32s2beta/rom/uart.h"
|
||||
#include "esp32s2beta/rom/rtc.h"
|
||||
#include "esp32s2/rom/ets_sys.h"
|
||||
#include "esp32s2/rom/uart.h"
|
||||
#include "esp32s2/rom/rtc.h"
|
||||
#include "soc/system_reg.h"
|
||||
#include "soc/dport_access.h"
|
||||
#include "soc/soc.h"
|
||||
@ -18,14 +18,14 @@
|
||||
#include "esp_attr.h"
|
||||
#include "esp_err.h"
|
||||
|
||||
#include "esp32s2beta/rom/ets_sys.h"
|
||||
#include "esp32s2beta/rom/uart.h"
|
||||
#include "esp32s2beta/rom/rtc.h"
|
||||
#include "esp32s2beta/rom/cache.h"
|
||||
#include "esp32s2beta/dport_access.h"
|
||||
#include "esp32s2beta/brownout.h"
|
||||
#include "esp32s2beta/cache_err_int.h"
|
||||
#include "esp32s2beta/spiram.h"
|
||||
#include "esp32s2/rom/ets_sys.h"
|
||||
#include "esp32s2/rom/uart.h"
|
||||
#include "esp32s2/rom/rtc.h"
|
||||
#include "esp32s2/rom/cache.h"
|
||||
#include "esp32s2/dport_access.h"
|
||||
#include "esp32s2/brownout.h"
|
||||
#include "esp32s2/cache_err_int.h"
|
||||
#include "esp32s2/spiram.h"
|
||||
|
||||
#include "soc/cpu.h"
|
||||
#include "soc/rtc.h"
|
||||
@ -18,8 +18,8 @@
|
||||
#include "esp_err.h"
|
||||
#include "esp_intr_alloc.h"
|
||||
|
||||
#include "esp32s2beta/rom/ets_sys.h"
|
||||
#include "esp32s2beta/rom/uart.h"
|
||||
#include "esp32s2/rom/ets_sys.h"
|
||||
#include "esp32s2/rom/uart.h"
|
||||
|
||||
#include "soc/cpu.h"
|
||||
#include "soc/dport_reg.h"
|
||||
@ -19,7 +19,7 @@
|
||||
#include "esp_attr.h"
|
||||
#include "esp_intr_alloc.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp32s2beta/clk.h"
|
||||
#include "esp32s2/clk.h"
|
||||
#include "esp_private/esp_timer_impl.h"
|
||||
#include "soc/frc_timer_reg.h"
|
||||
#include "soc/rtc.h"
|
||||
@ -18,7 +18,7 @@
|
||||
#include <string.h>
|
||||
#include <sys/param.h>
|
||||
#include "esp_attr.h"
|
||||
#include "esp32s2beta/clk.h"
|
||||
#include "esp32s2/clk.h"
|
||||
#include "soc/wdev_reg.h"
|
||||
#include "freertos/FreeRTOSConfig.h"
|
||||
#include "xtensa/core-macros.h"
|
||||
@ -15,7 +15,7 @@
|
||||
#ifndef __ESP_INTR_H__
|
||||
#define __ESP_INTR_H__
|
||||
|
||||
#include "esp32s2beta/rom/ets_sys.h"
|
||||
#include "esp32s2/rom/ets_sys.h"
|
||||
#include "freertos/xtensa_api.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user