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spi_flash: update def header of MXIC

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This commit is contained in:
Michael (XIAO Xufeng) 2022-03-21 14:39:45 +08:00
parent cabdd25e7f
commit e2ecdfc0a7
3 changed files with 34 additions and 27 deletions
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49
components/spi_flash/esp32s3/opi_flash_cmd_format_mxic.h
View File

@ -1,16 +1,20 @@
/*
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#if CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP
#if CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR
#define OPI_CMD_FORMAT_MXIC() { \
#include <stdint.h>
#include "spi_flash_defs.h"
//MXIC OPI mode needs two bytes of command - 2nd byte is the inversion of the command (1st) byte. S3 HW send LSB first
#define MXIC_CMD16(cmd8) ( (uint8_t)(cmd8) | ((uint8_t)(~(cmd8)) << 8) )
#define OPI_CMD_FORMAT_MXIC_STR() { \
.rdid = { \
.mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
.cmd_bit_len = 16, \
.cmd = 0x609f, \
.cmd = MXIC_CMD16(CMD_RDID), \
.addr = 0, \
.addr_bit_len = 4*8, \
.dummy_bit_len = 4, \
@ -21,7 +25,7 @@
.rdsr = { \
.mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
.cmd_bit_len = 16, \
.cmd = 0xfa05, \
.cmd = MXIC_CMD16(CMD_RDSR), \
.addr = 0, \
.addr_bit_len = 4*8, \
.dummy_bit_len = 4, \
@ -32,7 +36,7 @@
.wren = { \
.mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
.cmd_bit_len = 16, \
.cmd = 0xf906, \
.cmd = MXIC_CMD16(CMD_WREN), \
.addr = 0, \
.addr_bit_len = 0, \
.dummy_bit_len = 0, \
@ -43,7 +47,7 @@
.se = { \
.mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
.cmd_bit_len = 16, \
.cmd = 0xde21, \
.cmd = MXIC_CMD16(CMD_SECTOR_ERASE_4B), \
.addr = 0, \
.addr_bit_len = 32, \
.dummy_bit_len = 0, \
@ -54,7 +58,7 @@
.be64k = { \
.mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
.cmd_bit_len = 16, \
.cmd = 0x23dc, \
.cmd = MXIC_CMD16(CMD_LARGE_BLOCK_ERASE_4B), \
.addr = 0, \
.addr_bit_len = 32, \
.dummy_bit_len = 0, \
@ -65,7 +69,7 @@
.read = { \
.mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
.cmd_bit_len = 16, \
.cmd = 0x13ec, \
.cmd = MXIC_CMD16(CMD_8READ), \
.addr = 0, \
.addr_bit_len = 32, \
.dummy_bit_len = 20, \
@ -76,7 +80,7 @@
.pp = { \
.mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
.cmd_bit_len = 16, \
.cmd = 0xed12, \
.cmd = MXIC_CMD16(CMD_PROGRAM_PAGE_4B), \
.addr = 0, \
.addr_bit_len = 32, \
.dummy_bit_len = 0, \
@ -87,18 +91,17 @@
.cache_rd_cmd = { \
.addr_bit_len = 32, \
.dummy_bit_len = 20, \
.cmd = 0x13ec, \
.cmd = MXIC_CMD16(CMD_8READ), \
.cmd_bit_len = 16, \
.var_dummy_en = 1, \
} \
}
#elif CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR
#define OPI_CMD_FORMAT_MXIC() { \
#define OPI_CMD_FORMAT_MXIC_DTR() { \
.rdid = { \
.mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
.cmd_bit_len = 16, \
.cmd = 0x609f, \
.cmd = MXIC_CMD16(CMD_RDID), \
.addr = 0, \
.addr_bit_len = 4*8, \
.dummy_bit_len = 4*2, \
@ -109,7 +112,7 @@
.rdsr = { \
.mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
.cmd_bit_len = 16, \
.cmd = 0xfa05, \
.cmd = MXIC_CMD16(CMD_RDSR), \
.addr = 0, \
.addr_bit_len = 4*8, \
.dummy_bit_len = 4*2, \
@ -120,7 +123,7 @@
.wren = { \
.mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
.cmd_bit_len = 16, \
.cmd = 0xf906, \
.cmd = MXIC_CMD16(CMD_WREN), \
.addr = 0, \
.addr_bit_len = 0, \
.dummy_bit_len = 0, \
@ -131,7 +134,7 @@
.se = { \
.mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
.cmd_bit_len = 16, \
.cmd = 0xde21, \
.cmd = MXIC_CMD16(CMD_SECTOR_ERASE_4B), \
.addr = 0, \
.addr_bit_len = 32, \
.dummy_bit_len = 0, \
@ -142,7 +145,7 @@
.be64k = { \
.mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
.cmd_bit_len = 16, \
.cmd = 0x23dc, \
.cmd = MXIC_CMD16(CMD_LARGE_BLOCK_ERASE_4B), \
.addr = 0, \
.addr_bit_len = 32, \
.dummy_bit_len = 0, \
@ -153,7 +156,7 @@
.read = { \
.mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
.cmd_bit_len = 16, \
.cmd = 0x11ee, \
.cmd = MXIC_CMD16(CMD_8DTRD), \
.addr = 0, \
.addr_bit_len = 32, \
.dummy_bit_len = 20*2, \
@ -164,7 +167,7 @@
.pp = { \
.mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
.cmd_bit_len = 16, \
.cmd = 0xed12, \
.cmd = MXIC_CMD16(CMD_PROGRAM_PAGE_4B), \
.addr = 0, \
.addr_bit_len = 32, \
.dummy_bit_len = 0, \
@ -175,10 +178,8 @@
.cache_rd_cmd = { \
.addr_bit_len = 32, \
.dummy_bit_len = 20*2, \
.cmd = 0x11ee, \
.cmd = MXIC_CMD16(CMD_8DTRD), \
.cmd_bit_len = 16, \
.var_dummy_en = 1, \
} \
}
#endif // DTR / STR
#endif // #if CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP

6
components/spi_flash/esp32s3/spi_flash_oct_flash_init.c
View File

@ -189,7 +189,11 @@ static void s_set_pin_drive_capability(uint8_t drv)
static void s_flash_init_mxic(esp_rom_spiflash_read_mode_t mode)
{
static const esp_rom_opiflash_def_t opiflash_cmd_def_mxic = OPI_CMD_FORMAT_MXIC();
#if CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR
static const esp_rom_opiflash_def_t opiflash_cmd_def_mxic = OPI_CMD_FORMAT_MXIC_STR();
#elif CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR
static const esp_rom_opiflash_def_t opiflash_cmd_def_mxic = OPI_CMD_FORMAT_MXIC_DTR();
#endif
esp_rom_opiflash_legacy_driver_init(&opiflash_cmd_def_mxic);
esp_rom_spiflash_wait_idle(&g_rom_flashchip);

6
components/spi_flash/include/spi_flash/spi_flash_defs.h
View File

@ -19,8 +19,10 @@
#define CMD_WRDI 0x04
#define CMD_RDSR 0x05
#define CMD_RDSR2 0x35 /* Not all SPI flash uses this command */
#define CMD_RDSCUR 0x2B /* on specific(MXIC) board, read security register */
#define CMD_RDFR 0x48 /* on specific(ISSI) board, read function register */
#define CMD_RDSCUR 0x2B /* MXIC-specific, read security register */
#define CMD_8READ 0xEC /* MXIC-specific, 8 I/O read */
#define CMD_8DTRD 0xEE /* MXIC-specific, 8 I/O DTR read */
#define CMD_RDFR 0x48 /* ISSI-specific, read function register */
#define CMD_FASTRD_QIO 0xEB
#define CMD_FASTRD_QIO_4B 0xEC