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Merge branch 'refactor/rename_to_esp_clk_tree_prefix' into 'master'

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esp_clk_tree: Rename clk_tree_xxx to esp_clk_tree_xxx

See merge request espressif/esp-idf!23362
This commit is contained in:
Song Ruo Jing 2023-04-25 19:41:39 +08:00
commit e2a5c092f7
40 changed files with 215 additions and 215 deletions
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6
components/driver/analog_comparator/ana_cmpr.c
View File

@ -13,7 +13,7 @@
#define LOG_LOCAL_LEVEL ESP_LOG_DEBUG
#endif
#include "freertos/FreeRTOS.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_types.h"
#include "esp_attr.h"
#include "esp_check.h"
@ -116,8 +116,8 @@ esp_err_t ana_cmpr_new_unit(const ana_cmpr_config_t *config, ana_cmpr_handle_t *
#endif
/* Analog clock comes from IO MUX, but IO MUX clock might be shared with other submodules as well */
ESP_GOTO_ON_ERROR(clk_tree_src_get_freq_hz((soc_module_clk_t)config->clk_src,
CLK_TREE_SRC_FREQ_PRECISION_CACHED,
ESP_GOTO_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)config->clk_src,
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
&s_ana_cmpr[unit]->src_clk_freq_hz),
err, TAG, "get source clock frequency failed");
ESP_GOTO_ON_ERROR(io_mux_set_clock_source((soc_module_clk_t)(config->clk_src)), err, TAG,

10
components/driver/deprecated/adc_legacy.c
View File

@ -27,7 +27,7 @@
#include "hal/adc_hal_common.h"
#include "esp_private/periph_ctrl.h"
#include "driver/adc_types_legacy.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#if SOC_DAC_SUPPORTED
#include "hal/dac_types.h"
@ -281,7 +281,7 @@ esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
if (!clk_src_freq_hz) {
//should never fail
clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
esp_clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
}
#endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
@ -440,7 +440,7 @@ esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten)
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
if (!clk_src_freq_hz) {
//should never fail
clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
esp_clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
}
#endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
@ -753,7 +753,7 @@ esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
if (!clk_src_freq_hz) {
//should never fail
clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
esp_clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
}
#endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
@ -823,7 +823,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
if (!clk_src_freq_hz) {
//should never fail
clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
esp_clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
}
#endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED

8
components/driver/deprecated/mcpwm_legacy.c
View File

@ -19,7 +19,7 @@
#include "driver/mcpwm_types_legacy.h"
#include "driver/gpio.h"
#include "esp_private/periph_ctrl.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_private/esp_clk.h"
static const char *TAG = "mcpwm(legacy)";
@ -225,7 +225,7 @@ esp_err_t mcpwm_group_set_resolution(mcpwm_unit_t mcpwm_num, uint32_t resolution
{
mcpwm_hal_context_t *hal = &context[mcpwm_num].hal;
uint32_t clk_src_hz = 0;
clk_tree_src_get_freq_hz(MCPWM_TIMER_CLK_SRC_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz);
esp_clk_tree_src_get_freq_hz(MCPWM_TIMER_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz);
int pre_scale_temp = clk_src_hz / resolution;
ESP_RETURN_ON_FALSE(pre_scale_temp >= 1, ESP_ERR_INVALID_ARG, TAG, "invalid resolution");
@ -415,7 +415,7 @@ esp_err_t mcpwm_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpw
mcpwm_hal_init(hal, &config);
uint32_t clk_src_hz = 0;
clk_tree_src_get_freq_hz(MCPWM_TIMER_CLK_SRC_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz);
esp_clk_tree_src_get_freq_hz(MCPWM_TIMER_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz);
uint32_t group_resolution = mcpwm_group_get_resolution(mcpwm_num);
uint32_t timer_resolution = mcpwm_timer_get_resolution(mcpwm_num, timer_num);
uint32_t group_pre_scale = clk_src_hz / group_resolution;
@ -812,7 +812,7 @@ esp_err_t mcpwm_capture_enable_channel(mcpwm_unit_t mcpwm_num, mcpwm_capture_cha
mcpwm_hal_init(hal, &init_config);
uint32_t clk_src_hz = 0;
clk_tree_src_get_freq_hz(MCPWM_TIMER_CLK_SRC_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz);
esp_clk_tree_src_get_freq_hz(MCPWM_TIMER_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz);
uint32_t group_resolution = mcpwm_group_get_resolution(mcpwm_num);
uint32_t group_pre_scale = clk_src_hz / group_resolution;

8
components/driver/deprecated/rmt_legacy.c
View File

@ -21,7 +21,7 @@
#include "soc/soc_memory_layout.h"
#include "soc/rmt_periph.h"
#include "soc/rmt_struct.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "hal/rmt_hal.h"
#include "hal/rmt_ll.h"
#include "hal/gpio_hal.h"
@ -567,18 +567,18 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par
if (rmt_param->flags & RMT_CHANNEL_FLAGS_AWARE_DFS) {
#if SOC_RMT_SUPPORT_XTAL
// clock src: XTAL_CLK
clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_XTAL, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz);
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_XTAL, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz);
rmt_ll_set_group_clock_src(dev, channel, (rmt_clock_source_t)RMT_BASECLK_XTAL, 1, 0, 0);
#elif SOC_RMT_SUPPORT_REF_TICK
// clock src: REF_CLK
clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_REF, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz);
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_REF, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz);
rmt_ll_set_group_clock_src(dev, channel, (rmt_clock_source_t)RMT_BASECLK_REF, 1, 0, 0);
#else
#error "No clock source is aware of DFS"
#endif
} else {
// fallback to use default clock source
clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz);
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz);
rmt_ll_set_group_clock_src(dev, channel, (rmt_clock_source_t)RMT_BASECLK_DEFAULT, 1, 0, 0);
}
RMT_EXIT_CRITICAL();

6
components/driver/deprecated/timer_legacy.c
View File

@ -15,7 +15,7 @@
#include "hal/timer_ll.h"
#include "hal/check.h"
#include "soc/timer_periph.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "soc/timer_group_reg.h"
#include "esp_private/periph_ctrl.h"
@ -78,8 +78,8 @@ esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_
uint32_t div = p_timer_obj[group_num][timer_num]->divider;
// get clock source frequency
uint32_t counter_src_hz = 0;
ESP_RETURN_ON_ERROR(clk_tree_src_get_freq_hz((soc_module_clk_t)p_timer_obj[group_num][timer_num]->clk_src,
CLK_TREE_SRC_FREQ_PRECISION_CACHED, &counter_src_hz),
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)p_timer_obj[group_num][timer_num]->clk_src,
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &counter_src_hz),
TIMER_TAG, "get clock source frequency failed");
*time = (double)timer_val * div / counter_src_hz;
return ESP_OK;

4
components/driver/gpio/gpio_flex_glitch_filter.c
View File

@ -12,7 +12,7 @@
#include "soc/soc_caps.h"
#include "hal/gpio_glitch_filter_ll.h"
#include "esp_pm.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
static const char *TAG = "gpio-filter";
@ -137,7 +137,7 @@ esp_err_t gpio_new_flex_glitch_filter(const gpio_flex_glitch_filter_config_t *co
// set clock source
uint32_t clk_freq_hz = 0;
ESP_GOTO_ON_ERROR(clk_tree_src_get_freq_hz((soc_module_clk_t)config->clk_src, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_freq_hz),
ESP_GOTO_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)config->clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_freq_hz),
err, TAG, "get clock source frequency failed");
// create pm_lock according to different clock source

2
components/driver/gpio/gpio_pin_glitch_filter.c
View File

@ -10,7 +10,7 @@
#include "esp_pm.h"
#include "glitch_filter_priv.h"
#include "hal/gpio_ll.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_private/io_mux.h"
static const char *TAG = "gpio-filter";

4
components/driver/gptimer/gptimer.c
View File

@ -27,7 +27,7 @@
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_clk.h"
#include "clk_ctrl_os.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "gptimer_priv.h"
static const char *TAG = "gptimer";
@ -430,7 +430,7 @@ static esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_sou
#endif // SOC_TIMER_GROUP_SUPPORT_RC_FAST
// get clock source frequency
ESP_RETURN_ON_ERROR(clk_tree_src_get_freq_hz((soc_module_clk_t)src_clk, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &counter_src_hz),
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)src_clk, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &counter_src_hz),
TAG, "get clock source frequency failed");
#if CONFIG_PM_ENABLE

18
components/driver/ledc/ledc.c
View File

@ -11,7 +11,7 @@
#include "esp_check.h"
#include "soc/gpio_periph.h"
#include "soc/ledc_periph.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "soc/soc_caps.h"
#include "hal/ledc_hal.h"
#include "hal/gpio_hal.h"
@ -33,11 +33,11 @@ static __attribute__((unused)) const char *LEDC_TAG = "ledc";
// Precision degree only affects RC_FAST, other clock sources' frequences are fixed values
// For targets that do not support RC_FAST calibration, can only use its approx. value. Precision degree other than
// APPROX will trigger LOGW during the call to `clk_tree_src_get_freq_hz`.
// APPROX will trigger LOGW during the call to `esp_clk_tree_src_get_freq_hz`.
#if SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
#define LEDC_CLK_SRC_FREQ_PRECISION CLK_TREE_SRC_FREQ_PRECISION_CACHED
#define LEDC_CLK_SRC_FREQ_PRECISION ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED
#else
#define LEDC_CLK_SRC_FREQ_PRECISION CLK_TREE_SRC_FREQ_PRECISION_APPROX
#define LEDC_CLK_SRC_FREQ_PRECISION ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX
#endif
typedef enum {
@ -351,7 +351,7 @@ static inline uint32_t ledc_auto_global_clk_divisor(int freq_hz, uint32_t precis
continue;
}
clk_tree_src_get_freq_hz((soc_module_clk_t)s_glb_clks[i], LEDC_CLK_SRC_FREQ_PRECISION, &clk_freq);
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)s_glb_clks[i], LEDC_CLK_SRC_FREQ_PRECISION, &clk_freq);
uint32_t div_param = ledc_calculate_divisor(clk_freq, freq_hz, precision);
/* If the divisor is valid, we can return this value. */
@ -373,7 +373,7 @@ static inline uint32_t ledc_auto_timer_specific_clk_divisor(ledc_mode_t speed_mo
uint32_t clk_freq = 0;
for (int i = 0; i < DIM(s_timer_specific_clks); i++) {
clk_tree_src_get_freq_hz((soc_module_clk_t)s_timer_specific_clks[i], LEDC_CLK_SRC_FREQ_PRECISION, &clk_freq);
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)s_timer_specific_clks[i], LEDC_CLK_SRC_FREQ_PRECISION, &clk_freq);
uint32_t div_param = ledc_calculate_divisor(clk_freq, freq_hz, precision);
/* If the divisor is valid, we can return this value. */
@ -390,7 +390,7 @@ static inline uint32_t ledc_auto_timer_specific_clk_divisor(ledc_mode_t speed_mo
* to test APB. */
if (speed_mode == LEDC_HIGH_SPEED_MODE && ret == LEDC_CLK_NOT_FOUND) {
/* No divider was found yet, try with APB! */
clk_tree_src_get_freq_hz((soc_module_clk_t)LEDC_APB_CLK, LEDC_CLK_SRC_FREQ_PRECISION, &clk_freq);
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)LEDC_APB_CLK, LEDC_CLK_SRC_FREQ_PRECISION, &clk_freq);
uint32_t div_param = ledc_calculate_divisor(clk_freq, freq_hz, precision);
if (!LEDC_IS_DIV_INVALID(div_param)) {
@ -500,7 +500,7 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n
}
uint32_t src_clk_freq = 0;
clk_tree_src_get_freq_hz((soc_module_clk_t)clk_cfg, LEDC_CLK_SRC_FREQ_PRECISION, &src_clk_freq);
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_cfg, LEDC_CLK_SRC_FREQ_PRECISION, &src_clk_freq);
div_param = ledc_calculate_divisor(src_clk_freq, freq_hz, precision);
if (LEDC_IS_DIV_INVALID(div_param)) {
div_param = LEDC_CLK_NOT_FOUND;
@ -845,7 +845,7 @@ uint32_t ledc_get_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num)
ledc_hal_get_clk_cfg(&(p_ledc_obj[speed_mode]->ledc_hal), timer_num, &clk_cfg);
uint32_t precision = (0x1 << duty_resolution);
uint32_t src_clk_freq = 0;
clk_tree_src_get_freq_hz((soc_module_clk_t)clk_cfg, LEDC_CLK_SRC_FREQ_PRECISION, &src_clk_freq);
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_cfg, LEDC_CLK_SRC_FREQ_PRECISION, &src_clk_freq);
portEXIT_CRITICAL(&ledc_spinlock);
if (clock_divider == 0) {
ESP_LOGW(LEDC_TAG, "LEDC timer not configured, call ledc_timer_config to set timer frequency");

4
components/driver/mcpwm/mcpwm_com.c
View File

@ -14,7 +14,7 @@
#endif
#include "esp_log.h"
#include "esp_check.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_private/periph_ctrl.h"
#include "soc/mcpwm_periph.h"
#include "hal/mcpwm_ll.h"
@ -115,7 +115,7 @@ esp_err_t mcpwm_select_periph_clock(mcpwm_group_t *group, soc_module_clk_t clk_s
"group clock conflict, already is %d but attempt to %d", group->clk_src, clk_src);
if (do_clock_init) {
ESP_RETURN_ON_ERROR(clk_tree_src_get_freq_hz(clk_src, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &periph_src_clk_hz), TAG, "get clock source freq failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &periph_src_clk_hz), TAG, "get clock source freq failed");
#if CONFIG_PM_ENABLE
sprintf(group->pm_lock_name, "mcpwm_%d", group->group_id); // e.g. mcpwm_0

4
components/driver/parlio/parlio_tx.c
View File

@ -33,7 +33,7 @@
#include "driver/parlio_tx.h"
#include "parlio_private.h"
#include "esp_memory_utils.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_private/gdma.h"
static const char *TAG = "parlio-tx";
@ -238,7 +238,7 @@ static esp_err_t parlio_select_periph_clock(parlio_tx_unit_t *tx_unit, const par
periph_src_clk_hz = config->input_clk_src_freq_hz;
} else {
// get the internal clock source frequency
clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &periph_src_clk_hz);
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &periph_src_clk_hz);
}
ESP_RETURN_ON_FALSE(periph_src_clk_hz, ESP_ERR_INVALID_ARG, TAG, "invalid clock source frequency");

4
components/driver/rmt/rmt_common.c
View File

@ -19,7 +19,7 @@
#include "soc/rmt_periph.h"
#include "hal/rmt_ll.h"
#include "driver/gpio.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_private/periph_ctrl.h"
static const char *TAG = "rmt";
@ -132,7 +132,7 @@ esp_err_t rmt_select_periph_clock(rmt_channel_handle_t chan, rmt_clock_source_t
#endif // SOC_RMT_SUPPORT_RC_FAST
// get clock source frequency
ESP_RETURN_ON_ERROR(clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &periph_src_clk_hz),
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &periph_src_clk_hz),
TAG, "get clock source frequency failed");
#if CONFIG_PM_ENABLE

6
components/driver/sigma_delta/sdm.c
View File

@ -19,7 +19,7 @@
#include "esp_log.h"
#include "esp_check.h"
#include "esp_pm.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "driver/gpio.h"
#include "driver/sdm.h"
#include "hal/gpio_hal.h"
@ -210,8 +210,8 @@ esp_err_t sdm_new_channel(const sdm_config_t *config, sdm_channel_handle_t *ret_
ESP_GOTO_ON_FALSE(group->clk_src == 0 || group->clk_src == config->clk_src, ESP_ERR_INVALID_ARG, err, TAG, "clock source conflict");
uint32_t src_clk_hz = 0;
ESP_GOTO_ON_ERROR(clk_tree_src_get_freq_hz((soc_module_clk_t)config->clk_src,
CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz), err, TAG, "get source clock frequency failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)config->clk_src,
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz), err, TAG, "get source clock frequency failed");
#if CONFIG_PM_ENABLE
esp_pm_lock_type_t pm_type = ESP_PM_NO_LIGHT_SLEEP;

4
components/driver/spi/gpspi/spi_master.c
View File

@ -113,7 +113,7 @@ We have two bits to control the interrupt:
#include <string.h>
#include "esp_private/spi_common_internal.h"
#include "driver/spi_master.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "clk_ctrl_os.h"
#include "esp_log.h"
#include "esp_check.h"
@ -363,7 +363,7 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa
if (dev_config->clock_source) {
clk_src = dev_config->clock_source;
}
clk_tree_src_get_freq_hz(clk_src, CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
SPI_CHECK((dev_config->clock_speed_hz > 0) && (dev_config->clock_speed_hz <= clock_source_hz), "invalid sclk speed", ESP_ERR_INVALID_ARG);
#ifdef CONFIG_IDF_TARGET_ESP32
//The hardware looks like it would support this, but actually setting cs_ena_pretrans when transferring in full

4
components/driver/test_apps/ledc/main/test_ledc.c
View File

@ -20,7 +20,7 @@
#include "esp_timer.h"
#include "driver/ledc.h"
#include "soc/ledc_struct.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#define PULSE_IO 5
@ -551,7 +551,7 @@ static void timer_frequency_test(ledc_channel_t channel, ledc_timer_bit_t timer_
// Try a frequency that couldn't be exactly achieved, requires rounding
uint32_t theoretical_freq = 9000;
uint32_t clk_src_freq = 0;
clk_tree_src_get_freq_hz((soc_module_clk_t)TEST_DEFAULT_CLK_CFG, CLK_TREE_SRC_FREQ_PRECISION_EXACT, &clk_src_freq);
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TEST_DEFAULT_CLK_CFG, ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT, &clk_src_freq);
if (clk_src_freq == 80 * 1000 * 1000) {
theoretical_freq = 8992;
} else if (clk_src_freq == 96 * 1000 * 1000) {

36
components/driver/test_apps/legacy_timer_driver/main/test_legacy_timer.c
View File

@ -11,7 +11,7 @@
#include "unity.h"
#include "driver/timer.h"
#include "esp_private/esp_clk.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "soc/soc_caps.h"
#include "esp_rom_sys.h"
#include "soc/soc.h"
@ -288,7 +288,7 @@ static void timer_intr_enable_disable_test(timer_group_t group_num, timer_idx_t
TEST_CASE("Timer_init", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
TEST_ESP_OK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
// Test init 1:config parameter
// empty parameter
timer_config_t config0 = { };
@ -359,7 +359,7 @@ TEST_CASE("Timer_init", "[hw_timer]")
TEST_CASE("Timer_read_counter_value", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
TEST_ESP_OK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
@ -401,7 +401,7 @@ TEST_CASE("Timer_read_counter_value", "[hw_timer]")
TEST_CASE("Timer_start", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
TEST_ESP_OK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
@ -435,7 +435,7 @@ TEST_CASE("Timer_start", "[hw_timer]")
TEST_CASE("Timer_pause", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
TEST_ESP_OK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
@ -465,7 +465,7 @@ TEST_CASE("Timer_pause", "[hw_timer]")
TEST_CASE("Timer_counter_direction", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
TEST_ESP_OK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
@ -504,7 +504,7 @@ TEST_CASE("Timer_counter_direction", "[hw_timer]")
TEST_CASE("Timer_divider", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
TEST_ESP_OK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
@ -582,7 +582,7 @@ TEST_CASE("Timer_divider", "[hw_timer]")
TEST_CASE("Timer_enable_alarm", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
TEST_ESP_OK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config_test = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
@ -636,7 +636,7 @@ TEST_CASE("Timer_enable_alarm", "[hw_timer]")
TEST_CASE("Timer_set_alarm_value", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
TEST_ESP_OK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
uint64_t alarm_val[SOC_TIMER_GROUP_TOTAL_TIMERS];
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
@ -676,7 +676,7 @@ TEST_CASE("Timer_set_alarm_value", "[hw_timer]")
TEST_CASE("Timer_auto_reload", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
TEST_ESP_OK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
@ -718,7 +718,7 @@ TEST_CASE("Timer_auto_reload", "[hw_timer]")
TEST_CASE("Timer_enable_timer_interrupt", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
TEST_ESP_OK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
@ -760,7 +760,7 @@ TEST_CASE("Timer_enable_timer_interrupt", "[hw_timer]")
TEST_CASE("Timer_enable_timer_group_interrupt", "[hw_timer][ignore]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
TEST_ESP_OK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
intr_handle_t isr_handle = NULL;
alarm_flag = false;
timer_config_t config = {
@ -803,7 +803,7 @@ TEST_CASE("Timer_enable_timer_group_interrupt", "[hw_timer][ignore]")
TEST_CASE("Timer_interrupt_register", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
TEST_ESP_OK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
@ -855,7 +855,7 @@ TEST_CASE("Timer_interrupt_register", "[hw_timer]")
TEST_CASE("Timer_xtal_clock_source", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_XTAL, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
TEST_ESP_OK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_XTAL, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
// configure clock source: XTAL
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_XTAL,
@ -888,7 +888,7 @@ TEST_CASE("Timer_xtal_clock_source", "[hw_timer]")
TEST_CASE("Timer_ISR_callback", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
TEST_ESP_OK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
alarm_flag = false;
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
@ -951,7 +951,7 @@ TEST_CASE("Timer_ISR_callback", "[hw_timer]")
TEST_CASE("Timer_init_deinit_stress_test", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
TEST_ESP_OK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
@ -974,7 +974,7 @@ TEST_CASE("Timer_init_deinit_stress_test", "[hw_timer]")
static void timer_group_test_init(void)
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
TEST_ESP_OK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
static const uint32_t time_ms = 100; // Alarm value 100ms.
static const uint32_t ste_val = time_ms * TEST_TIMER_RESOLUTION_HZ / 1000;
timer_config_t config = {
@ -999,7 +999,7 @@ static void timer_group_test_init(void)
TEST_CASE("Timer_check_reinitialization_sequence", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
TEST_ESP_OK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
// 1. step - install driver
timer_group_test_init();
// 2 - register interrupt and start timer

16
components/driver/test_apps/spi/master/main/test_spi_master.c
View File

@ -19,7 +19,7 @@
#include "esp_private/spi_common_internal.h"
#include "esp_private/esp_clk.h"
#include "esp_heap_caps.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_log.h"
#include "test_utils.h"
#include "test_spi_utils.h"
@ -100,7 +100,7 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")
uint32_t clock_source_hz;
// Test main clock source
#if SOC_SPI_SUPPORT_CLK_PLL_F80M
clk_tree_src_get_freq_hz(SPI_CLK_SRC_PLL_F80M, CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
esp_clk_tree_src_get_freq_hz(SPI_CLK_SRC_PLL_F80M, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
printf("\nTest clock source PLL_80M = %ld\n", clock_source_hz);
TEST_ASSERT((80 * 1000 * 1000) == clock_source_hz);
for (int i = 0; i < TEST_CLK_TIMES; i++) {
@ -109,7 +109,7 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")
#endif
#if SOC_SPI_SUPPORT_CLK_PLL_F48M
clk_tree_src_get_freq_hz(SPI_CLK_SRC_PLL_F48M, CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
esp_clk_tree_src_get_freq_hz(SPI_CLK_SRC_PLL_F48M, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
printf("\nTest clock source PLL_48M = %ld\n", clock_source_hz);
TEST_ASSERT((48 * 1000 * 1000) == clock_source_hz);
for (int i = 0; i < TEST_CLK_TIMES; i++) {
@ -118,7 +118,7 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")
#endif
#if SOC_SPI_SUPPORT_CLK_AHB
clk_tree_src_get_freq_hz(SPI_CLK_SRC_AHB, CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
esp_clk_tree_src_get_freq_hz(SPI_CLK_SRC_AHB, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
printf("\nTest clock source AHB = %ld\n", clock_source_hz);
TEST_ASSERT((48 * 1000 * 1000) == clock_source_hz);
for (int i = 0; i < TEST_CLK_TIMES; i++) {
@ -127,7 +127,7 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")
#endif
#if SOC_SPI_SUPPORT_CLK_PLL_F40M
clk_tree_src_get_freq_hz(SPI_CLK_SRC_PLL_F40M, CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
esp_clk_tree_src_get_freq_hz(SPI_CLK_SRC_PLL_F40M, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
printf("\nTest clock source PLL_40M = %ld\n", clock_source_hz);
TEST_ASSERT((40 * 1000 * 1000) == clock_source_hz);
for (int i = 0; i < TEST_CLK_TIMES; i++) {
@ -136,7 +136,7 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")
#endif
#if SOC_SPI_SUPPORT_CLK_APB
clk_tree_src_get_freq_hz(SPI_CLK_SRC_APB, CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
esp_clk_tree_src_get_freq_hz(SPI_CLK_SRC_APB, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
printf("\nTest clock source APB = %ld\n", clock_source_hz);
TEST_ASSERT((80 * 1000 * 1000) == clock_source_hz);
for (int i = 0; i < TEST_CLK_TIMES; i++) {
@ -146,7 +146,7 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")
// Test XTAL clock source
#if SOC_SPI_SUPPORT_CLK_XTAL
clk_tree_src_get_freq_hz(SPI_CLK_SRC_XTAL, CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
esp_clk_tree_src_get_freq_hz(SPI_CLK_SRC_XTAL, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
printf("\nTest clock source XTAL = %ld\n", clock_source_hz);
if((40 * 1000 * 1000) == clock_source_hz){
for (int i = 0; i < TEST_CLK_TIMES; i++) {
@ -162,7 +162,7 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")
// Test RC fast osc clock source
#if SOC_SPI_SUPPORT_CLK_RC_FAST
clk_tree_src_get_freq_hz(SPI_CLK_SRC_RC_FAST, CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
esp_clk_tree_src_get_freq_hz(SPI_CLK_SRC_RC_FAST, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
printf("\nTest clock source RC_FAST = %ld\n", clock_source_hz);
if((17500000) == clock_source_hz){
for (int i = 0; i < TEST_CLK_TIMES; i++) {

4
components/driver/twai/twai.c
View File

@ -16,7 +16,7 @@
#include "esp_pm.h"
#include "esp_attr.h"
#include "esp_heap_caps.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "clk_ctrl_os.h"
#include "driver/gpio.h"
#include "esp_private/periph_ctrl.h"
@ -428,7 +428,7 @@ esp_err_t twai_driver_install(const twai_general_config_t *g_config, const twai_
if (clk_src == 0) {
clk_src = TWAI_CLK_SRC_DEFAULT;
}
clk_tree_src_get_freq_hz(clk_src, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clock_source_hz);
esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clock_source_hz);
//Check brp validation
uint32_t brp = t_config->brp;

6
components/driver/uart/uart.c
View File

@ -24,7 +24,7 @@
#include "driver/gpio.h"
#include "driver/uart_select.h"
#include "esp_private/periph_ctrl.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "sdkconfig.h"
#include "esp_rom_gpio.h"
#include "clk_ctrl_os.h"
@ -202,7 +202,7 @@ static void uart_module_disable(uart_port_t uart_num)
esp_err_t uart_get_sclk_freq(uart_sclk_t sclk, uint32_t *out_freq_hz)
{
return clk_tree_src_get_freq_hz((soc_module_clk_t)sclk, CLK_TREE_SRC_FREQ_PRECISION_CACHED, out_freq_hz);
return esp_clk_tree_src_get_freq_hz((soc_module_clk_t)sclk, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, out_freq_hz);
}
esp_err_t uart_set_word_length(uart_port_t uart_num, uart_word_length_t data_bit)
@ -527,7 +527,7 @@ esp_err_t uart_enable_pattern_det_baud_intr(uart_port_t uart_num, char pattern_c
uint32_t uart_baud = 0;
uint32_t uart_div = 0;
uart_get_baudrate(uart_num, &uart_baud);
clk_tree_src_get_freq_hz((soc_module_clk_t)UART_SCLK_APB, CLK_TREE_SRC_FREQ_PRECISION_EXACT, &apb_clk_freq);
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)UART_SCLK_APB, ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT, &apb_clk_freq);
uart_div = apb_clk_freq / uart_baud;
at_cmd.gap_tout = chr_tout * uart_div;

4
components/esp_adc/adc_continuous.c
View File

@ -22,7 +22,7 @@
#include "esp_private/adc_private.h"
#include "esp_private/adc_share_hw_ctrl.h"
#include "esp_private/sar_periph_ctrl.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "driver/gpio.h"
#include "esp_adc/adc_continuous.h"
#include "hal/adc_types.h"
@ -523,7 +523,7 @@ esp_err_t adc_continuous_config(adc_continuous_handle_t handle, const adc_contin
#endif
uint32_t clk_src_freq_hz = 0;
clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
esp_clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
handle->hal_digi_ctrlr_cfg.adc_pattern_len = config->pattern_num;
handle->hal_digi_ctrlr_cfg.sample_freq_hz = config->sample_freq_hz;

4
components/esp_adc/adc_oneshot.c
View File

@ -15,7 +15,7 @@
#include "driver/gpio.h"
#include "driver/rtc_io.h"
#include "esp_adc/adc_oneshot.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_private/adc_private.h"
#include "esp_private/adc_share_hw_ctrl.h"
#include "esp_private/sar_periph_ctrl.h"
@ -102,7 +102,7 @@ esp_err_t adc_oneshot_new_unit(const adc_oneshot_unit_init_cfg_t *init_config, a
clk_src = init_config->clk_src;
}
uint32_t clk_src_freq_hz = 0;
ESP_GOTO_ON_ERROR(clk_tree_src_get_freq_hz(clk_src, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz), err, TAG, "clock source not supported");
ESP_GOTO_ON_ERROR(esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz), err, TAG, "clock source not supported");
adc_oneshot_hal_cfg_t config = {
.unit = init_config->unit_id,

4
components/esp_hw_support/CMakeLists.txt
View File

@ -27,8 +27,8 @@ if(NOT BOOTLOADER_BUILD)
"regi2c_ctrl.c"
"esp_gpio_reserve.c"
"port/${target}/io_mux.c"
"port/${target}/clk_tree.c"
"port/clk_tree_common.c")
"port/${target}/esp_clk_tree.c"
"port/esp_clk_tree_common.c")
if(CONFIG_SOC_ADC_SUPPORTED)
list(APPEND srcs "adc_share_hw_ctrl.c")

4
components/esp_hw_support/clk_ctrl_os.c
View File

@ -7,7 +7,7 @@
#include <freertos/FreeRTOS.h>
#include "clk_ctrl_os.h"
#include "soc/rtc.h"
#include "esp_private/clk_tree_common.h"
#include "esp_private/esp_clk_tree_common.h"
#include "esp_check.h"
static portMUX_TYPE periph_spinlock = portMUX_INITIALIZER_UNLOCKED;
@ -28,7 +28,7 @@ bool periph_rtc_dig_clk8m_enable(void)
if (s_periph_ref_counts == 0) {
rtc_dig_clk8m_enable();
#if SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
s_rc_fast_freq = clk_tree_rc_fast_get_freq_hz(CLK_TREE_SRC_FREQ_PRECISION_EXACT);
s_rc_fast_freq = esp_clk_tree_rc_fast_get_freq_hz(ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT);
if (s_rc_fast_freq == 0) {
rtc_dig_clk8m_disable();
portEXIT_CRITICAL(&periph_spinlock);

16
components/esp_hw_support/include/clk_tree.h → components/esp_hw_support/include/esp_clk_tree.h
View File

@ -14,20 +14,20 @@ extern "C" {
#endif
/**
* @brief Degree of precision of frequency value to be returned by clk_tree_src_get_freq_hz()
* @brief Degree of precision of frequency value to be returned by esp_clk_tree_src_get_freq_hz()
*/
typedef enum {
CLK_TREE_SRC_FREQ_PRECISION_CACHED, /*< Get value from the data cached by the driver; If the data is 0, then a calibration will be performed */
CLK_TREE_SRC_FREQ_PRECISION_APPROX, /*< Get its approxiamte frequency value */
CLK_TREE_SRC_FREQ_PRECISION_EXACT, /*< Always perform a calibration */
CLK_TREE_SRC_FREQ_PRECISION_INVALID, /*< Invalid degree of precision */
} clk_tree_src_freq_precision_t;
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, /*< Get value from the data cached by the driver; If the data is 0, then a calibration will be performed */
ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, /*< Get its approxiamte frequency value */
ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT, /*< Always perform a calibration */
ESP_CLK_TREE_SRC_FREQ_PRECISION_INVALID, /*< Invalid degree of precision */
} esp_clk_tree_src_freq_precision_t;
/**
* @brief Get frequency of module clock source
*
* @param[in] clk_src Clock source available to modules, in soc_module_clk_t
* @param[in] precision Degree of precision, one of clk_tree_src_freq_precision_t values
* @param[in] precision Degree of precision, one of esp_clk_tree_src_freq_precision_t values
* This arg only applies to the clock sources that their frequencies can vary:
* SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_RTC_SLOW, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_RC_FAST_D256,
* SOC_MOD_CLK_XTAL32K
@ -39,7 +39,7 @@ typedef enum {
* - ESP_ERR_INVALID_ARG Parameter error
* - ESP_FAIL Calibration failed
*/
esp_err_t clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, clk_tree_src_freq_precision_t precision,
esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_src_freq_precision_t precision,
uint32_t *freq_value);
#ifdef __cplusplus

26
components/esp_hw_support/include/esp_private/clk_tree_common.h → components/esp_hw_support/include/esp_private/esp_clk_tree_common.h
View File

@ -7,7 +7,7 @@
#pragma once
#include <stdint.h>
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
@ -18,61 +18,61 @@ extern "C" {
/**
* @brief Get frequency of RC_FAST_D256_CLK
*
* @param precision Degree of precision of the returned frequency value, one of clk_tree_src_freq_precision_t values
* @param precision Degree of precision of the returned frequency value, one of esp_clk_tree_src_freq_precision_t values
*
* @return RC_FAST_D256 clock frequency, in Hz. Returns 0 if degree of precision is invalid or calibration failed.
*/
uint32_t clk_tree_rc_fast_d256_get_freq_hz(clk_tree_src_freq_precision_t precision);
uint32_t esp_clk_tree_rc_fast_d256_get_freq_hz(esp_clk_tree_src_freq_precision_t precision);
#endif
#if SOC_CLK_XTAL32K_SUPPORTED
/**
* @brief Get frequency of XTAL32K_CLK
*
* @param precision Degree of precision of the returned frequency value, one of clk_tree_src_freq_precision_t values
* @param precision Degree of precision of the returned frequency value, one of esp_clk_tree_src_freq_precision_t values
*
* @return XTAL32K clock frequency, in Hz. Returns 0 if degree of precision is invalid or calibration failed.
*/
uint32_t clk_tree_xtal32k_get_freq_hz(clk_tree_src_freq_precision_t precision);
uint32_t esp_clk_tree_xtal32k_get_freq_hz(esp_clk_tree_src_freq_precision_t precision);
#endif
#if SOC_CLK_OSC_SLOW_SUPPORTED
/**
* @brief Get frequency of OSC_SLOW_CLK
*
* @param precision Degree of precision of the returned frequency value, one of clk_tree_src_freq_precision_t values
* @param precision Degree of precision of the returned frequency value, one of esp_clk_tree_src_freq_precision_t values
*
* @return OSC_SLOW clock frequency, in Hz. Returns 0 if degree of precision is invalid or calibration failed.
*/
uint32_t clk_tree_osc_slow_get_freq_hz(clk_tree_src_freq_precision_t precision);
uint32_t esp_clk_tree_osc_slow_get_freq_hz(esp_clk_tree_src_freq_precision_t precision);
#endif
/**
* @brief Get frequency of RC_FAST_CLK
*
* @param precision Degree of precision of the returned frequency value, one of clk_tree_src_freq_precision_t values
* @param precision Degree of precision of the returned frequency value, one of esp_clk_tree_src_freq_precision_t values
*
* @return RC_FAST clock frequency, in Hz. Returns 0 if degree of precision is invalid or calibration failed.
*/
uint32_t clk_tree_rc_fast_get_freq_hz(clk_tree_src_freq_precision_t precision);
uint32_t esp_clk_tree_rc_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t precision);
/**
* @brief Get frequency of LP_SLOW_CLK (i.e. RTC_SLOW_CLK)
*
* @param precision Degree of precision of the returned frequency value, one of clk_tree_src_freq_precision_t values
* @param precision Degree of precision of the returned frequency value, one of esp_clk_tree_src_freq_precision_t values
*
* @return LP_SLOW clock frequency, in Hz. Returns 0 if degree of precision is invalid or calibration failed.
*/
uint32_t clk_tree_lp_slow_get_freq_hz(clk_tree_src_freq_precision_t precision);
uint32_t esp_clk_tree_lp_slow_get_freq_hz(esp_clk_tree_src_freq_precision_t precision);
/**
* @brief Get frequency of LP_FAST_CLK (i.e. RTC_FAST_CLK)
*
* @param precision Degree of precision of the returned frequency value, one of clk_tree_src_freq_precision_t values
* @param precision Degree of precision of the returned frequency value, one of esp_clk_tree_src_freq_precision_t values
*
* @return LP_FAST clock frequency, in Hz. Returns 0 if degree of precision is invalid or calibration failed.
*/
uint32_t clk_tree_lp_fast_get_freq_hz(clk_tree_src_freq_precision_t precision);
uint32_t esp_clk_tree_lp_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t precision);
#ifdef __cplusplus
}

20
components/esp_hw_support/port/esp32/clk_tree.c → components/esp_hw_support/port/esp32/esp_clk_tree.c
View File

@ -5,21 +5,21 @@
*/
#include <stdint.h>
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_err.h"
#include "esp_check.h"
#include "soc/rtc.h"
#include "hal/clk_tree_hal.h"
#include "hal/clk_tree_ll.h"
#include "esp_private/clk_tree_common.h"
#include "esp_private/esp_clk_tree_common.h"
static const char *TAG = "clk_tree";
static const char *TAG = "esp_clk_tree";
esp_err_t clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, clk_tree_src_freq_precision_t precision,
esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_src_freq_precision_t precision,
uint32_t *freq_value)
{
ESP_RETURN_ON_FALSE(clk_src > 0 && clk_src < SOC_MOD_CLK_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown clk src");
ESP_RETURN_ON_FALSE(precision < CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision");
ESP_RETURN_ON_FALSE(precision < ESP_CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision");
ESP_RETURN_ON_FALSE(freq_value, ESP_ERR_INVALID_ARG, TAG, "null pointer");
uint32_t clk_src_freq = 0;
@ -40,19 +40,19 @@ uint32_t *freq_value)
clk_src_freq = CLK_LL_PLL_160M_FREQ_MHZ * MHZ;
break;
case SOC_MOD_CLK_RTC_SLOW:
clk_src_freq = clk_tree_lp_slow_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_lp_slow_get_freq_hz(precision);
break;
case SOC_MOD_CLK_RTC_FAST:
clk_src_freq = clk_tree_lp_fast_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_lp_fast_get_freq_hz(precision);
break;
case SOC_MOD_CLK_RC_FAST:
clk_src_freq = clk_tree_rc_fast_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_rc_fast_get_freq_hz(precision);
break;
case SOC_MOD_CLK_RC_FAST_D256:
clk_src_freq = clk_tree_rc_fast_d256_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_rc_fast_d256_get_freq_hz(precision);
break;
case SOC_MOD_CLK_XTAL32K:
clk_src_freq = clk_tree_xtal32k_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_xtal32k_get_freq_hz(precision);
break;
case SOC_MOD_CLK_REF_TICK:
clk_src_freq = 1 * MHZ;

20
components/esp_hw_support/port/esp32c2/clk_tree.c → components/esp_hw_support/port/esp32c2/esp_clk_tree.c
View File

@ -5,21 +5,21 @@
*/
#include <stdint.h>
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_err.h"
#include "esp_check.h"
#include "soc/rtc.h"
#include "hal/clk_tree_hal.h"
#include "hal/clk_tree_ll.h"
#include "esp_private/clk_tree_common.h"
#include "esp_private/esp_clk_tree_common.h"
static const char *TAG = "clk_tree";
static const char *TAG = "esp_clk_tree";
esp_err_t clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, clk_tree_src_freq_precision_t precision,
esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_src_freq_precision_t precision,
uint32_t *freq_value)
{
ESP_RETURN_ON_FALSE(clk_src > 0 && clk_src < SOC_MOD_CLK_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown clk src");
ESP_RETURN_ON_FALSE(precision < CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision");
ESP_RETURN_ON_FALSE(precision < ESP_CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision");
ESP_RETURN_ON_FALSE(freq_value, ESP_ERR_INVALID_ARG, TAG, "null pointer");
uint32_t clk_src_freq = 0;
@ -40,19 +40,19 @@ uint32_t *freq_value)
clk_src_freq = CLK_LL_PLL_80M_FREQ_MHZ * MHZ;
break;
case SOC_MOD_CLK_RTC_SLOW:
clk_src_freq = clk_tree_lp_slow_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_lp_slow_get_freq_hz(precision);
break;
case SOC_MOD_CLK_RTC_FAST:
clk_src_freq = clk_tree_lp_fast_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_lp_fast_get_freq_hz(precision);
break;
case SOC_MOD_CLK_RC_FAST:
clk_src_freq = clk_tree_rc_fast_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_rc_fast_get_freq_hz(precision);
break;
case SOC_MOD_CLK_RC_FAST_D256:
clk_src_freq = clk_tree_rc_fast_d256_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_rc_fast_d256_get_freq_hz(precision);
break;
case SOC_MOD_CLK_OSC_SLOW:
clk_src_freq = clk_tree_osc_slow_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_osc_slow_get_freq_hz(precision);
break;
default:
break;

20
components/esp_hw_support/port/esp32c3/clk_tree.c → components/esp_hw_support/port/esp32c3/esp_clk_tree.c
View File

@ -5,21 +5,21 @@
*/
#include <stdint.h>
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_err.h"
#include "esp_check.h"
#include "soc/rtc.h"
#include "hal/clk_tree_hal.h"
#include "hal/clk_tree_ll.h"
#include "esp_private/clk_tree_common.h"
#include "esp_private/esp_clk_tree_common.h"
static const char *TAG = "clk_tree";
static const char *TAG = "esp_clk_tree";
esp_err_t clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, clk_tree_src_freq_precision_t precision,
esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_src_freq_precision_t precision,
uint32_t *freq_value)
{
ESP_RETURN_ON_FALSE(clk_src > 0 && clk_src < SOC_MOD_CLK_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown clk src");
ESP_RETURN_ON_FALSE(precision < CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision");
ESP_RETURN_ON_FALSE(precision < ESP_CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision");
ESP_RETURN_ON_FALSE(freq_value, ESP_ERR_INVALID_ARG, TAG, "null pointer");
uint32_t clk_src_freq = 0;
@ -40,19 +40,19 @@ uint32_t *freq_value)
clk_src_freq = CLK_LL_PLL_160M_FREQ_MHZ * MHZ;
break;
case SOC_MOD_CLK_RTC_SLOW:
clk_src_freq = clk_tree_lp_slow_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_lp_slow_get_freq_hz(precision);
break;
case SOC_MOD_CLK_RTC_FAST:
clk_src_freq = clk_tree_lp_fast_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_lp_fast_get_freq_hz(precision);
break;
case SOC_MOD_CLK_RC_FAST:
clk_src_freq = clk_tree_rc_fast_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_rc_fast_get_freq_hz(precision);
break;
case SOC_MOD_CLK_RC_FAST_D256:
clk_src_freq = clk_tree_rc_fast_d256_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_rc_fast_d256_get_freq_hz(precision);
break;
case SOC_MOD_CLK_XTAL32K:
clk_src_freq = clk_tree_xtal32k_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_xtal32k_get_freq_hz(precision);
break;
default:
break;

18
components/esp_hw_support/port/esp32c6/clk_tree.c → components/esp_hw_support/port/esp32c6/esp_clk_tree.c
View File

@ -5,21 +5,21 @@
*/
#include <stdint.h>
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_err.h"
#include "esp_check.h"
#include "soc/rtc.h"
#include "hal/clk_tree_hal.h"
#include "hal/clk_tree_ll.h"
#include "esp_private/clk_tree_common.h"
#include "esp_private/esp_clk_tree_common.h"
static const char *TAG = "clk_tree";
static const char *TAG = "esp_clk_tree";
esp_err_t clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, clk_tree_src_freq_precision_t precision,
esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_src_freq_precision_t precision,
uint32_t *freq_value)
{
ESP_RETURN_ON_FALSE(clk_src > 0 && clk_src < SOC_MOD_CLK_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown clk src");
ESP_RETURN_ON_FALSE(precision < CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision");
ESP_RETURN_ON_FALSE(precision < ESP_CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision");
ESP_RETURN_ON_FALSE(freq_value, ESP_ERR_INVALID_ARG, TAG, "null pointer");
uint32_t clk_src_freq = 0;
@ -40,16 +40,16 @@ uint32_t *freq_value)
clk_src_freq = CLK_LL_PLL_240M_FREQ_MHZ * MHZ;
break;
case SOC_MOD_CLK_RTC_SLOW:
clk_src_freq = clk_tree_lp_slow_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_lp_slow_get_freq_hz(precision);
break;
case SOC_MOD_CLK_RTC_FAST:
clk_src_freq = clk_tree_lp_fast_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_lp_fast_get_freq_hz(precision);
break;
case SOC_MOD_CLK_RC_FAST:
clk_src_freq = clk_tree_rc_fast_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_rc_fast_get_freq_hz(precision);
break;
case SOC_MOD_CLK_XTAL32K:
clk_src_freq = clk_tree_xtal32k_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_xtal32k_get_freq_hz(precision);
break;
default:
break;

18
components/esp_hw_support/port/esp32h2/clk_tree.c → components/esp_hw_support/port/esp32h2/esp_clk_tree.c
View File

@ -5,21 +5,21 @@
*/
#include <stdint.h>
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_err.h"
#include "esp_check.h"
#include "soc/rtc.h"
#include "hal/clk_tree_hal.h"
#include "hal/clk_tree_ll.h"
#include "esp_private/clk_tree_common.h"
#include "esp_private/esp_clk_tree_common.h"
static const char *TAG = "clk_tree";
static const char *TAG = "esp_clk_tree";
esp_err_t clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, clk_tree_src_freq_precision_t precision,
esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_src_freq_precision_t precision,
uint32_t *freq_value)
{
ESP_RETURN_ON_FALSE(clk_src > 0 && clk_src < SOC_MOD_CLK_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown clk src");
ESP_RETURN_ON_FALSE(precision < CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision");
ESP_RETURN_ON_FALSE(precision < ESP_CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision");
ESP_RETURN_ON_FALSE(freq_value, ESP_ERR_INVALID_ARG, TAG, "null pointer");
uint32_t clk_src_freq = 0;
@ -40,16 +40,16 @@ uint32_t *freq_value)
clk_src_freq = CLK_LL_PLL_96M_FREQ_MHZ * MHZ;
break;
case SOC_MOD_CLK_RTC_SLOW:
clk_src_freq = clk_tree_lp_slow_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_lp_slow_get_freq_hz(precision);
break;
case SOC_MOD_CLK_RTC_FAST:
clk_src_freq = clk_tree_lp_fast_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_lp_fast_get_freq_hz(precision);
break;
case SOC_MOD_CLK_RC_FAST:
clk_src_freq = clk_tree_rc_fast_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_rc_fast_get_freq_hz(precision);
break;
case SOC_MOD_CLK_XTAL32K:
clk_src_freq = clk_tree_xtal32k_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_xtal32k_get_freq_hz(precision);
break;
default:
break;

20
components/esp_hw_support/port/esp32s2/clk_tree.c → components/esp_hw_support/port/esp32s2/esp_clk_tree.c
View File

@ -5,21 +5,21 @@
*/
#include <stdint.h>
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_err.h"
#include "esp_check.h"
#include "soc/rtc.h"
#include "hal/clk_tree_hal.h"
#include "hal/clk_tree_ll.h"
#include "esp_private/clk_tree_common.h"
#include "esp_private/esp_clk_tree_common.h"
static const char *TAG = "clk_tree";
static const char *TAG = "esp_clk_tree";
esp_err_t clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, clk_tree_src_freq_precision_t precision,
esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_src_freq_precision_t precision,
uint32_t *freq_value)
{
ESP_RETURN_ON_FALSE(clk_src > 0 && clk_src < SOC_MOD_CLK_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown clk src");
ESP_RETURN_ON_FALSE(precision < CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision");
ESP_RETURN_ON_FALSE(precision < ESP_CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision");
ESP_RETURN_ON_FALSE(freq_value, ESP_ERR_INVALID_ARG, TAG, "null pointer");
uint32_t clk_src_freq = 0;
@ -37,20 +37,20 @@ uint32_t *freq_value)
clk_src_freq = CLK_LL_PLL_160M_FREQ_MHZ * MHZ;
break;
case SOC_MOD_CLK_RTC_SLOW:
clk_src_freq = clk_tree_lp_slow_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_lp_slow_get_freq_hz(precision);
break;
case SOC_MOD_CLK_RTC_FAST:
clk_src_freq = clk_tree_lp_fast_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_lp_fast_get_freq_hz(precision);
break;
case SOC_MOD_CLK_RC_FAST:
case SOC_MOD_CLK_TEMP_SENSOR:
clk_src_freq = clk_tree_rc_fast_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_rc_fast_get_freq_hz(precision);
break;
case SOC_MOD_CLK_RC_FAST_D256:
clk_src_freq = clk_tree_rc_fast_d256_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_rc_fast_d256_get_freq_hz(precision);
break;
case SOC_MOD_CLK_XTAL32K:
clk_src_freq = clk_tree_xtal32k_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_xtal32k_get_freq_hz(precision);
break;
case SOC_MOD_CLK_REF_TICK:
clk_src_freq = 1 * MHZ;

20
components/esp_hw_support/port/esp32s3/clk_tree.c → components/esp_hw_support/port/esp32s3/esp_clk_tree.c
View File

@ -5,21 +5,21 @@
*/
#include <stdint.h>
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_err.h"
#include "esp_check.h"
#include "soc/rtc.h"
#include "hal/clk_tree_hal.h"
#include "hal/clk_tree_ll.h"
#include "esp_private/clk_tree_common.h"
#include "esp_private/esp_clk_tree_common.h"
static const char *TAG = "clk_tree";
static const char *TAG = "esp_clk_tree";
esp_err_t clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, clk_tree_src_freq_precision_t precision,
esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_src_freq_precision_t precision,
uint32_t *freq_value)
{
ESP_RETURN_ON_FALSE(clk_src > 0 && clk_src < SOC_MOD_CLK_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown clk src");
ESP_RETURN_ON_FALSE(precision < CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision");
ESP_RETURN_ON_FALSE(precision < ESP_CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision");
ESP_RETURN_ON_FALSE(freq_value, ESP_ERR_INVALID_ARG, TAG, "null pointer");
uint32_t clk_src_freq = 0;
@ -43,20 +43,20 @@ uint32_t *freq_value)
clk_src_freq = (clk_ll_bbpll_get_freq_mhz() * MHZ) >> 1;
break;
case SOC_MOD_CLK_RTC_SLOW:
clk_src_freq = clk_tree_lp_slow_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_lp_slow_get_freq_hz(precision);
break;
case SOC_MOD_CLK_RTC_FAST:
clk_src_freq = clk_tree_lp_fast_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_lp_fast_get_freq_hz(precision);
break;
case SOC_MOD_CLK_RC_FAST:
case SOC_MOD_CLK_TEMP_SENSOR:
clk_src_freq = clk_tree_rc_fast_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_rc_fast_get_freq_hz(precision);
break;
case SOC_MOD_CLK_RC_FAST_D256:
clk_src_freq = clk_tree_rc_fast_d256_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_rc_fast_d256_get_freq_hz(precision);
break;
case SOC_MOD_CLK_XTAL32K:
clk_src_freq = clk_tree_xtal32k_get_freq_hz(precision);
clk_src_freq = esp_clk_tree_xtal32k_get_freq_hz(precision);
break;
default:
break;

56
components/esp_hw_support/port/clk_tree_common.c → components/esp_hw_support/port/esp_clk_tree_common.c
View File

@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "esp_private/clk_tree_common.h"
#include "esp_private/esp_clk_tree_common.h"
#include "hal/clk_tree_hal.h"
#include "hal/clk_tree_ll.h"
#include "soc/rtc.h"
@ -14,11 +14,11 @@
#include "sdkconfig.h"
#include "esp_hw_log.h"
static const char *TAG = "clk_tree_common";
static const char *TAG = "esp_clk_tree_common";
typedef struct clk_tree_calibrated_freq_t clk_tree_calibrated_freq_t;
typedef struct esp_clk_tree_calibrated_freq_t esp_clk_tree_calibrated_freq_t;
struct clk_tree_calibrated_freq_t {
struct esp_clk_tree_calibrated_freq_t {
#if SOC_CLK_RC_FAST_D256_SUPPORTED
uint32_t rc_fast_d256;
#elif SOC_CLK_RC_FAST_SUPPORT_CALIBRATION // && !SOC_CLK_RC_FAST_D256_SUPPORTED
@ -33,7 +33,7 @@ struct clk_tree_calibrated_freq_t {
};
// TODO: Better to implement a spinlock for the static variables
static clk_tree_calibrated_freq_t s_calibrated_freq = {};
static esp_clk_tree_calibrated_freq_t s_calibrated_freq = {};
/* Number of cycles for RTC_SLOW_CLK calibration */
#define RTC_SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
@ -72,17 +72,17 @@ static uint32_t clk_tree_rtc_slow_calibration(uint32_t slowclk_cycles)
}
#if SOC_CLK_RC_FAST_D256_SUPPORTED
uint32_t clk_tree_rc_fast_d256_get_freq_hz(clk_tree_src_freq_precision_t precision)
uint32_t esp_clk_tree_rc_fast_d256_get_freq_hz(esp_clk_tree_src_freq_precision_t precision)
{
switch (precision) {
case CLK_TREE_SRC_FREQ_PRECISION_APPROX:
case ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX:
return SOC_CLK_RC_FAST_D256_FREQ_APPROX;
case CLK_TREE_SRC_FREQ_PRECISION_CACHED:
case ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED:
if (!s_calibrated_freq.rc_fast_d256) {
s_calibrated_freq.rc_fast_d256 = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_8MD256, DEFAULT_32K_CLK_CAL_CYCLES));
}
return s_calibrated_freq.rc_fast_d256;
case CLK_TREE_SRC_FREQ_PRECISION_EXACT:
case ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT:
s_calibrated_freq.rc_fast_d256 = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_8MD256, DEFAULT_32K_CLK_CAL_CYCLES));
return s_calibrated_freq.rc_fast_d256;
default:
@ -92,17 +92,17 @@ uint32_t clk_tree_rc_fast_d256_get_freq_hz(clk_tree_src_freq_precision_t precisi
#endif
#if SOC_CLK_XTAL32K_SUPPORTED
uint32_t clk_tree_xtal32k_get_freq_hz(clk_tree_src_freq_precision_t precision)
uint32_t esp_clk_tree_xtal32k_get_freq_hz(esp_clk_tree_src_freq_precision_t precision)
{
switch (precision) {
case CLK_TREE_SRC_FREQ_PRECISION_APPROX:
case ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX:
return SOC_CLK_XTAL32K_FREQ_APPROX;
case CLK_TREE_SRC_FREQ_PRECISION_CACHED:
case ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED:
if (!s_calibrated_freq.xtal32k) {
s_calibrated_freq.xtal32k = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_32K_XTAL, DEFAULT_32K_CLK_CAL_CYCLES));
}
return s_calibrated_freq.xtal32k;
case CLK_TREE_SRC_FREQ_PRECISION_EXACT:
case ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT:
s_calibrated_freq.xtal32k = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_32K_XTAL, DEFAULT_32K_CLK_CAL_CYCLES));
return s_calibrated_freq.xtal32k;
default:
@ -112,17 +112,17 @@ uint32_t clk_tree_xtal32k_get_freq_hz(clk_tree_src_freq_precision_t precision)
#endif
#if SOC_CLK_OSC_SLOW_SUPPORTED
uint32_t clk_tree_osc_slow_get_freq_hz(clk_tree_src_freq_precision_t precision)
uint32_t esp_clk_tree_osc_slow_get_freq_hz(esp_clk_tree_src_freq_precision_t precision)
{
switch (precision) {
case CLK_TREE_SRC_FREQ_PRECISION_APPROX:
case ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX:
return SOC_CLK_OSC_SLOW_FREQ_APPROX;
case CLK_TREE_SRC_FREQ_PRECISION_CACHED:
case ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED:
if (!s_calibrated_freq.osc_slow) {
s_calibrated_freq.osc_slow = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_32K_OSC_SLOW, DEFAULT_32K_CLK_CAL_CYCLES));
}
return s_calibrated_freq.osc_slow;
case CLK_TREE_SRC_FREQ_PRECISION_EXACT:
case ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT:
s_calibrated_freq.osc_slow = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_32K_OSC_SLOW, DEFAULT_32K_CLK_CAL_CYCLES));
return s_calibrated_freq.osc_slow;
default:
@ -131,39 +131,39 @@ uint32_t clk_tree_osc_slow_get_freq_hz(clk_tree_src_freq_precision_t precision)
}
#endif
uint32_t clk_tree_lp_slow_get_freq_hz(clk_tree_src_freq_precision_t precision)
uint32_t esp_clk_tree_lp_slow_get_freq_hz(esp_clk_tree_src_freq_precision_t precision)
{
switch (precision) {
case CLK_TREE_SRC_FREQ_PRECISION_CACHED:
case ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED:
// This returns calibrated (if CONFIG_xxx_RTC_CLK_CAL_CYCLES) value stored in RTC storage register
return rtc_clk_freq_cal(clk_ll_rtc_slow_load_cal());
case CLK_TREE_SRC_FREQ_PRECISION_APPROX:
case ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX:
return clk_hal_lp_slow_get_freq_hz();
case CLK_TREE_SRC_FREQ_PRECISION_EXACT:
case ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT:
return rtc_clk_freq_cal(clk_tree_rtc_slow_calibration(RTC_SLOW_CLK_CAL_CYCLES));
default:
return 0;
}
}
uint32_t clk_tree_rc_fast_get_freq_hz(clk_tree_src_freq_precision_t precision)
uint32_t esp_clk_tree_rc_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t precision)
{
#if SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
if (precision == CLK_TREE_SRC_FREQ_PRECISION_APPROX) {
if (precision == ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX) {
return SOC_CLK_RC_FAST_FREQ_APPROX;
}
#if SOC_CLK_RC_FAST_D256_SUPPORTED
// If RC_FAST_D256 clock exists, calibration on a slow freq clock is much faster (less slow clock cycles need to wait)
return clk_tree_rc_fast_d256_get_freq_hz(precision) << 8;
return esp_clk_tree_rc_fast_d256_get_freq_hz(precision) << 8;
#else
// Calibrate directly on the RC_FAST clock requires much more slow clock cycles to get an accurate freq value
if (precision != CLK_TREE_SRC_FREQ_PRECISION_CACHED || !s_calibrated_freq.rc_fast) {
if (precision != ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED || !s_calibrated_freq.rc_fast) {
s_calibrated_freq.rc_fast = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_RC_FAST, DEFAULT_RC_FAST_CAL_CYCLES));
}
return s_calibrated_freq.rc_fast;
#endif //SOC_CLK_RC_FAST_D256_SUPPORTED
#else //!SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
if (precision != CLK_TREE_SRC_FREQ_PRECISION_APPROX) {
if (precision != ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX) {
// No way of getting exact rc_fast freq
ESP_HW_LOGW(TAG, "unable to get the exact freq of rc_fast_clk, returning its approx. freq value");
}
@ -171,7 +171,7 @@ uint32_t clk_tree_rc_fast_get_freq_hz(clk_tree_src_freq_precision_t precision)
#endif //SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
}
uint32_t clk_tree_lp_fast_get_freq_hz(clk_tree_src_freq_precision_t precision)
uint32_t esp_clk_tree_lp_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t precision)
{
switch (clk_ll_rtc_fast_get_src()) {
case SOC_RTC_FAST_CLK_SRC_XTAL_DIV:
@ -181,7 +181,7 @@ uint32_t clk_tree_lp_fast_get_freq_hz(clk_tree_src_freq_precision_t precision)
return clk_hal_xtal_get_freq_mhz() * MHZ >> 1;
#endif
case SOC_RTC_FAST_CLK_SRC_RC_FAST:
return clk_tree_rc_fast_get_freq_hz(precision) / clk_ll_rc_fast_get_divider();
return esp_clk_tree_rc_fast_get_freq_hz(precision) / clk_ll_rc_fast_get_divider();
#if SOC_CLK_LP_FAST_SUPPORT_LP_PLL
case SOC_RTC_FAST_CLK_SRC_LP_PLL:
return clk_ll_lp_pll_get_freq_mhz() * MHZ;

4
components/esp_lcd/src/esp_lcd_panel_io_i2s.c
View File

@ -36,7 +36,7 @@
#include "hal/dma_types.h"
#include "hal/gpio_hal.h"
#include "driver/gpio.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/i2s_platform.h"
#include "soc/lcd_periph.h"
@ -608,7 +608,7 @@ static esp_err_t i2s_lcd_select_periph_clock(esp_lcd_i80_bus_handle_t bus, lcd_c
{
// get clock source frequency
uint32_t src_clk_hz = 0;
ESP_RETURN_ON_ERROR(clk_tree_src_get_freq_hz((soc_module_clk_t)src, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz),
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz),
TAG, "get clock source frequency failed");
// I2S clock source is binary compatible with lcd_clock_source_t

4
components/esp_lcd/src/esp_lcd_panel_io_i80.c
View File

@ -25,7 +25,7 @@
#include "esp_lcd_panel_io.h"
#include "esp_rom_gpio.h"
#include "soc/soc_caps.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_memory_utils.h"
#include "hal/dma_types.h"
#include "hal/gpio_hal.h"
@ -492,7 +492,7 @@ static esp_err_t lcd_i80_select_periph_clock(esp_lcd_i80_bus_handle_t bus, lcd_c
{
// get clock source frequency
uint32_t src_clk_hz = 0;
ESP_RETURN_ON_ERROR(clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz),
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz),
TAG, "get clock source frequency failed");
// force to use integer division, as fractional division might lead to clock jitter

4
components/esp_lcd/src/esp_lcd_panel_rgb.c
View File

@ -26,7 +26,7 @@
#include "esp_lcd_panel_ops.h"
#include "esp_rom_gpio.h"
#include "soc/soc_caps.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "hal/dma_types.h"
#include "hal/gpio_hal.h"
#include "esp_private/gdma.h"
@ -920,7 +920,7 @@ static esp_err_t lcd_rgb_panel_select_clock_src(esp_rgb_panel_t *panel, lcd_cloc
{
// get clock source frequency
uint32_t src_clk_hz = 0;
ESP_RETURN_ON_ERROR(clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz),
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz),
TAG, "get clock source frequency failed");
panel->src_clk_hz = src_clk_hz;
lcd_ll_select_clk_src(panel->hal.dev, clk_src);

4
components/vfs/test/test_vfs_uart.c
View File

@ -19,7 +19,7 @@
#include "hal/uart_ll.h"
#include "esp_vfs_dev.h"
#include "esp_vfs.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "test_utils.h"
#include "sdkconfig.h"
@ -217,7 +217,7 @@ TEST_CASE("fcntl supported in UART VFS", "[vfs]")
TEST_CASE("Can use termios for UART", "[vfs]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)UART_SCLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
TEST_ESP_OK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)UART_SCLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
uart_config_t uart_config = {
.baud_rate = 115200,
.data_bits = UART_DATA_8_BITS,

2
docs/doxygen/Doxyfile
View File

@ -137,7 +137,7 @@ INPUT = \
$(PROJECT_PATH)/components/esp_http_server/include/esp_http_server.h \
$(PROJECT_PATH)/components/esp_https_ota/include/esp_https_ota.h \
$(PROJECT_PATH)/components/esp_https_server/include/esp_https_server.h \
$(PROJECT_PATH)/components/esp_hw_support/include/clk_tree.h \
$(PROJECT_PATH)/components/esp_hw_support/include/esp_clk_tree.h \
$(PROJECT_PATH)/components/esp_hw_support/include/esp_async_memcpy.h \
$(PROJECT_PATH)/components/esp_hw_support/include/esp_chip_info.h \
$(PROJECT_PATH)/components/esp_hw_support/include/esp_cpu.h \

4
docs/en/api-reference/peripherals/clk_tree.rst
View File

@ -87,10 +87,10 @@ Module Clocks
API Usage
---------
The clock tree driver provides an all-in-one API to get the frequency of the module clocks, :cpp:func:`clk_tree_src_get_freq_hz`. Users can call this function at any moment, with specifying the clock name (:cpp:enum:`soc_module_clk_t`) and the desired degree of precision of the returned frequency value (:cpp:enum:`clk_tree_src_freq_precision_t`).
The clock tree driver provides an all-in-one API to get the frequency of the module clocks, :cpp:func:`esp_clk_tree_src_get_freq_hz`. Users can call this function at any moment, with specifying the clock name (:cpp:enum:`soc_module_clk_t`) and the desired degree of precision of the returned frequency value (:cpp:enum:`esp_clk_tree_src_freq_precision_t`).
API Reference
-------------
.. include-build-file:: inc/clk_tree_defs.inc
.. include-build-file:: inc/clk_tree.inc
.. include-build-file:: inc/esp_clk_tree.inc

4
examples/peripherals/timer_group/legacy_driver/main/timer_group_example_main.c
View File

@ -10,7 +10,7 @@
#include "freertos/task.h"
#include "freertos/queue.h"
#include "driver/timer.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_log.h"
#define TIMER_RESOLUTION_HZ 1000000 // 1MHz resolution
@ -64,7 +64,7 @@ static void example_tg_timer_init(example_timer_user_data_t *user_data)
int timer = user_data->timer_idx;
uint32_t clk_src_hz = 0;
ESP_ERROR_CHECK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
ESP_ERROR_CHECK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = clk_src_hz / TIMER_RESOLUTION_HZ,