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https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
secure boot: Fix bootloader image verification failure
* Failure prevented secure boot from enabling. * Also adds unit test cases for esp_image_basic_verify() Ref https://esp32.com/viewtopic.php?f=2&t=1602 TW11878
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@ -22,16 +22,9 @@ extern "C"
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#endif
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#endif
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#include "esp_flash_data_types.h"
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#include "esp_flash_data_types.h"
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#include "soc/soc.h"
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#define SPI_SEC_SIZE 0x1000
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#define SPI_SEC_SIZE 0x1000
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#define IROM_LOW 0x400D0000
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#define IROM_HIGH 0x40400000
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#define DROM_LOW 0x3F400000
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#define DROM_HIGH 0x3F800000
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#define RTC_IRAM_LOW 0x400C0000
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#define RTC_IRAM_HIGH 0x400C2000
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#define RTC_DATA_LOW 0x50000000
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#define RTC_DATA_HIGH 0x50002000
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#define SPI_ERROR_LOG "spi flash error"
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#define SPI_ERROR_LOG "spi flash error"
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@ -475,7 +475,7 @@ static void unpack_load_app(const esp_partition_pos_t* partition)
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// TODO: actually check md5
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// TODO: actually check md5
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}
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}
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if (address >= DROM_LOW && address < DROM_HIGH) {
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if (address >= SOC_DROM_LOW && address < SOC_DROM_HIGH) {
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ESP_LOGD(TAG, "found drom segment, map from %08x to %08x", data_offs,
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ESP_LOGD(TAG, "found drom segment, map from %08x to %08x", data_offs,
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segment_header.load_addr);
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segment_header.load_addr);
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drom_addr = data_offs;
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drom_addr = data_offs;
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@ -485,7 +485,7 @@ static void unpack_load_app(const esp_partition_pos_t* partition)
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map = true;
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map = true;
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}
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}
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if (address >= IROM_LOW && address < IROM_HIGH) {
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if (address >= SOC_IROM_LOW && address < SOC_IROM_HIGH) {
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ESP_LOGD(TAG, "found irom segment, map from %08x to %08x", data_offs,
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ESP_LOGD(TAG, "found irom segment, map from %08x to %08x", data_offs,
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segment_header.load_addr);
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segment_header.load_addr);
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irom_addr = data_offs;
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irom_addr = data_offs;
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@ -495,12 +495,12 @@ static void unpack_load_app(const esp_partition_pos_t* partition)
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map = true;
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map = true;
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}
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}
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if (!load_rtc_memory && address >= RTC_IRAM_LOW && address < RTC_IRAM_HIGH) {
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if (!load_rtc_memory && address >= SOC_RTC_IRAM_LOW && address < SOC_RTC_IRAM_HIGH) {
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ESP_LOGD(TAG, "Skipping RTC code segment at %08x\n", data_offs);
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ESP_LOGD(TAG, "Skipping RTC code segment at %08x\n", data_offs);
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load = false;
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load = false;
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}
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}
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if (!load_rtc_memory && address >= RTC_DATA_LOW && address < RTC_DATA_HIGH) {
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if (!load_rtc_memory && address >= SOC_RTC_DATA_LOW && address < SOC_RTC_DATA_HIGH) {
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ESP_LOGD(TAG, "Skipping RTC data segment at %08x\n", data_offs);
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ESP_LOGD(TAG, "Skipping RTC data segment at %08x\n", data_offs);
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load = false;
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load = false;
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}
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}
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@ -108,16 +108,6 @@ esp_err_t esp_image_basic_verify(uint32_t src_addr, bool log_errors, uint32_t *p
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*p_length = 0;
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*p_length = 0;
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}
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}
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if (src_addr % SPI_FLASH_MMU_PAGE_SIZE != 0) {
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/* Image must start on a 64KB boundary
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(This is not a technical limitation, only the flash mapped regions need to be 64KB aligned. But the most
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consistent way to do this is to have all the offsets internal to the image correctly 64KB aligned, and then
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start the image on a 64KB boundary also.)
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*/
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return ESP_ERR_INVALID_ARG;
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}
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err = esp_image_load_header(src_addr, log_errors, &image_header);
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err = esp_image_load_header(src_addr, log_errors, &image_header);
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if (err != ESP_OK) {
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if (err != ESP_OK) {
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return err;
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return err;
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@ -133,6 +123,21 @@ esp_err_t esp_image_basic_verify(uint32_t src_addr, bool log_errors, uint32_t *p
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return err;
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return err;
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}
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}
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uint32_t load_addr = segment_header.load_addr;
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bool map_segment = (load_addr >= SOC_DROM_LOW && load_addr < SOC_DROM_HIGH)
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|| (load_addr >= SOC_IROM_LOW && load_addr < SOC_IROM_HIGH);
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/* Check that flash cache mapped segment aligns correctly from flash it's mapped address,
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relative to the 64KB page mapping size.
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*/
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ESP_LOGV(TAG, "segment %d map_segment %d segment_data_offs 0x%x load_addr 0x%x",
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i, map_segment, segment_data_offs, load_addr);
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if (map_segment && ((segment_data_offs % SPI_FLASH_MMU_PAGE_SIZE) != (load_addr % SPI_FLASH_MMU_PAGE_SIZE))) {
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ESP_LOGE(TAG, "Segment %d has load address 0x%08x, conflict with segment data at 0x%08x",
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i, load_addr, segment_data_offs);
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}
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for (int i = 0; i < segment_header.data_len; i += sizeof(buf)) {
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for (int i = 0; i < segment_header.data_len; i += sizeof(buf)) {
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err = bootloader_flash_read(segment_data_offs + i, buf, sizeof(buf), true);
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err = bootloader_flash_read(segment_data_offs + i, buf, sizeof(buf), true);
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if (err != ESP_OK) {
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if (err != ESP_OK) {
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4
components/bootloader_support/test/component.mk
Normal file
4
components/bootloader_support/test/component.mk
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@ -0,0 +1,4 @@
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#
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#Component Makefile
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#
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COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive
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37
components/bootloader_support/test/test_verify_image.c
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37
components/bootloader_support/test/test_verify_image.c
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@ -0,0 +1,37 @@
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/*
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* Tests for bootloader_support esp_image_basic_verify()
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*/
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#include <esp_types.h>
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#include <stdio.h>
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#include "rom/ets_sys.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/queue.h"
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#include "freertos/xtensa_api.h"
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#include "unity.h"
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#include "esp_partition.h"
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#include "esp_ota_ops.h"
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#include "esp_image_format.h"
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TEST_CASE("Verify bootloader image in flash", "[bootloader_support]")
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{
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uint32_t image_len = 0;
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TEST_ASSERT_EQUAL_HEX(ESP_OK, esp_image_basic_verify(0x1000, true, &image_len));
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TEST_ASSERT_NOT_EQUAL(0, image_len);
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}
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TEST_CASE("Verify unit test app image", "[bootloader_support]")
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{
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uint32_t image_len = 0;
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const esp_partition_t *running = esp_ota_get_running_partition();
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TEST_ASSERT_NOT_EQUAL(NULL, running);
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TEST_ASSERT_EQUAL_HEX(ESP_OK, esp_image_basic_verify(running->address, true, &image_len));
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TEST_ASSERT_NOT_EQUAL(0, image_len);
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TEST_ASSERT_TRUE(image_len <= running->size);
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}
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@ -149,6 +149,16 @@
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#define TICKS_PER_US_ROM 26 // CPU is 80MHz
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#define TICKS_PER_US_ROM 26 // CPU is 80MHz
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//}}
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//}}
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/* Overall memory map */
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#define SOC_IROM_LOW 0x400D0000
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#define SOC_IROM_HIGH 0x40400000
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#define SOC_DROM_LOW 0x3F400000
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#define SOC_DROM_HIGH 0x3F800000
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#define SOC_RTC_IRAM_LOW 0x400C0000
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#define SOC_RTC_IRAM_HIGH 0x400C2000
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#define SOC_RTC_DATA_LOW 0x50000000
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#define SOC_RTC_DATA_HIGH 0x50002000
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#define DR_REG_DPORT_BASE 0x3ff00000
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#define DR_REG_DPORT_BASE 0x3ff00000
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#define DR_REG_RSA_BASE 0x3ff02000
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#define DR_REG_RSA_BASE 0x3ff02000
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#define DR_REG_SHA_BASE 0x3ff03000
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#define DR_REG_SHA_BASE 0x3ff03000
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