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RISC-V: Fix vectors.S assembly file indentation and macro usage
The file is now more consistent as the macros have been fixed, more comments have been added and the indentation is now using spaces only.
This commit is contained in:
Omar Chebib
Alexey Gerenkov
parent
dfd3a9c3bc
commit
e1d3993309
@ -18,10 +18,10 @@
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#include "sdkconfig.h"
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.equ SAVE_REGS, 32
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.equ CONTEXT_SIZE, (SAVE_REGS * 4)
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.equ panic_from_exception, xt_unhandled_exception
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.equ panic_from_isr, panicHandler
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.equ SAVE_REGS, 32
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.equ CONTEXT_SIZE, (SAVE_REGS * 4)
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.equ panic_from_exception, xt_unhandled_exception
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.equ panic_from_isr, panicHandler
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/* Macro which first allocates space on the stack to save general
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* purpose registers, and then save them. GP register is excluded.
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@ -61,8 +61,8 @@
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.endm
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.macro save_mepc
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csrr t0, mepc
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sw t0, RV_STK_MEPC(sp)
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csrr t0, mepc
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sw t0, RV_STK_MEPC(sp)
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.endm
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/* Restore the general purpose registers (excluding gp) from the context on
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@ -102,51 +102,51 @@
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.endm
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.macro restore_mepc
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lw t0, RV_STK_MEPC(sp)
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csrw mepc, t0
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lw t0, RV_STK_MEPC(sp)
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csrw mepc, t0
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.endm
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.global rtos_int_enter
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.global rtos_int_exit
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.global _global_interrupt_handler
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.global rtos_int_enter
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.global rtos_int_exit
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.global _global_interrupt_handler
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.section .exception_vectors.text
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/* This is the vector table. MTVEC points here.
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*
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* Use 4-byte intructions here. 1 instruction = 1 entry of the table.
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* The CPU jumps to MTVEC (i.e. the first entry) in case of an exception,
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* and (MTVEC & 0xfffffffc) + (mcause & 0x7fffffff) * 4, in case of an interrupt.
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*
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* Note: for our CPU, we need to place this on a 256-byte boundary, as CPU
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* only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00).
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*/
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.section .exception_vectors.text
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/* This is the vector table. MTVEC points here.
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*
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* Use 4-byte intructions here. 1 instruction = 1 entry of the table.
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* The CPU jumps to MTVEC (i.e. the first entry) in case of an exception,
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* and (MTVEC & 0xfffffffc) + (mcause & 0x7fffffff) * 4, in case of an interrupt.
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*
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* Note: for our CPU, we need to place this on a 256-byte boundary, as CPU
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* only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00).
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*/
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.balign 0x100
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.global _vector_table
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.type _vector_table, @function
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.balign 0x100
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.global _vector_table
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.type _vector_table, @function
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_vector_table:
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.option push
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.option norvc
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j _panic_handler /* exception handler, entry 0 */
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.rept (ETS_T1_WDT_INUM - 1)
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j _interrupt_handler /* 24 identical entries, all pointing to the interrupt handler */
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.endr
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j _panic_handler /* Call panic handler for ETS_T1_WDT_INUM interrupt (soc-level panic)*/
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.option push
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.option norvc
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j _panic_handler /* exception handler, entry 0 */
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.rept (ETS_T1_WDT_INUM - 1)
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j _interrupt_handler /* 24 identical entries, all pointing to the interrupt handler */
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.endr
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j _panic_handler /* Call panic handler for ETS_T1_WDT_INUM interrupt (soc-level panic)*/
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j _panic_handler /* Call panic handler for ETS_CACHEERR_INUM interrupt (soc-level panic)*/
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#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
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j _panic_handler /* Call panic handler for ETS_MEMPROT_ERR_INUM interrupt (soc-level panic)*/
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.rept (ETS_MAX_INUM - ETS_MEMPROT_ERR_INUM)
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#else
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.rept (ETS_MAX_INUM - ETS_CACHEERR_INUM)
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#endif
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j _interrupt_handler /* 6 identical entries, all pointing to the interrupt handler */
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.endr
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.rept (ETS_MAX_INUM - ETS_MEMPROT_ERR_INUM)
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#else
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.rept (ETS_MAX_INUM - ETS_CACHEERR_INUM)
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#endif //CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
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j _interrupt_handler /* 6 identical entries, all pointing to the interrupt handler */
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.endr
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.option pop
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.size _vector_table, .-_vector_table
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.option pop
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.size _vector_table, .-_vector_table
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/* Exception handler.*/
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.type _panic_handler, @function
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/* Exception handler.*/
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.type _panic_handler, @function
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_panic_handler:
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/* Allocate space on the stack and store general purpose registers */
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save_general_regs RV_STK_FRMSZ
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@ -154,44 +154,44 @@ _panic_handler:
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/* As gp register is not saved by the macro, save it here */
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sw gp, RV_STK_GP(sp)
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/* Same goes for the SP value before trapping */
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addi t0, sp, RV_STK_FRMSZ /* restore sp with the value when trap happened */
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sw t0, RV_STK_SP(sp)
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/* Same goes for the SP value before trapping */
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addi t0, sp, RV_STK_FRMSZ /* restore sp with the value when trap happened */
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/* Save CSRs */
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csrr t0, mepc
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sw t0, RV_STK_MEPC(sp)
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csrr t0, mstatus
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sw t0, RV_STK_MSTATUS(sp)
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csrr t0, mtvec
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sw t0, RV_STK_MTVEC(sp)
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csrr t0, mtval
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sw t0, RV_STK_MTVAL(sp)
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csrr t0, mhartid
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sw t0, RV_STK_MHARTID(sp)
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/* Save CSRs */
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sw t0, RV_STK_SP(sp)
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csrr t0, mepc
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sw t0, RV_STK_MEPC(sp)
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csrr t0, mstatus
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sw t0, RV_STK_MSTATUS(sp)
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csrr t0, mtvec
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sw t0, RV_STK_MTVEC(sp)
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csrr t0, mtval
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sw t0, RV_STK_MTVAL(sp)
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csrr t0, mhartid
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sw t0, RV_STK_MHARTID(sp)
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/* Call panic_from_exception(sp) or panic_from_isr(sp)
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* depending on whether we have a pseudo excause or not.
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* If mcause's highest bit is 1, then an interrupt called this routine,
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* so we have a pseudo excause. Else, it is due to a exception, we don't
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* have an pseudo excause */
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mv a0, sp
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csrr a1, mcause
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/* Branches instructions don't accept immediates values, so use t1 to
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* store our comparator */
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li t0, 0x80000000
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bgeu a1, t0, _call_panic_handler
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sw a1, RV_STK_MCAUSE(sp)
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/* Call panic_from_exception(sp) or panic_from_isr(sp)
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* depending on whether we have a pseudo excause or not.
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* If mcause's highest bit is 1, then an interrupt called this routine,
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* so we have a pseudo excause. Else, it is due to a exception, we don't
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* have an pseudo excause */
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mv a0, sp
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csrr a1, mcause
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/* Branches instructions don't accept immediates values, so use t1 to
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* store our comparator */
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li t0, 0x80000000
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bgeu a1, t0, _call_panic_handler
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sw a1, RV_STK_MCAUSE(sp)
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jal panic_from_exception
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/* We arrive here if the exception handler has returned. */
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j _return_from_exception
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_call_panic_handler:
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/* Remove highest bit from mcause (a1) register and save it in the
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* structure */
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not t0, t0
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and a1, a1, t0
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sw a1, RV_STK_MCAUSE(sp)
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/* Remove highest bit from mcause (a1) register and save it in the
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* structure */
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not t0, t0
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and a1, a1, t0
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sw a1, RV_STK_MCAUSE(sp)
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jal panic_from_isr
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/* We arrive here if the exception handler has returned. This means that
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@ -208,18 +208,19 @@ _return_from_exception:
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mret
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.size _panic_handler, .-_panic_handler
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/* This is the interrupt handler.
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* It saves the registers on the stack,
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* prepares for interrupt nesting,
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* re-enables the interrupts,
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* then jumps to the C dispatcher in interrupt.c.
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*/
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.global _interrupt_handler
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.type _interrupt_handler, @function
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/* This is the interrupt handler.
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* It saves the registers on the stack,
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* prepares for interrupt nesting,
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* re-enables the interrupts,
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* then jumps to the C dispatcher in interrupt.c.
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*/
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.global _interrupt_handler
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.type _interrupt_handler, @function
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_interrupt_handler:
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/* entry */
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save_general_regs
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save_mepc
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/* Start by saving the general purpose registers and the PC value before
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* the interrupt happened. */
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save_general_regs
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save_mepc
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/* Though it is not necessary we save GP and SP here.
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* SP is necessary to help GDB to properly unwind
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@ -232,80 +233,84 @@ _interrupt_handler:
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/* Save SP */
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sw t0, RV_STK_SP(sp)
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/* Before doing anythig preserve the stack pointer */
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/* It will be saved in current TCB, if needed */
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mv a0, sp
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call rtos_int_enter
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/* Before doing anythig preserve the stack pointer */
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/* It will be saved in current TCB, if needed */
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mv a0, sp
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call rtos_int_enter
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/* If this is a non-nested interrupt, SP now points to the interrupt stack */
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/* Before dispatch c handler, restore interrupt to enable nested intr */
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csrr s1, mcause
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csrr s2, mstatus
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/* Before dispatch c handler, restore interrupt to enable nested intr */
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csrr s1, mcause
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csrr s2, mstatus
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/* Save the interrupt threshold level */
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la t0, INTERRUPT_CORE0_CPU_INT_THRESH_REG
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lw s3, 0(t0)
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/* Save the interrupt threshold level */
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la t0, INTERRUPT_CORE0_CPU_INT_THRESH_REG
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lw s3, 0(t0)
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/* Increase interrupt threshold level */
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li t2, 0x7fffffff
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and t1, s1, t2 /* t1 = mcause & mask */
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slli t1, t1, 2 /* t1 = mcause * 4 */
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la t2, INTC_INT_PRIO_REG(0)
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add t1, t2, t1 /* t1 = INTC_INT_PRIO_REG + 4 * mcause */
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lw t2, 0(t1) /* t2 = INTC_INT_PRIO_REG[mcause] */
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addi t2, t2, 1 /* t2 = t2 +1 */
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sw t2, 0(t0) /* INTERRUPT_CORE0_CPU_INT_THRESH_REG = t2 */
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fence
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/* Increase interrupt threshold level */
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li t2, 0x7fffffff
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and t1, s1, t2 /* t1 = mcause & mask */
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slli t1, t1, 2 /* t1 = mcause * 4 */
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la t2, INTC_INT_PRIO_REG(0)
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add t1, t2, t1 /* t1 = INTC_INT_PRIO_REG + 4 * mcause */
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lw t2, 0(t1) /* t2 = INTC_INT_PRIO_REG[mcause] */
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addi t2, t2, 1 /* t2 = t2 +1 */
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sw t2, 0(t0) /* INTERRUPT_CORE0_CPU_INT_THRESH_REG = t2 */
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fence
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li t0, 0x8
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csrrs t0, mstatus, t0
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li t0, 0x8
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csrrs t0, mstatus, t0
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/* MIE set. Nested interrupts can now occur */
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#ifdef CONFIG_PM_TRACE
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li a0, 0 /* = ESP_PM_TRACE_IDLE */
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#if SOC_CPU_CORES_NUM == 1
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li a1, 0 /* No need to check core ID on single core hardware */
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#else
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csrr a1, mhartid
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#endif
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la t0, esp_pm_trace_exit
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jalr t0 /* absolute jump, avoid the 1 MiB range constraint */
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#endif
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#ifdef CONFIG_PM_TRACE
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li a0, 0 /* = ESP_PM_TRACE_IDLE */
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#if SOC_CPU_CORES_NUM == 1
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li a1, 0 /* No need to check core ID on single core hardware */
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#else
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csrr a1, mhartid
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#endif
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la t0, esp_pm_trace_exit
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jalr t0 /* absolute jump, avoid the 1 MiB range constraint */
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#endif
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#ifdef CONFIG_PM_ENABLE
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la t0, esp_pm_impl_isr_hook
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jalr t0 /* absolute jump, avoid the 1 MiB range constraint */
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#endif
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#ifdef CONFIG_PM_ENABLE
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la t0, esp_pm_impl_isr_hook
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jalr t0 /* absolute jump, avoid the 1 MiB range constraint */
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#endif
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/* call the C dispatcher */
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mv a0, sp /* argument 1, stack pointer */
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mv a1, s1 /* argument 2, interrupt number (mcause) */
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/* mask off the interrupt flag of mcause */
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li t0, 0x7fffffff
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and a1, a1, t0
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jal _global_interrupt_handler
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/* call the C dispatcher */
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mv a0, sp /* argument 1, stack pointer */
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mv a1, s1 /* argument 2, interrupt number (mcause) */
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/* mask off the interrupt flag of mcause */
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li t0, 0x7fffffff
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and a1, a1, t0
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jal _global_interrupt_handler
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/* After dispatch c handler, disable interrupt to make freertos make context switch */
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/* After dispatch c handler, disable interrupt to make freertos make context switch */
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li t0, 0x8
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csrrc t0, mstatus, t0
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li t0, 0x8
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csrrc t0, mstatus, t0
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/* MIE cleared. Nested interrupts are disabled */
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/* restore the interrupt threshold level */
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la t0, INTERRUPT_CORE0_CPU_INT_THRESH_REG
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sw s3, 0(t0)
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fence
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/* restore the interrupt threshold level */
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la t0, INTERRUPT_CORE0_CPU_INT_THRESH_REG
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sw s3, 0(t0)
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fence
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/* Yield to the next task is needed: */
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mv a0, sp
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call rtos_int_exit
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/* Yield to the next task is needed: */
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mv a0, sp
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call rtos_int_exit
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/* If this is a non-nested interrupt, context switch called, SP now points to back to task stack. */
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/* The next (or current) stack pointer is returned in a0 */
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mv sp, a0
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/* The next (or current) stack pointer is returned in a0 */
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mv sp, a0
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/* restore the rest of the registers */
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csrw mcause, s1
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csrw mstatus, s2
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restore_mepc
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restore_general_regs
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/* restore the rest of the registers */
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csrw mcause, s1
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csrw mstatus, s2
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restore_mepc
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restore_general_regs
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/* exit, this will also re-enable the interrupts */
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mret
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.size _interrupt_handler, .-_interrupt_handler
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/* exit, this will also re-enable the interrupts */
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mret
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.size _interrupt_handler, .-_interrupt_handler
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