From 458b14a8eadc7914a39d2246b571d963d1f4de48 Mon Sep 17 00:00:00 2001 From: morris Date: Mon, 13 Jul 2020 21:57:24 +0800 Subject: [PATCH] esp_rom: extract common efuse apis into esp_rom_efuse.h --- .../include/esp_secure_boot.h | 11 ++- .../src/bootloader_flash_config_esp32.c | 6 +- .../src/bootloader_flash_config_esp32s2.c | 1 - .../src/bootloader_utility.c | 2 - .../src/esp32/bootloader_esp32.c | 10 +-- .../src/esp32s2/bootloader_esp32s2.c | 10 +-- .../src/esp32s2/secure_boot.c | 4 +- .../bootloader_support/src/flash_qio_mode.c | 11 ++- components/efuse/src/esp32/esp_efuse_fields.c | 1 - .../efuse/src/esp32s2/esp_efuse_fields.c | 1 - components/efuse/src/esp_efuse_fields.c | 6 -- components/efuse/test/test_efuse.c | 4 +- components/esp32/spiram_psram.c | 7 +- components/esp32/system_api_esp32.c | 1 - components/esp32s2/spiram_psram.c | 7 +- components/esp32s2/test/test_ds.c | 4 -- components/esp32s2/test/test_hmac.c | 4 -- components/esp_common/src/mac_addr.c | 11 +-- components/esp_rom/esp32/ld/esp32.rom.api.ld | 4 ++ .../esp_rom/esp32s2/ld/esp32s2.rom.api.ld | 5 ++ .../esp_rom/esp32s3/ld/esp32s3.rom.api.ld | 5 ++ components/esp_rom/include/esp_rom_efuse.h | 68 +++++++++++++++++++ components/esp_system/port/cpu_start.c | 5 +- components/spi_flash/esp_flash_spi_init.c | 4 +- 24 files changed, 124 insertions(+), 68 deletions(-) create mode 100644 components/esp_rom/include/esp_rom_efuse.h diff --git a/components/bootloader_support/include/esp_secure_boot.h b/components/bootloader_support/include/esp_secure_boot.h index 551a737050..f15c240d33 100644 --- a/components/bootloader_support/include/esp_secure_boot.h +++ b/components/bootloader_support/include/esp_secure_boot.h @@ -17,11 +17,10 @@ #include #include "soc/efuse_periph.h" #include "esp_image_format.h" - +#include "esp_rom_efuse.h" #include "sdkconfig.h" -#if CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/efuse.h" -#else + +#if CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/secure_boot.h" #endif @@ -57,8 +56,8 @@ static inline bool esp_secure_boot_enabled(void) #elif CONFIG_SECURE_BOOT_V2_ENABLED return ets_use_secure_boot_v2(); #endif -#elif CONFIG_IDF_TARGET_ESP32S2 - return ets_efuse_secure_boot_enabled(); +#else + return esp_rom_efuse_is_secure_boot_enabled(); #endif return false; /* Secure Boot not enabled in menuconfig */ } diff --git a/components/bootloader_support/src/bootloader_flash_config_esp32.c b/components/bootloader_support/src/bootloader_flash_config_esp32.c index 96bd856ccf..5fb25c7c8a 100644 --- a/components/bootloader_support/src/bootloader_flash_config_esp32.c +++ b/components/bootloader_support/src/bootloader_flash_config_esp32.c @@ -18,8 +18,8 @@ #include "esp_err.h" #include "esp_log.h" #include "esp_rom_gpio.h" +#include "esp_rom_efuse.h" #include "esp32/rom/spi_flash.h" -#include "esp32/rom/efuse.h" #include "soc/gpio_periph.h" #include "soc/efuse_reg.h" #include "soc/spi_reg.h" @@ -91,8 +91,8 @@ void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr) PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S); } else { - const uint32_t spiconfig = ets_efuse_get_spiconfig(); - if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) { + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) { esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_CS, SPICS0_OUT_IDX, 0, 0); esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_OUT_IDX, 0, 0); esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_IN_IDX, 0); diff --git a/components/bootloader_support/src/bootloader_flash_config_esp32s2.c b/components/bootloader_support/src/bootloader_flash_config_esp32s2.c index 98c60102e4..1edc4a957b 100644 --- a/components/bootloader_support/src/bootloader_flash_config_esp32s2.c +++ b/components/bootloader_support/src/bootloader_flash_config_esp32s2.c @@ -18,7 +18,6 @@ #include "esp_err.h" #include "esp_log.h" #include "esp32s2/rom/spi_flash.h" -#include "esp32s2/rom/efuse.h" #include "soc/efuse_reg.h" #include "soc/spi_reg.h" #include "soc/spi_mem_reg.h" diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c index fee195857d..10b26d9482 100644 --- a/components/bootloader_support/src/bootloader_utility.c +++ b/components/bootloader_support/src/bootloader_utility.c @@ -21,7 +21,6 @@ #if CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/cache.h" -#include "esp32/rom/efuse.h" #include "esp32/rom/ets_sys.h" #include "esp32/rom/spi_flash.h" #include "esp32/rom/rtc.h" @@ -29,7 +28,6 @@ #include "esp32/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/cache.h" -#include "esp32s2/rom/efuse.h" #include "esp32s2/rom/ets_sys.h" #include "esp32s2/rom/spi_flash.h" #include "esp32s2/rom/rtc.h" diff --git a/components/bootloader_support/src/esp32/bootloader_esp32.c b/components/bootloader_support/src/esp32/bootloader_esp32.c index f99e951c33..c7e580e3a9 100644 --- a/components/bootloader_support/src/esp32/bootloader_esp32.c +++ b/components/bootloader_support/src/esp32/bootloader_esp32.c @@ -35,9 +35,9 @@ #include "soc/spi_periph.h" #include "esp32/rom/cache.h" -#include "esp32/rom/efuse.h" #include "esp32/rom/ets_sys.h" #include "esp_rom_gpio.h" +#include "esp_rom_efuse.h" #include "esp32/rom/spi_flash.h" #include "esp32/rom/rtc.h" #include "esp32/rom/uart.h" @@ -72,8 +72,8 @@ void bootloader_configure_spi_pins(int drv) PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S); } else { - const uint32_t spiconfig = ets_efuse_get_spiconfig(); - if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) { + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) { esp_rom_gpio_connect_out_signal(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0); esp_rom_gpio_connect_out_signal(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0); esp_rom_gpio_connect_in_signal(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0); @@ -260,8 +260,8 @@ static esp_err_t bootloader_init_spi_flash(void) { bootloader_init_flash_configure(); #ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH - const uint32_t spiconfig = ets_efuse_get_spiconfig(); - if (spiconfig != EFUSE_SPICONFIG_SPI_DEFAULTS && spiconfig != EFUSE_SPICONFIG_HSPI_DEFAULTS) { + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) { ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig"); return ESP_FAIL; } diff --git a/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c b/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c index 76ea6a9415..e4d5e499d2 100644 --- a/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c +++ b/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c @@ -18,8 +18,8 @@ #include "soc/gpio_periph.h" #include "soc/gpio_sig_map.h" #include "soc/io_mux_reg.h" -#include "esp32s2/rom/efuse.h" #include "esp_rom_gpio.h" +#include "esp_rom_efuse.h" #include "esp32s2/rom/spi_flash.h" #include "bootloader_init.h" @@ -48,8 +48,8 @@ static const char *TAG = "boot.esp32s2"; void bootloader_configure_spi_pins(int drv) { - const uint32_t spiconfig = ets_efuse_get_spiconfig(); - uint8_t wp_pin = ets_efuse_get_wp_pad(); + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio(); uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; uint8_t q_gpio_num = SPI_Q_GPIO_NUM; uint8_t d_gpio_num = SPI_D_GPIO_NUM; @@ -199,8 +199,8 @@ static esp_err_t bootloader_init_spi_flash(void) { bootloader_init_flash_configure(); #ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH - const uint32_t spiconfig = ets_efuse_get_spiconfig(); - if (spiconfig != EFUSE_SPICONFIG_SPI_DEFAULTS && spiconfig != EFUSE_SPICONFIG_HSPI_DEFAULTS) { + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) { ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig"); return ESP_FAIL; } diff --git a/components/bootloader_support/src/esp32s2/secure_boot.c b/components/bootloader_support/src/esp32s2/secure_boot.c index 4deb5d1728..11ba0e2e94 100644 --- a/components/bootloader_support/src/esp32s2/secure_boot.c +++ b/components/bootloader_support/src/esp32s2/secure_boot.c @@ -21,7 +21,7 @@ esp_err_t esp_secure_boot_permanently_enable(void) { uint8_t hash[32]; - if (ets_efuse_secure_boot_enabled()) + if (esp_rom_efuse_is_secure_boot_enabled()) { ESP_LOGI(TAG, "secure boot is already enabled, continuing.."); return ESP_OK; @@ -45,7 +45,7 @@ esp_err_t esp_secure_boot_permanently_enable(void) esp_err_t err = esp_efuse_batch_write_commit(); if (err == ESP_OK) { - assert(ets_efuse_secure_boot_enabled()); + assert(esp_rom_efuse_is_secure_boot_enabled()); ESP_LOGI(TAG, "Secure boot permanently enabled"); } diff --git a/components/bootloader_support/src/flash_qio_mode.c b/components/bootloader_support/src/flash_qio_mode.c index 94da524f9c..abf71481d3 100644 --- a/components/bootloader_support/src/flash_qio_mode.c +++ b/components/bootloader_support/src/flash_qio_mode.c @@ -16,12 +16,11 @@ #include "flash_qio_mode.h" #include "esp_log.h" #include "esp_err.h" +#include "esp_rom_efuse.h" #if CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/spi_flash.h" -#include "esp32/rom/efuse.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/spi_flash.h" -#include "esp32s2/rom/efuse.h" #include "soc/spi_mem_struct.h" #endif #include "soc/spi_struct.h" @@ -222,10 +221,10 @@ static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn, uint8_t status_qio_bit) { uint32_t status; - const uint32_t spiconfig = ets_efuse_get_spiconfig(); + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); #if CONFIG_IDF_TARGET_ESP32 - if (spiconfig != EFUSE_SPICONFIG_SPI_DEFAULTS && spiconfig != EFUSE_SPICONFIG_HSPI_DEFAULTS) { + if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) { // spiconfig specifies a custom efuse pin configuration. This config defines all pins -except- WP, // which is compiled into the bootloader instead. // @@ -278,8 +277,8 @@ static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn, #if CONFIG_IDF_TARGET_ESP32 esp_rom_spiflash_select_qio_pins(CONFIG_BOOTLOADER_SPI_WP_PIN, spiconfig); #elif CONFIG_IDF_TARGET_ESP32S2 - if (ets_efuse_get_wp_pad() <= MAX_PAD_GPIO_NUM) { - esp_rom_spiflash_select_qio_pins(ets_efuse_get_wp_pad(), spiconfig); + if (esp_rom_efuse_get_flash_wp_gpio() <= MAX_PAD_GPIO_NUM) { + esp_rom_spiflash_select_qio_pins(esp_rom_efuse_get_flash_wp_gpio(), spiconfig); } else { esp_rom_spiflash_select_qio_pins(CONFIG_BOOTLOADER_SPI_WP_PIN, spiconfig); } diff --git a/components/efuse/src/esp32/esp_efuse_fields.c b/components/efuse/src/esp32/esp_efuse_fields.c index dd665b219f..9049f23dca 100644 --- a/components/efuse/src/esp32/esp_efuse_fields.c +++ b/components/efuse/src/esp32/esp_efuse_fields.c @@ -17,7 +17,6 @@ #include "esp_efuse_table.h" #include "stdlib.h" #include "esp_types.h" -#include "esp32/rom/efuse.h" #include "assert.h" #include "esp_err.h" #include "esp_log.h" diff --git a/components/efuse/src/esp32s2/esp_efuse_fields.c b/components/efuse/src/esp32s2/esp_efuse_fields.c index ab53343308..d2af212d64 100644 --- a/components/efuse/src/esp32s2/esp_efuse_fields.c +++ b/components/efuse/src/esp32s2/esp_efuse_fields.c @@ -17,7 +17,6 @@ #include "esp_efuse_table.h" #include "stdlib.h" #include "esp_types.h" -#include "esp32s2/rom/efuse.h" #include "assert.h" #include "esp_err.h" #include "esp_log.h" diff --git a/components/efuse/src/esp_efuse_fields.c b/components/efuse/src/esp_efuse_fields.c index d3a07bef9f..54d577a0ed 100644 --- a/components/efuse/src/esp_efuse_fields.c +++ b/components/efuse/src/esp_efuse_fields.c @@ -26,12 +26,6 @@ #include "soc/apb_ctrl_reg.h" #include "sys/param.h" -#if CONFIG_IDF_TARGET_ESP32 -#include "esp32/rom/efuse.h" -#elif CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/efuse.h" -#endif - static __attribute__((unused)) const char *TAG = "efuse"; // Permanently update values written to the efuse write registers void esp_efuse_burn_new_values(void) diff --git a/components/efuse/test/test_efuse.c b/components/efuse/test/test_efuse.c index 0d9e095855..a72eb9e0c1 100644 --- a/components/efuse/test/test_efuse.c +++ b/components/efuse/test/test_efuse.c @@ -10,13 +10,13 @@ #include "esp_efuse_table.h" #include "esp_efuse_utility.h" #include "esp_efuse_test_table.h" -#include "esp32/rom/efuse.h" #include "bootloader_random.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/semphr.h" #include "test_utils.h" #include "sdkconfig.h" +#include "esp_rom_efuse.h" static const char* TAG = "efuse_test"; @@ -37,7 +37,7 @@ static void test_read_blob(void) ESP_LOGI(TAG, "2. Check CRC by MAC"); uint8_t crc; TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_MAC_FACTORY_CRC, &crc, 8)); - TEST_ASSERT_EQUAL_HEX8(crc, esp_crc8(mac, sizeof(mac))); + TEST_ASSERT_EQUAL_HEX8(crc, esp_rom_efuse_mac_address_crc8(mac, sizeof(mac))); #endif // CONFIG_IDF_TARGET_ESP32 ESP_LOGI(TAG, "3. Test check args"); diff --git a/components/esp32/spiram_psram.c b/components/esp32/spiram_psram.c index f2f90ecfeb..57c9a9f727 100644 --- a/components/esp32/spiram_psram.c +++ b/components/esp32/spiram_psram.c @@ -27,6 +27,7 @@ #include "esp32/rom/spi_flash.h" #include "esp32/rom/cache.h" #include "esp32/rom/efuse.h" +#include "esp_rom_efuse.h" #include "soc/dport_reg.h" #include "soc/efuse_periph.h" #include "soc/spi_caps.h" @@ -829,15 +830,15 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad abort(); } - const uint32_t spiconfig = ets_efuse_get_spiconfig(); - if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) { + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) { psram_io.flash_clk_io = SPI_IOMUX_PIN_NUM_CLK; psram_io.flash_cs_io = SPI_IOMUX_PIN_NUM_CS; psram_io.psram_spiq_sd0_io = PSRAM_SPIQ_SD0_IO; psram_io.psram_spid_sd1_io = PSRAM_SPID_SD1_IO; psram_io.psram_spiwp_sd3_io = PSRAM_SPIWP_SD3_IO; psram_io.psram_spihd_sd2_io = PSRAM_SPIHD_SD2_IO; - } else if (spiconfig == EFUSE_SPICONFIG_HSPI_DEFAULTS) { + } else if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) { psram_io.flash_clk_io = FLASH_HSPI_CLK_IO; psram_io.flash_cs_io = FLASH_HSPI_CS_IO; psram_io.psram_spiq_sd0_io = PSRAM_HSPI_SPIQ_SD0_IO; diff --git a/components/esp32/system_api_esp32.c b/components/esp32/system_api_esp32.c index 66bf18f96f..f6bc93fef2 100644 --- a/components/esp32/system_api_esp32.c +++ b/components/esp32/system_api_esp32.c @@ -20,7 +20,6 @@ #include "esp_wifi.h" #include "esp_log.h" #include "sdkconfig.h" -#include "esp32/rom/efuse.h" #include "esp32/rom/cache.h" #include "esp32/rom/uart.h" #include "soc/dport_reg.h" diff --git a/components/esp32s2/spiram_psram.c b/components/esp32s2/spiram_psram.c index b4dc8fb43a..6a91cbffbb 100644 --- a/components/esp32s2/spiram_psram.c +++ b/components/esp32s2/spiram_psram.c @@ -29,6 +29,7 @@ #include "esp32s2/rom/opi_flash.h" #include "esp32s2/rom/cache.h" #include "esp32s2/rom/efuse.h" +#include "esp_rom_efuse.h" #include "soc/dport_reg.h" #include "soc/efuse_periph.h" #include "soc/spi_caps.h" @@ -362,8 +363,8 @@ static void psram_set_spi0_cache_cs_timing(psram_clk_mode_t clk_mode) static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode) { psram_io_t psram_io = PSRAM_IO_CONF_DEFAULT(); - const uint32_t spiconfig = ets_efuse_get_spiconfig(); - if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) { + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) { /* FLASH pins(except wp / hd) are all configured via IO_MUX in rom. */ } else { // FLASH pins are all configured via GPIO matrix in ROM. @@ -372,7 +373,7 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode) psram_io.psram_spiq_sd0_io = EFUSE_SPICONFIG_RET_SPIQ(spiconfig); psram_io.psram_spid_sd1_io = EFUSE_SPICONFIG_RET_SPID(spiconfig); psram_io.psram_spihd_sd2_io = EFUSE_SPICONFIG_RET_SPIHD(spiconfig); - psram_io.psram_spiwp_sd3_io = ets_efuse_get_wp_pad(); + psram_io.psram_spiwp_sd3_io = esp_rom_efuse_get_flash_wp_gpio(); } #if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_FLASHMODE_QOUT diff --git a/components/esp32s2/test/test_ds.c b/components/esp32s2/test/test_ds.c index 2ff1430430..719f24adb6 100644 --- a/components/esp32s2/test/test_ds.c +++ b/components/esp32s2/test/test_ds.c @@ -21,8 +21,6 @@ #include "esp_ds.h" -#if CONFIG_IDF_TARGET_ESP32S2 - #define NUM_RESULTS 10 typedef struct { @@ -379,5 +377,3 @@ TEST_CASE("Digital Signature Invalid Data (FPGA only)", "[hw_crypto]") } #endif // CONFIG_IDF_ENV_FPGA - -#endif // CONFIG_IDF_TARGET_ESP32S2 diff --git a/components/esp32s2/test/test_hmac.c b/components/esp32s2/test/test_hmac.c index 45fc67feea..96861996f5 100644 --- a/components/esp32s2/test/test_hmac.c +++ b/components/esp32s2/test/test_hmac.c @@ -17,8 +17,6 @@ #if CONFIG_IDF_ENV_FPGA -#if CONFIG_IDF_TARGET_ESP32S2 - #include "esp32s2/rom/efuse.h" /* Allow testing varying message lengths (truncating the same message) @@ -972,6 +970,4 @@ TEST_CASE("HMAC key out of range", "[hw_crypto]") TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_hmac_calculate(HMAC_KEY5 + 1, message, 47, hmac)); } -#endif // CONFIG_IDF_TARGET_ESP32S2 - #endif // CONFIG_IDF_ENV_FPGA diff --git a/components/esp_common/src/mac_addr.c b/components/esp_common/src/mac_addr.c index 2bbd5de523..f54c955843 100644 --- a/components/esp_common/src/mac_addr.c +++ b/components/esp_common/src/mac_addr.c @@ -13,16 +13,11 @@ // limitations under the License. #include #include "sdkconfig.h" +#include "esp_rom_efuse.h" #include "esp_system.h" #include "esp_efuse.h" #include "esp_efuse_table.h" -#ifdef CONFIG_IDF_TARGET_ESP32 -#include "esp32/rom/efuse.h" -#elif CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/efuse.h" -#endif - /* esp_system.h APIs relating to MAC addresses */ static const char* TAG = "system_api"; @@ -74,7 +69,7 @@ esp_err_t esp_efuse_mac_get_custom(uint8_t *mac) uint8_t efuse_crc; esp_efuse_read_field_blob(ESP_EFUSE_MAC_CUSTOM, mac, 48); esp_efuse_read_field_blob(ESP_EFUSE_MAC_CUSTOM_CRC, &efuse_crc, 8); - uint8_t calc_crc = esp_crc8(mac, 6); + uint8_t calc_crc = esp_rom_efuse_mac_address_crc8(mac, 6); if (efuse_crc != calc_crc) { ESP_LOGE(TAG, "Base MAC address from BLK3 of EFUSE CRC error, efuse_crc = 0x%02x; calc_crc = 0x%02x", efuse_crc, calc_crc); @@ -94,7 +89,7 @@ esp_err_t esp_efuse_mac_get_default(uint8_t* mac) // Only ESP32 has MAC CRC in efuse, ESP32-S2 has internal efuse consistency checks uint8_t efuse_crc; esp_efuse_read_field_blob(ESP_EFUSE_MAC_FACTORY_CRC, &efuse_crc, 8); - uint8_t calc_crc = esp_crc8(mac, 6); + uint8_t calc_crc = esp_rom_efuse_mac_address_crc8(mac, 6); if (efuse_crc != calc_crc) { // Small range of MAC addresses are accepted even if CRC is invalid. diff --git a/components/esp_rom/esp32/ld/esp32.rom.api.ld b/components/esp_rom/esp32/ld/esp32.rom.api.ld index 58c694baf5..3060a7e86e 100644 --- a/components/esp_rom/esp32/ld/esp32.rom.api.ld +++ b/components/esp_rom/esp32/ld/esp32.rom.api.ld @@ -15,3 +15,7 @@ PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv ); PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold ); PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in ); PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out ); + +PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 ); +PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig ); +PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled ); diff --git a/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld b/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld index e38f45c1c5..dd60212e35 100644 --- a/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld +++ b/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld @@ -12,3 +12,8 @@ PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv ); PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold ); PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in ); PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out ); + +PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 ); +PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig ); +PROVIDE ( esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad ); +PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled ); diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld index 58c694baf5..8063f752e8 100644 --- a/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld +++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld @@ -15,3 +15,8 @@ PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv ); PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold ); PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in ); PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out ); + +PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 ); +PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig ); +PROVIDE ( esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad ); +PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled ); diff --git a/components/esp_rom/include/esp_rom_efuse.h b/components/esp_rom/include/esp_rom_efuse.h new file mode 100644 index 0000000000..907e175eca --- /dev/null +++ b/components/esp_rom/include/esp_rom_efuse.h @@ -0,0 +1,68 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#define ESP_ROM_EFUSE_FLASH_DEFAULT_SPI (0) +#define ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI (1) + +/** + * @brief A CRC8 algorithm used for MAC addresses stored in eFuse + * + * @param data Pointer to the original data + * @param len Data length in byte + * @return uint8_t CRC value + */ +uint8_t esp_rom_efuse_mac_address_crc8(const uint8_t *data, uint32_t len); + +/** + * @brief Get SPI Flash GPIO pin configurations from eFuse + * + * @return uint32_t + * - 0: default SPI pins (ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) + * - 1: default HSPI pins (ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) + * - Others: Customized pin configuration mask. Pins are encoded as per the + * EFUSE_SPICONFIG_RET_SPICLK, EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, + * EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros. + * + * @note WP pin (for quad I/O modes) is not saved in eFuse and not returned by this function. + */ +uint32_t esp_rom_efuse_get_flash_gpio_info(void); + +/** + * @brief Get SPI Flash WP pin information from eFuse + * + * @return uint32_t + * - 0x3F: invalid GPIO number + * - 0~46: valid GPIO number + */ +uint32_t esp_rom_efuse_get_flash_wp_gpio(void); + +/** + * @brief Read eFuse to check whether secure boot has been enabled or not + * + * @return true if secure boot is enabled, otherwise false + */ +bool esp_rom_efuse_is_secure_boot_enabled(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 4a4f8b0ece..92447bf7ce 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -23,7 +23,7 @@ #include "esp_system.h" #include "esp_clk_internal.h" - +#include "esp_rom_efuse.h" #include "sdkconfig.h" #if CONFIG_IDF_TARGET_ESP32 @@ -61,7 +61,6 @@ #if CONFIG_IDF_TARGET_ESP32 #if CONFIG_APP_BUILD_TYPE_ELF_RAM -#include "esp32/rom/efuse.h" #include "esp32/rom/spi_flash.h" #endif // CONFIG_APP_BUILD_TYPE_ELF_RAM #endif @@ -385,7 +384,7 @@ void IRAM_ATTR call_start_cpu0(void) fhdr.spi_size = ESP_IMAGE_FLASH_SIZE_4MB; extern void esp_rom_spiflash_attach(uint32_t, bool); - esp_rom_spiflash_attach(ets_efuse_get_spiconfig(), false); + esp_rom_spiflash_attach(esp_rom_efuse_get_flash_gpio_info(), false); esp_rom_spiflash_unlock(); #else // This assumes that DROM is the first segment in the application binary, i.e. that we can read diff --git a/components/spi_flash/esp_flash_spi_init.c b/components/spi_flash/esp_flash_spi_init.c index 261331723c..e6c40d804f 100644 --- a/components/spi_flash/esp_flash_spi_init.c +++ b/components/spi_flash/esp_flash_spi_init.c @@ -19,6 +19,7 @@ #include "driver/gpio.h" #include "esp32/rom/spi_flash.h" #include "esp_rom_gpio.h" +#include "esp_rom_efuse.h" #include "esp_log.h" #include "esp_heap_caps.h" #include "hal/spi_types.h" @@ -60,7 +61,6 @@ __attribute__((unused)) static const char TAG[] = "spi_flash"; .input_delay_ns = 0,\ } #elif CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/efuse.h" #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \ .host_id = SPI_HOST,\ .speed = DEFAULT_FLASH_SPEED, \ @@ -225,7 +225,7 @@ esp_err_t esp_flash_init_default_chip(void) #ifdef CONFIG_IDF_TARGET_ESP32S2 // For esp32s2 spi IOs are configured as from IO MUX by default - cfg.iomux = ets_efuse_get_spiconfig() == 0 ? true : false; + cfg.iomux = esp_rom_efuse_get_flash_gpio_info() == 0 ? true : false; #endif //the host is already initialized, only do init for the data and load it to the host