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change(hal): add hal interface to configure pau regdma wait timeout parameter

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This commit is contained in:
Li Shuai 2024-06-28 18:11:30 +08:00 committed by Lou Tianhao
parent d6737c3207
commit debb6ab6a1
10 changed files with 81 additions and 1 deletions
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3
components/esp_hw_support/port/pau_regdma.c
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@ -20,6 +20,8 @@
#define PAU_REGDMA_LINK_LOOP (0x3FF)
#define PAU_REGDMA_REG_ACCESS_TIME (0x3FF)
#define PAU_REGDMA_LINK_WAIT_RETRY_COUNT (1000)
#define PAU_REGDMA_LINK_WAIT_READ_INTERNAL (32)
static __attribute__((unused)) const char *TAG = "pau_regdma";
@ -38,6 +40,7 @@ pau_context_t * __attribute__((weak)) IRAM_ATTR PAU_instance(void)
if (pau_hal.dev == NULL) {
pau_hal.dev = &PAU;
pau_hal_enable_bus_clock(true);
pau_hal_set_regdma_wait_timeout(&pau_hal, PAU_REGDMA_LINK_WAIT_RETRY_COUNT, PAU_REGDMA_LINK_WAIT_READ_INTERNAL);
pau_hal_set_regdma_work_timeout(&pau_hal, PAU_REGDMA_LINK_LOOP, PAU_REGDMA_REG_ACCESS_TIME);
#if SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE
pau_hal_regdma_link_count_config(&pau_hal, SOC_PM_PAU_LINK_NUM);

10
components/hal/esp32c5/include/hal/lp_aon_ll.h
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@ -148,6 +148,16 @@ static inline void lp_aon_ll_set_regdma_link_addr(uint32_t addr)
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg2, link_addr_aon, addr);
}
static inline void lp_aon_ll_set_regdma_link_wait_retry_count(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, link_wait_tout_thres_aon, count);
}
static inline void lp_aon_ll_set_regdma_link_wait_read_interval(int interval)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, read_interval_aon, interval);
}
#ifdef __cplusplus
}
#endif

7
components/hal/esp32c5/pau_hal.c
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@ -69,3 +69,10 @@ void pau_hal_set_regdma_work_timeout(pau_hal_context_t *hal, uint32_t loop_num,
lp_aon_ll_set_regdma_link_loop_threshold(loop_num);
lp_aon_ll_set_regdma_link_reg_access_tout_threshold(time);
}
void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval)
{
HAL_ASSERT(count > 0 && interval > 0);
lp_aon_ll_set_regdma_link_wait_retry_count(count);
lp_aon_ll_set_regdma_link_wait_read_interval(interval);
}

10
components/hal/esp32c6/include/hal/pau_ll.h
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@ -157,6 +157,16 @@ static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev)
dev->int_clr.error_int_clr = 1;
}
static inline void pau_ll_set_regdma_link_wait_retry_count(pau_dev_t *dev, int count)
{
dev->regdma_bkp_conf.link_tout_thres = count;
}
static inline void pau_ll_set_regdma_link_wait_read_interval(pau_dev_t *dev, int interval)
{
dev->regdma_bkp_conf.read_interval = interval;
}
#ifdef __cplusplus
}
#endif

7
components/hal/esp32c6/pau_hal.c
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@ -61,3 +61,10 @@ void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal)
void pau_hal_set_regdma_work_timeout(pau_hal_context_t *hal, uint32_t loop_num, uint32_t time)
{
}
void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval)
{
HAL_ASSERT(count > 0 && interval > 0);
pau_ll_set_regdma_link_wait_retry_count(hal->dev, count);
pau_ll_set_regdma_link_wait_read_interval(hal->dev, interval);
}

10
components/hal/esp32h2/include/hal/pau_ll.h
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@ -127,6 +127,16 @@ static inline __attribute__((always_inline)) void pau_ll_clear_regdma_backup_err
dev->int_clr.error_int_clr = 1;
}
static inline void pau_ll_set_regdma_link_wait_retry_count(pau_dev_t *dev, int count)
{
dev->regdma_bkp_conf.link_tout_thres = count;
}
static inline void pau_ll_set_regdma_link_wait_read_interval(pau_dev_t *dev, int interval)
{
dev->regdma_bkp_conf.read_interval = interval;
}
#ifdef __cplusplus
}
#endif

9
components/hal/esp32h2/pau_hal.c
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@ -46,6 +46,13 @@ void pau_hal_set_regdma_work_timeout(pau_hal_context_t *hal, uint32_t loop_num,
{
}
void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval)
{
HAL_ASSERT(count > 0 && interval > 0);
pau_ll_set_regdma_link_wait_retry_count(hal->dev, count);
pau_ll_set_regdma_link_wait_read_interval(hal->dev, interval);
}
void IRAM_ATTR pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool backup_or_restore)
{
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
@ -67,4 +74,4 @@ void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal)
pau_ll_set_regdma_entry_link_backup_start_disable(hal->dev);
pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
}
}

10
components/hal/esp32p4/include/hal/pau_ll.h
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@ -158,6 +158,16 @@ static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev)
dev->int_clr.error_int_clr = 1;
}
static inline void pau_ll_set_regdma_link_wait_retry_count(pau_dev_t *dev, int count)
{
dev->regdma_bkp_conf.link_tout_thres = count;
}
static inline void pau_ll_set_regdma_link_wait_read_interval(pau_dev_t *dev, int interval)
{
dev->regdma_bkp_conf.read_interval = interval;
}
#ifdef __cplusplus
}
#endif

7
components/hal/esp32p4/pau_hal.c
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@ -67,6 +67,13 @@ void pau_hal_set_regdma_work_timeout(pau_hal_context_t *hal, uint32_t loop_num,
{
}
void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval)
{
HAL_ASSERT(count > 0 && interval > 0);
pau_ll_set_regdma_link_wait_retry_count(hal->dev, count);
pau_ll_set_regdma_link_wait_read_interval(hal->dev, interval);
}
#if SOC_PAU_IN_TOP_DOMAIN
void IRAM_ATTR pau_hal_lp_sys_initialize(void)
{

9
components/hal/include/hal/pau_hal.h
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@ -143,6 +143,15 @@ void pau_hal_regdma_link_count_config(pau_hal_context_t *hal, int count);
*/
void pau_hal_set_regdma_work_timeout(pau_hal_context_t *hal, uint32_t loop_num, uint32_t count);
/**
* @brief Set regdma link wait timeout, include wait retry count and register read interval
*
* @param hal regdma hal context
* @param count the maximum number of regdma wait retry count
* @param interval the interval of regdma wait link to read register
*/
void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval);
#if SOC_PAU_IN_TOP_DOMAIN
/**
* If PAU is in TOP power domain, configuration will be lost after sleep, it is necessary