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feat(i2c): Add I2C driver support for esp32p4

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This commit is contained in:
Cao Sen Miao 2023-08-09 11:30:13 +08:00
parent 080087a9a0
commit de85f47bc9
9 changed files with 1175 additions and 171 deletions
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1118
components/hal/esp32p4/include/hal/i2c_ll.h Normal file
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File diff suppressed because it is too large Load Diff

4
components/hal/i2c_hal.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -49,8 +49,8 @@ void i2c_hal_init(i2c_hal_context_t *hal, int i2c_port)
{
if (hal->dev == NULL) {
hal->dev = I2C_LL_GET_HW(i2c_port);
i2c_ll_enable_controller_clock(hal->dev, true);
}
i2c_ll_enable_controller_clock(hal->dev, true);
}
void i2c_hal_deinit(i2c_hal_context_t *hal)

16
components/soc/esp32p4/i2c_periph.c
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@ -11,4 +11,20 @@
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
{
.sda_out_sig = I2C0_SDA_PAD_OUT_IDX,
.sda_in_sig = I2C0_SDA_PAD_IN_IDX,
.scl_out_sig = I2C0_SCL_PAD_OUT_IDX,
.scl_in_sig = I2C0_SCL_PAD_IN_IDX,
.irq = ETS_I2C0_INTR_SOURCE,
.module = PERIPH_I2C0_MODULE,
},
{
.sda_out_sig = I2C1_SDA_PAD_OUT_IDX,
.sda_in_sig = I2C1_SDA_PAD_IN_IDX,
.scl_out_sig = I2C1_SCL_PAD_OUT_IDX,
.scl_in_sig = I2C1_SCL_PAD_IN_IDX,
.irq = ETS_I2C1_INTR_SOURCE,
.module = PERIPH_I2C1_MODULE,
},
};

10
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@ -51,6 +51,10 @@ config SOC_RTC_MEM_SUPPORTED
bool
default y
config SOC_I2C_SUPPORTED
bool
default y
config SOC_SYSTIMER_SUPPORTED
bool
default y
@ -313,12 +317,16 @@ config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
config SOC_I2C_NUM
int
default 1
default 2
config SOC_I2C_FIFO_LEN
int
default 32
config SOC_I2C_CMD_REG_NUM
int
default 8
config SOC_I2C_SUPPORT_SLAVE
bool
default y

12
components/soc/esp32p4/include/soc/clk_tree_defs.h
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@ -278,6 +278,18 @@ typedef enum {
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of I2C
*/
#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of I2C clock source.
*/
typedef enum {
I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */
} soc_periph_i2c_clk_src_t;
/////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
//TODO: IDF-7502

176
components/soc/esp32p4/include/soc/i2c_struct.h
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@ -1002,12 +1002,12 @@ typedef union {
/** Group: Command registers */
/** Type of comd0 register
* I2C command register 0
* I2C command register 0~7
*/
typedef union {
struct {
/** command0 : R/W; bitpos: [13:0]; default: 0;
* Configures command 0. It consists of three parts:
/** command : R/W; bitpos: [13:0]; default: 0;
* Configures command. It consists of three parts:
* op_code is the command,
* 0: RSTART,
* 1: WRITE,
@ -1019,166 +1019,18 @@ typedef union {
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more information.
*/
uint32_t command0:14;
uint32_t command:14;
uint32_t reserved_14:17;
/** command0_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 0 is done in I2C Master mode.
/** command_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command0_done:1;
uint32_t command_done:1;
};
uint32_t val;
} i2c_comd0_reg_t;
/** Type of comd1 register
* I2C command register 1
*/
typedef union {
struct {
/** command1 : R/W; bitpos: [13:0]; default: 0;
* Configures command 1. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command1:14;
uint32_t reserved_14:17;
/** command1_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 1 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command1_done:1;
};
uint32_t val;
} i2c_comd1_reg_t;
/** Type of comd2 register
* I2C command register 2
*/
typedef union {
struct {
/** command2 : R/W; bitpos: [13:0]; default: 0;
* Configures command 2. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command2:14;
uint32_t reserved_14:17;
/** command2_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 2 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command2_done:1;
};
uint32_t val;
} i2c_comd2_reg_t;
/** Type of comd3 register
* I2C command register 3
*/
typedef union {
struct {
/** command3 : R/W; bitpos: [13:0]; default: 0;
* Configures command 3. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command3:14;
uint32_t reserved_14:17;
/** command3_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 3 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command3_done:1;
};
uint32_t val;
} i2c_comd3_reg_t;
/** Type of comd4 register
* I2C command register 4
*/
typedef union {
struct {
/** command4 : R/W; bitpos: [13:0]; default: 0;
* Configures command 4. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command4:14;
uint32_t reserved_14:17;
/** command4_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 4 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command4_done:1;
};
uint32_t val;
} i2c_comd4_reg_t;
/** Type of comd5 register
* I2C command register 5
*/
typedef union {
struct {
/** command5 : R/W; bitpos: [13:0]; default: 0;
* Configures command 5. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command5:14;
uint32_t reserved_14:17;
/** command5_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 5 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command5_done:1;
};
uint32_t val;
} i2c_comd5_reg_t;
/** Type of comd6 register
* I2C command register 6
*/
typedef union {
struct {
/** command6 : R/W; bitpos: [13:0]; default: 0;
* Configures command 6. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command6:14;
uint32_t reserved_14:17;
/** command6_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 6 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command6_done:1;
};
uint32_t val;
} i2c_comd6_reg_t;
/** Type of comd7 register
* I2C command register 7
*/
typedef union {
struct {
/** command7 : R/W; bitpos: [13:0]; default: 0;
* Configures command 7. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command7:14;
uint32_t reserved_14:17;
/** command7_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 7 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command7_done:1;
};
uint32_t val;
} i2c_comd7_reg_t;
} i2c_comd_reg_t;
/** Group: Version register */
/** Type of date register
@ -1246,14 +1098,7 @@ typedef struct {
volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
volatile i2c_filter_cfg_reg_t filter_cfg;
uint32_t reserved_054;
volatile i2c_comd0_reg_t comd0;
volatile i2c_comd1_reg_t comd1;
volatile i2c_comd2_reg_t comd2;
volatile i2c_comd3_reg_t comd3;
volatile i2c_comd4_reg_t comd4;
volatile i2c_comd5_reg_t comd5;
volatile i2c_comd6_reg_t comd6;
volatile i2c_comd7_reg_t comd7;
volatile i2c_comd_reg_t command[8];
volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
@ -1266,6 +1111,9 @@ typedef struct {
volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr;
} i2c_dev_t;
extern i2c_dev_t I2C0;
extern i2c_dev_t I2C1;
extern i2c_dev_t LP_I2C;
#ifndef __cplusplus
_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure");

7
components/soc/esp32p4/include/soc/soc_caps.h
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@ -52,7 +52,7 @@
// #define SOC_SDM_SUPPORTED 1 //TODO: IDF-7551
// #define SOC_GPSPI_SUPPORTED 1 //TODO: IDF-7502, TODO: IDF-7503
// #define SOC_LEDC_SUPPORTED 1 //TODO: IDF-6510
// #define SOC_I2C_SUPPORTED 1 //TODO: IDF-6507, TODO: IDF-7491
#define SOC_I2C_SUPPORTED 1 //TODO: IDF-6507, TODO: IDF-7491
#define SOC_SYSTIMER_SUPPORTED 1
// #define SOC_AES_SUPPORTED 1 //TODO: IDF-6519
#define SOC_MPI_SUPPORTED 1
@ -211,10 +211,11 @@
#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-P4 has 1 I2C
#define SOC_I2C_NUM (1U)
// ESP32-P4 has 2 I2Cs
#define SOC_I2C_NUM (2U)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
#define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */
#define SOC_I2C_SUPPORT_SLAVE (1)
// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.

2
examples/peripherals/i2c/i2c_self_test/main/i2c_example_main.c
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@ -280,7 +280,7 @@ static void i2c_test_task(void *arg)
ret = i2c_master_write_slave(I2C_MASTER_NUM, data_wr, RW_TEST_LENGTH);
if (ret == ESP_OK) {
size = i2c_slave_read_buffer(I2C_SLAVE_NUM, data, RW_TEST_LENGTH, 1000 / portTICK_PERIOD_MS);
}
}
if (ret == ESP_ERR_TIMEOUT) {
ESP_LOGE(TAG, "I2C Timeout");
} else if (ret == ESP_OK) {

1
tools/ci/check_public_headers_exceptions.txt
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@ -194,6 +194,7 @@ components/hal/esp32p4/include/hal/cache_ll.h
components/hal/esp32p4/include/hal/clk_tree_ll.h
components/hal/esp32p4/include/hal/ecc_ll.h
components/hal/esp32p4/include/hal/gpspi_flash_ll.h
components/hal/esp32p4/include/hal/i2c_ll.h
components/hal/esp32p4/include/hal/mcpwm_ll.h
components/hal/esp32p4/include/hal/mpi_ll.h
components/hal/esp32p4/include/hal/mpu_ll.h