change(header): modify p4 headers issues from check_header_py

components/driver/deprecated/adc_i2s_deprecated.c

@@ -13,7 +13,6 @@
 #include "esp_log.h"
 #include "esp_intr_alloc.h"
 #include "driver/rtc_io.h"
-#include "hal/adc_hal.h"
 #include "hal/adc_ll.h"
 #include "hal/adc_types.h"
 #ifdef CONFIG_PM_ENABLE
@@ -237,7 +236,7 @@ esp_err_t adc_i2s_mode_init(adc_unit_t adc_unit, adc_channel_t channel)
     adc_ll_digi_set_fsm_time(ADC_LL_FSM_RSTB_WAIT_DEFAULT, ADC_LL_FSM_START_WAIT_DEFAULT,
                              ADC_LL_FSM_STANDBY_WAIT_DEFAULT);
     adc_ll_set_sample_cycle(ADC_LL_SAMPLE_CYCLE_DEFAULT);
-    adc_hal_pwdet_set_cct(ADC_LL_PWDET_CCT_DEFAULT);
+    adc_ll_pwdet_set_cct(ADC_LL_PWDET_CCT_DEFAULT);
     adc_ll_digi_output_invert(ADC_UNIT_1, ADC_LL_DIGI_DATA_INVERT_DEFAULT(ADC_UNIT_1));
     adc_ll_digi_output_invert(ADC_UNIT_2, ADC_LL_DIGI_DATA_INVERT_DEFAULT(ADC_UNIT_2));
     adc_ll_digi_set_clk_div(ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT);

components/driver/deprecated/adc_legacy.c

@@ -23,7 +23,7 @@
 #include "esp_private/sar_periph_ctrl.h"
 #include "adc1_private.h"
 #include "hal/adc_types.h"
-#include "hal/adc_hal.h"
+#include "hal/adc_ll.h"
 #include "hal/adc_hal_common.h"
 #include "esp_private/periph_ctrl.h"
 #include "driver/adc_types_legacy.h"
@@ -164,7 +164,7 @@ static void adc_rtc_chan_init(adc_unit_t adc_unit)
 #endif
     }
     if (adc_unit == ADC_UNIT_2) {
-        adc_hal_pwdet_set_cct(ADC_LL_PWDET_CCT_DEFAULT);
+        adc_ll_pwdet_set_cct(ADC_LL_PWDET_CCT_DEFAULT);
         adc_oneshot_ll_output_invert(ADC_UNIT_2, ADC_LL_DATA_INVERT_DEFAULT(ADC_UNIT_2));
         adc_ll_set_sar_clk_div(ADC_UNIT_2, ADC_LL_SAR_CLK_DIV_DEFAULT(ADC_UNIT_2));
     }

components/driver/deprecated/driver/adc_types_legacy.h

@@ -70,7 +70,7 @@ typedef enum {
     ADC1_CHANNEL_4,     /*!< ADC1 channel 4 is GPIO4 */
     ADC1_CHANNEL_MAX,
 } adc1_channel_t;
-#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
+#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
 typedef enum {
     ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO0 */
     ADC1_CHANNEL_1,     /*!< ADC1 channel 1 is GPIO1 */

components/driver/deprecated/driver/timer_types_legacy.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -96,10 +96,17 @@ typedef enum {
     TIMER_AUTORELOAD_MAX,
 } timer_autoreload_t;
 
+#if SOC_GPTIMER_SUPPORTED
 /**
  * @brief Timer group clock source
  */
 typedef soc_periph_tg_clk_src_legacy_t timer_src_clk_t;
+#else
+/**
+ *  @brief Default type
+ */
+typedef int                            timer_src_clk_t;
+#endif
 
 /**
  * @brief Interrupt handler callback function

components/esp_adc/adc_filter.c

@@ -13,6 +13,7 @@
 #include "freertos/FreeRTOS.h"
 #include "hal/adc_types.h"
 #include "hal/adc_hal.h"
+#include "hal/adc_ll.h"
 #include "adc_continuous_internal.h"
 #include "esp_adc/adc_filter.h"
 

components/esp_adc/esp32p4/include/adc_cali_schemes.h

@@ -0,0 +1,15 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+/**
+ * @file adc_cali_schemes.h
+ *
+ * @brief Supported calibration schemes
+ */
+
+//Now no scheme supported

components/esp_hw_support/adc_share_hw_ctrl.c

@@ -24,8 +24,8 @@
 #include "esp_check.h"
 #include "freertos/FreeRTOS.h"
 #include "hal/adc_types.h"
-#include "hal/adc_hal.h"
 #include "hal/adc_hal_common.h"
+#include "hal/adc_ll.h"
 #include "esp_private/adc_share_hw_ctrl.h"
 #include "esp_private/sar_periph_ctrl.h"
 //For calibration

components/esp_hw_support/port/esp32p4/systimer.c

@@ -0,0 +1,22 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp_private/systimer.h"
+
+/**
+ * @brief systimer's clock source is fixed to XTAL (40MHz), and has a fixed fractional divider (2.5).
+ *        So the resolution of the systimer is 40MHz/2.5 = 16MHz.
+ */
+
+uint64_t systimer_ticks_to_us(uint64_t ticks)
+{
+    return ticks / 16;
+}
+
+uint64_t systimer_us_to_ticks(uint64_t us)
+{
+    return us * 16;
+}

components/hal/esp32p4/include/hal/clk_gate_ll.h

@@ -225,7 +225,7 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
     }
 }
 
-static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
+static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
 {
     switch (periph) {
     case PERIPH_AHB_PDMA_MODULE:
@@ -293,7 +293,7 @@ static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
     }
 }
 
-static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
+static inline uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
 {
     switch (periph) {
     case PERIPH_PVT_MODULE:

components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h

@@ -6,6 +6,7 @@
 
 #pragma once
 
+#include <stdbool.h>
 #include <stdint.h>
 #include "soc/soc.h"
 #include "soc/regi2c_defs.h"

components/hal/esp32p4/include/hal/spimem_flash_ll.h

@@ -24,6 +24,7 @@
 #include "hal/assert.h"
 #include "hal/spi_types.h"
 #include "hal/spi_flash_types.h"
+#include "hal/misc.h"
 
 #ifdef __cplusplus
 extern "C" {

components/hal/esp32p4/include/hal/uart_ll.h

@@ -163,9 +163,9 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t
 
     //needs force u32 write
     if ((hw) == &UART0) {
-        HP_SYSTEM.peri_clk_ctrl111.reg_uart0_sclk_div_num = sclk_div - 1;
+        HP_SYS_CLKRST.peri_clk_ctrl111.reg_uart0_sclk_div_num = sclk_div - 1;
     } else {
-        HP_SYSTEM.peri_clk_ctrl112.reg_uart1_sclk_div_num = sclk_div - 1;
+        HP_SYS_CLKRST.peri_clk_ctrl112.reg_uart1_sclk_div_num = sclk_div - 1;
     }
 
 #undef DIV_UP

components/hal/include/hal/adc_hal.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,9 +10,10 @@
 #include "soc/soc_caps.h"
 #include "hal/dma_types.h"
 #include "hal/adc_types.h"
-#include "hal/adc_ll.h"
 #include "hal/adc_hal_common.h"
-#include "esp_err.h"
+#if SOC_ADC_DMA_SUPPORTED
+#include "hal/adc_ll.h"
+#endif
 
 #if SOC_GDMA_SUPPORTED
 #include "soc/gdma_struct.h"

components/hal/include/hal/adc_types.h

@@ -89,6 +89,9 @@ typedef soc_periph_adc_digi_clk_src_t    adc_continuous_clk_src_t;  ///< Clock s
 #elif SOC_ADC_RTC_CTRL_SUPPORTED
 typedef soc_periph_adc_rtc_clk_src_t     adc_oneshot_clk_src_t;     ///< Clock source type of oneshot mode which uses RTC controller
 typedef soc_periph_adc_digi_clk_src_t    adc_continuous_clk_src_t;  ///< Clock source type of continuous mode which uses digital controller
+#else
+typedef int                              adc_oneshot_clk_src_t;     ///< Default type
+typedef int                              adc_continuous_clk_src_t;  ///< Default type
 #endif
 
 /**

components/hal/include/hal/aes_hal.h

@@ -12,11 +12,14 @@
 
 #pragma once
 
+#include <stdint.h>
 #include <stddef.h>
 #include <stdbool.h>
 #include "soc/soc_caps.h"
 #include "hal/aes_types.h"
+#if SOC_AES_SUPPORTED
 #include "hal/aes_ll.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {

components/hal/include/hal/i2c_hal.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -14,13 +14,18 @@
 
 #pragma once
 
-#include "hal/i2c_ll.h"
+#include "soc/soc_caps.h"
 #include "hal/i2c_types.h"
+#if SOC_I2C_SUPPORTED
+#include "hal/i2c_ll.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#if SOC_I2C_SUPPORTED
+
 /**
  * @brief I2C hal Context definition
  */
@@ -131,6 +136,8 @@ void i2c_hal_get_timing_config(i2c_hal_context_t *hal, i2c_hal_timing_config_t *
  */
 void i2c_hal_set_timing_config(i2c_hal_context_t *hal, i2c_hal_timing_config_t *timing_config);
 
+#endif  // #if SOC_I2C_SUPPORTED
+
 #ifdef __cplusplus
 }
 #endif

components/hal/include/hal/i2c_types.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -97,6 +97,11 @@ typedef struct {
  * @brief I2C group clock source
  */
 typedef soc_periph_i2c_clk_src_t i2c_clock_source_t;
+#else
+/**
+ * @brief Default type
+ */
+typedef int                      i2c_clock_source_t;
 #endif
 
 

components/hal/include/hal/ledc_hal.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,14 +15,18 @@
 
 #pragma once
 
-#include "hal/ledc_ll.h"
-#include "hal/ledc_types.h"
 #include "soc/soc_caps.h"
+#include "hal/ledc_types.h"
+#if SOC_LEDC_SUPPORTED
+#include "hal/ledc_ll.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+
+#if SOC_LEDC_SUPPORTED
 /**
  * Context that should be maintained by both the driver and the HAL
  */
@@ -439,6 +443,8 @@ void ledc_hal_clear_fade_end_intr_status(ledc_hal_context_t *hal, ledc_channel_t
  */
 void ledc_hal_get_clk_cfg(ledc_hal_context_t *hal, ledc_timer_t timer_sel, ledc_clk_cfg_t *clk_cfg);
 
+#endif  //#if SOC_LEDC_SUPPORTED
+
 #ifdef __cplusplus
 }
 #endif

components/hal/include/hal/rtc_hal.h

@@ -9,10 +9,13 @@
 #include <stdint.h>
 #include "soc/soc_caps.h"
 #include "hal/gpio_types.h"
+#include "sdkconfig.h"
 
+#if !CONFIG_IDF_TARGET_ESP32P4  //TODO: IDF-7532
 #if !SOC_LP_TIMER_SUPPORTED
 #include "hal/rtc_cntl_ll.h"
 #endif
+#endif  //#if !CONFIG_IDF_TARGET_ESP32P4
 #if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
 #include "hal/rtc_io_ll.h"
 #endif

components/hal/include/hal/spi_hal.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -26,16 +26,20 @@
 // field comments.
 
 #pragma once
-#include "hal/spi_ll.h"
+#include "esp_err.h"
-#include <esp_err.h>
-#include "soc/lldesc.h"
 #include "soc/soc_caps.h"
 #include "hal/spi_types.h"
+#if SOC_GPSPI_SUPPORTED
+#include "hal/spi_ll.h"
+#include "soc/lldesc.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#if SOC_GPSPI_SUPPORTED
+
 /**
  * Input parameters to the ``spi_hal_cal_clock_conf`` to calculate the timing configuration
  */
@@ -269,6 +273,8 @@ void spi_hal_cal_timing(int source_freq_hz, int eff_clk, bool gpio_is_used, int
  */
 int spi_hal_get_freq_limit(bool gpio_is_used, int input_delay_ns);
 
+#endif  //#if SOC_GPSPI_SUPPORTED
+
 #ifdef __cplusplus
 }
 #endif

components/hal/include/hal/spi_slave_hal.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -24,16 +24,20 @@
 
 #pragma once
 
-#include <esp_types.h>
+#include "sdkconfig.h"
-#include "soc/lldesc.h"
+#include "esp_types.h"
-#include "soc/spi_struct.h"
 #include "soc/soc_caps.h"
+#if SOC_GPSPI_SUPPORTED
+#include "soc/lldesc.h"
 #include "hal/spi_ll.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#if SOC_GPSPI_SUPPORTED
+
 /**
  * Context that should be maintained by both the driver and the HAL.
  */
@@ -160,6 +164,8 @@ uint32_t spi_slave_hal_get_rcv_bitlen(spi_slave_hal_context_t *hal);
 bool spi_slave_hal_dma_need_reset(const spi_slave_hal_context_t *hal);
 #endif //#if CONFIG_IDF_TARGET_ESP32
 
+#endif  //#if SOC_GPSPI_SUPPORTED
+
 #ifdef __cplusplus
 }
 #endif

components/hal/include/hal/spi_slave_hd_hal.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -43,15 +43,20 @@
 
 #pragma once
 
-#include <esp_types.h>
+#include "esp_types.h"
 #include "esp_err.h"
-#include "hal/spi_ll.h"
+#include "soc/soc_caps.h"
 #include "hal/spi_types.h"
+#if SOC_GPSPI_SUPPORTED
+#include "hal/spi_ll.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#if SOC_GPSPI_SUPPORTED
+
 /**
  * @brief Type of dma descriptor with appended members
  *        this structure inherits DMA descriptor, with a pointer to the transaction descriptor passed from users.
@@ -311,6 +316,8 @@ esp_err_t spi_slave_hd_hal_txdma_append(spi_slave_hd_hal_context_t *hal, uint8_t
  */
 esp_err_t spi_slave_hd_hal_rxdma_append(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len, void *arg);
 
+#endif  //#if SOC_GPSPI_SUPPORTED
+
 #ifdef __cplusplus
 }
 #endif

components/hal/include/hal/timer_types.h

@@ -1,22 +1,30 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #pragma once
 
+#include "soc/soc_caps.h"
 #include "soc/clk_tree_defs.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#if SOC_GPTIMER_SUPPORTED
 /**
  * @brief GPTimer clock source
  * @note User should select the clock source based on the power and resolution requirement
  */
 typedef soc_periph_gptimer_clk_src_t gptimer_clock_source_t;
+#else
+/**
+ * @brief Default type
+ */
+typedef int                          gptimer_clock_source_t;
+#endif
 
 /**
  * @brief GPTimer count direction

components/soc/esp32p4/include/soc/clk_tree_defs.h

@@ -278,6 +278,24 @@ typedef enum {
 
 //////////////////////////////////////////////////LEDC/////////////////////////////////////////////////////////////////
 
+//TODO: IDF-6510
+/**
+ * @brief Array initializer for all supported clock sources of LEDC
+ */
+#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
+
+/**
+ * @brief Type of LEDC clock source, reserved for the legacy LEDC driver
+ */
+typedef enum {
+    LEDC_AUTO_CLK = 0,                              /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/
+    LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M,    /*!< Select PLL_F80M clock as the source clock */
+    LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST,     /*!< Select RC_FAST as the source clock */
+    LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
+
+    LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK,   /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
+} soc_periph_ledc_clk_src_legacy_t;
+
 //////////////////////////////////////////////////PARLIO////////////////////////////////////////////////////////////////
 
 #ifdef __cplusplus

components/soc/esp32p4/include/soc/hp_sys_clkrst_struct.h

@@ -2922,7 +2922,7 @@ typedef union {
 } hp_sys_clkrst_hpcore_wdt_reset_source0_reg_t;
 
 
-typedef struct {
+typedef struct hp_sys_clkrst_dev_t {
     volatile hp_sys_clkrst_clk_en0_reg_t clk_en0;
     volatile hp_sys_clkrst_root_clk_ctrl0_reg_t root_clk_ctrl0;
     volatile hp_sys_clkrst_root_clk_ctrl1_reg_t root_clk_ctrl1;
@@ -2985,7 +2985,7 @@ typedef struct {
     volatile hp_sys_clkrst_hpcore_wdt_reset_source0_reg_t hpcore_wdt_reset_source0;
 } hp_sys_clkrst_dev_t;
 
-extern hp_sys_clkrst_dev_t HP_SYSTEM;
+extern hp_sys_clkrst_dev_t HP_SYS_CLKRST;
 
 
 #ifndef __cplusplus

components/soc/esp32p4/ld/esp32p4.peripherals.ld

@@ -55,6 +55,7 @@ PROVIDE ( GPIO           = 0x500E0000 );
 PROVIDE ( SIGMADELTA     = 0x500E0F00 );
 
 PROVIDE ( HP_SYSTEM         = 0x500E5000 );
+PROVIDE ( HP_SYS_CLKRST     = 0x500E6000 );
 PROVIDE ( TEE               = 0x60098000 ); /* TODO: IDF-7542 */
 PROVIDE ( HP_APM            = 0x60099000 ); /* TODO: IDF-7542 */
 

examples/common_components/env_caps/esp32p4/Kconfig.env_caps

@@ -0,0 +1,15 @@
+config ENV_GPIO_RANGE_MIN
+    int
+    default 0
+
+config ENV_GPIO_RANGE_MAX
+    int
+    default 56
+
+config ENV_GPIO_IN_RANGE_MAX
+    int
+    default ENV_GPIO_RANGE_MAX
+
+config ENV_GPIO_OUT_RANGE_MAX
+    int
+    default ENV_GPIO_RANGE_MAX