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feat(mcpwm): driver support on esp32-c5

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This commit is contained in:
morris 2024-03-19 15:51:15 +08:00
parent 80f5444f86
commit de5fb9f070
23 changed files with 2053 additions and 355 deletions
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19
components/driver/deprecated/mcpwm_legacy.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -13,14 +13,16 @@
#include "esp_rom_gpio.h"
#include "esp_intr_alloc.h"
#include "soc/mcpwm_periph.h"
#include "soc/io_mux_reg.h"
#include "hal/mcpwm_hal.h"
#include "hal/gpio_hal.h"
#include "hal/mcpwm_ll.h"
#include "driver/mcpwm_types_legacy.h"
#include "driver/gpio.h"
#include "esp_private/periph_ctrl.h"
#include "esp_clk_tree.h"
#include "esp_private/gpio.h"
#include "esp_private/esp_clk.h"
#include "esp_clk_tree.h"
static const char *TAG = "mcpwm(legacy)";
@ -204,7 +206,7 @@ esp_err_t mcpwm_gpio_init(mcpwm_unit_t mcpwm_num, mcpwm_io_signals_t io_signal,
int capture_id = io_signal - MCPWM_CAP_0;
esp_rom_gpio_connect_in_signal(gpio_num, mcpwm_periph_signals.groups[mcpwm_num].captures[capture_id].cap_sig, 0);
}
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
gpio_func_sel(gpio_num, PIN_FUNC_GPIO);
return ESP_OK;
}
@ -268,7 +270,6 @@ static inline uint32_t mcpwm_timer_get_resolution(mcpwm_unit_t mcpwm_num, mcpwm_
esp_err_t mcpwm_group_set_resolution(mcpwm_unit_t mcpwm_num, uint32_t resolution)
{
mcpwm_module_enable(mcpwm_num);
mcpwm_hal_context_t *hal = &context[mcpwm_num].hal;
uint32_t clk_src_hz = 0;
esp_clk_tree_src_get_freq_hz(MCPWM_TIMER_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz);
@ -277,7 +278,7 @@ esp_err_t mcpwm_group_set_resolution(mcpwm_unit_t mcpwm_num, uint32_t resolution
context[mcpwm_num].group_resolution_hz = clk_src_hz / pre_scale_temp;
MCPWM_CLOCK_SRC_ATOMIC() {
mcpwm_ll_group_set_clock_prescale(hal->dev, pre_scale_temp);
mcpwm_ll_group_set_clock_prescale(mcpwm_num, pre_scale_temp);
}
return ESP_OK;
}
@ -467,8 +468,8 @@ esp_err_t mcpwm_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpw
uint32_t timer_pre_scale = group_resolution / timer_resolution;
MCPWM_CLOCK_SRC_ATOMIC() {
mcpwm_ll_group_set_clock_source(hal->dev, (soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT);
mcpwm_ll_group_set_clock_prescale(hal->dev, group_pre_scale);
mcpwm_ll_group_set_clock_source(mcpwm_num, (soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT);
mcpwm_ll_group_set_clock_prescale(mcpwm_num, group_pre_scale);
}
mcpwm_critical_enter(mcpwm_num);
@ -864,8 +865,8 @@ esp_err_t mcpwm_capture_enable_channel(mcpwm_unit_t mcpwm_num, mcpwm_capture_cha
uint32_t group_pre_scale = clk_src_hz / group_resolution;
MCPWM_CLOCK_SRC_ATOMIC() {
mcpwm_ll_group_set_clock_source(hal->dev, (soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT);
mcpwm_ll_group_set_clock_prescale(hal->dev, group_pre_scale);
mcpwm_ll_group_set_clock_source(mcpwm_num, (soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT);
mcpwm_ll_group_set_clock_prescale(mcpwm_num, group_pre_scale);
}
mcpwm_critical_enter(mcpwm_num);

14
components/driver/test_apps/legacy_mcpwm_driver/main/test_legacy_mcpwm.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -12,7 +12,9 @@
#include "hal/gpio_hal.h"
#include "esp_rom_gpio.h"
#include "esp_private/esp_clk.h"
#include "esp_private/gpio.h"
#include "soc/mcpwm_periph.h"
#include "soc/io_mux_reg.h"
#include "driver/pulse_cnt.h"
#include "driver/mcpwm.h"
#include "driver/gpio.h"
@ -61,10 +63,12 @@ const static mcpwm_io_signals_t sync_io_sig_array[] = {MCPWM_SYNC_0, MCPWM_SYNC_
const static mcpwm_capture_signal_t cap_sig_array[] = {MCPWM_SELECT_CAP0, MCPWM_SELECT_CAP1, MCPWM_SELECT_CAP2};
const static mcpwm_io_signals_t cap_io_sig_array[] = {MCPWM_CAP_0, MCPWM_CAP_1, MCPWM_CAP_2};
#if SOC_PCNT_SUPPORTED
static pcnt_unit_handle_t pcnt_unit_a;
static pcnt_channel_handle_t pcnt_chan_a;
static pcnt_unit_handle_t pcnt_unit_b;
static pcnt_channel_handle_t pcnt_chan_b;
#endif
// This GPIO init function is almost the same to public API `mcpwm_gpio_init()`, except that
// this function will configure all MCPWM GPIOs into output and input capable
@ -93,7 +97,7 @@ static esp_err_t test_mcpwm_gpio_init(mcpwm_unit_t mcpwm_num, mcpwm_io_signals_t
int capture_id = io_signal - MCPWM_CAP_0;
esp_rom_gpio_connect_in_signal(gpio_num, mcpwm_periph_signals.groups[mcpwm_num].captures[capture_id].cap_sig, 0);
}
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
gpio_func_sel(gpio_num, PIN_FUNC_GPIO);
return ESP_OK;
}
@ -119,6 +123,7 @@ static void mcpwm_setup_testbench(mcpwm_unit_t group, mcpwm_timer_t timer, uint3
TEST_ESP_OK(mcpwm_init(group, timer, &pwm_config));
}
#if SOC_PCNT_SUPPORTED
static void pcnt_setup_testbench(void)
{
// PWMA <--> PCNT UNIT0
@ -173,6 +178,7 @@ static uint32_t pcnt_get_pulse_number(pcnt_unit_handle_t pwm_pcnt_unit, int capt
printf("count value: %d\r\n", count_value);
return (uint32_t)count_value;
}
#endif // SOC_PCNT_SUPPORTED
static void mcpwm_timer_duty_test(mcpwm_unit_t unit, mcpwm_timer_t timer, unsigned long int group_resolution, unsigned long int timer_resolution)
{
@ -210,6 +216,7 @@ TEST_CASE("MCPWM duty test", "[mcpwm]")
// -------------------------------------------------------------------------------------
#if SOC_PCNT_SUPPORTED
static void mcpwm_start_stop_test(mcpwm_unit_t unit, mcpwm_timer_t timer)
{
uint32_t pulse_number = 0;
@ -244,6 +251,7 @@ TEST_CASE("MCPWM start and stop test", "[mcpwm]")
}
}
}
#endif // SOC_PCNT_SUPPORTED
// -------------------------------------------------------------------------------------
@ -276,6 +284,7 @@ TEST_CASE("MCPWM deadtime test", "[mcpwm]")
}
// -------------------------------------------------------------------------------------
#if SOC_PCNT_SUPPORTED
#define TEST_CARRIER_FREQ 250000
static void mcpwm_carrier_test(mcpwm_unit_t unit, mcpwm_timer_t timer, mcpwm_carrier_out_ivt_t invert_or_not,
uint8_t period, uint8_t duty, uint8_t os_width)
@ -315,6 +324,7 @@ TEST_CASE("MCPWM carrier test", "[mcpwm]")
}
}
}
#endif // SOC_PCNT_SUPPORTED
// -------------------------------------------------------------------------------------

4
components/esp_driver_mcpwm/src/mcpwm_com.c
View File

@ -173,7 +173,7 @@ esp_err_t mcpwm_select_periph_clock(mcpwm_group_t *group, soc_module_clk_t clk_s
#endif // CONFIG_PM_ENABLE
MCPWM_CLOCK_SRC_ATOMIC() {
mcpwm_ll_group_set_clock_source(group->hal.dev, clk_src);
mcpwm_ll_group_set_clock_source(group->group_id, clk_src);
}
}
return ret;
@ -232,7 +232,7 @@ esp_err_t mcpwm_set_prescale(mcpwm_group_t *group, uint32_t expect_module_resolu
group->prescale = group_prescale;
group->resolution_hz = group_resolution_hz;
MCPWM_CLOCK_SRC_ATOMIC() {
mcpwm_ll_group_set_clock_prescale(group->hal.dev, group_prescale);
mcpwm_ll_group_set_clock_prescale(group_id, group_prescale);
}
} else {
prescale_conflict = (group->prescale != group_prescale);

6
components/esp_driver_mcpwm/test_apps/mcpwm/main/CMakeLists.txt
View File

@ -13,8 +13,12 @@ if(CONFIG_MCPWM_ISR_IRAM_SAFE)
list(APPEND srcs "test_mcpwm_iram.c")
endif()
if(CONFIG_SOC_ETM_SUPPORTED AND CONFIG_SOC_MCPWM_SUPPORT_ETM)
list(APPEND srcs "test_mcpwm_etm.c")
endif()
# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
# the component can be registered as WHOLE_ARCHIVE
idf_component_register(SRCS ${srcs}
PRIV_REQUIRES unity esp_driver_mcpwm esp_driver_gpio
PRIV_REQUIRES unity esp_driver_mcpwm esp_driver_gpio esp_driver_gptimer
WHOLE_ARCHIVE)

6
components/esp_hw_support/test_apps/etm/main/test_mcpwm_etm.c → components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_etm.c
View File

@ -14,7 +14,7 @@
#include "driver/gpio.h"
#include "driver/mcpwm_prelude.h"
TEST_CASE("mcpwm_comparator_etm_event", "[etm]")
TEST_CASE("mcpwm_comparator_etm_event", "[mcpwm][etm]")
{
// MCPWM cmpra -------------------------------------> ETM channel A ---> GPTimer start
// MCPWM cmprb / evt_cmpra (if support evt_cmpr) ---> ETM channel B ---> GPTimer stop
@ -58,9 +58,9 @@ TEST_CASE("mcpwm_comparator_etm_event", "[etm]")
};
TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &generator));
TEST_ESP_OK(mcpwm_generator_set_action_on_compare_event(generator,
MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, comparator_a, MCPWM_GEN_ACTION_HIGH)));
MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, comparator_a, MCPWM_GEN_ACTION_HIGH)));
TEST_ESP_OK(mcpwm_generator_set_action_on_compare_event(generator,
MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, comparator_b, MCPWM_GEN_ACTION_LOW)));
MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, comparator_b, MCPWM_GEN_ACTION_LOW)));
// allocate etm channels
printf("allocate etm channels\r\n");

4
components/esp_hw_support/test_apps/etm/main/CMakeLists.txt
View File

@ -13,10 +13,6 @@ if(CONFIG_SOC_SYSTIMER_SUPPORT_ETM)
list(APPEND srcs "test_systimer_etm.c")
endif()
if(CONFIG_SOC_MCPWM_SUPPORT_ETM)
list(APPEND srcs "test_mcpwm_etm.c")
endif()
if(CONFIG_SOC_ANA_CMPR_SUPPORT_ETM AND CONFIG_SOC_TIMER_SUPPORT_ETM)
# Analog Comparator event test relies on GPTIMER task
list(APPEND srcs "test_ana_cmpr_etm.c")

27
components/hal/esp32/include/hal/mcpwm_ll.h
View File

@ -112,7 +112,7 @@ static inline void mcpwm_ll_reset_register(int group_id)
#define mcpwm_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; mcpwm_ll_reset_register(__VA_ARGS__)
/**
* @brief Enable MCPWM module clock
* @brief Enable MCPWM function clock
*
* @note Not support to enable/disable the peripheral clock
*
@ -128,25 +128,26 @@ static inline void mcpwm_ll_group_enable_clock(int group_id, bool en)
/**
* @brief Set the clock source for MCPWM
*
* @param mcpwm Peripheral instance address
* @param group_id Group ID
* @param clk_src Clock source for the MCPWM peripheral
*/
static inline void mcpwm_ll_group_set_clock_source(mcpwm_dev_t *mcpwm, mcpwm_timer_clock_source_t clk_src)
static inline void mcpwm_ll_group_set_clock_source(int group_id, mcpwm_timer_clock_source_t clk_src)
{
(void)mcpwm;
(void)group_id;
(void)clk_src;
}
/**
* @brief Set the MCPWM group clock prescale
*
* @param mcpwm Peripheral instance address
* @param group_id Group ID
* @param pre_scale Prescale value
*/
static inline void mcpwm_ll_group_set_clock_prescale(mcpwm_dev_t *mcpwm, int prescale)
static inline void mcpwm_ll_group_set_clock_prescale(int group_id, int prescale)
{
// group clock: PWM_clk = CLK_160M / (prescale)
HAL_ASSERT(prescale <= 256 && prescale > 0);
mcpwm_dev_t *mcpwm = MCPWM_LL_GET_HW(group_id);
HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->clk_cfg, clk_prescale, prescale - 1);
}
@ -220,7 +221,7 @@ static inline uint32_t mcpwm_ll_intr_get_status(mcpwm_dev_t *mcpwm)
* @brief Clear MCPWM interrupt status by mask
*
* @param mcpwm Peripheral instance address
* @param mask Interupt status mask
* @param mask Interrupt status mask
*/
__attribute__((always_inline))
static inline void mcpwm_ll_intr_clear_status(mcpwm_dev_t *mcpwm, uint32_t mask)
@ -1620,18 +1621,6 @@ static inline void mcpwm_ll_capture_set_prescale(mcpwm_dev_t *mcpwm, int channel
/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
static inline uint32_t mcpwm_ll_group_get_clock_prescale(mcpwm_dev_t *mcpwm)
{
return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->clk_cfg, clk_prescale) + 1;
}
static inline uint32_t mcpwm_ll_timer_get_clock_prescale(mcpwm_dev_t *mcpwm, int timer_id)
{
mcpwm_timer_cfg0_reg_t cfg0;
cfg0.val = mcpwm->timer[timer_id].timer_cfg0.val;
return cfg0.timer_prescale + 1;
}
static inline uint32_t mcpwm_ll_timer_get_peak(mcpwm_dev_t *mcpwm, int timer_id, bool symmetric)
{
return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period) + (symmetric ? 0 : 1);

1730
components/hal/esp32c5/include/hal/mcpwm_ll.h Normal file
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File diff suppressed because it is too large Load Diff

29
components/hal/esp32c6/include/hal/mcpwm_ll.h
View File

@ -101,7 +101,7 @@ static inline void mcpwm_ll_reset_register(int group_id)
}
/**
* @brief Enable MCPWM module clock
* @brief Enable MCPWM function clock
*
* @param group_id Group ID
* @param en true to enable, false to disable
@ -115,12 +115,12 @@ static inline void mcpwm_ll_group_enable_clock(int group_id, bool en)
/**
* @brief Set the clock source for MCPWM
*
* @param mcpwm Peripheral instance address
* @param group_id Group ID
* @param clk_src Clock source for the MCPWM peripheral
*/
static inline void mcpwm_ll_group_set_clock_source(mcpwm_dev_t *mcpwm, soc_module_clk_t clk_src)
static inline void mcpwm_ll_group_set_clock_source(int group_id, soc_module_clk_t clk_src)
{
(void)mcpwm; // only one MCPWM instance
(void)group_id;
switch (clk_src) {
case SOC_MOD_CLK_PLL_F160M:
PCR.pwm_clk_conf.pwm_clkm_sel = 1;
@ -137,12 +137,12 @@ static inline void mcpwm_ll_group_set_clock_source(mcpwm_dev_t *mcpwm, soc_modul
/**
* @brief Set the MCPWM group clock prescale
*
* @param mcpwm Peripheral instance address
* @param group_id Group ID
* @param prescale Prescale value
*/
static inline void mcpwm_ll_group_set_clock_prescale(mcpwm_dev_t *mcpwm, int prescale)
static inline void mcpwm_ll_group_set_clock_prescale(int group_id, int prescale)
{
(void)mcpwm; // only one MCPWM instance
(void)group_id;
// group clock: PWM_clk = source_clock / (prescale)
HAL_ASSERT(prescale <= 256 && prescale > 0);
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.pwm_clk_conf, pwm_div_num, prescale - 1);
@ -218,7 +218,7 @@ static inline uint32_t mcpwm_ll_intr_get_status(mcpwm_dev_t *mcpwm)
* @brief Clear MCPWM interrupt status by mask
*
* @param mcpwm Peripheral instance address
* @param mask Interupt status mask
* @param mask Interrupt status mask
*/
__attribute__((always_inline))
static inline void mcpwm_ll_intr_clear_status(mcpwm_dev_t *mcpwm, uint32_t mask)
@ -1649,19 +1649,6 @@ static inline void mcpwm_ll_etm_enable_comparator_event(mcpwm_dev_t *mcpwm, int
/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
static inline uint32_t mcpwm_ll_group_get_clock_prescale(mcpwm_dev_t *mcpwm)
{
(void)mcpwm; // only one MCPWM instance
return HAL_FORCE_READ_U32_REG_FIELD(PCR.pwm_clk_conf, pwm_div_num) + 1;
}
static inline uint32_t mcpwm_ll_timer_get_clock_prescale(mcpwm_dev_t *mcpwm, int timer_id)
{
mcpwm_timer_cfg0_reg_t cfg0;
cfg0.val = mcpwm->timer[timer_id].timer_cfg0.val;
return cfg0.timer_prescale + 1;
}
static inline uint32_t mcpwm_ll_timer_get_peak(mcpwm_dev_t *mcpwm, int timer_id, bool symmetric)
{
return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period) + (symmetric ? 0 : 1);

29
components/hal/esp32h2/include/hal/mcpwm_ll.h
View File

@ -99,7 +99,7 @@ static inline void mcpwm_ll_reset_register(int group_id)
}
/**
* @brief Enable MCPWM module clock
* @brief Enable MCPWM function clock
*
* @param group_id Group ID
* @param en true to enable, false to disable
@ -113,12 +113,12 @@ static inline void mcpwm_ll_group_enable_clock(int group_id, bool en)
/**
* @brief Set the clock source for MCPWM
*
* @param mcpwm Peripheral instance address
* @param group_id Group ID
* @param clk_src Clock source for the MCPWM peripheral
*/
static inline void mcpwm_ll_group_set_clock_source(mcpwm_dev_t *mcpwm, soc_module_clk_t clk_src)
static inline void mcpwm_ll_group_set_clock_source(int group_id, soc_module_clk_t clk_src)
{
(void)mcpwm; // only one MCPWM instance
(void)group_id;
switch (clk_src) {
case SOC_MOD_CLK_XTAL:
PCR.pwm_clk_conf.pwm_clkm_sel = 0;
@ -135,12 +135,12 @@ static inline void mcpwm_ll_group_set_clock_source(mcpwm_dev_t *mcpwm, soc_modul
/**
* @brief Set the MCPWM group clock prescale
*
* @param mcpwm Peripheral instance address
* @param group_id Group ID
* @param prescale Prescale value
*/
static inline void mcpwm_ll_group_set_clock_prescale(mcpwm_dev_t *mcpwm, int prescale)
static inline void mcpwm_ll_group_set_clock_prescale(int group_id, int prescale)
{
(void)mcpwm; // only one MCPWM instance
(void)group_id;
// group clock: PWM_clk = source_clock / (prescale)
HAL_ASSERT(prescale <= 256 && prescale > 0);
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.pwm_clk_conf, pwm_div_num, prescale - 1);
@ -216,7 +216,7 @@ static inline uint32_t mcpwm_ll_intr_get_status(mcpwm_dev_t *mcpwm)
* @brief Clear MCPWM interrupt status by mask
*
* @param mcpwm Peripheral instance address
* @param mask Interupt status mask
* @param mask Interrupt status mask
*/
__attribute__((always_inline))
static inline void mcpwm_ll_intr_clear_status(mcpwm_dev_t *mcpwm, uint32_t mask)
@ -1647,19 +1647,6 @@ static inline void mcpwm_ll_etm_enable_comparator_event(mcpwm_dev_t *mcpwm, int
/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
static inline uint32_t mcpwm_ll_group_get_clock_prescale(mcpwm_dev_t *mcpwm)
{
(void)mcpwm; // only one MCPWM instance
return HAL_FORCE_READ_U32_REG_FIELD(PCR.pwm_clk_conf, pwm_div_num) + 1;
}
static inline uint32_t mcpwm_ll_timer_get_clock_prescale(mcpwm_dev_t *mcpwm, int timer_id)
{
mcpwm_timer_cfg0_reg_t cfg0;
cfg0.val = mcpwm->timer[timer_id].timer_cfg0.val;
return cfg0.timer_prescale + 1;
}
static inline uint32_t mcpwm_ll_timer_get_peak(mcpwm_dev_t *mcpwm, int timer_id, bool symmetric)
{
return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period) + (symmetric ? 0 : 1);

39
components/hal/esp32p4/include/hal/mcpwm_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -15,6 +15,7 @@
#pragma once
#include <stdbool.h>
#include <stdio.h>
#include "soc/soc_caps.h"
#include "soc/mcpwm_struct.h"
#include "soc/clk_tree_defs.h"
@ -22,7 +23,6 @@
#include "hal/mcpwm_types.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include <stdio.h>
#include "soc/soc_etm_source.h"
#ifdef __cplusplus
@ -133,7 +133,7 @@ static inline void mcpwm_ll_reset_register(int group_id)
#define mcpwm_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; mcpwm_ll_reset_register(__VA_ARGS__)
/**
* @brief Enable MCPWM module clock
* @brief Enable MCPWM function clock
*
* @param group_id Group ID
* @param en true to enable, false to disable
@ -154,10 +154,10 @@ static inline void mcpwm_ll_group_enable_clock(int group_id, bool en)
/**
* @brief Set the clock source for MCPWM
*
* @param mcpwm Peripheral instance address
* @param group_id Group ID
* @param clk_src Clock source for the MCPWM peripheral
*/
static inline void mcpwm_ll_group_set_clock_source(mcpwm_dev_t *mcpwm, soc_module_clk_t clk_src)
static inline void mcpwm_ll_group_set_clock_source(int group_id, soc_module_clk_t clk_src)
{
uint8_t clk_id = 0;
switch (clk_src) {
@ -174,9 +174,9 @@ static inline void mcpwm_ll_group_set_clock_source(mcpwm_dev_t *mcpwm, soc_modul
HAL_ASSERT(false);
break;
}
if (mcpwm == &MCPWM0) {
if (group_id == 0) {
HP_SYS_CLKRST.peri_clk_ctrl20.reg_mcpwm0_clk_src_sel = clk_id;
} else if (mcpwm == &MCPWM1) {
} else if (group_id == 1) {
HP_SYS_CLKRST.peri_clk_ctrl20.reg_mcpwm1_clk_src_sel = clk_id;
}
}
@ -188,16 +188,16 @@ static inline void mcpwm_ll_group_set_clock_source(mcpwm_dev_t *mcpwm, soc_modul
/**
* @brief Set the MCPWM group clock prescale
*
* @param mcpwm Peripheral instance address
* @param group_id Group ID
* @param prescale Prescale value
*/
static inline void mcpwm_ll_group_set_clock_prescale(mcpwm_dev_t *mcpwm, int prescale)
static inline void mcpwm_ll_group_set_clock_prescale(int group_id, int prescale)
{
// group clock: PWM_clk = source_clock / (prescale)
HAL_ASSERT(prescale <= 256 && prescale > 0);
if (mcpwm == &MCPWM0) {
if (group_id == 0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl20, reg_mcpwm0_clk_div_num, prescale - 1);
} else if (mcpwm == &MCPWM1) {
} else if (group_id == 1) {
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl20, reg_mcpwm1_clk_div_num, prescale - 1);
}
}
@ -1738,23 +1738,6 @@ static inline void mcpwm_ll_etm_enable_evt_comparator_event(mcpwm_dev_t *mcpwm,
/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
static inline uint32_t mcpwm_ll_group_get_clock_prescale(mcpwm_dev_t *mcpwm)
{
if (mcpwm == &MCPWM0) {
return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl20, reg_mcpwm0_clk_div_num) + 1;
} else if (mcpwm == &MCPWM1) {
return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl20, reg_mcpwm1_clk_div_num) + 1;
}
return 0;
}
static inline uint32_t mcpwm_ll_timer_get_clock_prescale(mcpwm_dev_t *mcpwm, int timer_id)
{
mcpwm_timer_cfg0_reg_t cfg0;
cfg0.val = mcpwm->timer[timer_id].timer_cfg0.val;
return cfg0.timer_prescale + 1;
}
static inline uint32_t mcpwm_ll_timer_get_peak(mcpwm_dev_t *mcpwm, int timer_id, bool symmetric)
{
return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period) + (symmetric ? 0 : 1);

27
components/hal/esp32s3/include/hal/mcpwm_ll.h
View File

@ -108,7 +108,7 @@ static inline void mcpwm_ll_reset_register(int group_id)
#define mcpwm_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; mcpwm_ll_reset_register(__VA_ARGS__)
/**
* @brief Enable MCPWM module clock
* @brief Enable MCPWM function clock
*
* @note Not support to enable/disable the peripheral clock
*
@ -124,25 +124,26 @@ static inline void mcpwm_ll_group_enable_clock(int group_id, bool en)
/**
* @brief Set the clock source for MCPWM
*
* @param mcpwm Peripheral instance address
* @param group_id Group ID
* @param clk_src Clock source for the MCPWM peripheral
*/
static inline void mcpwm_ll_group_set_clock_source(mcpwm_dev_t *mcpwm, mcpwm_timer_clock_source_t clk_src)
static inline void mcpwm_ll_group_set_clock_source(int group_id, mcpwm_timer_clock_source_t clk_src)
{
(void)mcpwm;
(void)group_id;
(void)clk_src;
}
/**
* @brief Set the MCPWM group clock prescale
*
* @param mcpwm Peripheral instance address
* @param group_id Group ID
* @param prescale Prescale value
*/
static inline void mcpwm_ll_group_set_clock_prescale(mcpwm_dev_t *mcpwm, int prescale)
static inline void mcpwm_ll_group_set_clock_prescale(int group_id, int prescale)
{
// group clock: PWM_clk = CLK_160M / (prescale)
HAL_ASSERT(prescale <= 256 && prescale > 0);
mcpwm_dev_t *mcpwm = MCPWM_LL_GET_HW(group_id);
HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->clk_cfg, clk_prescale, prescale - 1);
}
@ -216,7 +217,7 @@ static inline uint32_t mcpwm_ll_intr_get_status(mcpwm_dev_t *mcpwm)
* @brief Clear MCPWM interrupt status by mask
*
* @param mcpwm Peripheral instance address
* @param mask Interupt status mask
* @param mask Interrupt status mask
*/
__attribute__((always_inline))
static inline void mcpwm_ll_intr_clear_status(mcpwm_dev_t *mcpwm, uint32_t mask)
@ -1628,18 +1629,6 @@ static inline void mcpwm_ll_capture_set_prescale(mcpwm_dev_t *mcpwm, int channel
/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
static inline uint32_t mcpwm_ll_group_get_clock_prescale(mcpwm_dev_t *mcpwm)
{
return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->clk_cfg, clk_prescale) + 1;
}
static inline uint32_t mcpwm_ll_timer_get_clock_prescale(mcpwm_dev_t *mcpwm, int timer_id)
{
mcpwm_timer_cfg0_reg_t cfg0;
cfg0.val = mcpwm->timer[timer_id].timer_cfg0.val;
return cfg0.timer_prescale + 1;
}
static inline uint32_t mcpwm_ll_timer_get_peak(mcpwm_dev_t *mcpwm, int timer_id, bool symmetric)
{
return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period) + (symmetric ? 0 : 1);

60
components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
View File

@ -23,6 +23,10 @@ config SOC_PCNT_SUPPORTED
bool
default y
config SOC_MCPWM_SUPPORTED
bool
default y
config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
@ -375,6 +379,62 @@ config SOC_RMT_SUPPORT_XTAL
bool
default y
config SOC_MCPWM_GROUPS
int
default 1
config SOC_MCPWM_TIMERS_PER_GROUP
int
default 3
config SOC_MCPWM_OPERATORS_PER_GROUP
int
default 3
config SOC_MCPWM_COMPARATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GENERATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_EVENT_COMPARATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_TRIGGERS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GPIO_FAULTS_PER_GROUP
int
default 3
config SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP
bool
default y
config SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER
int
default 3
config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP
int
default 3
config SOC_MCPWM_SWSYNC_CAN_PROPAGATE
bool
default y
config SOC_MCPWM_SUPPORT_EVENT_COMPARATOR
bool
default y
config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
bool
default y
config SOC_MPI_MEM_BLOCKS_NUM
int
default 4

18
components/soc/esp32c5/mp/include/soc/clk_tree_defs.h
View File

@ -276,10 +276,14 @@ typedef enum { // TODO: [ESP32C5] IDF-8633 (inherit from C6)
/**
* @brief Type of MCPWM timer clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6)
typedef enum {
MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
#if SOC_CLK_TREE_SUPPORTED
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
#else
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
#endif
} soc_periph_mcpwm_timer_clk_src_t;
/**
@ -290,10 +294,14 @@ typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6)
/**
* @brief Type of MCPWM capture clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6)
typedef enum {
MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
#if SOC_CLK_TREE_SUPPORTED
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
#else
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
#endif
} soc_periph_mcpwm_capture_clk_src_t;
/**
@ -304,10 +312,14 @@ typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6)
/**
* @brief Type of MCPWM carrier clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6)
typedef enum {
MCPWM_CARRIER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_CARRIER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
#if SOC_CLK_TREE_SUPPORTED
MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
#else
MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
#endif
} soc_periph_mcpwm_carrier_clk_src_t;
///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////

6
components/soc/esp32c5/mp/include/soc/mcpwm_reg.h
View File

@ -2764,7 +2764,7 @@ extern "C" {
#define MCPWM_CAP0_MODE_V 0x00000003U
#define MCPWM_CAP0_MODE_S 1
/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
* Configures prescale value on possitive edge of CAP0. Prescale value =
* Configures prescale value on positive edge of CAP0. Prescale value =
* PWM_CAP0_PRESCALE + 1
*/
#define MCPWM_CAP0_PRESCALE 0x000000FFU
@ -2809,7 +2809,7 @@ extern "C" {
#define MCPWM_CAP1_MODE_V 0x00000003U
#define MCPWM_CAP1_MODE_S 1
/** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0;
* Configures prescale value on possitive edge of CAP1. Prescale value =
* Configures prescale value on positive edge of CAP1. Prescale value =
* PWM_CAP1_PRESCALE + 1
*/
#define MCPWM_CAP1_PRESCALE 0x000000FFU
@ -2854,7 +2854,7 @@ extern "C" {
#define MCPWM_CAP2_MODE_V 0x00000003U
#define MCPWM_CAP2_MODE_S 1
/** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0;
* Configures prescale value on possitive edge of CAP2. Prescale value =
* Configures prescale value on positive edge of CAP2. Prescale value =
* PWM_CAP2_PRESCALE + 1
*/
#define MCPWM_CAP2_PRESCALE 0x000000FFU

267
components/soc/esp32c5/mp/include/soc/mcpwm_struct.h
View File

@ -210,33 +210,19 @@ typedef union {
uint32_t val;
} mcpwm_genn_stmp_cfg_reg_t;
/** Type of genn_tstmp_a register
* Generatorn time stamp A's shadow register
/** Type of genn_tstmp register
* Generatorn time stamp shadow register
*/
typedef union {
struct {
/** cmprn_a : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM generator n time stamp A's shadow register.
/** cmprn : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM generator n time stamp shadow register.
*/
uint32_t cmprn_a:16;
uint32_t cmprn:16;
uint32_t reserved_16:16;
};
uint32_t val;
} mcpwm_genn_tstmp_a_reg_t;
/** Type of genn_tstmp_b register
* Generatorn time stamp B's shadow register
*/
typedef union {
struct {
/** cmprn_b : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM generator n time stamp B's shadow register.
*/
uint32_t cmprn_b:16;
uint32_t reserved_16:16;
};
uint32_t val;
} mcpwm_genn_tstmp_b_reg_t;
} mcpwm_genn_tstmp_reg_t;
/** Type of genn_cfg0 register
* Generatorn fault event T0 and T1 configuration register
@ -314,145 +300,75 @@ typedef union {
uint32_t val;
} mcpwm_genn_force_reg_t;
/** Type of genn_a register
/** Type of genn register
* PWMn output signal A actions configuration register
*/
typedef union {
struct {
/** genn_a_utez : R/W; bitpos: [1:0]; default: 0;
/** genn_utez : R/W; bitpos: [1:0]; default: 0;
* Configures action on PWMn A triggered by event TEZ when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_utez:2;
/** genn_a_utep : R/W; bitpos: [3:2]; default: 0;
uint32_t genn_utez:2;
/** genn_utep : R/W; bitpos: [3:2]; default: 0;
* Configures action on PWMn A triggered by event TEP when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_utep:2;
/** genn_a_utea : R/W; bitpos: [5:4]; default: 0;
uint32_t genn_utep:2;
/** genn_utea : R/W; bitpos: [5:4]; default: 0;
* Configures action on PWMn A triggered by event TEA when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_utea:2;
/** genn_a_uteb : R/W; bitpos: [7:6]; default: 0;
uint32_t genn_utea:2;
/** genn_uteb : R/W; bitpos: [7:6]; default: 0;
* Configures action on PWMn A triggered by event TEB when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_uteb:2;
/** genn_a_ut0 : R/W; bitpos: [9:8]; default: 0;
uint32_t genn_uteb:2;
/** genn_ut0 : R/W; bitpos: [9:8]; default: 0;
* Configures action on PWMn A triggered by event_t0 when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_ut0:2;
/** genn_a_ut1 : R/W; bitpos: [11:10]; default: 0;
uint32_t genn_ut0:2;
/** genn_ut1 : R/W; bitpos: [11:10]; default: 0;
* Configures action on PWMn A triggered by event_t1 when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_ut1:2;
/** genn_a_dtez : R/W; bitpos: [13:12]; default: 0;
uint32_t genn_ut1:2;
/** genn_dtez : R/W; bitpos: [13:12]; default: 0;
* Configures action on PWMn A triggered by event TEZ when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_dtez:2;
/** genn_a_dtep : R/W; bitpos: [15:14]; default: 0;
uint32_t genn_dtez:2;
/** genn_dtep : R/W; bitpos: [15:14]; default: 0;
* Configures action on PWMn A triggered by event TEP when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_dtep:2;
/** genn_a_dtea : R/W; bitpos: [17:16]; default: 0;
uint32_t genn_dtep:2;
/** genn_dtea : R/W; bitpos: [17:16]; default: 0;
* Configures action on PWMn A triggered by event TEA when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_dtea:2;
/** genn_a_dteb : R/W; bitpos: [19:18]; default: 0;
uint32_t genn_dtea:2;
/** genn_dteb : R/W; bitpos: [19:18]; default: 0;
* Configures action on PWMn A triggered by event TEB when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_dteb:2;
/** genn_a_dt0 : R/W; bitpos: [21:20]; default: 0;
uint32_t genn_dteb:2;
/** genn_dt0 : R/W; bitpos: [21:20]; default: 0;
* Configures action on PWMn A triggered by event_t0 when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_dt0:2;
/** genn_a_dt1 : R/W; bitpos: [23:22]; default: 0;
uint32_t genn_dt0:2;
/** genn_dt1 : R/W; bitpos: [23:22]; default: 0;
* Configures action on PWMn A triggered by event_t1 when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_dt1:2;
uint32_t genn_dt1:2;
uint32_t reserved_24:8;
};
uint32_t val;
} mcpwm_genn_a_reg_t;
/** Type of genn_b register
* PWMn output signal B actions configuration register
*/
typedef union {
struct {
/** genn_b_utez : R/W; bitpos: [1:0]; default: 0;
* Configures action on PWMn B triggered by event TEZ when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_utez:2;
/** genn_b_utep : R/W; bitpos: [3:2]; default: 0;
* Configures action on PWMn B triggered by event TEP when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_utep:2;
/** genn_b_utea : R/W; bitpos: [5:4]; default: 0;
* Configures action on PWMn B triggered by event TEA when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_utea:2;
/** genn_b_uteb : R/W; bitpos: [7:6]; default: 0;
* Configures action on PWMn B triggered by event TEB when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_uteb:2;
/** genn_b_ut0 : R/W; bitpos: [9:8]; default: 0;
* Configures action on PWMn B triggered by event_t0 when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_ut0:2;
/** genn_b_ut1 : R/W; bitpos: [11:10]; default: 0;
* Configures action on PWMn B triggered by event_t1 when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_ut1:2;
/** genn_b_dtez : R/W; bitpos: [13:12]; default: 0;
* Configures action on PWMn B triggered by event TEZ when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_dtez:2;
/** genn_b_dtep : R/W; bitpos: [15:14]; default: 0;
* Configures action on PWMn B triggered by event TEP when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_dtep:2;
/** genn_b_dtea : R/W; bitpos: [17:16]; default: 0;
* Configures action on PWMn B triggered by event TEA when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_dtea:2;
/** genn_b_dteb : R/W; bitpos: [19:18]; default: 0;
* Configures action on PWMn B triggered by event TEB when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_dteb:2;
/** genn_b_dt0 : R/W; bitpos: [21:20]; default: 0;
* Configures action on PWMn B triggered by event_t0 when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_dt0:2;
/** genn_b_dt1 : R/W; bitpos: [23:22]; default: 0;
* Configures action on PWMn B triggered by event_t1 when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_dt1:2;
uint32_t reserved_24:8;
};
uint32_t val;
} mcpwm_genn_b_reg_t;
} mcpwm_genn_reg_t;
/** Type of dtn_cfg register
* Dead time configuration register
@ -810,7 +726,7 @@ typedef union {
*/
uint32_t capn_mode:2;
/** capn_prescale : R/W; bitpos: [10:3]; default: 0;
* Configures prescale value on possitive edge of CAPn. Prescale value =
* Configures prescale value on positive edge of CAPn. Prescale value =
* PWM_CAPn_PRESCALE + 1
*/
uint32_t capn_prescale:8;
@ -1191,33 +1107,19 @@ typedef union {
uint32_t val;
} mcpwm_evt_en2_reg_t;
/** Type of opn_tstmp_e1 register
* Generatorn timer stamp E1 value register
/** Type of opn_tstmp register
* Generatorn timer stamp value register
*/
typedef union {
struct {
/** opn_tstmp_e1 : R/W; bitpos: [15:0]; default: 0;
/** opn_tstmp_e : R/W; bitpos: [15:0]; default: 0;
* Configures generatorn timer stamp E1 value register
*/
uint32_t opn_tstmp_e1:16;
uint32_t opn_tstmp_e:16;
uint32_t reserved_16:16;
};
uint32_t val;
} mcpwm_opn_tstmp_e1_reg_t;
/** Type of opn_tstmp_e2 register
* Generatorn timer stamp E2 value register
*/
typedef union {
struct {
/** opn_tstmp_e2 : R/W; bitpos: [15:0]; default: 0;
* Configures generatorn timer stamp E2 value register
*/
uint32_t opn_tstmp_e2:16;
uint32_t reserved_16:16;
};
uint32_t val;
} mcpwm_opn_tstmp_e2_reg_t;
} mcpwm_opn_tstmp_reg_t;
/** Type of clk register
* Global configuration register
@ -1234,7 +1136,6 @@ typedef union {
uint32_t val;
} mcpwm_clk_reg_t;
/** Group: Status register */
/** Type of timern_status register
* PWM timern status register.
@ -1309,7 +1210,6 @@ typedef union {
uint32_t val;
} mcpwm_cap_status_reg_t;
/** Group: Interrupt register */
/** Type of int_ena register
* Interrupt enable register
@ -1903,7 +1803,6 @@ typedef union {
uint32_t val;
} mcpwm_int_clr_reg_t;
/** Group: Version register */
/** Type of version register
* Version register.
@ -1919,65 +1818,38 @@ typedef union {
uint32_t val;
} mcpwm_version_reg_t;
typedef struct {
volatile mcpwm_timern_cfg0_reg_t timer_cfg0;
volatile mcpwm_timern_cfg1_reg_t timer_cfg1;
volatile mcpwm_timern_sync_reg_t timer_sync;
volatile mcpwm_timern_status_reg_t timer_status;
} mcpwm_timer_regs_t;
typedef struct {
volatile mcpwm_genn_stmp_cfg_reg_t gen_stmp_cfg;
volatile mcpwm_genn_tstmp_reg_t timestamp[2];
volatile mcpwm_genn_cfg0_reg_t gen_cfg0;
volatile mcpwm_genn_force_reg_t gen_force;
volatile mcpwm_genn_reg_t generator[2];
volatile mcpwm_dtn_cfg_reg_t dt_cfg;
volatile mcpwm_dtn_fed_cfg_reg_t dt_fed_cfg;
volatile mcpwm_dtn_red_cfg_reg_t dt_red_cfg;
volatile mcpwm_carriern_cfg_reg_t carrier_cfg;
volatile mcpwm_fhn_cfg0_reg_t fh_cfg0;
volatile mcpwm_fhn_cfg1_reg_t fh_cfg1;
volatile mcpwm_fhn_status_reg_t fh_status;
} mcpwm_operator_reg_t;
typedef struct {
volatile mcpwm_opn_tstmp_reg_t timestamp[2];
} mcpwm_operator_tstmp_reg_t;
typedef struct mcpwm_dev_t {
volatile mcpwm_clk_cfg_reg_t clk_cfg;
volatile mcpwm_timern_cfg0_reg_t timer0_cfg0;
volatile mcpwm_timern_cfg1_reg_t timer0_cfg1;
volatile mcpwm_timern_sync_reg_t timer0_sync;
volatile mcpwm_timern_status_reg_t timer0_status;
volatile mcpwm_timern_cfg0_reg_t timer1_cfg0;
volatile mcpwm_timern_cfg1_reg_t timer1_cfg1;
volatile mcpwm_timern_sync_reg_t timer1_sync;
volatile mcpwm_timern_status_reg_t timer1_status;
volatile mcpwm_timern_cfg0_reg_t timer2_cfg0;
volatile mcpwm_timern_cfg1_reg_t timer2_cfg1;
volatile mcpwm_timern_sync_reg_t timer2_sync;
volatile mcpwm_timern_status_reg_t timer2_status;
volatile mcpwm_timer_regs_t timer[3];
volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;
volatile mcpwm_operator_timersel_reg_t operator_timersel;
volatile mcpwm_genn_stmp_cfg_reg_t gen0_stmp_cfg;
volatile mcpwm_genn_tstmp_a_reg_t gen0_tstmp_a;
volatile mcpwm_genn_tstmp_b_reg_t gen0_tstmp_b;
volatile mcpwm_genn_cfg0_reg_t gen0_cfg0;
volatile mcpwm_genn_force_reg_t gen0_force;
volatile mcpwm_genn_a_reg_t gen0_a;
volatile mcpwm_genn_b_reg_t gen0_b;
volatile mcpwm_dtn_cfg_reg_t dt0_cfg;
volatile mcpwm_dtn_fed_cfg_reg_t dt0_fed_cfg;
volatile mcpwm_dtn_red_cfg_reg_t dt0_red_cfg;
volatile mcpwm_carriern_cfg_reg_t carrier0_cfg;
volatile mcpwm_fhn_cfg0_reg_t fh0_cfg0;
volatile mcpwm_fhn_cfg1_reg_t fh0_cfg1;
volatile mcpwm_fhn_status_reg_t fh0_status;
volatile mcpwm_genn_stmp_cfg_reg_t gen1_stmp_cfg;
volatile mcpwm_genn_tstmp_a_reg_t gen1_tstmp_a;
volatile mcpwm_genn_tstmp_b_reg_t gen1_tstmp_b;
volatile mcpwm_genn_cfg0_reg_t gen1_cfg0;
volatile mcpwm_genn_force_reg_t gen1_force;
volatile mcpwm_genn_a_reg_t gen1_a;
volatile mcpwm_genn_b_reg_t gen1_b;
volatile mcpwm_dtn_cfg_reg_t dt1_cfg;
volatile mcpwm_dtn_fed_cfg_reg_t dt1_fed_cfg;
volatile mcpwm_dtn_red_cfg_reg_t dt1_red_cfg;
volatile mcpwm_carriern_cfg_reg_t carrier1_cfg;
volatile mcpwm_fhn_cfg0_reg_t fh1_cfg0;
volatile mcpwm_fhn_cfg1_reg_t fh1_cfg1;
volatile mcpwm_fhn_status_reg_t fh1_status;
volatile mcpwm_genn_stmp_cfg_reg_t gen2_stmp_cfg;
volatile mcpwm_genn_tstmp_a_reg_t gen2_tstmp_a;
volatile mcpwm_genn_tstmp_b_reg_t gen2_tstmp_b;
volatile mcpwm_genn_cfg0_reg_t gen2_cfg0;
volatile mcpwm_genn_force_reg_t gen2_force;
volatile mcpwm_genn_a_reg_t gen2_a;
volatile mcpwm_genn_b_reg_t gen2_b;
volatile mcpwm_dtn_cfg_reg_t dt2_cfg;
volatile mcpwm_dtn_fed_cfg_reg_t dt2_fed_cfg;
volatile mcpwm_dtn_red_cfg_reg_t dt2_red_cfg;
volatile mcpwm_carriern_cfg_reg_t carrier2_cfg;
volatile mcpwm_fhn_cfg0_reg_t fh2_cfg0;
volatile mcpwm_fhn_cfg1_reg_t fh2_cfg1;
volatile mcpwm_fhn_status_reg_t fh2_status;
volatile mcpwm_operator_reg_t operators[3];
volatile mcpwm_fault_detect_reg_t fault_detect;
volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg;
volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase;
@ -1992,17 +1864,12 @@ typedef struct {
volatile mcpwm_evt_en_reg_t evt_en;
volatile mcpwm_task_en_reg_t task_en;
volatile mcpwm_evt_en2_reg_t evt_en2;
volatile mcpwm_opn_tstmp_e1_reg_t op0_tstmp_e1;
volatile mcpwm_opn_tstmp_e2_reg_t op0_tstmp_e2;
volatile mcpwm_opn_tstmp_e1_reg_t op1_tstmp_e1;
volatile mcpwm_opn_tstmp_e2_reg_t op1_tstmp_e2;
volatile mcpwm_opn_tstmp_e1_reg_t op2_tstmp_e1;
volatile mcpwm_opn_tstmp_e2_reg_t op2_tstmp_e2;
volatile mcpwm_operator_tstmp_reg_t operators_timestamp[3];
volatile mcpwm_clk_reg_t clk;
volatile mcpwm_version_reg_t version;
} mcpwm_dev_t;
extern mcpwm_dev_t MCPWM;
extern mcpwm_dev_t MCPWM0;
#ifndef __cplusplus
_Static_assert(sizeof(mcpwm_dev_t) == 0x14c, "Invalid size of mcpwm_dev_t structure");

31
components/soc/esp32c5/mp/include/soc/soc_caps.h
View File

@ -24,7 +24,7 @@
#define SOC_AHB_GDMA_SUPPORTED 1
#define SOC_GPTIMER_SUPPORTED 1
#define SOC_PCNT_SUPPORTED 1
// #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8709
#define SOC_MCPWM_SUPPORTED 1
// #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8691
// #define SOC_ETM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8693
// #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8685, IDF-8686
@ -324,19 +324,21 @@
// #define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST as the RMT clock source */
/*-------------------------- MCPWM CAPS --------------------------------------*/
// #define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
// #define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
// #define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
// #define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
// #define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
// #define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
// #define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
// #define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
// #define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
// #define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
// #define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
// #define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix)
// #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
#define SOC_MCPWM_GROUPS 1U ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
#define SOC_MCPWM_TIMERS_PER_GROUP 3 ///< The number of timers that each group has
#define SOC_MCPWM_OPERATORS_PER_GROUP 3 ///< The number of operators that each group has
#define SOC_MCPWM_COMPARATORS_PER_OPERATOR 2 ///< The number of comparators that each operator has
#define SOC_MCPWM_GENERATORS_PER_OPERATOR 2 ///< The number of generators that each operator has
#define SOC_MCPWM_EVENT_COMPARATORS_PER_OPERATOR 2 ///< The number of event comparators that each operator has
#define SOC_MCPWM_TRIGGERS_PER_OPERATOR 2 ///< The number of triggers that each operator has
#define SOC_MCPWM_GPIO_FAULTS_PER_GROUP 3 ///< The number of fault signal detectors that each group has
#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP 1 ///< The number of capture timers that each group has
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER 3 ///< The number of capture channels that each capture timer has
#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP 3 ///< The number of GPIO synchros that each group has
#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE 1 ///< Software sync event can be routed to its output
// #define SOC_MCPWM_SUPPORT_ETM 1 ///< Support ETM (Event Task Matrix)
#define SOC_MCPWM_SUPPORT_EVENT_COMPARATOR 1 ///< Support event comparator (based on ETM)
#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP 1 ///< Capture timer shares clock with other PWM timers
/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
@ -530,7 +532,6 @@
/* macro redefine for pass esp_wifi headers md5sum check */
// #define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE
// #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
// #define SOC_PM_CPU_RETENTION_BY_SW (1)

2
components/soc/esp32c5/mp/ld/esp32c5.peripherals.ld
View File

@ -24,7 +24,7 @@ PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 );
PROVIDE ( INTMTX = 0x60010000 );
PROVIDE ( PCNT = 0x60012000 );
PROVIDE ( SOC_ETM = 0x60013000 );
PROVIDE ( MCPWM = 0x60014000 );
PROVIDE ( MCPWM0 = 0x60014000 );
PROVIDE ( PARL_IO = 0x60015000 );
PROVIDE ( PVT_MONITOR = 0x60019000 );
PROVIDE ( PSRAM_MEM_MONITOR = 0x6001A000 );

83
components/soc/esp32c5/mp/mcpwm_periph.c Normal file
View File

@ -0,0 +1,83 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "soc/mcpwm_periph.h"
#include "soc/gpio_sig_map.h"
const mcpwm_signal_conn_t mcpwm_periph_signals = {
.groups = {
[0] = {
.module = PERIPH_MCPWM0_MODULE,
.irq_id = ETS_MCPWM0_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM0_F0_IN_IDX
},
[1] = {
.fault_sig = PWM0_F1_IN_IDX
},
[2] = {
.fault_sig = PWM0_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM0_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM0_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM0_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM0_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM0_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM0_SYNC2_IN_IDX
}
}
}
}
};

1
docs/docs_not_updated/esp32c5.txt
View File

@ -114,7 +114,6 @@ api-reference/peripherals/etm.rst
api-reference/peripherals/gptimer.rst
api-reference/peripherals/touch_element.rst
api-reference/peripherals/lcd.rst
api-reference/peripherals/mcpwm.rst
api-reference/peripherals/ana_cmpr.rst
api-reference/peripherals/ledc.rst
api-reference/peripherals/temp_sensor.rst

2
docs/en/api-reference/peripherals/mcpwm.rst
View File

@ -111,7 +111,7 @@ The :cpp:func:`mcpwm_new_comparator` will return a pointer to the allocated comp
On the contrary, calling the :cpp:func:`mcpwm_del_comparator` function will free the allocated comparator object.
.. only:: SOC_MCPWM_SUPPORT_EVENT_COMPARATOR
.. only:: SOC_MCPWM_SUPPORT_EVENT_COMPARATOR and SOC_MCPWM_SUPPORT_ETM
There's another kind of comparator called "Event Comparator", which **can not** control the final PWM directly but only generates the ETM events at a configurable time stamp. You can allocate an event comparator by calling the :cpp:func:`mcpwm_new_event_comparator` function. This function will return the same handle type as :cpp:func:`mcpwm_new_comparator`, but with a different configuration structure :cpp:type:`mcpwm_event_comparator_config_t`. For more information, please refer to :ref:`mcpwm-etm-event-and-task`.

2
docs/zh_CN/api-reference/peripherals/mcpwm.rst
View File

@ -111,7 +111,7 @@ MCPWM 比较器
反之，调用 :cpp:func:`mcpwm_del_comparator` 函数将释放已分配的比较器。
.. only:: SOC_MCPWM_SUPPORT_EVENT_COMPARATOR
.. only:: SOC_MCPWM_SUPPORT_EVENT_COMPARATOR and SOC_MCPWM_SUPPORT_ETM
MCPWM 中还有另外一种比较器 —— “事件比较器”，它不能直接控制 PWM 的输出，只能用来产生 EMT 子系统中使用到的事件。事件比较器能够设置的阈值也是可配的。调用 :cpp:func:`mcpwm_new_event_comparator` 函数可以申请一个事件比较器，该函数返回的句柄类型和 :cpp:func:`mcpwm_new_comparator` 函数一样，但是需要的配置结构体是不同的。事件比较器的配置位于 :cpp:type:`mcpwm_event_comparator_config_t`。更多相关内容请参阅 :ref:`mcpwm-etm-event-and-task`。

2
examples/peripherals/mcpwm/mcpwm_servo_control/README.md
View File

@ -62,7 +62,7 @@ I (9345) example: Angle of rotation: 18
...
```
The servo will rotate from -90 degree to 90 degree, and then turn back again.
The servo will rotate from -60 degree to 60 degree, and then turn back again.
## Troubleshooting