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https://github.com/espressif/esp-idf.git
synced 2024-09-20 00:36:01 -04:00
bugfix: fix esp32c6eco1 fosc calibration cycles during sleep
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@ -3,6 +3,15 @@ menu "Hardware Settings"
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menu "Chip revision"
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menu "Chip revision"
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# Insert chip-specific HW config
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# Insert chip-specific HW config
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orsource "./port/$IDF_TARGET/Kconfig.hw_support"
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orsource "./port/$IDF_TARGET/Kconfig.hw_support"
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config ESP_REV_NEW_CHIP_TEST
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bool "Internal test mode"
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depends on IDF_CI_BUILD
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default n
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help
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For internal chip testing, a small number of new versions chips didn't
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update the version field in eFuse, you can enable this option to force the
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software recognize the chip version based on the rev selected in menuconfig.
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endmenu
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endmenu
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orsource "./port/$IDF_TARGET/Kconfig.spiram"
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orsource "./port/$IDF_TARGET/Kconfig.spiram"
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@ -11,11 +11,14 @@ choice ESP32C6_REV_MIN
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config ESP32C6_REV_MIN_0
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config ESP32C6_REV_MIN_0
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bool "Rev v0.0"
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bool "Rev v0.0"
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config ESP32C6_REV_MIN_1
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bool "Rev v0.1 (ECO1)"
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endchoice
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endchoice
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config ESP32C6_REV_MIN_FULL
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config ESP32C6_REV_MIN_FULL
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int
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int
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default 0 if ESP32C6_REV_MIN_0
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default 0 if ESP32C6_REV_MIN_0
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default 1 if ESP32C6_REV_MIN_1
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config ESP_REV_MIN_FULL
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config ESP_REV_MIN_FULL
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int
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int
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@ -103,6 +103,15 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
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&& !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT));
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&& !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT));
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}
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}
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/*The Fosc CLK of calibration circuit is divided by 32 for ECO1.
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So we need to divide the calibrate cycles of the FOSC for ECO1 and above chips by 32 to
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avoid excessive calibration time.*/
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if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
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if (cal_clk == RTC_CAL_RC_FAST) {
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slowclk_cycles = slowclk_cycles >> 5;
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}
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}
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/* Prepare calibration */
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/* Prepare calibration */
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cali_clk_sel);
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cali_clk_sel);
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CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
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CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
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@ -11,11 +11,17 @@ choice ESP32H2_REV_MIN
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config ESP32H2_REV_MIN_0
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config ESP32H2_REV_MIN_0
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bool "Rev v0.0"
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bool "Rev v0.0"
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config ESP32H2_REV_MIN_1
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bool "Rev v0.1 (ECO1)"
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config ESP32H2_REV_MIN_2
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bool "Rev v0.2 (ECO2)"
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endchoice
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endchoice
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config ESP32H2_REV_MIN_FULL
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config ESP32H2_REV_MIN_FULL
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int
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int
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default 0 if ESP32H2_REV_MIN_0
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default 0 if ESP32H2_REV_MIN_0
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default 1 if ESP32H2_REV_MIN_1
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default 2 if ESP32H2_REV_MIN_2
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config ESP_REV_MIN_FULL
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config ESP_REV_MIN_FULL
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int
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int
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@ -102,6 +102,15 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
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&& !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT));
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&& !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT));
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}
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}
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/*The Fosc CLK of calibration circuit is divided by 32 for ECO2.
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So we need to divide the calibrate cycles of the FOSC for ECO1 and above chips by 32 to
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avoid excessive calibration time.*/
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if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) {
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if (cal_clk == RTC_CAL_RC_FAST) {
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slowclk_cycles = slowclk_cycles >> 5;
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}
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}
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/* Prepare calibration */
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/* Prepare calibration */
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cali_clk_sel);
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cali_clk_sel);
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CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
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CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
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@ -99,7 +99,7 @@
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// Cycles for RTC Timer clock source (internal oscillator) calibrate
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// Cycles for RTC Timer clock source (internal oscillator) calibrate
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#define RTC_CLK_SRC_CAL_CYCLES (10)
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#define RTC_CLK_SRC_CAL_CYCLES (10)
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#define FAST_CLK_SRC_CAL_CYCLES (2000) /* ~ 127.4 us */
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#define FAST_CLK_SRC_CAL_CYCLES (2048) /* ~ 127.4 us */
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#ifdef CONFIG_IDF_TARGET_ESP32
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#ifdef CONFIG_IDF_TARGET_ESP32
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#define DEFAULT_SLEEP_OUT_OVERHEAD_US (212)
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#define DEFAULT_SLEEP_OUT_OVERHEAD_US (212)
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@ -16,12 +16,20 @@
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uint32_t efuse_hal_get_major_chip_version(void)
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uint32_t efuse_hal_get_major_chip_version(void)
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{
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{
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#ifdef CONFIG_ESP_REV_NEW_CHIP_TEST
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return CONFIG_ESP_REV_MIN_FULL / 100;
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#else
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return efuse_ll_get_chip_wafer_version_major();
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return efuse_ll_get_chip_wafer_version_major();
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#endif
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}
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}
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uint32_t efuse_hal_get_minor_chip_version(void)
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uint32_t efuse_hal_get_minor_chip_version(void)
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{
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{
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#ifdef CONFIG_ESP_REV_NEW_CHIP_TEST
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return CONFIG_ESP_REV_MIN_FULL % 100;
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#else
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return efuse_ll_get_chip_wafer_version_minor();
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return efuse_ll_get_chip_wafer_version_minor();
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#endif
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}
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}
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/******************* eFuse control functions *************************/
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/******************* eFuse control functions *************************/
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@ -16,12 +16,20 @@
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uint32_t efuse_hal_get_major_chip_version(void)
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uint32_t efuse_hal_get_major_chip_version(void)
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{
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{
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#ifdef CONFIG_ESP_REV_NEW_CHIP_TEST
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return CONFIG_ESP_REV_MIN_FULL / 100;
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#else
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return efuse_ll_get_chip_wafer_version_major();
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return efuse_ll_get_chip_wafer_version_major();
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#endif
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}
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}
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uint32_t efuse_hal_get_minor_chip_version(void)
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uint32_t efuse_hal_get_minor_chip_version(void)
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{
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{
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#ifdef CONFIG_ESP_REV_NEW_CHIP_TEST
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return CONFIG_ESP_REV_MIN_FULL % 100;
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#else
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return efuse_ll_get_chip_wafer_version_minor();
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return efuse_ll_get_chip_wafer_version_minor();
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#endif
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}
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}
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/******************* eFuse control functions *************************/
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/******************* eFuse control functions *************************/
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