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Merge branch 'bugfix/workaround_reset_eof_counter_c3_v5.2' into 'release/v5.2'

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fix(adc): workaround to fix adc continuous get less results on c3 (v5.2)

See merge request espressif/esp-idf!29136
This commit is contained in:
Michael (XIAO Xufeng) 2024-02-21 20:08:57 +08:00
commit db3aa57a9b
5 changed files with 43 additions and 8 deletions
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5
components/esp_adc/adc_continuous.c
View File

@ -413,6 +413,11 @@ esp_err_t adc_continuous_stop(adc_continuous_handle_t handle)
//stop ADC
adc_hal_digi_stop(&handle->hal);
#if ADC_LL_WORKAROUND_CLEAR_EOF_COUNTER
periph_module_reset(PERIPH_SARADC_MODULE);
adc_hal_digi_clr_eof();
#endif
adc_hal_digi_deinit(&handle->hal);
if (handle->use_adc2) {

7
components/esp_adc/test_apps/adc/main/test_adc_driver.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -264,10 +264,8 @@ TEST_CASE("ADC continuous flush internal pool", "[adc_continuous][mannual][ignor
TEST_ESP_OK(adc_continuous_deinit(handle));
}
#if !CONFIG_IDF_TARGET_ESP32C3 //TODO: DIG-270
#define ADC_RESTART_TEST_SIZE 4096
#define ADC_READ_TEST_COUNT 10
#define ADC_READ_TEST_COUNT 100
TEST_CASE("ADC continuous test after restarting", "[adc_continuous]")
{
@ -313,7 +311,6 @@ TEST_CASE("ADC continuous test after restarting", "[adc_continuous]")
TEST_ESP_OK(adc_continuous_deinit(handle));
free(result);
}
#endif //!CONFIG_IDF_TARGET_ESP32C3
#if SOC_ADC_DIG_IIR_FILTER_SUPPORTED
TEST_CASE("ADC filter exhausted allocation", "[adc_continuous]")

9
components/hal/adc_hal.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -358,3 +358,10 @@ void adc_hal_digi_stop(adc_hal_dma_ctx_t *hal)
//disconnect DMA and peripheral
adc_ll_digi_dma_disable();
}
#if ADC_LL_WORKAROUND_CLEAR_EOF_COUNTER
void adc_hal_digi_clr_eof(void)
{
adc_ll_digi_dma_clr_eof();
}
#endif

21
components/hal/esp32c3/include/hal/adc_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -59,6 +59,13 @@ extern "C" {
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10
/**
* Workaround: on ESP32C3, the internal hardware counter that counts ADC samples will not be automatically cleared,
* and there is no dedicated register to manually clear it. (see section 3.2 of the errata document).
* Therefore, traverse from 0 to the value configured last time, so as to clear the ADC sample counter.
*/
#define ADC_LL_WORKAROUND_CLEAR_EOF_COUNTER (1)
/*---------------------------------------------------------------
PWDET (Power Detect)
---------------------------------------------------------------*/
@ -486,6 +493,18 @@ static inline void adc_ll_digi_dma_set_eof_num(uint32_t num)
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num);
}
/**
* Clear ADC sample counter of adc digital controller.
*/
static inline void adc_ll_digi_dma_clr_eof(void)
{
uint32_t eof_num = HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num);
for (int i = 0; i <= eof_num; i++)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, i);
}
}
/**
* Enable output data to DMA from adc digital controller.
*/

9
components/hal/include/hal/adc_hal.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -207,6 +207,13 @@ void adc_hal_digi_dis_intr(adc_hal_dma_ctx_t *hal, uint32_t mask);
*/
void adc_hal_digi_stop(adc_hal_dma_ctx_t *hal);
#if ADC_LL_WORKAROUND_CLEAR_EOF_COUNTER
/**
* @brief Clear the ADC sample counter
*/
void adc_hal_digi_clr_eof(void);
#endif
#ifdef __cplusplus
}
#endif