diff --git a/components/esp_hw_support/port/esp32c3/i2c_rtc_clk.h b/components/esp_hw_support/port/esp32c3/i2c_rtc_clk.h deleted file mode 100644 index dbb7d73dc4..0000000000 --- a/components/esp_hw_support/port/esp32c3/i2c_rtc_clk.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include "regi2c_ctrl.h" - -/* Analog function control register */ -#define ANA_CONFIG_REG 0x6000E044 -#define ANA_CONFIG_S (8) -#define ANA_CONFIG_M (0x3FF) -/* Clear to enable APLL */ -#define I2C_APLL_M (BIT(14)) -/* Clear to enable BBPLL */ -#define I2C_BBPLL_M (BIT(17)) - -/* ROM functions which read/write internal control bus */ -uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add); -uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb); -void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data); -void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data); - -/* Convenience macros for the above functions, these use register definitions - * from i2c_apll.h/i2c_bbpll.h header files. - */ -#define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \ - rom_i2c_writeReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata) - -#define I2C_READREG_MASK_RTC(block, reg_add) \ - rom_i2c_readReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB) - -#define I2C_WRITEREG_RTC(block, reg_add, indata) \ - rom_i2c_writeReg(block, block##_HOSTID, reg_add, indata) - -#define I2C_READREG_RTC(block, reg_add) \ - rom_i2c_readReg(block, block##_HOSTID, reg_add) diff --git a/components/esp_hw_support/port/esp32h2/i2c_rtc_clk.h b/components/esp_hw_support/port/esp32h2/i2c_rtc_clk.h deleted file mode 100644 index dbb7d73dc4..0000000000 --- a/components/esp_hw_support/port/esp32h2/i2c_rtc_clk.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include "regi2c_ctrl.h" - -/* Analog function control register */ -#define ANA_CONFIG_REG 0x6000E044 -#define ANA_CONFIG_S (8) -#define ANA_CONFIG_M (0x3FF) -/* Clear to enable APLL */ -#define I2C_APLL_M (BIT(14)) -/* Clear to enable BBPLL */ -#define I2C_BBPLL_M (BIT(17)) - -/* ROM functions which read/write internal control bus */ -uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add); -uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb); -void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data); -void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data); - -/* Convenience macros for the above functions, these use register definitions - * from i2c_apll.h/i2c_bbpll.h header files. - */ -#define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \ - rom_i2c_writeReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata) - -#define I2C_READREG_MASK_RTC(block, reg_add) \ - rom_i2c_readReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB) - -#define I2C_WRITEREG_RTC(block, reg_add, indata) \ - rom_i2c_writeReg(block, block##_HOSTID, reg_add, indata) - -#define I2C_READREG_RTC(block, reg_add) \ - rom_i2c_readReg(block, block##_HOSTID, reg_add) diff --git a/components/esp_hw_support/port/esp8684/i2c_rtc_clk.h b/components/esp_hw_support/port/esp8684/i2c_rtc_clk.h deleted file mode 100644 index dbb7d73dc4..0000000000 --- a/components/esp_hw_support/port/esp8684/i2c_rtc_clk.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include "regi2c_ctrl.h" - -/* Analog function control register */ -#define ANA_CONFIG_REG 0x6000E044 -#define ANA_CONFIG_S (8) -#define ANA_CONFIG_M (0x3FF) -/* Clear to enable APLL */ -#define I2C_APLL_M (BIT(14)) -/* Clear to enable BBPLL */ -#define I2C_BBPLL_M (BIT(17)) - -/* ROM functions which read/write internal control bus */ -uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add); -uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb); -void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data); -void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data); - -/* Convenience macros for the above functions, these use register definitions - * from i2c_apll.h/i2c_bbpll.h header files. - */ -#define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \ - rom_i2c_writeReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata) - -#define I2C_READREG_MASK_RTC(block, reg_add) \ - rom_i2c_readReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB) - -#define I2C_WRITEREG_RTC(block, reg_add, indata) \ - rom_i2c_writeReg(block, block##_HOSTID, reg_add, indata) - -#define I2C_READREG_RTC(block, reg_add) \ - rom_i2c_readReg(block, block##_HOSTID, reg_add) diff --git a/components/esp_hw_support/port/esp8684/rtc_clk_init.c b/components/esp_hw_support/port/esp8684/rtc_clk_init.c index 8b573ba0d5..57d8062007 100644 --- a/components/esp_hw_support/port/esp8684/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp8684/rtc_clk_init.c @@ -14,7 +14,6 @@ #include "soc/rtc.h" #include "soc/rtc_periph.h" #include "soc/efuse_periph.h" -#include "soc/apb_ctrl_reg.h" #include "hal/cpu_hal.h" #include "regi2c_ctrl.h" #include "soc_log.h" diff --git a/components/esp_hw_support/port/esp8684/rtc_pm.c b/components/esp_hw_support/port/esp8684/rtc_pm.c index c73ae9edf3..1790d1fdd8 100644 --- a/components/esp_hw_support/port/esp8684/rtc_pm.c +++ b/components/esp_hw_support/port/esp8684/rtc_pm.c @@ -8,7 +8,6 @@ #include #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" -#include "soc/apb_ctrl_reg.h" typedef enum { PM_LIGHT_SLEEP = BIT(2), /*!< WiFi PD, memory in light sleep */ diff --git a/components/esp_hw_support/port/esp8684/rtc_sleep.c b/components/esp_hw_support/port/esp8684/rtc_sleep.c index e0b5f251d2..acd30c3a69 100644 --- a/components/esp_hw_support/port/esp8684/rtc_sleep.c +++ b/components/esp_hw_support/port/esp8684/rtc_sleep.c @@ -9,7 +9,7 @@ #include "soc/soc.h" #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" -#include "soc/apb_ctrl_reg.h" +#include "soc/syscon_reg.h" #include "soc/rtc.h" #include "soc/bb_reg.h" #include "soc/nrx_reg.h" @@ -29,9 +29,9 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg) { REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu); - REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_DC_MEM_FORCE_PU, cfg.fe_fpu); - REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_PBUS_MEM_FORCE_PU, cfg.fe_fpu); - REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_AGC_MEM_FORCE_PU, cfg.fe_fpu); + REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu); + REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu); + REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu); REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu); REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu); REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu); @@ -40,14 +40,14 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg) REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu); REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu); if (cfg.sram_fpu) { - REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_SRAM_POWER_UP, APB_CTRL_SRAM_POWER_UP); + REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, SYSCON_SRAM_POWER_UP); } else { - REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_SRAM_POWER_UP, 0); + REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, 0); } if (cfg.rom_ram_fpu) { - REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_ROM_POWER_UP, APB_CTRL_ROM_POWER_UP); + REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, SYSCON_ROM_POWER_UP); } else { - REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_ROM_POWER_UP, 0); + REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, 0); } } diff --git a/components/esp_rom/include/esp8684/rom/rtc.h b/components/esp_rom/include/esp8684/rom/rtc.h index 258a1ecbec..be3562de97 100644 --- a/components/esp_rom/include/esp8684/rom/rtc.h +++ b/components/esp_rom/include/esp8684/rom/rtc.h @@ -101,13 +101,11 @@ typedef enum { MAC_TRIG = BIT5, UART0_TRIG = BIT6, UART1_TRIG = BIT7, - TOUCH_TRIG = BIT8, SAR_TRIG = BIT9, BT_TRIG = BIT10, RISCV_TRIG = BIT11, XTAL_DEAD_TRIG = BIT12, - RISCV_TRAP_TRIG = BIT13, - USB_TRIG = BIT14 + RISCV_TRAP_TRIG = BIT13 } WAKEUP_REASON; typedef enum { @@ -120,13 +118,11 @@ typedef enum { MAC_TRIG_EN = MAC_TRIG, UART0_TRIG_EN = UART0_TRIG, UART1_TRIG_EN = UART1_TRIG, - TOUCH_TRIG_EN = TOUCH_TRIG, SAR_TRIG_EN = SAR_TRIG, BT_TRIG_EN = BT_TRIG, RISCV_TRIG_EN = RISCV_TRIG, XTAL_DEAD_TRIG_EN = XTAL_DEAD_TRIG, - RISCV_TRAP_TRIG_EN = RISCV_TRAP_TRIG, - USB_TRIG_EN = USB_TRIG + RISCV_TRAP_TRIG_EN = RISCV_TRAP_TRIG } WAKEUP_ENABLE; /** diff --git a/components/hal/esp8684/include/hal/rtc_cntl_ll.h b/components/hal/esp8684/include/hal/rtc_cntl_ll.h index 56b2a07ed9..5d3b4a2723 100644 --- a/components/hal/esp8684/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp8684/include/hal/rtc_cntl_ll.h @@ -9,7 +9,7 @@ #include "soc/soc.h" #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" -#include "soc/apb_ctrl_reg.h" +#include "soc/syscon_reg.h" #ifdef __cplusplus extern "C" { @@ -42,7 +42,7 @@ static inline void rtc_cntl_ll_gpio_clear_wakeup_pins(void) static inline void rtc_cntl_ll_enable_cpu_retention(uint32_t addr) { /* write memory address to register */ - REG_SET_FIELD(APB_CTRL_RETENTION_CTRL_REG, APB_CTRL_RETENTION_LINK_ADDR, (uint32_t)addr); + REG_SET_FIELD(SYSCON_RETENTION_CTRL_REG, SYSCON_RETENTION_LINK_ADDR, (uint32_t)addr); /* Enable clock */ REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); /* Enable retention when cpu sleep enable */ diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index 72dbb15a60..bd2d552514 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -20,8 +12,6 @@ #include "esp_bit_defs.h" #endif -#include "sdkconfig.h" - #define PRO_CPU_NUM (0) #define DR_REG_SYSTEM_BASE 0x600c0000 diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index 649612ac0a..69a3fa0b9f 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -12,8 +12,6 @@ #include "esp_bit_defs.h" #endif -#include "sdkconfig.h" - #define PRO_CPU_NUM (0) #define DR_REG_SYSTEM_BASE 0x600c0000 diff --git a/components/soc/esp8684/include/soc/Kconfig.soc_caps.in b/components/soc/esp8684/include/soc/Kconfig.soc_caps.in index eb34021dbe..7d649da742 100644 --- a/components/soc/esp8684/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp8684/include/soc/Kconfig.soc_caps.in @@ -235,46 +235,6 @@ config SOC_MPU_REGION_WO_SUPPORTED bool default n -config SOC_RMT_GROUPS - int - default 1 - -config SOC_RMT_TX_CANDIDATES_PER_GROUP - int - default 2 - -config SOC_RMT_RX_CANDIDATES_PER_GROUP - int - default 2 - -config SOC_RMT_CHANNELS_PER_GROUP - int - default 4 - -config SOC_RMT_MEM_WORDS_PER_CHANNEL - int - default 48 - -config SOC_RMT_SUPPORT_RX_PINGPONG - bool - default y - -config SOC_RMT_SUPPORT_RX_DEMODULATION - bool - default y - -config SOC_RMT_SUPPORT_TX_LOOP_COUNT - bool - default y - -config SOC_RMT_SUPPORT_TX_SYNCHRO - bool - default y - -config SOC_RMT_SUPPORT_XTAL - bool - default y - config SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH int default 128 diff --git a/components/soc/esp8684/include/soc/apb_ctrl_reg.h b/components/soc/esp8684/include/soc/apb_ctrl_reg.h deleted file mode 100644 index 00170232aa..0000000000 --- a/components/soc/esp8684/include/soc/apb_ctrl_reg.h +++ /dev/null @@ -1,584 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_APB_CTRL_REG_H_ -#define _SOC_APB_CTRL_REG_H_ - - -#ifdef __cplusplus -extern "C" { -#endif -#include "soc.h" - -#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0) -/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: reg_rst_tick_cnt.*/ -#define APB_CTRL_RST_TICK_CNT (BIT(12)) -#define APB_CTRL_RST_TICK_CNT_M (BIT(12)) -#define APB_CTRL_RST_TICK_CNT_V 0x1 -#define APB_CTRL_RST_TICK_CNT_S 12 -/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: reg_clk_en.*/ -#define APB_CTRL_CLK_EN (BIT(11)) -#define APB_CTRL_CLK_EN_M (BIT(11)) -#define APB_CTRL_CLK_EN_V 0x1 -#define APB_CTRL_CLK_EN_S 11 -/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: reg_clk_320m_en.*/ -#define APB_CTRL_CLK_320M_EN (BIT(10)) -#define APB_CTRL_CLK_320M_EN_M (BIT(10)) -#define APB_CTRL_CLK_320M_EN_V 0x1 -#define APB_CTRL_CLK_320M_EN_S 10 -/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ -/*description: reg_pre_div_cnt.*/ -#define APB_CTRL_PRE_DIV_CNT 0x000003FF -#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S)) -#define APB_CTRL_PRE_DIV_CNT_V 0x3FF -#define APB_CTRL_PRE_DIV_CNT_S 0 - -#define APB_CTRL_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x4) -/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */ -/*description: reg_tick_enable.*/ -#define APB_CTRL_TICK_ENABLE (BIT(16)) -#define APB_CTRL_TICK_ENABLE_M (BIT(16)) -#define APB_CTRL_TICK_ENABLE_V 0x1 -#define APB_CTRL_TICK_ENABLE_S 16 -/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */ -/*description: reg_ck8m_tick_num.*/ -#define APB_CTRL_CK8M_TICK_NUM 0x000000FF -#define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S)) -#define APB_CTRL_CK8M_TICK_NUM_V 0xFF -#define APB_CTRL_CK8M_TICK_NUM_S 8 -/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ -/*description: reg_xtal_tick_num.*/ -#define APB_CTRL_XTAL_TICK_NUM 0x000000FF -#define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S)) -#define APB_CTRL_XTAL_TICK_NUM_V 0xFF -#define APB_CTRL_XTAL_TICK_NUM_S 0 - -#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x8) -/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: reg_clk_xtal_oen.*/ -#define APB_CTRL_CLK_XTAL_OEN (BIT(10)) -#define APB_CTRL_CLK_XTAL_OEN_M (BIT(10)) -#define APB_CTRL_CLK_XTAL_OEN_V 0x1 -#define APB_CTRL_CLK_XTAL_OEN_S 10 -/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: reg_clk40x_bb_oen.*/ -#define APB_CTRL_CLK40X_BB_OEN (BIT(9)) -#define APB_CTRL_CLK40X_BB_OEN_M (BIT(9)) -#define APB_CTRL_CLK40X_BB_OEN_V 0x1 -#define APB_CTRL_CLK40X_BB_OEN_S 9 -/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: reg_clk_dac_cpu_oen.*/ -#define APB_CTRL_CLK_DAC_CPU_OEN (BIT(8)) -#define APB_CTRL_CLK_DAC_CPU_OEN_M (BIT(8)) -#define APB_CTRL_CLK_DAC_CPU_OEN_V 0x1 -#define APB_CTRL_CLK_DAC_CPU_OEN_S 8 -/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: reg_clk_adc_inf_oen.*/ -#define APB_CTRL_CLK_ADC_INF_OEN (BIT(7)) -#define APB_CTRL_CLK_ADC_INF_OEN_M (BIT(7)) -#define APB_CTRL_CLK_ADC_INF_OEN_V 0x1 -#define APB_CTRL_CLK_ADC_INF_OEN_S 7 -/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: reg_clk_320m_oen.*/ -#define APB_CTRL_CLK_320M_OEN (BIT(6)) -#define APB_CTRL_CLK_320M_OEN_M (BIT(6)) -#define APB_CTRL_CLK_320M_OEN_V 0x1 -#define APB_CTRL_CLK_320M_OEN_S 6 -/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: reg_clk160_oen.*/ -#define APB_CTRL_CLK160_OEN (BIT(5)) -#define APB_CTRL_CLK160_OEN_M (BIT(5)) -#define APB_CTRL_CLK160_OEN_V 0x1 -#define APB_CTRL_CLK160_OEN_S 5 -/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: reg_clk80_oen.*/ -#define APB_CTRL_CLK80_OEN (BIT(4)) -#define APB_CTRL_CLK80_OEN_M (BIT(4)) -#define APB_CTRL_CLK80_OEN_V 0x1 -#define APB_CTRL_CLK80_OEN_S 4 -/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: reg_clk_bb_oen.*/ -#define APB_CTRL_CLK_BB_OEN (BIT(3)) -#define APB_CTRL_CLK_BB_OEN_M (BIT(3)) -#define APB_CTRL_CLK_BB_OEN_V 0x1 -#define APB_CTRL_CLK_BB_OEN_S 3 -/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: reg_clk44_oen.*/ -#define APB_CTRL_CLK44_OEN (BIT(2)) -#define APB_CTRL_CLK44_OEN_M (BIT(2)) -#define APB_CTRL_CLK44_OEN_V 0x1 -#define APB_CTRL_CLK44_OEN_S 2 -/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: reg_clk22_oen.*/ -#define APB_CTRL_CLK22_OEN (BIT(1)) -#define APB_CTRL_CLK22_OEN_M (BIT(1)) -#define APB_CTRL_CLK22_OEN_V 0x1 -#define APB_CTRL_CLK22_OEN_S 1 -/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: reg_clk20_oen.*/ -#define APB_CTRL_CLK20_OEN (BIT(0)) -#define APB_CTRL_CLK20_OEN_M (BIT(0)) -#define APB_CTRL_CLK20_OEN_V 0x1 -#define APB_CTRL_CLK20_OEN_S 0 - -#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0xC) -/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: reg_wifi_bb_cfg.*/ -#define APB_CTRL_WIFI_BB_CFG 0xFFFFFFFF -#define APB_CTRL_WIFI_BB_CFG_M ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S)) -#define APB_CTRL_WIFI_BB_CFG_V 0xFFFFFFFF -#define APB_CTRL_WIFI_BB_CFG_S 0 - -#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x10) -/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: reg_wifi_bb_cfg_2.*/ -#define APB_CTRL_WIFI_BB_CFG_2 0xFFFFFFFF -#define APB_CTRL_WIFI_BB_CFG_2_M ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S)) -#define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF -#define APB_CTRL_WIFI_BB_CFG_2_S 0 - -#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x14) -/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ -/*description: reg_wifi_clk_en.*/ -#define APB_CTRL_WIFI_CLK_EN 0xFFFFFFFF -#define APB_CTRL_WIFI_CLK_EN_M ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S)) -#define APB_CTRL_WIFI_CLK_EN_V 0xFFFFFFFF -#define APB_CTRL_WIFI_CLK_EN_S 0 - -#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x18) -/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: reg_wifi_rst.*/ -#define APB_CTRL_WIFI_RST 0xFFFFFFFF -#define APB_CTRL_WIFI_RST_M ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S)) -#define APB_CTRL_WIFI_RST_V 0xFFFFFFFF -#define APB_CTRL_WIFI_RST_S 0 - -#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x1C) -/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: reg_peri_io_swap.*/ -#define APB_CTRL_PERI_IO_SWAP 0x000000FF -#define APB_CTRL_PERI_IO_SWAP_M ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S)) -#define APB_CTRL_PERI_IO_SWAP_V 0xFF -#define APB_CTRL_PERI_IO_SWAP_S 0 - -#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x20) -/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: reg_ext_mem_pms_lock.*/ -#define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0)) -#define APB_CTRL_EXT_MEM_PMS_LOCK_M (BIT(0)) -#define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x1 -#define APB_CTRL_EXT_MEM_PMS_LOCK_S 0 - -#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x28) -/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ -/*description: reg_flash_ace0_attr.*/ -#define APB_CTRL_FLASH_ACE0_ATTR 0x00000003 -#define APB_CTRL_FLASH_ACE0_ATTR_M ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S)) -#define APB_CTRL_FLASH_ACE0_ATTR_V 0x3 -#define APB_CTRL_FLASH_ACE0_ATTR_S 0 - -#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x2C) -/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ -/*description: reg_flash_ace1_attr.*/ -#define APB_CTRL_FLASH_ACE1_ATTR 0x00000003 -#define APB_CTRL_FLASH_ACE1_ATTR_M ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S)) -#define APB_CTRL_FLASH_ACE1_ATTR_V 0x3 -#define APB_CTRL_FLASH_ACE1_ATTR_S 0 - -#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x30) -/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ -/*description: reg_flash_ace2_attr.*/ -#define APB_CTRL_FLASH_ACE2_ATTR 0x00000003 -#define APB_CTRL_FLASH_ACE2_ATTR_M ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S)) -#define APB_CTRL_FLASH_ACE2_ATTR_V 0x3 -#define APB_CTRL_FLASH_ACE2_ATTR_S 0 - -#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x34) -/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ -/*description: reg_flash_ace3_attr.*/ -#define APB_CTRL_FLASH_ACE3_ATTR 0x00000003 -#define APB_CTRL_FLASH_ACE3_ATTR_M ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S)) -#define APB_CTRL_FLASH_ACE3_ATTR_V 0x3 -#define APB_CTRL_FLASH_ACE3_ATTR_S 0 - -#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x38) -/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: reg_flash_ace0_addr_s.*/ -#define APB_CTRL_FLASH_ACE0_ADDR_S 0xFFFFFFFF -#define APB_CTRL_FLASH_ACE0_ADDR_S_M ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S)) -#define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF -#define APB_CTRL_FLASH_ACE0_ADDR_S_S 0 - -#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x3C) -/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */ -/*description: reg_flash_ace1_addr_s.*/ -#define APB_CTRL_FLASH_ACE1_ADDR_S 0xFFFFFFFF -#define APB_CTRL_FLASH_ACE1_ADDR_S_M ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S)) -#define APB_CTRL_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF -#define APB_CTRL_FLASH_ACE1_ADDR_S_S 0 - -#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x40) -/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */ -/*description: reg_flash_ace2_addr_s.*/ -#define APB_CTRL_FLASH_ACE2_ADDR_S 0xFFFFFFFF -#define APB_CTRL_FLASH_ACE2_ADDR_S_M ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S)) -#define APB_CTRL_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF -#define APB_CTRL_FLASH_ACE2_ADDR_S_S 0 - -#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x44) -/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hc00000 ; */ -/*description: reg_flash_ace3_addr_s.*/ -#define APB_CTRL_FLASH_ACE3_ADDR_S 0xFFFFFFFF -#define APB_CTRL_FLASH_ACE3_ADDR_S_M ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S)) -#define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF -#define APB_CTRL_FLASH_ACE3_ADDR_S_S 0 - -#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x48) -/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ -/*description: reg_flash_ace0_size.*/ -#define APB_CTRL_FLASH_ACE0_SIZE 0x00001FFF -#define APB_CTRL_FLASH_ACE0_SIZE_M ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S)) -#define APB_CTRL_FLASH_ACE0_SIZE_V 0x1FFF -#define APB_CTRL_FLASH_ACE0_SIZE_S 0 - -#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x4C) -/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ -/*description: reg_flash_ace1_size.*/ -#define APB_CTRL_FLASH_ACE1_SIZE 0x00001FFF -#define APB_CTRL_FLASH_ACE1_SIZE_M ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S)) -#define APB_CTRL_FLASH_ACE1_SIZE_V 0x1FFF -#define APB_CTRL_FLASH_ACE1_SIZE_S 0 - -#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x50) -/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ -/*description: reg_flash_ace2_size.*/ -#define APB_CTRL_FLASH_ACE2_SIZE 0x00001FFF -#define APB_CTRL_FLASH_ACE2_SIZE_M ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S)) -#define APB_CTRL_FLASH_ACE2_SIZE_V 0x1FFF -#define APB_CTRL_FLASH_ACE2_SIZE_S 0 - -#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x54) -/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ -/*description: reg_flash_ace3_size.*/ -#define APB_CTRL_FLASH_ACE3_SIZE 0x00001FFF -#define APB_CTRL_FLASH_ACE3_SIZE_M ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S)) -#define APB_CTRL_FLASH_ACE3_SIZE_V 0x1FFF -#define APB_CTRL_FLASH_ACE3_SIZE_S 0 - -#define APB_CTRL_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x88) -/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ -/*description: reg_spi_mem_reject_cde.*/ -#define APB_CTRL_SPI_MEM_REJECT_CDE 0x0000001F -#define APB_CTRL_SPI_MEM_REJECT_CDE_M ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S)) -#define APB_CTRL_SPI_MEM_REJECT_CDE_V 0x1F -#define APB_CTRL_SPI_MEM_REJECT_CDE_S 2 -/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ -/*description: reg_spi_mem_reject_clr.*/ -#define APB_CTRL_SPI_MEM_REJECT_CLR (BIT(1)) -#define APB_CTRL_SPI_MEM_REJECT_CLR_M (BIT(1)) -#define APB_CTRL_SPI_MEM_REJECT_CLR_V 0x1 -#define APB_CTRL_SPI_MEM_REJECT_CLR_S 1 -/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: reg_spi_mem_reject_int.*/ -#define APB_CTRL_SPI_MEM_REJECT_INT (BIT(0)) -#define APB_CTRL_SPI_MEM_REJECT_INT_M (BIT(0)) -#define APB_CTRL_SPI_MEM_REJECT_INT_V 0x1 -#define APB_CTRL_SPI_MEM_REJECT_INT_S 0 - -#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x8C) -/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: reg_spi_mem_reject_addr.*/ -#define APB_CTRL_SPI_MEM_REJECT_ADDR 0xFFFFFFFF -#define APB_CTRL_SPI_MEM_REJECT_ADDR_M ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S)) -#define APB_CTRL_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF -#define APB_CTRL_SPI_MEM_REJECT_ADDR_S 0 - -#define APB_CTRL_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x90) -/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: reg_sdio_win_access_en.*/ -#define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0)) -#define APB_CTRL_SDIO_WIN_ACCESS_EN_M (BIT(0)) -#define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x1 -#define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0 - -#define APB_CTRL_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x94) -/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: reg_redcy_andor.*/ -#define APB_CTRL_REDCY_ANDOR (BIT(31)) -#define APB_CTRL_REDCY_ANDOR_M (BIT(31)) -#define APB_CTRL_REDCY_ANDOR_V 0x1 -#define APB_CTRL_REDCY_ANDOR_S 31 -/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ -/*description: reg_redcy_sig0.*/ -#define APB_CTRL_REDCY_SIG0 0x7FFFFFFF -#define APB_CTRL_REDCY_SIG0_M ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S)) -#define APB_CTRL_REDCY_SIG0_V 0x7FFFFFFF -#define APB_CTRL_REDCY_SIG0_S 0 - -#define APB_CTRL_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x98) -/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: reg_redcy_nandor.*/ -#define APB_CTRL_REDCY_NANDOR (BIT(31)) -#define APB_CTRL_REDCY_NANDOR_M (BIT(31)) -#define APB_CTRL_REDCY_NANDOR_V 0x1 -#define APB_CTRL_REDCY_NANDOR_S 31 -/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ -/*description: reg_redcy_sig1.*/ -#define APB_CTRL_REDCY_SIG1 0x7FFFFFFF -#define APB_CTRL_REDCY_SIG1_M ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S)) -#define APB_CTRL_REDCY_SIG1_V 0x7FFFFFFF -#define APB_CTRL_REDCY_SIG1_S 0 - -#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x9C) -/* APB_CTRL_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: reg_freq_mem_force_pd.*/ -#define APB_CTRL_FREQ_MEM_FORCE_PD (BIT(7)) -#define APB_CTRL_FREQ_MEM_FORCE_PD_M (BIT(7)) -#define APB_CTRL_FREQ_MEM_FORCE_PD_V 0x1 -#define APB_CTRL_FREQ_MEM_FORCE_PD_S 7 -/* APB_CTRL_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: reg_freq_mem_force_pu.*/ -#define APB_CTRL_FREQ_MEM_FORCE_PU (BIT(6)) -#define APB_CTRL_FREQ_MEM_FORCE_PU_M (BIT(6)) -#define APB_CTRL_FREQ_MEM_FORCE_PU_V 0x1 -#define APB_CTRL_FREQ_MEM_FORCE_PU_S 6 -/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: reg_dc_mem_force_pd.*/ -#define APB_CTRL_DC_MEM_FORCE_PD (BIT(5)) -#define APB_CTRL_DC_MEM_FORCE_PD_M (BIT(5)) -#define APB_CTRL_DC_MEM_FORCE_PD_V 0x1 -#define APB_CTRL_DC_MEM_FORCE_PD_S 5 -/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: reg_dc_mem_force_pu.*/ -#define APB_CTRL_DC_MEM_FORCE_PU (BIT(4)) -#define APB_CTRL_DC_MEM_FORCE_PU_M (BIT(4)) -#define APB_CTRL_DC_MEM_FORCE_PU_V 0x1 -#define APB_CTRL_DC_MEM_FORCE_PU_S 4 -/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: reg_pbus_mem_force_pd.*/ -#define APB_CTRL_PBUS_MEM_FORCE_PD (BIT(3)) -#define APB_CTRL_PBUS_MEM_FORCE_PD_M (BIT(3)) -#define APB_CTRL_PBUS_MEM_FORCE_PD_V 0x1 -#define APB_CTRL_PBUS_MEM_FORCE_PD_S 3 -/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: reg_pbus_mem_force_pu.*/ -#define APB_CTRL_PBUS_MEM_FORCE_PU (BIT(2)) -#define APB_CTRL_PBUS_MEM_FORCE_PU_M (BIT(2)) -#define APB_CTRL_PBUS_MEM_FORCE_PU_V 0x1 -#define APB_CTRL_PBUS_MEM_FORCE_PU_S 2 -/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: reg_agc_mem_force_pd.*/ -#define APB_CTRL_AGC_MEM_FORCE_PD (BIT(1)) -#define APB_CTRL_AGC_MEM_FORCE_PD_M (BIT(1)) -#define APB_CTRL_AGC_MEM_FORCE_PD_V 0x1 -#define APB_CTRL_AGC_MEM_FORCE_PD_S 1 -/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: reg_agc_mem_force_pu.*/ -#define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0)) -#define APB_CTRL_AGC_MEM_FORCE_PU_M (BIT(0)) -#define APB_CTRL_AGC_MEM_FORCE_PU_V 0x1 -#define APB_CTRL_AGC_MEM_FORCE_PU_S 0 - -#define APB_CTRL_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0xA0) -/* APB_CTRL_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: reg_nobypass_cpu_iso_rst.*/ -#define APB_CTRL_NOBYPASS_CPU_ISO_RST (BIT(27)) -#define APB_CTRL_NOBYPASS_CPU_ISO_RST_M (BIT(27)) -#define APB_CTRL_NOBYPASS_CPU_ISO_RST_V 0x1 -#define APB_CTRL_NOBYPASS_CPU_ISO_RST_S 27 -/* APB_CTRL_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ -/*description: reg_retention_link_addr.*/ -#define APB_CTRL_RETENTION_LINK_ADDR 0x07FFFFFF -#define APB_CTRL_RETENTION_LINK_ADDR_M ((APB_CTRL_RETENTION_LINK_ADDR_V)<<(APB_CTRL_RETENTION_LINK_ADDR_S)) -#define APB_CTRL_RETENTION_LINK_ADDR_V 0x7FFFFFF -#define APB_CTRL_RETENTION_LINK_ADDR_S 0 - -#define APB_CTRL_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0xA4) -/* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[6:3] ;default: 4'hf ; */ -/*description: Set the bit to 1 to force sram always have clock, for low power can clear to 0 t -hen only when have access the sram have clock.*/ -#define APB_CTRL_SRAM_CLKGATE_FORCE_ON 0x0000000F -#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_M ((APB_CTRL_SRAM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_SRAM_CLKGATE_FORCE_ON_S)) -#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_V 0xF -#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_S 3 -/* APB_CTRL_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ -/*description: Set the bit to 1 to force rom always have clock, for low power can clear to 0 th -en only when have access the rom have clock.*/ -#define APB_CTRL_ROM_CLKGATE_FORCE_ON 0x00000007 -#define APB_CTRL_ROM_CLKGATE_FORCE_ON_M ((APB_CTRL_ROM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_ROM_CLKGATE_FORCE_ON_S)) -#define APB_CTRL_ROM_CLKGATE_FORCE_ON_V 0x7 -#define APB_CTRL_ROM_CLKGATE_FORCE_ON_S 0 - -#define APB_CTRL_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0xA8) -/* APB_CTRL_SRAM_POWER_DOWN : R/W ;bitpos:[6:3] ;default: 4'hf ; */ -/*description: Set 1 to let sram power down.*/ -#define APB_CTRL_SRAM_POWER_DOWN 0x0000000F -#define APB_CTRL_SRAM_POWER_DOWN_M ((APB_CTRL_SRAM_POWER_DOWN_V)<<(APB_CTRL_SRAM_POWER_DOWN_S)) -#define APB_CTRL_SRAM_POWER_DOWN_V 0xF -#define APB_CTRL_SRAM_POWER_DOWN_S 3 -/* APB_CTRL_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ -/*description: Set 1 to let rom power down.*/ -#define APB_CTRL_ROM_POWER_DOWN 0x00000007 -#define APB_CTRL_ROM_POWER_DOWN_M ((APB_CTRL_ROM_POWER_DOWN_V)<<(APB_CTRL_ROM_POWER_DOWN_S)) -#define APB_CTRL_ROM_POWER_DOWN_V 0x7 -#define APB_CTRL_ROM_POWER_DOWN_S 0 - -#define APB_CTRL_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0xAC) -/* APB_CTRL_SRAM_POWER_UP : R/W ;bitpos:[6:3] ;default: 4'hf ; */ -/*description: Set 1 to let sram power up.*/ -#define APB_CTRL_SRAM_POWER_UP 0x0000000F -#define APB_CTRL_SRAM_POWER_UP_M ((APB_CTRL_SRAM_POWER_UP_V)<<(APB_CTRL_SRAM_POWER_UP_S)) -#define APB_CTRL_SRAM_POWER_UP_V 0xF -#define APB_CTRL_SRAM_POWER_UP_S 3 -/* APB_CTRL_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ -/*description: Set 1 to let rom power up.*/ -#define APB_CTRL_ROM_POWER_UP 0x00000007 -#define APB_CTRL_ROM_POWER_UP_M ((APB_CTRL_ROM_POWER_UP_V)<<(APB_CTRL_ROM_POWER_UP_S)) -#define APB_CTRL_ROM_POWER_UP_V 0x7 -#define APB_CTRL_ROM_POWER_UP_S 0 - -#define APB_CTRL_RND_DATA_REG (DR_REG_SYSCON_BASE + 0xB0) -/* APB_CTRL_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: reg_rnd_data.*/ -#define APB_CTRL_RND_DATA 0xFFFFFFFF -#define APB_CTRL_RND_DATA_M ((APB_CTRL_RND_DATA_V)<<(APB_CTRL_RND_DATA_S)) -#define APB_CTRL_RND_DATA_V 0xFFFFFFFF -#define APB_CTRL_RND_DATA_S 0 - -#define APB_CTRL_PERI_BACKUP_CONFIG_REG (DR_REG_SYSCON_BASE + 0xB4) -/* APB_CTRL_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: reg_peri_backup_ena.*/ -#define APB_CTRL_PERI_BACKUP_ENA (BIT(31)) -#define APB_CTRL_PERI_BACKUP_ENA_M (BIT(31)) -#define APB_CTRL_PERI_BACKUP_ENA_V 0x1 -#define APB_CTRL_PERI_BACKUP_ENA_S 31 -/* APB_CTRL_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: reg_peri_backup_to_mem.*/ -#define APB_CTRL_PERI_BACKUP_TO_MEM (BIT(30)) -#define APB_CTRL_PERI_BACKUP_TO_MEM_M (BIT(30)) -#define APB_CTRL_PERI_BACKUP_TO_MEM_V 0x1 -#define APB_CTRL_PERI_BACKUP_TO_MEM_S 30 -/* APB_CTRL_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: reg_peri_backup_start.*/ -#define APB_CTRL_PERI_BACKUP_START (BIT(29)) -#define APB_CTRL_PERI_BACKUP_START_M (BIT(29)) -#define APB_CTRL_PERI_BACKUP_START_V 0x1 -#define APB_CTRL_PERI_BACKUP_START_S 29 -/* APB_CTRL_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */ -/*description: reg_peri_backup_size.*/ -#define APB_CTRL_PERI_BACKUP_SIZE 0x000003FF -#define APB_CTRL_PERI_BACKUP_SIZE_M ((APB_CTRL_PERI_BACKUP_SIZE_V)<<(APB_CTRL_PERI_BACKUP_SIZE_S)) -#define APB_CTRL_PERI_BACKUP_SIZE_V 0x3FF -#define APB_CTRL_PERI_BACKUP_SIZE_S 19 -/* APB_CTRL_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */ -/*description: reg_peri_backup_tout_thres.*/ -#define APB_CTRL_PERI_BACKUP_TOUT_THRES 0x000003FF -#define APB_CTRL_PERI_BACKUP_TOUT_THRES_M ((APB_CTRL_PERI_BACKUP_TOUT_THRES_V)<<(APB_CTRL_PERI_BACKUP_TOUT_THRES_S)) -#define APB_CTRL_PERI_BACKUP_TOUT_THRES_V 0x3FF -#define APB_CTRL_PERI_BACKUP_TOUT_THRES_S 9 -/* APB_CTRL_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */ -/*description: reg_peri_backup_burst_limit.*/ -#define APB_CTRL_PERI_BACKUP_BURST_LIMIT 0x0000001F -#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_M ((APB_CTRL_PERI_BACKUP_BURST_LIMIT_V)<<(APB_CTRL_PERI_BACKUP_BURST_LIMIT_S)) -#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_V 0x1F -#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_S 4 -/* APB_CTRL_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: reg_peri_backup_flow_err.*/ -#define APB_CTRL_PERI_BACKUP_FLOW_ERR 0x00000003 -#define APB_CTRL_PERI_BACKUP_FLOW_ERR_M ((APB_CTRL_PERI_BACKUP_FLOW_ERR_V)<<(APB_CTRL_PERI_BACKUP_FLOW_ERR_S)) -#define APB_CTRL_PERI_BACKUP_FLOW_ERR_V 0x3 -#define APB_CTRL_PERI_BACKUP_FLOW_ERR_S 1 - -#define APB_CTRL_PERI_BACKUP_APB_ADDR_REG (DR_REG_SYSCON_BASE + 0xB8) -/* APB_CTRL_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: reg_backup_apb_start_addr.*/ -#define APB_CTRL_BACKUP_APB_START_ADDR 0xFFFFFFFF -#define APB_CTRL_BACKUP_APB_START_ADDR_M ((APB_CTRL_BACKUP_APB_START_ADDR_V)<<(APB_CTRL_BACKUP_APB_START_ADDR_S)) -#define APB_CTRL_BACKUP_APB_START_ADDR_V 0xFFFFFFFF -#define APB_CTRL_BACKUP_APB_START_ADDR_S 0 - -#define APB_CTRL_PERI_BACKUP_MEM_ADDR_REG (DR_REG_SYSCON_BASE + 0xBC) -/* APB_CTRL_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: reg_backup_mem_start_addr.*/ -#define APB_CTRL_BACKUP_MEM_START_ADDR 0xFFFFFFFF -#define APB_CTRL_BACKUP_MEM_START_ADDR_M ((APB_CTRL_BACKUP_MEM_START_ADDR_V)<<(APB_CTRL_BACKUP_MEM_START_ADDR_S)) -#define APB_CTRL_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF -#define APB_CTRL_BACKUP_MEM_START_ADDR_S 0 - -#define APB_CTRL_PERI_BACKUP_INT_RAW_REG (DR_REG_SYSCON_BASE + 0xC0) -/* APB_CTRL_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: reg_peri_backup_err_int_raw.*/ -#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW (BIT(1)) -#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_M (BIT(1)) -#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_V 0x1 -#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_S 1 -/* APB_CTRL_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: reg_peri_backup_done_int_raw.*/ -#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW (BIT(0)) -#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_M (BIT(0)) -#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_V 0x1 -#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_S 0 - -#define APB_CTRL_PERI_BACKUP_INT_ST_REG (DR_REG_SYSCON_BASE + 0xC4) -/* APB_CTRL_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: reg_peri_backup_err_int_st.*/ -#define APB_CTRL_PERI_BACKUP_ERR_INT_ST (BIT(1)) -#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_M (BIT(1)) -#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_V 0x1 -#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_S 1 -/* APB_CTRL_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: reg_peri_backup_done_int_st.*/ -#define APB_CTRL_PERI_BACKUP_DONE_INT_ST (BIT(0)) -#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_M (BIT(0)) -#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_V 0x1 -#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_S 0 - -#define APB_CTRL_PERI_BACKUP_INT_ENA_REG (DR_REG_SYSCON_BASE + 0xC8) -/* APB_CTRL_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: reg_peri_backup_err_int_ena.*/ -#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA (BIT(1)) -#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_M (BIT(1)) -#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_V 0x1 -#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_S 1 -/* APB_CTRL_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: reg_peri_backup_done_int_ena.*/ -#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA (BIT(0)) -#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_M (BIT(0)) -#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_V 0x1 -#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_S 0 - -#define APB_CTRL_PERI_BACKUP_INT_CLR_REG (DR_REG_SYSCON_BASE + 0xD0) -/* APB_CTRL_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: reg_peri_backup_err_int_clr.*/ -#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR (BIT(1)) -#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_M (BIT(1)) -#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_V 0x1 -#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_S 1 -/* APB_CTRL_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: reg_peri_backup_done_int_clr.*/ -#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR (BIT(0)) -#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_M (BIT(0)) -#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_V 0x1 -#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_S 0 - -#define APB_CTRL_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC) -/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2106080 ; */ -/*description: reg_dateVersion control.*/ -#define APB_CTRL_DATE 0xFFFFFFFF -#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S)) -#define APB_CTRL_DATE_V 0xFFFFFFFF -#define APB_CTRL_DATE_S 0 - - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_APB_CTRL_REG_H_ */ diff --git a/components/soc/esp8684/include/soc/apb_ctrl_struct.h b/components/soc/esp8684/include/soc/apb_ctrl_struct.h deleted file mode 100644 index 842c0bed55..0000000000 --- a/components/soc/esp8684/include/soc/apb_ctrl_struct.h +++ /dev/null @@ -1,481 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_APB_CTRL_STRUCT_H_ -#define _SOC_APB_CTRL_STRUCT_H_ - - -#ifdef __cplusplus -extern "C" { -#endif -#include "soc.h" - -typedef volatile struct apb_ctrl_dev_s{ - union { - struct { - uint32_t pre_div : 10; /*reg_pre_div_cnt*/ - uint32_t clk_320m_en : 1; /*reg_clk_320m_en*/ - uint32_t clk_en : 1; /*reg_clk_en*/ - uint32_t rst_tick : 1; /*reg_rst_tick_cnt*/ - uint32_t reserved13 : 19; /*Reserved.*/ - }; - uint32_t val; - } clk_conf; - union { - struct { - uint32_t xtal_tick : 8; /*reg_xtal_tick_num*/ - uint32_t ck8m_tick : 8; /*reg_ck8m_tick_num*/ - uint32_t tick_enable : 1; /*reg_tick_enable*/ - uint32_t reserved17 : 15; /*Reserved.*/ - }; - uint32_t val; - } tick_conf; - union { - struct { - uint32_t clk20_oen : 1; /*reg_clk20_oen*/ - uint32_t clk22_oen : 1; /*reg_clk22_oen*/ - uint32_t clk44_oen : 1; /*reg_clk44_oen*/ - uint32_t clk_bb_oen : 1; /*reg_clk_bb_oen*/ - uint32_t clk80_oen : 1; /*reg_clk80_oen*/ - uint32_t clk160_oen : 1; /*reg_clk160_oen*/ - uint32_t clk_320m_oen : 1; /*reg_clk_320m_oen*/ - uint32_t clk_adc_inf_oen : 1; /*reg_clk_adc_inf_oen*/ - uint32_t clk_dac_cpu_oen : 1; /*reg_clk_dac_cpu_oen*/ - uint32_t clk40x_bb_oen : 1; /*reg_clk40x_bb_oen*/ - uint32_t clk_xtal_oen : 1; /*reg_clk_xtal_oen*/ - uint32_t reserved11 : 21; /*Reserved.*/ - }; - uint32_t val; - } clk_out_en; - uint32_t wifi_bb_cfg; - uint32_t wifi_bb_cfg_2; - uint32_t wifi_clk_en; - uint32_t wifi_rst_en; - union { - struct { - uint32_t peri_io_swap : 8; /*reg_peri_io_swap*/ - uint32_t reserved8 : 24; /*Reserved.*/ - }; - uint32_t val; - } host_inf_sel; - union { - struct { - uint32_t ext_mem_pms_lock : 1; /*reg_ext_mem_pms_lock*/ - uint32_t reserved1 : 31; /*Reserved.*/ - }; - uint32_t val; - } ext_mem_pms_lock; - uint32_t reserved_24; - union { - struct { - uint32_t flash_ace0_attr : 2; /*reg_flash_ace0_attr*/ - uint32_t reserved2 : 30; /*Reserved.*/ - }; - uint32_t val; - } flash_ace0_attr; - union { - struct { - uint32_t flash_ace1_attr : 2; /*reg_flash_ace1_attr*/ - uint32_t reserved2 : 30; /*Reserved.*/ - }; - uint32_t val; - } flash_ace1_attr; - union { - struct { - uint32_t flash_ace2_attr : 2; /*reg_flash_ace2_attr*/ - uint32_t reserved2 : 30; /*Reserved.*/ - }; - uint32_t val; - } flash_ace2_attr; - union { - struct { - uint32_t flash_ace3_attr : 2; /*reg_flash_ace3_attr*/ - uint32_t reserved2 : 30; /*Reserved.*/ - }; - uint32_t val; - } flash_ace3_attr; - uint32_t flash_ace0_addr; - uint32_t flash_ace1_addr; - uint32_t flash_ace2_addr; - uint32_t flash_ace3_addr; - union { - struct { - uint32_t flash_ace0_size : 13; /*reg_flash_ace0_size*/ - uint32_t reserved13 : 19; /*Reserved.*/ - }; - uint32_t val; - } flash_ace0_size; - union { - struct { - uint32_t flash_ace1_size : 13; /*reg_flash_ace1_size*/ - uint32_t reserved13 : 19; /*Reserved.*/ - }; - uint32_t val; - } flash_ace1_size; - union { - struct { - uint32_t flash_ace2_size : 13; /*reg_flash_ace2_size*/ - uint32_t reserved13 : 19; /*Reserved.*/ - }; - uint32_t val; - } flash_ace2_size; - union { - struct { - uint32_t flash_ace3_size : 13; /*reg_flash_ace3_size*/ - uint32_t reserved13 : 19; /*Reserved.*/ - }; - uint32_t val; - } flash_ace3_size; - uint32_t reserved_58; - uint32_t reserved_5c; - uint32_t reserved_60; - uint32_t reserved_64; - uint32_t reserved_68; - uint32_t reserved_6c; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - union { - struct { - uint32_t spi_mem_reject_int : 1; /*reg_spi_mem_reject_int*/ - uint32_t spi_mem_reject_clr : 1; /*reg_spi_mem_reject_clr*/ - uint32_t spi_mem_reject_cde : 5; /*reg_spi_mem_reject_cde*/ - uint32_t reserved7 : 25; /*Reserved.*/ - }; - uint32_t val; - } spi_mem_pms_ctrl; - uint32_t spi_mem_reject_addr; - union { - struct { - uint32_t sdio_win_access_en : 1; /*reg_sdio_win_access_en*/ - uint32_t reserved1 : 31; /*Reserved.*/ - }; - uint32_t val; - } sdio_ctrl; - union { - struct { - uint32_t redcy_sig0 : 31; /*reg_redcy_sig0*/ - uint32_t redcy_andor : 1; /*reg_redcy_andor*/ - }; - uint32_t val; - } redcy_sig0; - union { - struct { - uint32_t redcy_sig1 : 31; /*reg_redcy_sig1*/ - uint32_t redcy_nandor : 1; /*reg_redcy_nandor*/ - }; - uint32_t val; - } redcy_sig1; - union { - struct { - uint32_t agc_mem_force_pu : 1; /*reg_agc_mem_force_pu*/ - uint32_t agc_mem_force_pd : 1; /*reg_agc_mem_force_pd*/ - uint32_t pbus_mem_force_pu : 1; /*reg_pbus_mem_force_pu*/ - uint32_t pbus_mem_force_pd : 1; /*reg_pbus_mem_force_pd*/ - uint32_t dc_mem_force_pu : 1; /*reg_dc_mem_force_pu*/ - uint32_t dc_mem_force_pd : 1; /*reg_dc_mem_force_pd*/ - uint32_t freq_mem_force_pu : 1; /*reg_freq_mem_force_pu*/ - uint32_t freq_mem_force_pd : 1; /*reg_freq_mem_force_pd*/ - uint32_t reserved8 : 24; /*Reserved.*/ - }; - uint32_t val; - } front_end_mem_pd; - union { - struct { - uint32_t retention_link_addr : 27; /*reg_retention_link_addr*/ - uint32_t nobypass_cpu_iso_rst : 1; /*reg_nobypass_cpu_iso_rst*/ - uint32_t reserved28 : 4; /*Reserved.*/ - }; - uint32_t val; - } retention_ctrl; - union { - struct { - uint32_t rom_clkgate_force_on : 3; /*Set the bit to 1 to force rom always have clock, for low power can clear to 0 then only when have access the rom have clock*/ - uint32_t sram_clkgate_force_on : 4; /*Set the bit to 1 to force sram always have clock, for low power can clear to 0 then only when have access the sram have clock*/ - uint32_t reserved7 : 25; /*Reserved.*/ - }; - uint32_t val; - } clkgate_force_on; - union { - struct { - uint32_t rom_power_down : 3; /*Set 1 to let rom power down*/ - uint32_t sram_power_down : 4; /*Set 1 to let sram power down*/ - uint32_t reserved7 : 25; /*Reserved.*/ - }; - uint32_t val; - } mem_power_down; - union { - struct { - uint32_t rom_power_up : 3; /*Set 1 to let rom power up*/ - uint32_t sram_power_up : 4; /*Set 1 to let sram power up*/ - uint32_t reserved7 : 25; /*Reserved.*/ - }; - uint32_t val; - } mem_power_up; - uint32_t rnd_data; - union { - struct { - uint32_t reserved0 : 1; /*Reserved.*/ - uint32_t peri_backup_flow_err : 2; /*reg_peri_backup_flow_err*/ - uint32_t reserved3 : 1; /*Reserved.*/ - uint32_t peri_backup_burst_limit : 5; /*reg_peri_backup_burst_limit*/ - uint32_t peri_backup_tout_thres : 10; /*reg_peri_backup_tout_thres*/ - uint32_t peri_backup_size : 10; /*reg_peri_backup_size*/ - uint32_t peri_backup_start : 1; /*reg_peri_backup_start*/ - uint32_t peri_backup_to_mem : 1; /*reg_peri_backup_to_mem*/ - uint32_t peri_backup_ena : 1; /*reg_peri_backup_ena*/ - }; - uint32_t val; - } peri_backup_config; - uint32_t peri_backup_addr; - uint32_t peri_backup_mem_addr; - union { - struct { - uint32_t peri_backup_done : 1; /*reg_peri_backup_done_int_raw*/ - uint32_t peri_backup_err : 1; /*reg_peri_backup_err_int_raw*/ - uint32_t reserved2 : 30; /*Reserved.*/ - }; - uint32_t val; - } peri_backup_int_raw; - union { - struct { - uint32_t peri_backup_done : 1; /*reg_peri_backup_done_int_st*/ - uint32_t peri_backup_err : 1; /*reg_peri_backup_err_int_st*/ - uint32_t reserved2 : 30; /*Reserved.*/ - }; - uint32_t val; - } peri_backup_int_st; - union { - struct { - uint32_t peri_backup_done : 1; /*reg_peri_backup_done_int_ena*/ - uint32_t peri_backup_err : 1; /*reg_peri_backup_err_int_ena*/ - uint32_t reserved2 : 30; /*Reserved.*/ - }; - uint32_t val; - } peri_backup_int_ena; - uint32_t reserved_cc; - union { - struct { - uint32_t peri_backup_done : 1; /*reg_peri_backup_done_int_clr*/ - uint32_t peri_backup_err : 1; /*reg_peri_backup_err_int_clr*/ - uint32_t reserved2 : 30; /*Reserved.*/ - }; - uint32_t val; - } peri_backup_int_clr; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t reserved_fc; - uint32_t reserved_100; - uint32_t reserved_104; - uint32_t reserved_108; - uint32_t reserved_10c; - uint32_t reserved_110; - uint32_t reserved_114; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t reserved_140; - uint32_t reserved_144; - uint32_t reserved_148; - uint32_t reserved_14c; - uint32_t reserved_150; - uint32_t reserved_154; - uint32_t reserved_158; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; - uint32_t reserved_18c; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; - uint32_t reserved_1cc; - uint32_t reserved_1d0; - uint32_t reserved_1d4; - uint32_t reserved_1d8; - uint32_t reserved_1dc; - uint32_t reserved_1e0; - uint32_t reserved_1e4; - uint32_t reserved_1e8; - uint32_t reserved_1ec; - uint32_t reserved_1f0; - uint32_t reserved_1f4; - uint32_t reserved_1f8; - uint32_t reserved_1fc; - uint32_t reserved_200; - uint32_t reserved_204; - uint32_t reserved_208; - uint32_t reserved_20c; - uint32_t reserved_210; - uint32_t reserved_214; - uint32_t reserved_218; - uint32_t reserved_21c; - uint32_t reserved_220; - uint32_t reserved_224; - uint32_t reserved_228; - uint32_t reserved_22c; - uint32_t reserved_230; - uint32_t reserved_234; - uint32_t reserved_238; - uint32_t reserved_23c; - uint32_t reserved_240; - uint32_t reserved_244; - uint32_t reserved_248; - uint32_t reserved_24c; - uint32_t reserved_250; - uint32_t reserved_254; - uint32_t reserved_258; - uint32_t reserved_25c; - uint32_t reserved_260; - uint32_t reserved_264; - uint32_t reserved_268; - uint32_t reserved_26c; - uint32_t reserved_270; - uint32_t reserved_274; - uint32_t reserved_278; - uint32_t reserved_27c; - uint32_t reserved_280; - uint32_t reserved_284; - uint32_t reserved_288; - uint32_t reserved_28c; - uint32_t reserved_290; - uint32_t reserved_294; - uint32_t reserved_298; - uint32_t reserved_29c; - uint32_t reserved_2a0; - uint32_t reserved_2a4; - uint32_t reserved_2a8; - uint32_t reserved_2ac; - uint32_t reserved_2b0; - uint32_t reserved_2b4; - uint32_t reserved_2b8; - uint32_t reserved_2bc; - uint32_t reserved_2c0; - uint32_t reserved_2c4; - uint32_t reserved_2c8; - uint32_t reserved_2cc; - uint32_t reserved_2d0; - uint32_t reserved_2d4; - uint32_t reserved_2d8; - uint32_t reserved_2dc; - uint32_t reserved_2e0; - uint32_t reserved_2e4; - uint32_t reserved_2e8; - uint32_t reserved_2ec; - uint32_t reserved_2f0; - uint32_t reserved_2f4; - uint32_t reserved_2f8; - uint32_t reserved_2fc; - uint32_t reserved_300; - uint32_t reserved_304; - uint32_t reserved_308; - uint32_t reserved_30c; - uint32_t reserved_310; - uint32_t reserved_314; - uint32_t reserved_318; - uint32_t reserved_31c; - uint32_t reserved_320; - uint32_t reserved_324; - uint32_t reserved_328; - uint32_t reserved_32c; - uint32_t reserved_330; - uint32_t reserved_334; - uint32_t reserved_338; - uint32_t reserved_33c; - uint32_t reserved_340; - uint32_t reserved_344; - uint32_t reserved_348; - uint32_t reserved_34c; - uint32_t reserved_350; - uint32_t reserved_354; - uint32_t reserved_358; - uint32_t reserved_35c; - uint32_t reserved_360; - uint32_t reserved_364; - uint32_t reserved_368; - uint32_t reserved_36c; - uint32_t reserved_370; - uint32_t reserved_374; - uint32_t reserved_378; - uint32_t reserved_37c; - uint32_t reserved_380; - uint32_t reserved_384; - uint32_t reserved_388; - uint32_t reserved_38c; - uint32_t reserved_390; - uint32_t reserved_394; - uint32_t reserved_398; - uint32_t reserved_39c; - uint32_t reserved_3a0; - uint32_t reserved_3a4; - uint32_t reserved_3a8; - uint32_t reserved_3ac; - uint32_t reserved_3b0; - uint32_t reserved_3b4; - uint32_t reserved_3b8; - uint32_t reserved_3bc; - uint32_t reserved_3c0; - uint32_t reserved_3c4; - uint32_t reserved_3c8; - uint32_t reserved_3cc; - uint32_t reserved_3d0; - uint32_t reserved_3d4; - uint32_t reserved_3d8; - uint32_t reserved_3dc; - uint32_t reserved_3e0; - uint32_t reserved_3e4; - uint32_t reserved_3e8; - uint32_t reserved_3ec; - uint32_t reserved_3f0; - uint32_t reserved_3f4; - uint32_t reserved_3f8; - uint32_t date; -} apb_ctrl_dev_t; -extern apb_ctrl_dev_t APB_CTRL; -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_APB_CTRL_STRUCT_H_ */ diff --git a/components/soc/esp8684/include/soc/apb_saradc_reg.h b/components/soc/esp8684/include/soc/apb_saradc_reg.h index a066019bbb..d144a2e557 100644 --- a/components/soc/esp8684/include/soc/apb_saradc_reg.h +++ b/components/soc/esp8684/include/soc/apb_saradc_reg.h @@ -1,638 +1,804 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_APB_SARADC_REG_H_ -#define _SOC_APB_SARADC_REG_H_ - +#pragma once +#include +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0) -/* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */ -/*description: wait arbit signal stable after sar_done.*/ -#define APB_SARADC_WAIT_ARB_CYCLE 0x00000003 -#define APB_SARADC_WAIT_ARB_CYCLE_M ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S)) -#define APB_SARADC_WAIT_ARB_CYCLE_V 0x3 -#define APB_SARADC_WAIT_ARB_CYCLE_S 30 -/* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ -/*description: force option to xpd sar blocks.*/ -#define APB_SARADC_XPD_SAR_FORCE 0x00000003 -#define APB_SARADC_XPD_SAR_FORCE_M ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S)) -#define APB_SARADC_XPD_SAR_FORCE_V 0x3 -#define APB_SARADC_XPD_SAR_FORCE_S 27 -/* APB_SARADC_SAR_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: clear the pointer of pattern table for DIG ADC1 CTRL.*/ -#define APB_SARADC_SAR_PATT_P_CLEAR (BIT(23)) -#define APB_SARADC_SAR_PATT_P_CLEAR_M (BIT(23)) -#define APB_SARADC_SAR_PATT_P_CLEAR_V 0x1 -#define APB_SARADC_SAR_PATT_P_CLEAR_S 23 -/* APB_SARADC_SAR_PATT_LEN : R/W ;bitpos:[17:15] ;default: 3'd7 ; */ -/*description: 0 ~ 15 means length 1 ~ 16.*/ -#define APB_SARADC_SAR_PATT_LEN 0x00000007 -#define APB_SARADC_SAR_PATT_LEN_M ((APB_SARADC_SAR_PATT_LEN_V)<<(APB_SARADC_SAR_PATT_LEN_S)) -#define APB_SARADC_SAR_PATT_LEN_V 0x7 -#define APB_SARADC_SAR_PATT_LEN_S 15 -/* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */ -/*description: SAR clock divider.*/ -#define APB_SARADC_SAR_CLK_DIV 0x000000FF -#define APB_SARADC_SAR_CLK_DIV_M ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S)) -#define APB_SARADC_SAR_CLK_DIV_V 0xFF -#define APB_SARADC_SAR_CLK_DIV_S 7 -/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: Need add description.*/ -#define APB_SARADC_SAR_CLK_GATED (BIT(6)) -#define APB_SARADC_SAR_CLK_GATED_M (BIT(6)) -#define APB_SARADC_SAR_CLK_GATED_V 0x1 -#define APB_SARADC_SAR_CLK_GATED_S 6 -/* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_START (BIT(1)) -#define APB_SARADC_START_M (BIT(1)) -#define APB_SARADC_START_V 0x1 -#define APB_SARADC_START_S 1 -/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_START_FORCE (BIT(0)) -#define APB_SARADC_START_FORCE_M (BIT(0)) -#define APB_SARADC_START_FORCE_V 0x1 -#define APB_SARADC_START_FORCE_S 0 +/** APB_SARADC_CTRL_REG register + * register description + */ +#define APB_SARADC_CTRL_REG (DR_REG_APB_BASE + 0x0) +/** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0; + * Need add description + */ +#define APB_SARADC_SARADC_START_FORCE (BIT(0)) +#define APB_SARADC_SARADC_START_FORCE_M (APB_SARADC_SARADC_START_FORCE_V << APB_SARADC_SARADC_START_FORCE_S) +#define APB_SARADC_SARADC_START_FORCE_V 0x00000001U +#define APB_SARADC_SARADC_START_FORCE_S 0 +/** APB_SARADC_SARADC_START : R/W; bitpos: [1]; default: 0; + * Need add description + */ +#define APB_SARADC_SARADC_START (BIT(1)) +#define APB_SARADC_SARADC_START_M (APB_SARADC_SARADC_START_V << APB_SARADC_SARADC_START_S) +#define APB_SARADC_SARADC_START_V 0x00000001U +#define APB_SARADC_SARADC_START_S 1 +/** APB_SARADC_SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1; + * Need add description + */ +#define APB_SARADC_SARADC_SAR_CLK_GATED (BIT(6)) +#define APB_SARADC_SARADC_SAR_CLK_GATED_M (APB_SARADC_SARADC_SAR_CLK_GATED_V << APB_SARADC_SARADC_SAR_CLK_GATED_S) +#define APB_SARADC_SARADC_SAR_CLK_GATED_V 0x00000001U +#define APB_SARADC_SARADC_SAR_CLK_GATED_S 6 +/** APB_SARADC_SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4; + * SAR clock divider + */ +#define APB_SARADC_SARADC_SAR_CLK_DIV 0x000000FFU +#define APB_SARADC_SARADC_SAR_CLK_DIV_M (APB_SARADC_SARADC_SAR_CLK_DIV_V << APB_SARADC_SARADC_SAR_CLK_DIV_S) +#define APB_SARADC_SARADC_SAR_CLK_DIV_V 0x000000FFU +#define APB_SARADC_SARADC_SAR_CLK_DIV_S 7 +/** APB_SARADC_SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7; + * 0 ~ 15 means length 1 ~ 16 + */ +#define APB_SARADC_SARADC_SAR_PATT_LEN 0x00000007U +#define APB_SARADC_SARADC_SAR_PATT_LEN_M (APB_SARADC_SARADC_SAR_PATT_LEN_V << APB_SARADC_SARADC_SAR_PATT_LEN_S) +#define APB_SARADC_SARADC_SAR_PATT_LEN_V 0x00000007U +#define APB_SARADC_SARADC_SAR_PATT_LEN_S 15 +/** APB_SARADC_SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0; + * clear the pointer of pattern table for DIG ADC1 CTRL + */ +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR (BIT(23)) +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_M (APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V << APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S) +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V 0x00000001U +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S 23 +/** APB_SARADC_SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0; + * force option to xpd sar blocks + */ +#define APB_SARADC_SARADC_XPD_SAR_FORCE 0x00000003U +#define APB_SARADC_SARADC_XPD_SAR_FORCE_M (APB_SARADC_SARADC_XPD_SAR_FORCE_V << APB_SARADC_SARADC_XPD_SAR_FORCE_S) +#define APB_SARADC_SARADC_XPD_SAR_FORCE_V 0x00000003U +#define APB_SARADC_SARADC_XPD_SAR_FORCE_S 27 +/** APB_SARADC_SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1; + * wait arbit signal stable after sar_done + */ +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE 0x00000003U +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_M (APB_SARADC_SARADC_WAIT_ARB_CYCLE_V << APB_SARADC_SARADC_WAIT_ARB_CYCLE_S) +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_V 0x00000003U +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_S 30 -#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4) -/* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: to enable saradc timer trigger.*/ -#define APB_SARADC_TIMER_EN (BIT(24)) -#define APB_SARADC_TIMER_EN_M (BIT(24)) -#define APB_SARADC_TIMER_EN_V 0x1 -#define APB_SARADC_TIMER_EN_S 24 -/* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */ -/*description: to set saradc timer target.*/ -#define APB_SARADC_TIMER_TARGET 0x00000FFF -#define APB_SARADC_TIMER_TARGET_M ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S)) -#define APB_SARADC_TIMER_TARGET_V 0xFFF -#define APB_SARADC_TIMER_TARGET_S 12 -/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: 1: data to DIG ADC2 CTRL is inverted, otherwise not.*/ -#define APB_SARADC_SAR2_INV (BIT(10)) -#define APB_SARADC_SAR2_INV_M (BIT(10)) -#define APB_SARADC_SAR2_INV_V 0x1 -#define APB_SARADC_SAR2_INV_S 10 -/* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: 1: data to DIG ADC1 CTRL is inverted, otherwise not.*/ -#define APB_SARADC_SAR1_INV (BIT(9)) -#define APB_SARADC_SAR1_INV_M (BIT(9)) -#define APB_SARADC_SAR1_INV_V 0x1 -#define APB_SARADC_SAR1_INV_S 9 -/* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */ -/*description: max conversion number.*/ -#define APB_SARADC_MAX_MEAS_NUM 0x000000FF -#define APB_SARADC_MAX_MEAS_NUM_M ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S)) -#define APB_SARADC_MAX_MEAS_NUM_V 0xFF -#define APB_SARADC_MAX_MEAS_NUM_S 1 -/* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_MEAS_NUM_LIMIT (BIT(0)) -#define APB_SARADC_MEAS_NUM_LIMIT_M (BIT(0)) -#define APB_SARADC_MEAS_NUM_LIMIT_V 0x1 -#define APB_SARADC_MEAS_NUM_LIMIT_S 0 +/** APB_SARADC_CTRL2_REG register + * register description + */ +#define APB_SARADC_CTRL2_REG (DR_REG_APB_BASE + 0x4) +/** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0; + * Need add description + */ +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT (BIT(0)) +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_M (APB_SARADC_SARADC_MEAS_NUM_LIMIT_V << APB_SARADC_SARADC_MEAS_NUM_LIMIT_S) +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_V 0x00000001U +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_S 0 +/** APB_SARADC_SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255; + * max conversion number + */ +#define APB_SARADC_SARADC_MAX_MEAS_NUM 0x000000FFU +#define APB_SARADC_SARADC_MAX_MEAS_NUM_M (APB_SARADC_SARADC_MAX_MEAS_NUM_V << APB_SARADC_SARADC_MAX_MEAS_NUM_S) +#define APB_SARADC_SARADC_MAX_MEAS_NUM_V 0x000000FFU +#define APB_SARADC_SARADC_MAX_MEAS_NUM_S 1 +/** APB_SARADC_SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0; + * 1: data to DIG ADC1 CTRL is inverted, otherwise not + */ +#define APB_SARADC_SARADC_SAR1_INV (BIT(9)) +#define APB_SARADC_SARADC_SAR1_INV_M (APB_SARADC_SARADC_SAR1_INV_V << APB_SARADC_SARADC_SAR1_INV_S) +#define APB_SARADC_SARADC_SAR1_INV_V 0x00000001U +#define APB_SARADC_SARADC_SAR1_INV_S 9 +/** APB_SARADC_SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0; + * 1: data to DIG ADC2 CTRL is inverted, otherwise not + */ +#define APB_SARADC_SARADC_SAR2_INV (BIT(10)) +#define APB_SARADC_SARADC_SAR2_INV_M (APB_SARADC_SARADC_SAR2_INV_V << APB_SARADC_SARADC_SAR2_INV_S) +#define APB_SARADC_SARADC_SAR2_INV_V 0x00000001U +#define APB_SARADC_SARADC_SAR2_INV_S 10 +/** APB_SARADC_SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10; + * to set saradc timer target + */ +#define APB_SARADC_SARADC_TIMER_TARGET 0x00000FFFU +#define APB_SARADC_SARADC_TIMER_TARGET_M (APB_SARADC_SARADC_TIMER_TARGET_V << APB_SARADC_SARADC_TIMER_TARGET_S) +#define APB_SARADC_SARADC_TIMER_TARGET_V 0x00000FFFU +#define APB_SARADC_SARADC_TIMER_TARGET_S 12 +/** APB_SARADC_SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0; + * to enable saradc timer trigger + */ +#define APB_SARADC_SARADC_TIMER_EN (BIT(24)) +#define APB_SARADC_SARADC_TIMER_EN_M (APB_SARADC_SARADC_TIMER_EN_V << APB_SARADC_SARADC_TIMER_EN_S) +#define APB_SARADC_SARADC_TIMER_EN_V 0x00000001U +#define APB_SARADC_SARADC_TIMER_EN_S 24 -#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8) -/* APB_SARADC_FILTER_FACTOR0 : R/W ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_FILTER_FACTOR0 0x00000007 -#define APB_SARADC_FILTER_FACTOR0_M ((APB_SARADC_FILTER_FACTOR0_V)<<(APB_SARADC_FILTER_FACTOR0_S)) -#define APB_SARADC_FILTER_FACTOR0_V 0x7 -#define APB_SARADC_FILTER_FACTOR0_S 29 -/* APB_SARADC_FILTER_FACTOR1 : R/W ;bitpos:[28:26] ;default: 3'd0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_FILTER_FACTOR1 0x00000007 -#define APB_SARADC_FILTER_FACTOR1_M ((APB_SARADC_FILTER_FACTOR1_V)<<(APB_SARADC_FILTER_FACTOR1_S)) -#define APB_SARADC_FILTER_FACTOR1_V 0x7 +/** APB_SARADC_FILTER_CTRL1_REG register + * register description + */ +#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_BASE + 0x8) +/** APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0; + * Need add description + */ +#define APB_SARADC_FILTER_FACTOR1 0x00000007U +#define APB_SARADC_FILTER_FACTOR1_M (APB_SARADC_FILTER_FACTOR1_V << APB_SARADC_FILTER_FACTOR1_S) +#define APB_SARADC_FILTER_FACTOR1_V 0x00000007U #define APB_SARADC_FILTER_FACTOR1_S 26 +/** APB_SARADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0; + * Need add description + */ +#define APB_SARADC_FILTER_FACTOR0 0x00000007U +#define APB_SARADC_FILTER_FACTOR0_M (APB_SARADC_FILTER_FACTOR0_V << APB_SARADC_FILTER_FACTOR0_S) +#define APB_SARADC_FILTER_FACTOR0_V 0x00000007U +#define APB_SARADC_FILTER_FACTOR0_S 29 -#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0xC) -/* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */ -/*description: Need add description.*/ -#define APB_SARADC_STANDBY_WAIT 0x000000FF -#define APB_SARADC_STANDBY_WAIT_M ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S)) -#define APB_SARADC_STANDBY_WAIT_V 0xFF -#define APB_SARADC_STANDBY_WAIT_S 16 -/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */ -/*description: Need add description.*/ -#define APB_SARADC_RSTB_WAIT 0x000000FF -#define APB_SARADC_RSTB_WAIT_M ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S)) -#define APB_SARADC_RSTB_WAIT_V 0xFF -#define APB_SARADC_RSTB_WAIT_S 8 -/* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */ -/*description: Need add description.*/ -#define APB_SARADC_XPD_WAIT 0x000000FF -#define APB_SARADC_XPD_WAIT_M ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S)) -#define APB_SARADC_XPD_WAIT_V 0xFF -#define APB_SARADC_XPD_WAIT_S 0 +/** APB_SARADC_FSM_WAIT_REG register + * register description + */ +#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_BASE + 0xc) +/** APB_SARADC_SARADC_XPD_WAIT : R/W; bitpos: [7:0]; default: 8; + * Need add description + */ +#define APB_SARADC_SARADC_XPD_WAIT 0x000000FFU +#define APB_SARADC_SARADC_XPD_WAIT_M (APB_SARADC_SARADC_XPD_WAIT_V << APB_SARADC_SARADC_XPD_WAIT_S) +#define APB_SARADC_SARADC_XPD_WAIT_V 0x000000FFU +#define APB_SARADC_SARADC_XPD_WAIT_S 0 +/** APB_SARADC_SARADC_RSTB_WAIT : R/W; bitpos: [15:8]; default: 8; + * Need add description + */ +#define APB_SARADC_SARADC_RSTB_WAIT 0x000000FFU +#define APB_SARADC_SARADC_RSTB_WAIT_M (APB_SARADC_SARADC_RSTB_WAIT_V << APB_SARADC_SARADC_RSTB_WAIT_S) +#define APB_SARADC_SARADC_RSTB_WAIT_V 0x000000FFU +#define APB_SARADC_SARADC_RSTB_WAIT_S 8 +/** APB_SARADC_SARADC_STANDBY_WAIT : R/W; bitpos: [23:16]; default: 255; + * Need add description + */ +#define APB_SARADC_SARADC_STANDBY_WAIT 0x000000FFU +#define APB_SARADC_SARADC_STANDBY_WAIT_M (APB_SARADC_SARADC_STANDBY_WAIT_V << APB_SARADC_SARADC_STANDBY_WAIT_S) +#define APB_SARADC_SARADC_STANDBY_WAIT_V 0x000000FFU +#define APB_SARADC_SARADC_STANDBY_WAIT_S 16 -#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x10) -/* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_SAR1_STATUS 0xFFFFFFFF -#define APB_SARADC_SAR1_STATUS_M ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S)) -#define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFF -#define APB_SARADC_SAR1_STATUS_S 0 +/** APB_SARADC_SAR1_STATUS_REG register + * register description + */ +#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_BASE + 0x10) +/** APB_SARADC_SARADC_SAR1_STATUS : RO; bitpos: [31:0]; default: 0; + * Need add description + */ +#define APB_SARADC_SARADC_SAR1_STATUS 0xFFFFFFFFU +#define APB_SARADC_SARADC_SAR1_STATUS_M (APB_SARADC_SARADC_SAR1_STATUS_V << APB_SARADC_SARADC_SAR1_STATUS_S) +#define APB_SARADC_SARADC_SAR1_STATUS_V 0xFFFFFFFFU +#define APB_SARADC_SARADC_SAR1_STATUS_S 0 -#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x14) -/* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_SAR2_STATUS 0xFFFFFFFF -#define APB_SARADC_SAR2_STATUS_M ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S)) -#define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFF -#define APB_SARADC_SAR2_STATUS_S 0 +/** APB_SARADC_SAR2_STATUS_REG register + * register description + */ +#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_BASE + 0x14) +/** APB_SARADC_SARADC_SAR2_STATUS : RO; bitpos: [31:0]; default: 0; + * Need add description + */ +#define APB_SARADC_SARADC_SAR2_STATUS 0xFFFFFFFFU +#define APB_SARADC_SARADC_SAR2_STATUS_M (APB_SARADC_SARADC_SAR2_STATUS_V << APB_SARADC_SARADC_SAR2_STATUS_S) +#define APB_SARADC_SARADC_SAR2_STATUS_V 0xFFFFFFFFU +#define APB_SARADC_SARADC_SAR2_STATUS_S 0 -#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18) -/* APB_SARADC_SAR_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'hffffff ; */ -/*description: item 0 ~ 3 for pattern table 1 (each item one byte).*/ -#define APB_SARADC_SAR_PATT_TAB1 0x00FFFFFF -#define APB_SARADC_SAR_PATT_TAB1_M ((APB_SARADC_SAR_PATT_TAB1_V)<<(APB_SARADC_SAR_PATT_TAB1_S)) -#define APB_SARADC_SAR_PATT_TAB1_V 0xFFFFFF -#define APB_SARADC_SAR_PATT_TAB1_S 0 +/** APB_SARADC_SAR_PATT_TAB1_REG register + * register description + */ +#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_BASE + 0x18) +/** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215; + * item 0 ~ 3 for pattern table 1 (each item one byte) + */ +#define APB_SARADC_SARADC_SAR_PATT_TAB1 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB1_M (APB_SARADC_SARADC_SAR_PATT_TAB1_V << APB_SARADC_SARADC_SAR_PATT_TAB1_S) +#define APB_SARADC_SARADC_SAR_PATT_TAB1_V 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB1_S 0 -#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1C) -/* APB_SARADC_SAR_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'hffffff ; */ -/*description: Item 4 ~ 7 for pattern table 1 (each item one byte).*/ -#define APB_SARADC_SAR_PATT_TAB2 0x00FFFFFF -#define APB_SARADC_SAR_PATT_TAB2_M ((APB_SARADC_SAR_PATT_TAB2_V)<<(APB_SARADC_SAR_PATT_TAB2_S)) -#define APB_SARADC_SAR_PATT_TAB2_V 0xFFFFFF -#define APB_SARADC_SAR_PATT_TAB2_S 0 +/** APB_SARADC_SAR_PATT_TAB2_REG register + * register description + */ +#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_BASE + 0x1c) +/** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215; + * Item 4 ~ 7 for pattern table 1 (each item one byte) + */ +#define APB_SARADC_SARADC_SAR_PATT_TAB2 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB2_M (APB_SARADC_SARADC_SAR_PATT_TAB2_V << APB_SARADC_SARADC_SAR_PATT_TAB2_S) +#define APB_SARADC_SARADC_SAR_PATT_TAB2_V 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB2_S 0 -#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20) -/* APB_SARADC1_ONETIME_SAMPLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC1_ONETIME_SAMPLE (BIT(31)) -#define APB_SARADC1_ONETIME_SAMPLE_M (BIT(31)) -#define APB_SARADC1_ONETIME_SAMPLE_V 0x1 -#define APB_SARADC1_ONETIME_SAMPLE_S 31 -/* APB_SARADC2_ONETIME_SAMPLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC2_ONETIME_SAMPLE (BIT(30)) -#define APB_SARADC2_ONETIME_SAMPLE_M (BIT(30)) -#define APB_SARADC2_ONETIME_SAMPLE_V 0x1 -#define APB_SARADC2_ONETIME_SAMPLE_S 30 -/* APB_SARADC_ONETIME_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_ONETIME_START (BIT(29)) -#define APB_SARADC_ONETIME_START_M (BIT(29)) -#define APB_SARADC_ONETIME_START_V 0x1 -#define APB_SARADC_ONETIME_START_S 29 -/* APB_SARADC_ONETIME_CHANNEL : R/W ;bitpos:[28:25] ;default: 4'd13 ; */ -/*description: Need add description.*/ -#define APB_SARADC_ONETIME_CHANNEL 0x0000000F -#define APB_SARADC_ONETIME_CHANNEL_M ((APB_SARADC_ONETIME_CHANNEL_V)<<(APB_SARADC_ONETIME_CHANNEL_S)) -#define APB_SARADC_ONETIME_CHANNEL_V 0xF -#define APB_SARADC_ONETIME_CHANNEL_S 25 -/* APB_SARADC_ONETIME_ATTEN : R/W ;bitpos:[24:23] ;default: 2'd0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_ONETIME_ATTEN 0x00000003 -#define APB_SARADC_ONETIME_ATTEN_M ((APB_SARADC_ONETIME_ATTEN_V)<<(APB_SARADC_ONETIME_ATTEN_S)) -#define APB_SARADC_ONETIME_ATTEN_V 0x3 -#define APB_SARADC_ONETIME_ATTEN_S 23 +/** APB_SARADC_ONETIME_SAMPLE_REG register + * register description + */ +#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_BASE + 0x20) +/** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0; + * Need add description + */ +#define APB_SARADC_SARADC_ONETIME_ATTEN 0x00000003U +#define APB_SARADC_SARADC_ONETIME_ATTEN_M (APB_SARADC_SARADC_ONETIME_ATTEN_V << APB_SARADC_SARADC_ONETIME_ATTEN_S) +#define APB_SARADC_SARADC_ONETIME_ATTEN_V 0x00000003U +#define APB_SARADC_SARADC_ONETIME_ATTEN_S 23 +/** APB_SARADC_SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13; + * Need add description + */ +#define APB_SARADC_SARADC_ONETIME_CHANNEL 0x0000000FU +#define APB_SARADC_SARADC_ONETIME_CHANNEL_M (APB_SARADC_SARADC_ONETIME_CHANNEL_V << APB_SARADC_SARADC_ONETIME_CHANNEL_S) +#define APB_SARADC_SARADC_ONETIME_CHANNEL_V 0x0000000FU +#define APB_SARADC_SARADC_ONETIME_CHANNEL_S 25 +/** APB_SARADC_SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0; + * Need add description + */ +#define APB_SARADC_SARADC_ONETIME_START (BIT(29)) +#define APB_SARADC_SARADC_ONETIME_START_M (APB_SARADC_SARADC_ONETIME_START_V << APB_SARADC_SARADC_ONETIME_START_S) +#define APB_SARADC_SARADC_ONETIME_START_V 0x00000001U +#define APB_SARADC_SARADC_ONETIME_START_S 29 +/** APB_SARADC_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0; + * Need add description + */ +#define APB_SARADC_SARADC2_ONETIME_SAMPLE (BIT(30)) +#define APB_SARADC_SARADC2_ONETIME_SAMPLE_M (APB_SARADC_SARADC2_ONETIME_SAMPLE_V << APB_SARADC_SARADC2_ONETIME_SAMPLE_S) +#define APB_SARADC_SARADC2_ONETIME_SAMPLE_V 0x00000001U +#define APB_SARADC_SARADC2_ONETIME_SAMPLE_S 30 +/** APB_SARADC_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0; + * Need add description + */ +#define APB_SARADC_SARADC1_ONETIME_SAMPLE (BIT(31)) +#define APB_SARADC_SARADC1_ONETIME_SAMPLE_M (APB_SARADC_SARADC1_ONETIME_SAMPLE_V << APB_SARADC_SARADC1_ONETIME_SAMPLE_S) +#define APB_SARADC_SARADC1_ONETIME_SAMPLE_V 0x00000001U +#define APB_SARADC_SARADC1_ONETIME_SAMPLE_S 31 -#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24) -/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: adc2 arbiter uses fixed priority.*/ -#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12)) -#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (BIT(12)) -#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x1 -#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12 -/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */ -/*description: Set adc2 arbiter wifi priority.*/ -#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003 -#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)) -#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x3 -#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10 -/* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */ -/*description: Set adc2 arbiter rtc priority.*/ -#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003 -#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S)) -#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x3 -#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8 -/* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Set adc2 arbiterapb priority.*/ -#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003 -#define APB_SARADC_ADC_ARB_APB_PRIORITY_M ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S)) -#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x3 -#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6 -/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: adc2 arbiter force grant.*/ -#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5)) -#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (BIT(5)) -#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x1 -#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5 -/* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: adc2 arbiter force to enable wifi controller.*/ -#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4)) -#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (BIT(4)) -#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x1 -#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4 -/* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: adc2 arbiter force to enable rtc controller.*/ -#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3)) -#define APB_SARADC_ADC_ARB_RTC_FORCE_M (BIT(3)) -#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x1 -#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3 -/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: adc2 arbiter force to enableapb controller.*/ +/** APB_SARADC_APB_ADC_ARB_CTRL_REG register + * register description + */ +#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_BASE + 0x24) +/** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0; + * adc2 arbiter force to enableapb controller + */ #define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2)) -#define APB_SARADC_ADC_ARB_APB_FORCE_M (BIT(2)) -#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_APB_FORCE_M (APB_SARADC_ADC_ARB_APB_FORCE_V << APB_SARADC_ADC_ARB_APB_FORCE_S) +#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x00000001U #define APB_SARADC_ADC_ARB_APB_FORCE_S 2 +/** APB_SARADC_ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0; + * adc2 arbiter force to enable rtc controller + */ +#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3)) +#define APB_SARADC_ADC_ARB_RTC_FORCE_M (APB_SARADC_ADC_ARB_RTC_FORCE_V << APB_SARADC_ADC_ARB_RTC_FORCE_S) +#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x00000001U +#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3 +/** APB_SARADC_ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0; + * adc2 arbiter force to enable wifi controller + */ +#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4)) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (APB_SARADC_ADC_ARB_WIFI_FORCE_V << APB_SARADC_ADC_ARB_WIFI_FORCE_S) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x00000001U +#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4 +/** APB_SARADC_ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0; + * adc2 arbiter force grant + */ +#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5)) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (APB_SARADC_ADC_ARB_GRANT_FORCE_V << APB_SARADC_ADC_ARB_GRANT_FORCE_S) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x00000001U +#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5 +/** APB_SARADC_ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0; + * Set adc2 arbiterapb priority + */ +#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003U +#define APB_SARADC_ADC_ARB_APB_PRIORITY_M (APB_SARADC_ADC_ARB_APB_PRIORITY_V << APB_SARADC_ADC_ARB_APB_PRIORITY_S) +#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x00000003U +#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6 +/** APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1; + * Set adc2 arbiter rtc priority + */ +#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003U +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M (APB_SARADC_ADC_ARB_RTC_PRIORITY_V << APB_SARADC_ADC_ARB_RTC_PRIORITY_S) +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x00000003U +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8 +/** APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2; + * Set adc2 arbiter wifi priority + */ +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003U +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M (APB_SARADC_ADC_ARB_WIFI_PRIORITY_V << APB_SARADC_ADC_ARB_WIFI_PRIORITY_S) +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x00000003U +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10 +/** APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0; + * adc2 arbiter uses fixed priority + */ +#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12)) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (APB_SARADC_ADC_ARB_FIX_PRIORITY_V << APB_SARADC_ADC_ARB_FIX_PRIORITY_S) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x00000001U +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12 -#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x28) -/* APB_SARADC_FILTER_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: enable apb_adc1_filter.*/ -#define APB_SARADC_FILTER_RESET (BIT(31)) -#define APB_SARADC_FILTER_RESET_M (BIT(31)) -#define APB_SARADC_FILTER_RESET_V 0x1 -#define APB_SARADC_FILTER_RESET_S 31 -/* APB_SARADC_FILTER_CHANNEL0 : R/W ;bitpos:[25:22] ;default: 4'd13 ; */ -/*description: apb_adc1_filter_factor.*/ -#define APB_SARADC_FILTER_CHANNEL0 0x0000000F -#define APB_SARADC_FILTER_CHANNEL0_M ((APB_SARADC_FILTER_CHANNEL0_V)<<(APB_SARADC_FILTER_CHANNEL0_S)) -#define APB_SARADC_FILTER_CHANNEL0_V 0xF -#define APB_SARADC_FILTER_CHANNEL0_S 22 -/* APB_SARADC_FILTER_CHANNEL1 : R/W ;bitpos:[21:18] ;default: 4'd13 ; */ -/*description: Need add description.*/ -#define APB_SARADC_FILTER_CHANNEL1 0x0000000F -#define APB_SARADC_FILTER_CHANNEL1_M ((APB_SARADC_FILTER_CHANNEL1_V)<<(APB_SARADC_FILTER_CHANNEL1_S)) -#define APB_SARADC_FILTER_CHANNEL1_V 0xF +/** APB_SARADC_FILTER_CTRL0_REG register + * register description + */ +#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_BASE + 0x28) +/** APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13; + * Need add description + */ +#define APB_SARADC_FILTER_CHANNEL1 0x0000000FU +#define APB_SARADC_FILTER_CHANNEL1_M (APB_SARADC_FILTER_CHANNEL1_V << APB_SARADC_FILTER_CHANNEL1_S) +#define APB_SARADC_FILTER_CHANNEL1_V 0x0000000FU #define APB_SARADC_FILTER_CHANNEL1_S 18 +/** APB_SARADC_FILTER_CHANNEL0 : R/W; bitpos: [25:22]; default: 13; + * apb_adc1_filter_factor + */ +#define APB_SARADC_FILTER_CHANNEL0 0x0000000FU +#define APB_SARADC_FILTER_CHANNEL0_M (APB_SARADC_FILTER_CHANNEL0_V << APB_SARADC_FILTER_CHANNEL0_S) +#define APB_SARADC_FILTER_CHANNEL0_V 0x0000000FU +#define APB_SARADC_FILTER_CHANNEL0_S 22 +/** APB_SARADC_FILTER_RESET : R/W; bitpos: [31]; default: 0; + * enable apb_adc1_filter + */ +#define APB_SARADC_FILTER_RESET (BIT(31)) +#define APB_SARADC_FILTER_RESET_M (APB_SARADC_FILTER_RESET_V << APB_SARADC_FILTER_RESET_S) +#define APB_SARADC_FILTER_RESET_V 0x00000001U +#define APB_SARADC_FILTER_RESET_S 31 -#define APB_SARADC_APB_SARADC1_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x2C) -/* APB_SARADC_ADC1_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_ADC1_DATA 0x0001FFFF -#define APB_SARADC_ADC1_DATA_M ((APB_SARADC_ADC1_DATA_V)<<(APB_SARADC_ADC1_DATA_S)) -#define APB_SARADC_ADC1_DATA_V 0x1FFFF -#define APB_SARADC_ADC1_DATA_S 0 +/** APB_SARADC1_DATA_STATUS_REG register + * register description + */ +#define APB_SARADC1_DATA_STATUS_REG (DR_REG_APB_BASE + 0x2c) +/** APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0; + * Need add description + */ +#define APB_SARADC1_DATA 0x0001FFFFU +#define APB_SARADC1_DATA_M (APB_SARADC1_DATA_V << APB_SARADC1_DATA_S) +#define APB_SARADC1_DATA_V 0x0001FFFFU +#define APB_SARADC1_DATA_S 0 -#define APB_SARADC_APB_SARADC2_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x30) -/* APB_SARADC_ADC2_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_ADC2_DATA 0x0001FFFF -#define APB_SARADC_ADC2_DATA_M ((APB_SARADC_ADC2_DATA_V)<<(APB_SARADC_ADC2_DATA_S)) -#define APB_SARADC_ADC2_DATA_V 0x1FFFF -#define APB_SARADC_ADC2_DATA_S 0 +/** APB_SARADC2_DATA_STATUS_REG register + * register description + */ +#define APB_SARADC2_DATA_STATUS_REG (DR_REG_APB_BASE + 0x30) +/** APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0; + * Need add description + */ +#define APB_SARADC2_DATA 0x0001FFFFU +#define APB_SARADC2_DATA_M (APB_SARADC2_DATA_V << APB_SARADC2_DATA_S) +#define APB_SARADC2_DATA_V 0x0001FFFFU +#define APB_SARADC2_DATA_S 0 -#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x34) -/* APB_SARADC_THRES0_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */ -/*description: saradc1's thres0 monitor thres.*/ -#define APB_SARADC_THRES0_LOW 0x00001FFF -#define APB_SARADC_THRES0_LOW_M ((APB_SARADC_THRES0_LOW_V)<<(APB_SARADC_THRES0_LOW_S)) -#define APB_SARADC_THRES0_LOW_V 0x1FFF -#define APB_SARADC_THRES0_LOW_S 18 -/* APB_SARADC_THRES0_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */ -/*description: saradc1's thres0 monitor thres.*/ -#define APB_SARADC_THRES0_HIGH 0x00001FFF -#define APB_SARADC_THRES0_HIGH_M ((APB_SARADC_THRES0_HIGH_V)<<(APB_SARADC_THRES0_HIGH_S)) -#define APB_SARADC_THRES0_HIGH_V 0x1FFF -#define APB_SARADC_THRES0_HIGH_S 5 -/* APB_SARADC_THRES0_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */ -/*description: Need add description.*/ -#define APB_SARADC_THRES0_CHANNEL 0x0000000F -#define APB_SARADC_THRES0_CHANNEL_M ((APB_SARADC_THRES0_CHANNEL_V)<<(APB_SARADC_THRES0_CHANNEL_S)) -#define APB_SARADC_THRES0_CHANNEL_V 0xF +/** APB_SARADC_THRES0_CTRL_REG register + * register description + */ +#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_BASE + 0x34) +/** APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13; + * Need add description + */ +#define APB_SARADC_THRES0_CHANNEL 0x0000000FU +#define APB_SARADC_THRES0_CHANNEL_M (APB_SARADC_THRES0_CHANNEL_V << APB_SARADC_THRES0_CHANNEL_S) +#define APB_SARADC_THRES0_CHANNEL_V 0x0000000FU #define APB_SARADC_THRES0_CHANNEL_S 0 +/** APB_SARADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191; + * saradc1's thres0 monitor thres + */ +#define APB_SARADC_THRES0_HIGH 0x00001FFFU +#define APB_SARADC_THRES0_HIGH_M (APB_SARADC_THRES0_HIGH_V << APB_SARADC_THRES0_HIGH_S) +#define APB_SARADC_THRES0_HIGH_V 0x00001FFFU +#define APB_SARADC_THRES0_HIGH_S 5 +/** APB_SARADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0; + * saradc1's thres0 monitor thres + */ +#define APB_SARADC_THRES0_LOW 0x00001FFFU +#define APB_SARADC_THRES0_LOW_M (APB_SARADC_THRES0_LOW_V << APB_SARADC_THRES0_LOW_S) +#define APB_SARADC_THRES0_LOW_V 0x00001FFFU +#define APB_SARADC_THRES0_LOW_S 18 -#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38) -/* APB_SARADC_THRES1_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */ -/*description: saradc1's thres0 monitor thres.*/ -#define APB_SARADC_THRES1_LOW 0x00001FFF -#define APB_SARADC_THRES1_LOW_M ((APB_SARADC_THRES1_LOW_V)<<(APB_SARADC_THRES1_LOW_S)) -#define APB_SARADC_THRES1_LOW_V 0x1FFF -#define APB_SARADC_THRES1_LOW_S 18 -/* APB_SARADC_THRES1_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */ -/*description: saradc1's thres0 monitor thres.*/ -#define APB_SARADC_THRES1_HIGH 0x00001FFF -#define APB_SARADC_THRES1_HIGH_M ((APB_SARADC_THRES1_HIGH_V)<<(APB_SARADC_THRES1_HIGH_S)) -#define APB_SARADC_THRES1_HIGH_V 0x1FFF -#define APB_SARADC_THRES1_HIGH_S 5 -/* APB_SARADC_THRES1_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */ -/*description: Need add description.*/ -#define APB_SARADC_THRES1_CHANNEL 0x0000000F -#define APB_SARADC_THRES1_CHANNEL_M ((APB_SARADC_THRES1_CHANNEL_V)<<(APB_SARADC_THRES1_CHANNEL_S)) -#define APB_SARADC_THRES1_CHANNEL_V 0xF +/** APB_SARADC_THRES1_CTRL_REG register + * register description + */ +#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_BASE + 0x38) +/** APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13; + * Need add description + */ +#define APB_SARADC_THRES1_CHANNEL 0x0000000FU +#define APB_SARADC_THRES1_CHANNEL_M (APB_SARADC_THRES1_CHANNEL_V << APB_SARADC_THRES1_CHANNEL_S) +#define APB_SARADC_THRES1_CHANNEL_V 0x0000000FU #define APB_SARADC_THRES1_CHANNEL_S 0 +/** APB_SARADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191; + * saradc1's thres0 monitor thres + */ +#define APB_SARADC_THRES1_HIGH 0x00001FFFU +#define APB_SARADC_THRES1_HIGH_M (APB_SARADC_THRES1_HIGH_V << APB_SARADC_THRES1_HIGH_S) +#define APB_SARADC_THRES1_HIGH_V 0x00001FFFU +#define APB_SARADC_THRES1_HIGH_S 5 +/** APB_SARADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0; + * saradc1's thres0 monitor thres + */ +#define APB_SARADC_THRES1_LOW 0x00001FFFU +#define APB_SARADC_THRES1_LOW_M (APB_SARADC_THRES1_LOW_V << APB_SARADC_THRES1_LOW_S) +#define APB_SARADC_THRES1_LOW_V 0x00001FFFU +#define APB_SARADC_THRES1_LOW_S 18 -#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x3C) -/* APB_SARADC_THRES0_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_THRES0_EN (BIT(31)) -#define APB_SARADC_THRES0_EN_M (BIT(31)) -#define APB_SARADC_THRES0_EN_V 0x1 -#define APB_SARADC_THRES0_EN_S 31 -/* APB_SARADC_THRES1_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_THRES1_EN (BIT(30)) -#define APB_SARADC_THRES1_EN_M (BIT(30)) -#define APB_SARADC_THRES1_EN_V 0x1 -#define APB_SARADC_THRES1_EN_S 30 -/* APB_SARADC_THRES2_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_THRES2_EN (BIT(29)) -#define APB_SARADC_THRES2_EN_M (BIT(29)) -#define APB_SARADC_THRES2_EN_V 0x1 -#define APB_SARADC_THRES2_EN_S 29 -/* APB_SARADC_THRES3_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_THRES3_EN (BIT(28)) -#define APB_SARADC_THRES3_EN_M (BIT(28)) -#define APB_SARADC_THRES3_EN_V 0x1 -#define APB_SARADC_THRES3_EN_S 28 -/* APB_SARADC_THRES_ALL_EN : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: Need add description.*/ +/** APB_SARADC_THRES_CTRL_REG register + * register description + */ +#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_BASE + 0x3c) +/** APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0; + * Need add description + */ #define APB_SARADC_THRES_ALL_EN (BIT(27)) -#define APB_SARADC_THRES_ALL_EN_M (BIT(27)) -#define APB_SARADC_THRES_ALL_EN_V 0x1 +#define APB_SARADC_THRES_ALL_EN_M (APB_SARADC_THRES_ALL_EN_V << APB_SARADC_THRES_ALL_EN_S) +#define APB_SARADC_THRES_ALL_EN_V 0x00000001U #define APB_SARADC_THRES_ALL_EN_S 27 +/** APB_SARADC_THRES3_EN : R/W; bitpos: [28]; default: 0; + * Need add description + */ +#define APB_SARADC_THRES3_EN (BIT(28)) +#define APB_SARADC_THRES3_EN_M (APB_SARADC_THRES3_EN_V << APB_SARADC_THRES3_EN_S) +#define APB_SARADC_THRES3_EN_V 0x00000001U +#define APB_SARADC_THRES3_EN_S 28 +/** APB_SARADC_THRES2_EN : R/W; bitpos: [29]; default: 0; + * Need add description + */ +#define APB_SARADC_THRES2_EN (BIT(29)) +#define APB_SARADC_THRES2_EN_M (APB_SARADC_THRES2_EN_V << APB_SARADC_THRES2_EN_S) +#define APB_SARADC_THRES2_EN_V 0x00000001U +#define APB_SARADC_THRES2_EN_S 29 +/** APB_SARADC_THRES1_EN : R/W; bitpos: [30]; default: 0; + * Need add description + */ +#define APB_SARADC_THRES1_EN (BIT(30)) +#define APB_SARADC_THRES1_EN_M (APB_SARADC_THRES1_EN_V << APB_SARADC_THRES1_EN_S) +#define APB_SARADC_THRES1_EN_V 0x00000001U +#define APB_SARADC_THRES1_EN_S 30 +/** APB_SARADC_THRES0_EN : R/W; bitpos: [31]; default: 0; + * Need add description + */ +#define APB_SARADC_THRES0_EN (BIT(31)) +#define APB_SARADC_THRES0_EN_M (APB_SARADC_THRES0_EN_V << APB_SARADC_THRES0_EN_S) +#define APB_SARADC_THRES0_EN_V 0x00000001U +#define APB_SARADC_THRES0_EN_S 31 -#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x40) -/* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_ADC1_DONE_INT_ENA (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_ENA_M (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_ENA_V 0x1 -#define APB_SARADC_ADC1_DONE_INT_ENA_S 31 -/* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_ENA_M (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_ENA_V 0x1 -#define APB_SARADC_ADC2_DONE_INT_ENA_S 30 -/* APB_SARADC_THRES0_HIGH_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_ENA_M (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_ENA_V 0x1 -#define APB_SARADC_THRES0_HIGH_INT_ENA_S 29 -/* APB_SARADC_THRES1_HIGH_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_ENA_M (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_ENA_V 0x1 -#define APB_SARADC_THRES1_HIGH_INT_ENA_S 28 -/* APB_SARADC_THRES0_LOW_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_THRES0_LOW_INT_ENA (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_ENA_M (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_ENA_V 0x1 -#define APB_SARADC_THRES0_LOW_INT_ENA_S 27 -/* APB_SARADC_THRES1_LOW_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Need add description.*/ +/** APB_SARADC_INT_ENA_REG register + * register description + */ +#define APB_SARADC_INT_ENA_REG (DR_REG_APB_BASE + 0x40) +/** APB_SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0; + * Need add description + */ #define APB_SARADC_THRES1_LOW_INT_ENA (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_ENA_M (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_ENA_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_ENA_M (APB_SARADC_THRES1_LOW_INT_ENA_V << APB_SARADC_THRES1_LOW_INT_ENA_S) +#define APB_SARADC_THRES1_LOW_INT_ENA_V 0x00000001U #define APB_SARADC_THRES1_LOW_INT_ENA_S 26 +/** APB_SARADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0; + * Need add description + */ +#define APB_SARADC_THRES0_LOW_INT_ENA (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_ENA_M (APB_SARADC_THRES0_LOW_INT_ENA_V << APB_SARADC_THRES0_LOW_INT_ENA_S) +#define APB_SARADC_THRES0_LOW_INT_ENA_V 0x00000001U +#define APB_SARADC_THRES0_LOW_INT_ENA_S 27 +/** APB_SARADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0; + * Need add description + */ +#define APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_ENA_M (APB_SARADC_THRES1_HIGH_INT_ENA_V << APB_SARADC_THRES1_HIGH_INT_ENA_S) +#define APB_SARADC_THRES1_HIGH_INT_ENA_V 0x00000001U +#define APB_SARADC_THRES1_HIGH_INT_ENA_S 28 +/** APB_SARADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0; + * Need add description + */ +#define APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_ENA_M (APB_SARADC_THRES0_HIGH_INT_ENA_V << APB_SARADC_THRES0_HIGH_INT_ENA_S) +#define APB_SARADC_THRES0_HIGH_INT_ENA_V 0x00000001U +#define APB_SARADC_THRES0_HIGH_INT_ENA_S 29 +/** APB_SARADC2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0; + * Need add description + */ +#define APB_SARADC2_DONE_INT_ENA (BIT(30)) +#define APB_SARADC2_DONE_INT_ENA_M (APB_SARADC2_DONE_INT_ENA_V << APB_SARADC2_DONE_INT_ENA_S) +#define APB_SARADC2_DONE_INT_ENA_V 0x00000001U +#define APB_SARADC2_DONE_INT_ENA_S 30 +/** APB_SARADC1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0; + * Need add description + */ +#define APB_SARADC1_DONE_INT_ENA (BIT(31)) +#define APB_SARADC1_DONE_INT_ENA_M (APB_SARADC1_DONE_INT_ENA_V << APB_SARADC1_DONE_INT_ENA_S) +#define APB_SARADC1_DONE_INT_ENA_V 0x00000001U +#define APB_SARADC1_DONE_INT_ENA_S 31 -#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x44) -/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_ADC1_DONE_INT_RAW (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_RAW_M (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_RAW_V 0x1 -#define APB_SARADC_ADC1_DONE_INT_RAW_S 31 -/* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_ADC2_DONE_INT_RAW (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_RAW_M (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_RAW_V 0x1 -#define APB_SARADC_ADC2_DONE_INT_RAW_S 30 -/* APB_SARADC_THRES0_HIGH_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_RAW_M (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_RAW_V 0x1 -#define APB_SARADC_THRES0_HIGH_INT_RAW_S 29 -/* APB_SARADC_THRES1_HIGH_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_RAW_M (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_RAW_V 0x1 -#define APB_SARADC_THRES1_HIGH_INT_RAW_S 28 -/* APB_SARADC_THRES0_LOW_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_THRES0_LOW_INT_RAW (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_RAW_M (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_RAW_V 0x1 -#define APB_SARADC_THRES0_LOW_INT_RAW_S 27 -/* APB_SARADC_THRES1_LOW_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Need add description.*/ +/** APB_SARADC_INT_RAW_REG register + * register description + */ +#define APB_SARADC_INT_RAW_REG (DR_REG_APB_BASE + 0x44) +/** APB_SARADC_THRES1_LOW_INT_RAW : RO; bitpos: [26]; default: 0; + * Need add description + */ #define APB_SARADC_THRES1_LOW_INT_RAW (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_RAW_M (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_RAW_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_RAW_M (APB_SARADC_THRES1_LOW_INT_RAW_V << APB_SARADC_THRES1_LOW_INT_RAW_S) +#define APB_SARADC_THRES1_LOW_INT_RAW_V 0x00000001U #define APB_SARADC_THRES1_LOW_INT_RAW_S 26 +/** APB_SARADC_THRES0_LOW_INT_RAW : RO; bitpos: [27]; default: 0; + * Need add description + */ +#define APB_SARADC_THRES0_LOW_INT_RAW (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_RAW_M (APB_SARADC_THRES0_LOW_INT_RAW_V << APB_SARADC_THRES0_LOW_INT_RAW_S) +#define APB_SARADC_THRES0_LOW_INT_RAW_V 0x00000001U +#define APB_SARADC_THRES0_LOW_INT_RAW_S 27 +/** APB_SARADC_THRES1_HIGH_INT_RAW : RO; bitpos: [28]; default: 0; + * Need add description + */ +#define APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_RAW_M (APB_SARADC_THRES1_HIGH_INT_RAW_V << APB_SARADC_THRES1_HIGH_INT_RAW_S) +#define APB_SARADC_THRES1_HIGH_INT_RAW_V 0x00000001U +#define APB_SARADC_THRES1_HIGH_INT_RAW_S 28 +/** APB_SARADC_THRES0_HIGH_INT_RAW : RO; bitpos: [29]; default: 0; + * Need add description + */ +#define APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_RAW_M (APB_SARADC_THRES0_HIGH_INT_RAW_V << APB_SARADC_THRES0_HIGH_INT_RAW_S) +#define APB_SARADC_THRES0_HIGH_INT_RAW_V 0x00000001U +#define APB_SARADC_THRES0_HIGH_INT_RAW_S 29 +/** APB_SARADC2_DONE_INT_RAW : RO; bitpos: [30]; default: 0; + * Need add description + */ +#define APB_SARADC2_DONE_INT_RAW (BIT(30)) +#define APB_SARADC2_DONE_INT_RAW_M (APB_SARADC2_DONE_INT_RAW_V << APB_SARADC2_DONE_INT_RAW_S) +#define APB_SARADC2_DONE_INT_RAW_V 0x00000001U +#define APB_SARADC2_DONE_INT_RAW_S 30 +/** APB_SARADC1_DONE_INT_RAW : RO; bitpos: [31]; default: 0; + * Need add description + */ +#define APB_SARADC1_DONE_INT_RAW (BIT(31)) +#define APB_SARADC1_DONE_INT_RAW_M (APB_SARADC1_DONE_INT_RAW_V << APB_SARADC1_DONE_INT_RAW_S) +#define APB_SARADC1_DONE_INT_RAW_V 0x00000001U +#define APB_SARADC1_DONE_INT_RAW_S 31 -#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x48) -/* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_ADC1_DONE_INT_ST (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_ST_M (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_ST_V 0x1 -#define APB_SARADC_ADC1_DONE_INT_ST_S 31 -/* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_ADC2_DONE_INT_ST (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_ST_M (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_ST_V 0x1 -#define APB_SARADC_ADC2_DONE_INT_ST_S 30 -/* APB_SARADC_THRES0_HIGH_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_THRES0_HIGH_INT_ST (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_ST_M (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_ST_V 0x1 -#define APB_SARADC_THRES0_HIGH_INT_ST_S 29 -/* APB_SARADC_THRES1_HIGH_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_THRES1_HIGH_INT_ST (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_ST_M (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_ST_V 0x1 -#define APB_SARADC_THRES1_HIGH_INT_ST_S 28 -/* APB_SARADC_THRES0_LOW_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_THRES0_LOW_INT_ST (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_ST_M (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_ST_V 0x1 -#define APB_SARADC_THRES0_LOW_INT_ST_S 27 -/* APB_SARADC_THRES1_LOW_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Need add description.*/ +/** APB_SARADC_INT_ST_REG register + * register description + */ +#define APB_SARADC_INT_ST_REG (DR_REG_APB_BASE + 0x48) +/** APB_SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0; + * Need add description + */ #define APB_SARADC_THRES1_LOW_INT_ST (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_ST_M (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_ST_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_ST_M (APB_SARADC_THRES1_LOW_INT_ST_V << APB_SARADC_THRES1_LOW_INT_ST_S) +#define APB_SARADC_THRES1_LOW_INT_ST_V 0x00000001U #define APB_SARADC_THRES1_LOW_INT_ST_S 26 +/** APB_SARADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0; + * Need add description + */ +#define APB_SARADC_THRES0_LOW_INT_ST (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_ST_M (APB_SARADC_THRES0_LOW_INT_ST_V << APB_SARADC_THRES0_LOW_INT_ST_S) +#define APB_SARADC_THRES0_LOW_INT_ST_V 0x00000001U +#define APB_SARADC_THRES0_LOW_INT_ST_S 27 +/** APB_SARADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0; + * Need add description + */ +#define APB_SARADC_THRES1_HIGH_INT_ST (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_ST_M (APB_SARADC_THRES1_HIGH_INT_ST_V << APB_SARADC_THRES1_HIGH_INT_ST_S) +#define APB_SARADC_THRES1_HIGH_INT_ST_V 0x00000001U +#define APB_SARADC_THRES1_HIGH_INT_ST_S 28 +/** APB_SARADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0; + * Need add description + */ +#define APB_SARADC_THRES0_HIGH_INT_ST (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_ST_M (APB_SARADC_THRES0_HIGH_INT_ST_V << APB_SARADC_THRES0_HIGH_INT_ST_S) +#define APB_SARADC_THRES0_HIGH_INT_ST_V 0x00000001U +#define APB_SARADC_THRES0_HIGH_INT_ST_S 29 +/** APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0; + * Need add description + */ +#define APB_SARADC2_DONE_INT_ST (BIT(30)) +#define APB_SARADC2_DONE_INT_ST_M (APB_SARADC2_DONE_INT_ST_V << APB_SARADC2_DONE_INT_ST_S) +#define APB_SARADC2_DONE_INT_ST_V 0x00000001U +#define APB_SARADC2_DONE_INT_ST_S 30 +/** APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0; + * Need add description + */ +#define APB_SARADC1_DONE_INT_ST (BIT(31)) +#define APB_SARADC1_DONE_INT_ST_M (APB_SARADC1_DONE_INT_ST_V << APB_SARADC1_DONE_INT_ST_S) +#define APB_SARADC1_DONE_INT_ST_V 0x00000001U +#define APB_SARADC1_DONE_INT_ST_S 31 -#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x4C) -/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_ADC1_DONE_INT_CLR (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_CLR_M (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_CLR_V 0x1 -#define APB_SARADC_ADC1_DONE_INT_CLR_S 31 -/* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_ADC2_DONE_INT_CLR (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_CLR_M (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_CLR_V 0x1 -#define APB_SARADC_ADC2_DONE_INT_CLR_S 30 -/* APB_SARADC_THRES0_HIGH_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_CLR_M (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_CLR_V 0x1 -#define APB_SARADC_THRES0_HIGH_INT_CLR_S 29 -/* APB_SARADC_THRES1_HIGH_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_CLR_M (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_CLR_V 0x1 -#define APB_SARADC_THRES1_HIGH_INT_CLR_S 28 -/* APB_SARADC_THRES0_LOW_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_THRES0_LOW_INT_CLR (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_CLR_M (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_CLR_V 0x1 -#define APB_SARADC_THRES0_LOW_INT_CLR_S 27 -/* APB_SARADC_THRES1_LOW_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Need add description.*/ +/** APB_SARADC_INT_CLR_REG register + * register description + */ +#define APB_SARADC_INT_CLR_REG (DR_REG_APB_BASE + 0x4c) +/** APB_SARADC_THRES1_LOW_INT_CLR : WO; bitpos: [26]; default: 0; + * Need add description + */ #define APB_SARADC_THRES1_LOW_INT_CLR (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_CLR_M (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_CLR_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_CLR_M (APB_SARADC_THRES1_LOW_INT_CLR_V << APB_SARADC_THRES1_LOW_INT_CLR_S) +#define APB_SARADC_THRES1_LOW_INT_CLR_V 0x00000001U #define APB_SARADC_THRES1_LOW_INT_CLR_S 26 +/** APB_SARADC_THRES0_LOW_INT_CLR : WO; bitpos: [27]; default: 0; + * Need add description + */ +#define APB_SARADC_THRES0_LOW_INT_CLR (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_CLR_M (APB_SARADC_THRES0_LOW_INT_CLR_V << APB_SARADC_THRES0_LOW_INT_CLR_S) +#define APB_SARADC_THRES0_LOW_INT_CLR_V 0x00000001U +#define APB_SARADC_THRES0_LOW_INT_CLR_S 27 +/** APB_SARADC_THRES1_HIGH_INT_CLR : WO; bitpos: [28]; default: 0; + * Need add description + */ +#define APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_CLR_M (APB_SARADC_THRES1_HIGH_INT_CLR_V << APB_SARADC_THRES1_HIGH_INT_CLR_S) +#define APB_SARADC_THRES1_HIGH_INT_CLR_V 0x00000001U +#define APB_SARADC_THRES1_HIGH_INT_CLR_S 28 +/** APB_SARADC_THRES0_HIGH_INT_CLR : WO; bitpos: [29]; default: 0; + * Need add description + */ +#define APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_CLR_M (APB_SARADC_THRES0_HIGH_INT_CLR_V << APB_SARADC_THRES0_HIGH_INT_CLR_S) +#define APB_SARADC_THRES0_HIGH_INT_CLR_V 0x00000001U +#define APB_SARADC_THRES0_HIGH_INT_CLR_S 29 +/** APB_SARADC2_DONE_INT_CLR : WO; bitpos: [30]; default: 0; + * Need add description + */ +#define APB_SARADC2_DONE_INT_CLR (BIT(30)) +#define APB_SARADC2_DONE_INT_CLR_M (APB_SARADC2_DONE_INT_CLR_V << APB_SARADC2_DONE_INT_CLR_S) +#define APB_SARADC2_DONE_INT_CLR_V 0x00000001U +#define APB_SARADC2_DONE_INT_CLR_S 30 +/** APB_SARADC1_DONE_INT_CLR : WO; bitpos: [31]; default: 0; + * Need add description + */ +#define APB_SARADC1_DONE_INT_CLR (BIT(31)) +#define APB_SARADC1_DONE_INT_CLR_M (APB_SARADC1_DONE_INT_CLR_V << APB_SARADC1_DONE_INT_CLR_S) +#define APB_SARADC1_DONE_INT_CLR_V 0x00000001U +#define APB_SARADC1_DONE_INT_CLR_S 31 -#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x50) -/* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: enable apb_adc use spi_dma.*/ -#define APB_SARADC_APB_ADC_TRANS (BIT(31)) -#define APB_SARADC_APB_ADC_TRANS_M (BIT(31)) -#define APB_SARADC_APB_ADC_TRANS_V 0x1 -#define APB_SARADC_APB_ADC_TRANS_S 31 -/* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: reset_apb_adc_state.*/ -#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30)) -#define APB_SARADC_APB_ADC_RESET_FSM_M (BIT(30)) -#define APB_SARADC_APB_ADC_RESET_FSM_V 0x1 -#define APB_SARADC_APB_ADC_RESET_FSM_S 30 -/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */ -/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num.*/ -#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFF -#define APB_SARADC_APB_ADC_EOF_NUM_M ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S)) -#define APB_SARADC_APB_ADC_EOF_NUM_V 0xFFFF +/** APB_SARADC_DMA_CONF_REG register + * register description + */ +#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_BASE + 0x50) +/** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255; + * the dma_in_suc_eof gen when sample cnt = spi_eof_num + */ +#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFFU +#define APB_SARADC_APB_ADC_EOF_NUM_M (APB_SARADC_APB_ADC_EOF_NUM_V << APB_SARADC_APB_ADC_EOF_NUM_S) +#define APB_SARADC_APB_ADC_EOF_NUM_V 0x0000FFFFU #define APB_SARADC_APB_ADC_EOF_NUM_S 0 +/** APB_SARADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0; + * reset_apb_adc_state + */ +#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30)) +#define APB_SARADC_APB_ADC_RESET_FSM_M (APB_SARADC_APB_ADC_RESET_FSM_V << APB_SARADC_APB_ADC_RESET_FSM_S) +#define APB_SARADC_APB_ADC_RESET_FSM_V 0x00000001U +#define APB_SARADC_APB_ADC_RESET_FSM_S 30 +/** APB_SARADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0; + * enable apb_adc use spi_dma + */ +#define APB_SARADC_APB_ADC_TRANS (BIT(31)) +#define APB_SARADC_APB_ADC_TRANS_M (APB_SARADC_APB_ADC_TRANS_V << APB_SARADC_APB_ADC_TRANS_S) +#define APB_SARADC_APB_ADC_TRANS_V 0x00000001U +#define APB_SARADC_APB_ADC_TRANS_S 31 -#define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x54) -/* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */ -/*description: Set this bit to enable clk_apll.*/ -#define APB_SARADC_CLK_SEL 0x00000003 -#define APB_SARADC_CLK_SEL_M ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S)) -#define APB_SARADC_CLK_SEL_V 0x3 -#define APB_SARADC_CLK_SEL_S 21 -/* APB_SARADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: Need add description.*/ +/** APB_SARADC_APB_ADC_CLKM_CONF_REG register + * register description + */ +#define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_BASE + 0x54) +/** APB_SARADC_REG_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4; + * Integral I2S clock divider value + */ +#define APB_SARADC_REG_CLKM_DIV_NUM 0x000000FFU +#define APB_SARADC_REG_CLKM_DIV_NUM_M (APB_SARADC_REG_CLKM_DIV_NUM_V << APB_SARADC_REG_CLKM_DIV_NUM_S) +#define APB_SARADC_REG_CLKM_DIV_NUM_V 0x000000FFU +#define APB_SARADC_REG_CLKM_DIV_NUM_S 0 +/** APB_SARADC_REG_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0; + * Fractional clock divider numerator value + */ +#define APB_SARADC_REG_CLKM_DIV_B 0x0000003FU +#define APB_SARADC_REG_CLKM_DIV_B_M (APB_SARADC_REG_CLKM_DIV_B_V << APB_SARADC_REG_CLKM_DIV_B_S) +#define APB_SARADC_REG_CLKM_DIV_B_V 0x0000003FU +#define APB_SARADC_REG_CLKM_DIV_B_S 8 +/** APB_SARADC_REG_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0; + * Fractional clock divider denominator value + */ +#define APB_SARADC_REG_CLKM_DIV_A 0x0000003FU +#define APB_SARADC_REG_CLKM_DIV_A_M (APB_SARADC_REG_CLKM_DIV_A_V << APB_SARADC_REG_CLKM_DIV_A_S) +#define APB_SARADC_REG_CLKM_DIV_A_V 0x0000003FU +#define APB_SARADC_REG_CLKM_DIV_A_S 14 +/** APB_SARADC_CLK_EN : R/W; bitpos: [20]; default: 0; + * Need add description + */ #define APB_SARADC_CLK_EN (BIT(20)) -#define APB_SARADC_CLK_EN_M (BIT(20)) -#define APB_SARADC_CLK_EN_V 0x1 +#define APB_SARADC_CLK_EN_M (APB_SARADC_CLK_EN_V << APB_SARADC_CLK_EN_S) +#define APB_SARADC_CLK_EN_V 0x00000001U #define APB_SARADC_CLK_EN_S 20 -/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */ -/*description: Fractional clock divider denominator value.*/ -#define APB_SARADC_CLKM_DIV_A 0x0000003F -#define APB_SARADC_CLKM_DIV_A_M ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S)) -#define APB_SARADC_CLKM_DIV_A_V 0x3F -#define APB_SARADC_CLKM_DIV_A_S 14 -/* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */ -/*description: Fractional clock divider numerator value.*/ -#define APB_SARADC_CLKM_DIV_B 0x0000003F -#define APB_SARADC_CLKM_DIV_B_M ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S)) -#define APB_SARADC_CLKM_DIV_B_V 0x3F -#define APB_SARADC_CLKM_DIV_B_S 8 -/* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */ -/*description: Integral I2S clock divider value.*/ -#define APB_SARADC_CLKM_DIV_NUM 0x000000FF -#define APB_SARADC_CLKM_DIV_NUM_M ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S)) -#define APB_SARADC_CLKM_DIV_NUM_V 0xFF -#define APB_SARADC_CLKM_DIV_NUM_S 0 +/** APB_SARADC_REG_CLK_SEL : R/W; bitpos: [22:21]; default: 0; + * Set this bit to enable clk_apll + */ +#define APB_SARADC_REG_CLK_SEL 0x00000003U +#define APB_SARADC_REG_CLK_SEL_M (APB_SARADC_REG_CLK_SEL_V << APB_SARADC_REG_CLK_SEL_S) +#define APB_SARADC_REG_CLK_SEL_V 0x00000003U +#define APB_SARADC_REG_CLK_SEL_S 21 -#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58) -/* APB_SARADC_TSENS_PU : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_TSENS_PU (BIT(22)) -#define APB_SARADC_TSENS_PU_M (BIT(22)) -#define APB_SARADC_TSENS_PU_V 0x1 -#define APB_SARADC_TSENS_PU_S 22 -/* APB_SARADC_TSENS_CLK_DIV : R/W ;bitpos:[21:14] ;default: 8'd6 ; */ -/*description: Need add description.*/ -#define APB_SARADC_TSENS_CLK_DIV 0x000000FF -#define APB_SARADC_TSENS_CLK_DIV_M ((APB_SARADC_TSENS_CLK_DIV_V)<<(APB_SARADC_TSENS_CLK_DIV_S)) -#define APB_SARADC_TSENS_CLK_DIV_V 0xFF -#define APB_SARADC_TSENS_CLK_DIV_S 14 -/* APB_SARADC_TSENS_IN_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_TSENS_IN_INV (BIT(13)) -#define APB_SARADC_TSENS_IN_INV_M (BIT(13)) -#define APB_SARADC_TSENS_IN_INV_V 0x1 -#define APB_SARADC_TSENS_IN_INV_S 13 -/* APB_SARADC_TSENS_OUT : RO ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_TSENS_OUT 0x000000FF -#define APB_SARADC_TSENS_OUT_M ((APB_SARADC_TSENS_OUT_V)<<(APB_SARADC_TSENS_OUT_S)) -#define APB_SARADC_TSENS_OUT_V 0xFF -#define APB_SARADC_TSENS_OUT_S 0 +/** APB_SARADC_APB_TSENS_CTRL_REG register + * register description + */ +#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_BASE + 0x58) +/** APB_SARADC_REG_TSENS_OUT : RO; bitpos: [7:0]; default: 0; + * Need add description + */ +#define APB_SARADC_REG_TSENS_OUT 0x000000FFU +#define APB_SARADC_REG_TSENS_OUT_M (APB_SARADC_REG_TSENS_OUT_V << APB_SARADC_REG_TSENS_OUT_S) +#define APB_SARADC_REG_TSENS_OUT_V 0x000000FFU +#define APB_SARADC_REG_TSENS_OUT_S 0 +/** APB_SARADC_REG_TSENS_IN_INV : R/W; bitpos: [13]; default: 0; + * Need add description + */ +#define APB_SARADC_REG_TSENS_IN_INV (BIT(13)) +#define APB_SARADC_REG_TSENS_IN_INV_M (APB_SARADC_REG_TSENS_IN_INV_V << APB_SARADC_REG_TSENS_IN_INV_S) +#define APB_SARADC_REG_TSENS_IN_INV_V 0x00000001U +#define APB_SARADC_REG_TSENS_IN_INV_S 13 +/** APB_SARADC_REG_TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6; + * Need add description + */ +#define APB_SARADC_REG_TSENS_CLK_DIV 0x000000FFU +#define APB_SARADC_REG_TSENS_CLK_DIV_M (APB_SARADC_REG_TSENS_CLK_DIV_V << APB_SARADC_REG_TSENS_CLK_DIV_S) +#define APB_SARADC_REG_TSENS_CLK_DIV_V 0x000000FFU +#define APB_SARADC_REG_TSENS_CLK_DIV_S 14 +/** APB_SARADC_REG_TSENS_PU : R/W; bitpos: [22]; default: 0; + * Need add description + */ +#define APB_SARADC_REG_TSENS_PU (BIT(22)) +#define APB_SARADC_REG_TSENS_PU_M (APB_SARADC_REG_TSENS_PU_V << APB_SARADC_REG_TSENS_PU_S) +#define APB_SARADC_REG_TSENS_PU_V 0x00000001U +#define APB_SARADC_REG_TSENS_PU_S 22 -#define APB_SARADC_ APB_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x5C) -/* APB_SARADC_TSENS_CLK_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Need add description.*/ +/** APB_SARADC_APB_TSENS_CTRL2_REG register + * register description + */ +#define APB_SARADC_APB_TSENS_CTRL2_REG (DR_REG_APB_BASE + 0x5c) +/** APB_SARADC_REG_TSENS_XPD_WAIT : R/W; bitpos: [11:0]; default: 2; + * Need add description + */ +#define APB_SARADC_REG_TSENS_XPD_WAIT 0x00000FFFU +#define APB_SARADC_REG_TSENS_XPD_WAIT_M (APB_SARADC_REG_TSENS_XPD_WAIT_V << APB_SARADC_REG_TSENS_XPD_WAIT_S) +#define APB_SARADC_REG_TSENS_XPD_WAIT_V 0x00000FFFU +#define APB_SARADC_REG_TSENS_XPD_WAIT_S 0 +/** APB_SARADC_REG_TSENS_XPD_FORCE : R/W; bitpos: [13:12]; default: 0; + * Need add description + */ +#define APB_SARADC_REG_TSENS_XPD_FORCE 0x00000003U +#define APB_SARADC_REG_TSENS_XPD_FORCE_M (APB_SARADC_REG_TSENS_XPD_FORCE_V << APB_SARADC_REG_TSENS_XPD_FORCE_S) +#define APB_SARADC_REG_TSENS_XPD_FORCE_V 0x00000003U +#define APB_SARADC_REG_TSENS_XPD_FORCE_S 12 +/** APB_SARADC_REG_TSENS_CLK_INV : R/W; bitpos: [14]; default: 1; + * Need add description + */ +#define APB_SARADC_REG_TSENS_CLK_INV (BIT(14)) +#define APB_SARADC_REG_TSENS_CLK_INV_M (APB_SARADC_REG_TSENS_CLK_INV_V << APB_SARADC_REG_TSENS_CLK_INV_S) +#define APB_SARADC_REG_TSENS_CLK_INV_V 0x00000001U +#define APB_SARADC_REG_TSENS_CLK_INV_S 14 +/** APB_SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0; + * Need add description + */ #define APB_SARADC_TSENS_CLK_SEL (BIT(15)) -#define APB_SARADC_TSENS_CLK_SEL_M (BIT(15)) -#define APB_SARADC_TSENS_CLK_SEL_V 0x1 +#define APB_SARADC_TSENS_CLK_SEL_M (APB_SARADC_TSENS_CLK_SEL_V << APB_SARADC_TSENS_CLK_SEL_S) +#define APB_SARADC_TSENS_CLK_SEL_V 0x00000001U #define APB_SARADC_TSENS_CLK_SEL_S 15 -/* APB_SARADC_TSENS_CLK_INV : R/W ;bitpos:[14] ;default: 1'b1 ; */ -/*description: Need add description.*/ -#define APB_SARADC_TSENS_CLK_INV (BIT(14)) -#define APB_SARADC_TSENS_CLK_INV_M (BIT(14)) -#define APB_SARADC_TSENS_CLK_INV_V 0x1 -#define APB_SARADC_TSENS_CLK_INV_S 14 -/* APB_SARADC_TSENS_XPD_FORCE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ -/*description: Need add description.*/ -#define APB_SARADC_TSENS_XPD_FORCE 0x00000003 -#define APB_SARADC_TSENS_XPD_FORCE_M ((APB_SARADC_TSENS_XPD_FORCE_V)<<(APB_SARADC_TSENS_XPD_FORCE_S)) -#define APB_SARADC_TSENS_XPD_FORCE_V 0x3 -#define APB_SARADC_TSENS_XPD_FORCE_S 12 -/* APB_SARADC_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */ -/*description: Need add description.*/ -#define APB_SARADC_TSENS_XPD_WAIT 0x00000FFF -#define APB_SARADC_TSENS_XPD_WAIT_M ((APB_SARADC_TSENS_XPD_WAIT_V)<<(APB_SARADC_TSENS_XPD_WAIT_S)) -#define APB_SARADC_TSENS_XPD_WAIT_V 0xFFF -#define APB_SARADC_TSENS_XPD_WAIT_S 0 -#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x60) -/* APB_SARADC_CALI_CFG : R/W ;bitpos:[16:0] ;default: 17'h8000 ; */ -/*description: Need add description.*/ -#define APB_SARADC_CALI_CFG 0x0001FFFF -#define APB_SARADC_CALI_CFG_M ((APB_SARADC_CALI_CFG_V)<<(APB_SARADC_CALI_CFG_S)) -#define APB_SARADC_CALI_CFG_V 0x1FFFF +/** APB_SARADC_CALI_REG register + * register description + */ +#define APB_SARADC_CALI_REG (DR_REG_APB_BASE + 0x60) +/** APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768; + * Need add description + */ +#define APB_SARADC_CALI_CFG 0x0001FFFFU +#define APB_SARADC_CALI_CFG_M (APB_SARADC_CALI_CFG_V << APB_SARADC_CALI_CFG_S) +#define APB_SARADC_CALI_CFG_V 0x0001FFFFU #define APB_SARADC_CALI_CFG_S 0 -#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3FC) -/* APB_SARADC_DATE : R/W ;bitpos:[31:0] ;default: 32'h02107210 ; */ -/*description: Need add description.*/ -#define APB_SARADC_DATE 0xFFFFFFFF -#define APB_SARADC_DATE_M ((APB_SARADC_DATE_V)<<(APB_SARADC_DATE_S)) -#define APB_SARADC_DATE_V 0xFFFFFFFF +/** APB_SARADC_APB_CTRL_DATE_REG register + * register description + */ +#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_BASE + 0x3fc) +/** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 34632208; + * Need add description + */ +#define APB_SARADC_DATE 0xFFFFFFFFU +#define APB_SARADC_DATE_M (APB_SARADC_DATE_V << APB_SARADC_DATE_S) +#define APB_SARADC_DATE_V 0xFFFFFFFFU #define APB_SARADC_DATE_S 0 - #ifdef __cplusplus } #endif - - - -#endif /*_SOC_APB_SARADC_REG_H_ */ diff --git a/components/soc/esp8684/include/soc/apb_saradc_struct.h b/components/soc/esp8684/include/soc/apb_saradc_struct.h index 95e231c947..d48083c3de 100644 --- a/components/soc/esp8684/include/soc/apb_saradc_struct.h +++ b/components/soc/esp8684/include/soc/apb_saradc_struct.h @@ -1,487 +1,694 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_APB_SARADC_STRUCT_H_ -#define _SOC_APB_SARADC_STRUCT_H_ - +#pragma once +#include #ifdef __cplusplus extern "C" { #endif -typedef volatile struct apb_saradc_dev_s { - union { - struct { - uint32_t start_force : 1; /*Need add description*/ - uint32_t start : 1; /*Need add description*/ - uint32_t reserved2 : 4; /*Reserved 0: single mode, 1: double mode, 2: alternate mode*/ - uint32_t sar_clk_gated : 1; /*Need add description*/ - uint32_t sar_clk_div : 8; /*SAR clock divider*/ - uint32_t sar_patt_len : 3; /* 0 ~ 15 means length 1 ~ 16*/ - uint32_t reserved18 : 5; /*Reserved*/ - uint32_t sar_patt_p_clear : 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/ - uint32_t reserved24 : 3; /*Reserved*/ - uint32_t xpd_sar_force : 2; /*force option to xpd sar blocks*/ - uint32_t reserved29 : 1; /*Reserved*/ - uint32_t wait_arb_cycle : 2; /*wait arbit signal stable after sar_done*/ - }; - uint32_t val; - } ctrl; - union { - struct { - uint32_t meas_num_limit : 1; /*Need add description*/ - uint32_t max_meas_num : 8; /*max conversion number*/ - uint32_t sar1_inv : 1; /*1: data to DIG ADC1 CTRL is inverted, otherwise not*/ - uint32_t sar2_inv : 1; /*1: data to DIG ADC2 CTRL is inverted, otherwise not*/ - uint32_t reserved11 : 1; /*Reserved1: select saradc timer 0: i2s_ws trigger*/ - uint32_t timer_target : 12; /*to set saradc timer target*/ - uint32_t timer_en : 1; /*to enable saradc timer trigger*/ - uint32_t reserved25 : 7; /*Reserved*/ - }; - uint32_t val; - } ctrl2; - union { - struct { - uint32_t reserved0 : 26; /*Reserved*/ - uint32_t filter_factor1 : 3; /*Need add description*/ - uint32_t filter_factor0 : 3; /*Need add description*/ - }; - uint32_t val; - } filter_ctrl1; - union { - struct { - uint32_t xpd_wait : 8; /*Need add description*/ - uint32_t rstb_wait : 8; /*Need add description*/ - uint32_t standby_wait : 8; /*Need add description*/ - uint32_t reserved24 : 8; /*Reserved*/ - }; - uint32_t val; - } fsm_wait; - uint32_t sar1_status; - uint32_t sar2_status; - union { - struct { - uint32_t sar_patt_tab1 : 24; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/ - uint32_t reserved24 : 8; /*Reserved*/ - }; - uint32_t val; - } sar_patt_tab[2]; - union { - struct { - uint32_t reserved0 : 23; /*Reserved*/ - uint32_t onetime_atten : 2; /*Need add description*/ - uint32_t onetime_channel : 4; /*Need add description*/ - uint32_t onetime_start : 1; /*Need add description*/ - uint32_t adc2_onetime_sample : 1; /*Need add description*/ - uint32_t adc1_onetime_sample : 1; /*Need add description*/ - }; - uint32_t val; - } onetime_sample; - union { - struct { - uint32_t reserved0 : 2; /*Reserved*/ - uint32_t adc_arb_apb_force : 1; /*adc2 arbiter force to enableapb controller*/ - uint32_t adc_arb_rtc_force : 1; /*adc2 arbiter force to enable rtc controller*/ - uint32_t adc_arb_wifi_force : 1; /*adc2 arbiter force to enable wifi controller*/ - uint32_t adc_arb_grant_force : 1; /*adc2 arbiter force grant*/ - uint32_t adc_arb_apb_priority : 2; /*Set adc2 arbiterapb priority*/ - uint32_t adc_arb_rtc_priority : 2; /*Set adc2 arbiter rtc priority*/ - uint32_t adc_arb_wifi_priority : 2; /*Set adc2 arbiter wifi priority*/ - uint32_t adc_arb_fix_priority : 1; /*adc2 arbiter uses fixed priority*/ - uint32_t reserved13 : 19; /*Reserved*/ - }; - uint32_t val; - } apb_adc_arb_ctrl; - union { - struct { - uint32_t reserved0 : 18; /*Reserved*/ - uint32_t filter_channel1 : 4; /*Need add description*/ - uint32_t filter_channel0 : 4; /*apb_adc1_filter_factor*/ - uint32_t reserved26 : 5; /*Reserved*/ - uint32_t filter_reset : 1; /*enable apb_adc1_filter*/ - }; - uint32_t val; - } filter_ctrl0; - union { - struct { - uint32_t adc1_data : 17; /*Need add description*/ - uint32_t reserved17 : 15; /*Reserved*/ - }; - uint32_t val; - } apb_saradc1_data_status; - union { - struct { - uint32_t adc2_data : 17; /*Need add description*/ - uint32_t reserved17 : 15; /*Reserved*/ - }; - uint32_t val; - } apb_saradc2_data_status; - union { - struct { - uint32_t thres0_channel : 4; /*Need add description*/ - uint32_t reserved4 : 1; /*Reserved*/ - uint32_t thres0_high : 13; /*saradc1's thres0 monitor thres*/ - uint32_t thres0_low : 13; /*saradc1's thres0 monitor thres*/ - uint32_t reserved31 : 1; /*Reserved*/ - }; - uint32_t val; - } thres0_ctrl; - union { - struct { - uint32_t thres1_channel : 4; /*Need add description*/ - uint32_t reserved4 : 1; /*Reserved*/ - uint32_t thres1_high : 13; /*saradc1's thres0 monitor thres*/ - uint32_t thres1_low : 13; /*saradc1's thres0 monitor thres*/ - uint32_t reserved31 : 1; /*Reserved*/ - }; - uint32_t val; - } thres1_ctrl; - union { - struct { - uint32_t reserved0 : 27; /*Reserved*/ - uint32_t thres_all_en : 1; /*Need add description*/ - uint32_t thres3_en : 1; /*Need add description*/ - uint32_t thres2_en : 1; /*Need add description*/ - uint32_t thres1_en : 1; /*Need add description*/ - uint32_t thres0_en : 1; /*Need add description*/ - }; - uint32_t val; - } thres_ctrl; - union { - struct { - uint32_t reserved0 : 26; /*Reserved*/ - uint32_t thres1_low : 1; /*Need add description*/ - uint32_t thres0_low : 1; /*Need add description*/ - uint32_t thres1_high : 1; /*Need add description*/ - uint32_t thres0_high : 1; /*Need add description*/ - uint32_t adc2_done : 1; /*Need add description*/ - uint32_t adc1_done : 1; /*Need add description*/ - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t reserved0 : 26; /*Reserved*/ - uint32_t thres1_low : 1; /*Need add description*/ - uint32_t thres0_low : 1; /*Need add description*/ - uint32_t thres1_high : 1; /*Need add description*/ - uint32_t thres0_high : 1; /*Need add description*/ - uint32_t adc2_done : 1; /*Need add description*/ - uint32_t adc1_done : 1; /*Need add description*/ - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t reserved0 : 26; /*Reserved*/ - uint32_t thres1_low : 1; /*Need add description*/ - uint32_t thres0_low : 1; /*Need add description*/ - uint32_t thres1_high : 1; /*Need add description*/ - uint32_t thres0_high : 1; /*Need add description*/ - uint32_t adc2_done : 1; /*Need add description*/ - uint32_t adc1_done : 1; /*Need add description*/ - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t reserved0 : 26; /*Reserved*/ - uint32_t thres1_low : 1; /*Need add description*/ - uint32_t thres0_low : 1; /*Need add description*/ - uint32_t thres1_high : 1; /*Need add description*/ - uint32_t thres0_high : 1; /*Need add description*/ - uint32_t adc2_done : 1; /*Need add description*/ - uint32_t adc1_done : 1; /*Need add description*/ - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t apb_adc_eof_num : 16; /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/ - uint32_t reserved16 : 14; /*Reserved*/ - uint32_t apb_adc_reset_fsm : 1; /*reset_apb_adc_state*/ - uint32_t apb_adc_trans : 1; /*enable apb_adc use spi_dma*/ - }; - uint32_t val; - } dma_conf; - union { - struct { - uint32_t clkm_div_num : 8; /*Integral I2S clock divider value*/ - uint32_t clkm_div_b : 6; /*Fractional clock divider numerator value*/ - uint32_t clkm_div_a : 6; /*Fractional clock divider denominator value*/ - uint32_t clk_en : 1; /*Need add description*/ - uint32_t clk_sel : 2; /*Set this bit to enable clk_apll*/ - uint32_t reserved23 : 9; /*Reserved*/ - }; - uint32_t val; - } apb_adc_clkm_conf; - union { - struct { - uint32_t tsens_out : 8; /*Need add description*/ - uint32_t reserved8 : 5; /*Reserved*/ - uint32_t tsens_in_inv : 1; /*Need add description*/ - uint32_t tsens_clk_div : 8; /*Need add description*/ - uint32_t tsens_pu : 1; /*Need add description*/ - uint32_t reserved23 : 9; /*Reserved*/ - }; - uint32_t val; - } apb_tsens_ctrl; - union { - struct { - uint32_t tsens_xpd_wait : 12; /*Need add description*/ - uint32_t tsens_xpd_force : 2; /*Need add description*/ - uint32_t tsens_clk_inv : 1; /*Need add description*/ - uint32_t tsens_clk_sel : 1; /*Need add description*/ - uint32_t reserved16 : 16; /*Reserved*/ - }; - uint32_t val; - } apb_tsens_ctrl2; - union { - struct { - uint32_t cali_cfg : 17; /*Need add description*/ - uint32_t reserved17 : 15; /*Reserved*/ - }; - uint32_t val; - } cali; - uint32_t reserved_64; - uint32_t reserved_68; - uint32_t reserved_6c; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t reserved_fc; - uint32_t reserved_100; - uint32_t reserved_104; - uint32_t reserved_108; - uint32_t reserved_10c; - uint32_t reserved_110; - uint32_t reserved_114; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t reserved_140; - uint32_t reserved_144; - uint32_t reserved_148; - uint32_t reserved_14c; - uint32_t reserved_150; - uint32_t reserved_154; - uint32_t reserved_158; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; - uint32_t reserved_18c; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; - uint32_t reserved_1cc; - uint32_t reserved_1d0; - uint32_t reserved_1d4; - uint32_t reserved_1d8; - uint32_t reserved_1dc; - uint32_t reserved_1e0; - uint32_t reserved_1e4; - uint32_t reserved_1e8; - uint32_t reserved_1ec; - uint32_t reserved_1f0; - uint32_t reserved_1f4; - uint32_t reserved_1f8; - uint32_t reserved_1fc; - uint32_t reserved_200; - uint32_t reserved_204; - uint32_t reserved_208; - uint32_t reserved_20c; - uint32_t reserved_210; - uint32_t reserved_214; - uint32_t reserved_218; - uint32_t reserved_21c; - uint32_t reserved_220; - uint32_t reserved_224; - uint32_t reserved_228; - uint32_t reserved_22c; - uint32_t reserved_230; - uint32_t reserved_234; - uint32_t reserved_238; - uint32_t reserved_23c; - uint32_t reserved_240; - uint32_t reserved_244; - uint32_t reserved_248; - uint32_t reserved_24c; - uint32_t reserved_250; - uint32_t reserved_254; - uint32_t reserved_258; - uint32_t reserved_25c; - uint32_t reserved_260; - uint32_t reserved_264; - uint32_t reserved_268; - uint32_t reserved_26c; - uint32_t reserved_270; - uint32_t reserved_274; - uint32_t reserved_278; - uint32_t reserved_27c; - uint32_t reserved_280; - uint32_t reserved_284; - uint32_t reserved_288; - uint32_t reserved_28c; - uint32_t reserved_290; - uint32_t reserved_294; - uint32_t reserved_298; - uint32_t reserved_29c; - uint32_t reserved_2a0; - uint32_t reserved_2a4; - uint32_t reserved_2a8; - uint32_t reserved_2ac; - uint32_t reserved_2b0; - uint32_t reserved_2b4; - uint32_t reserved_2b8; - uint32_t reserved_2bc; - uint32_t reserved_2c0; - uint32_t reserved_2c4; - uint32_t reserved_2c8; - uint32_t reserved_2cc; - uint32_t reserved_2d0; - uint32_t reserved_2d4; - uint32_t reserved_2d8; - uint32_t reserved_2dc; - uint32_t reserved_2e0; - uint32_t reserved_2e4; - uint32_t reserved_2e8; - uint32_t reserved_2ec; - uint32_t reserved_2f0; - uint32_t reserved_2f4; - uint32_t reserved_2f8; - uint32_t reserved_2fc; - uint32_t reserved_300; - uint32_t reserved_304; - uint32_t reserved_308; - uint32_t reserved_30c; - uint32_t reserved_310; - uint32_t reserved_314; - uint32_t reserved_318; - uint32_t reserved_31c; - uint32_t reserved_320; - uint32_t reserved_324; - uint32_t reserved_328; - uint32_t reserved_32c; - uint32_t reserved_330; - uint32_t reserved_334; - uint32_t reserved_338; - uint32_t reserved_33c; - uint32_t reserved_340; - uint32_t reserved_344; - uint32_t reserved_348; - uint32_t reserved_34c; - uint32_t reserved_350; - uint32_t reserved_354; - uint32_t reserved_358; - uint32_t reserved_35c; - uint32_t reserved_360; - uint32_t reserved_364; - uint32_t reserved_368; - uint32_t reserved_36c; - uint32_t reserved_370; - uint32_t reserved_374; - uint32_t reserved_378; - uint32_t reserved_37c; - uint32_t reserved_380; - uint32_t reserved_384; - uint32_t reserved_388; - uint32_t reserved_38c; - uint32_t reserved_390; - uint32_t reserved_394; - uint32_t reserved_398; - uint32_t reserved_39c; - uint32_t reserved_3a0; - uint32_t reserved_3a4; - uint32_t reserved_3a8; - uint32_t reserved_3ac; - uint32_t reserved_3b0; - uint32_t reserved_3b4; - uint32_t reserved_3b8; - uint32_t reserved_3bc; - uint32_t reserved_3c0; - uint32_t reserved_3c4; - uint32_t reserved_3c8; - uint32_t reserved_3cc; - uint32_t reserved_3d0; - uint32_t reserved_3d4; - uint32_t reserved_3d8; - uint32_t reserved_3dc; - uint32_t reserved_3e0; - uint32_t reserved_3e4; - uint32_t reserved_3e8; - uint32_t reserved_3ec; - uint32_t reserved_3f0; - uint32_t reserved_3f4; - uint32_t reserved_3f8; - uint32_t apb_ctrl_date; -} apb_saradc_dev_t; -extern apb_saradc_dev_t APB_SARADC; +/** Group: Configuration Registers */ +/** Type of saradc_ctrl register + * register description + */ +typedef union { + struct { + /** saradc_saradc_start_force : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t saradc_saradc_start_force:1; + /** saradc_saradc_start : R/W; bitpos: [1]; default: 0; + * Need add description + */ + uint32_t saradc_saradc_start:1; + uint32_t reserved_2:4; + /** saradc_saradc_sar_clk_gated : R/W; bitpos: [6]; default: 1; + * Need add description + */ + uint32_t saradc_saradc_sar_clk_gated:1; + /** saradc_saradc_sar_clk_div : R/W; bitpos: [14:7]; default: 4; + * SAR clock divider + */ + uint32_t saradc_saradc_sar_clk_div:8; + /** saradc_saradc_sar_patt_len : R/W; bitpos: [17:15]; default: 7; + * 0 ~ 15 means length 1 ~ 16 + */ + uint32_t saradc_saradc_sar_patt_len:3; + uint32_t reserved_18:5; + /** saradc_saradc_sar_patt_p_clear : R/W; bitpos: [23]; default: 0; + * clear the pointer of pattern table for DIG ADC1 CTRL + */ + uint32_t saradc_saradc_sar_patt_p_clear:1; + uint32_t reserved_24:3; + /** saradc_saradc_xpd_sar_force : R/W; bitpos: [28:27]; default: 0; + * force option to xpd sar blocks + */ + uint32_t saradc_saradc_xpd_sar_force:2; + uint32_t reserved_29:1; + /** saradc_saradc_wait_arb_cycle : R/W; bitpos: [31:30]; default: 1; + * wait arbit signal stable after sar_done + */ + uint32_t saradc_saradc_wait_arb_cycle:2; + }; + uint32_t val; +} apb_saradc_ctrl_reg_t; + +/** Type of saradc_ctrl2 register + * register description + */ +typedef union { + struct { + /** saradc_saradc_meas_num_limit : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t saradc_saradc_meas_num_limit:1; + /** saradc_saradc_max_meas_num : R/W; bitpos: [8:1]; default: 255; + * max conversion number + */ + uint32_t saradc_saradc_max_meas_num:8; + /** saradc_saradc_sar1_inv : R/W; bitpos: [9]; default: 0; + * 1: data to DIG ADC1 CTRL is inverted, otherwise not + */ + uint32_t saradc_saradc_sar1_inv:1; + /** saradc_saradc_sar2_inv : R/W; bitpos: [10]; default: 0; + * 1: data to DIG ADC2 CTRL is inverted, otherwise not + */ + uint32_t saradc_saradc_sar2_inv:1; + uint32_t reserved_11:1; + /** saradc_saradc_timer_target : R/W; bitpos: [23:12]; default: 10; + * to set saradc timer target + */ + uint32_t saradc_saradc_timer_target:12; + /** saradc_saradc_timer_en : R/W; bitpos: [24]; default: 0; + * to enable saradc timer trigger + */ + uint32_t saradc_saradc_timer_en:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} apb_saradc_ctrl2_reg_t; + +/** Type of saradc_filter_ctrl1 register + * register description + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** saradc_filter_factor1 : R/W; bitpos: [28:26]; default: 0; + * Need add description + */ + uint32_t saradc_filter_factor1:3; + /** saradc_filter_factor0 : R/W; bitpos: [31:29]; default: 0; + * Need add description + */ + uint32_t saradc_filter_factor0:3; + }; + uint32_t val; +} apb_saradc_filter_ctrl1_reg_t; + +/** Type of saradc_fsm_wait register + * register description + */ +typedef union { + struct { + /** saradc_saradc_xpd_wait : R/W; bitpos: [7:0]; default: 8; + * Need add description + */ + uint32_t saradc_saradc_xpd_wait:8; + /** saradc_saradc_rstb_wait : R/W; bitpos: [15:8]; default: 8; + * Need add description + */ + uint32_t saradc_saradc_rstb_wait:8; + /** saradc_saradc_standby_wait : R/W; bitpos: [23:16]; default: 255; + * Need add description + */ + uint32_t saradc_saradc_standby_wait:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} apb_saradc_fsm_wait_reg_t; + +/** Type of saradc_sar1_status register + * register description + */ +typedef union { + struct { + /** saradc_saradc_sar1_status : RO; bitpos: [31:0]; default: 0; + * Need add description + */ + uint32_t saradc_saradc_sar1_status:32; + }; + uint32_t val; +} apb_saradc_sar1_status_reg_t; + +/** Type of saradc_sar2_status register + * register description + */ +typedef union { + struct { + /** saradc_saradc_sar2_status : RO; bitpos: [31:0]; default: 0; + * Need add description + */ + uint32_t saradc_saradc_sar2_status:32; + }; + uint32_t val; +} apb_saradc_sar2_status_reg_t; + +/** Type of saradc_sar_patt_tab1 register + * register description + */ +typedef union { + struct { + /** saradc_saradc_sar_patt_tab1 : R/W; bitpos: [23:0]; default: 16777215; + * item 0 ~ 3 for pattern table 1 (each item one byte) + */ + uint32_t saradc_saradc_sar_patt_tab1:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} apb_saradc_sar_patt_tab1_reg_t; + +/** Type of saradc_sar_patt_tab2 register + * register description + */ +typedef union { + struct { + /** saradc_saradc_sar_patt_tab2 : R/W; bitpos: [23:0]; default: 16777215; + * Item 4 ~ 7 for pattern table 1 (each item one byte) + */ + uint32_t saradc_saradc_sar_patt_tab2:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} apb_saradc_sar_patt_tab2_reg_t; + +/** Type of saradc_onetime_sample register + * register description + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** saradc_saradc_onetime_atten : R/W; bitpos: [24:23]; default: 0; + * Need add description + */ + uint32_t saradc_saradc_onetime_atten:2; + /** saradc_saradc_onetime_channel : R/W; bitpos: [28:25]; default: 13; + * Need add description + */ + uint32_t saradc_saradc_onetime_channel:4; + /** saradc_saradc_onetime_start : R/W; bitpos: [29]; default: 0; + * Need add description + */ + uint32_t saradc_saradc_onetime_start:1; + /** saradc_saradc2_onetime_sample : R/W; bitpos: [30]; default: 0; + * Need add description + */ + uint32_t saradc_saradc2_onetime_sample:1; + /** saradc_saradc1_onetime_sample : R/W; bitpos: [31]; default: 0; + * Need add description + */ + uint32_t saradc_saradc1_onetime_sample:1; + }; + uint32_t val; +} apb_saradc_onetime_sample_reg_t; + +/** Type of saradc_apb_adc_arb_ctrl register + * register description + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** saradc_adc_arb_apb_force : R/W; bitpos: [2]; default: 0; + * adc2 arbiter force to enableapb controller + */ + uint32_t saradc_adc_arb_apb_force:1; + /** saradc_adc_arb_rtc_force : R/W; bitpos: [3]; default: 0; + * adc2 arbiter force to enable rtc controller + */ + uint32_t saradc_adc_arb_rtc_force:1; + /** saradc_adc_arb_wifi_force : R/W; bitpos: [4]; default: 0; + * adc2 arbiter force to enable wifi controller + */ + uint32_t saradc_adc_arb_wifi_force:1; + /** saradc_adc_arb_grant_force : R/W; bitpos: [5]; default: 0; + * adc2 arbiter force grant + */ + uint32_t saradc_adc_arb_grant_force:1; + /** saradc_adc_arb_apb_priority : R/W; bitpos: [7:6]; default: 0; + * Set adc2 arbiterapb priority + */ + uint32_t saradc_adc_arb_apb_priority:2; + /** saradc_adc_arb_rtc_priority : R/W; bitpos: [9:8]; default: 1; + * Set adc2 arbiter rtc priority + */ + uint32_t saradc_adc_arb_rtc_priority:2; + /** saradc_adc_arb_wifi_priority : R/W; bitpos: [11:10]; default: 2; + * Set adc2 arbiter wifi priority + */ + uint32_t saradc_adc_arb_wifi_priority:2; + /** saradc_adc_arb_fix_priority : R/W; bitpos: [12]; default: 0; + * adc2 arbiter uses fixed priority + */ + uint32_t saradc_adc_arb_fix_priority:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} apb_saradc_apb_adc_arb_ctrl_reg_t; + +/** Type of saradc_filter_ctrl0 register + * register description + */ +typedef union { + struct { + uint32_t reserved_0:18; + /** saradc_filter_channel1 : R/W; bitpos: [21:18]; default: 13; + * Need add description + */ + uint32_t saradc_filter_channel1:4; + /** saradc_filter_channel0 : R/W; bitpos: [25:22]; default: 13; + * apb_adc1_filter_factor + */ + uint32_t saradc_filter_channel0:4; + uint32_t reserved_26:5; + /** saradc_filter_reset : R/W; bitpos: [31]; default: 0; + * enable apb_adc1_filter + */ + uint32_t saradc_filter_reset:1; + }; + uint32_t val; +} apb_saradc_filter_ctrl0_reg_t; + +/** Type of saradc1_data_status register + * register description + */ +typedef union { + struct { + /** saradc1_data : RO; bitpos: [16:0]; default: 0; + * Need add description + */ + uint32_t saradc1_data:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_saradc1_data_status_reg_t; + +/** Type of saradc2_data_status register + * register description + */ +typedef union { + struct { + /** saradc2_data : RO; bitpos: [16:0]; default: 0; + * Need add description + */ + uint32_t saradc2_data:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_saradc2_data_status_reg_t; + +/** Type of saradc_thres0_ctrl register + * register description + */ +typedef union { + struct { + /** saradc_thres0_channel : R/W; bitpos: [3:0]; default: 13; + * Need add description + */ + uint32_t saradc_thres0_channel:4; + uint32_t reserved_4:1; + /** saradc_thres0_high : R/W; bitpos: [17:5]; default: 8191; + * saradc1's thres0 monitor thres + */ + uint32_t saradc_thres0_high:13; + /** saradc_thres0_low : R/W; bitpos: [30:18]; default: 0; + * saradc1's thres0 monitor thres + */ + uint32_t saradc_thres0_low:13; + uint32_t reserved_31:1; + }; + uint32_t val; +} apb_saradc_thres0_ctrl_reg_t; + +/** Type of saradc_thres1_ctrl register + * register description + */ +typedef union { + struct { + /** saradc_thres1_channel : R/W; bitpos: [3:0]; default: 13; + * Need add description + */ + uint32_t saradc_thres1_channel:4; + uint32_t reserved_4:1; + /** saradc_thres1_high : R/W; bitpos: [17:5]; default: 8191; + * saradc1's thres0 monitor thres + */ + uint32_t saradc_thres1_high:13; + /** saradc_thres1_low : R/W; bitpos: [30:18]; default: 0; + * saradc1's thres0 monitor thres + */ + uint32_t saradc_thres1_low:13; + uint32_t reserved_31:1; + }; + uint32_t val; +} apb_saradc_thres1_ctrl_reg_t; + +/** Type of saradc_thres_ctrl register + * register description + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** saradc_thres_all_en : R/W; bitpos: [27]; default: 0; + * Need add description + */ + uint32_t saradc_thres_all_en:1; + /** saradc_thres3_en : R/W; bitpos: [28]; default: 0; + * Need add description + */ + uint32_t saradc_thres3_en:1; + /** saradc_thres2_en : R/W; bitpos: [29]; default: 0; + * Need add description + */ + uint32_t saradc_thres2_en:1; + /** saradc_thres1_en : R/W; bitpos: [30]; default: 0; + * Need add description + */ + uint32_t saradc_thres1_en:1; + /** saradc_thres0_en : R/W; bitpos: [31]; default: 0; + * Need add description + */ + uint32_t saradc_thres0_en:1; + }; + uint32_t val; +} apb_saradc_thres_ctrl_reg_t; + +/** Type of saradc_int_ena register + * register description + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** saradc_thres1_low_int_ena : R/W; bitpos: [26]; default: 0; + * Need add description + */ + uint32_t saradc_thres1_low_int_ena:1; + /** saradc_thres0_low_int_ena : R/W; bitpos: [27]; default: 0; + * Need add description + */ + uint32_t saradc_thres0_low_int_ena:1; + /** saradc_thres1_high_int_ena : R/W; bitpos: [28]; default: 0; + * Need add description + */ + uint32_t saradc_thres1_high_int_ena:1; + /** saradc_thres0_high_int_ena : R/W; bitpos: [29]; default: 0; + * Need add description + */ + uint32_t saradc_thres0_high_int_ena:1; + /** saradc2_done_int_ena : R/W; bitpos: [30]; default: 0; + * Need add description + */ + uint32_t saradc2_done_int_ena:1; + /** saradc1_done_int_ena : R/W; bitpos: [31]; default: 0; + * Need add description + */ + uint32_t saradc1_done_int_ena:1; + }; + uint32_t val; +} apb_saradc_int_ena_reg_t; + +/** Type of saradc_int_raw register + * register description + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** saradc_thres1_low_int_raw : RO; bitpos: [26]; default: 0; + * Need add description + */ + uint32_t saradc_thres1_low_int_raw:1; + /** saradc_thres0_low_int_raw : RO; bitpos: [27]; default: 0; + * Need add description + */ + uint32_t saradc_thres0_low_int_raw:1; + /** saradc_thres1_high_int_raw : RO; bitpos: [28]; default: 0; + * Need add description + */ + uint32_t saradc_thres1_high_int_raw:1; + /** saradc_thres0_high_int_raw : RO; bitpos: [29]; default: 0; + * Need add description + */ + uint32_t saradc_thres0_high_int_raw:1; + /** saradc2_done_int_raw : RO; bitpos: [30]; default: 0; + * Need add description + */ + uint32_t saradc2_done_int_raw:1; + /** saradc1_done_int_raw : RO; bitpos: [31]; default: 0; + * Need add description + */ + uint32_t saradc1_done_int_raw:1; + }; + uint32_t val; +} apb_saradc_int_raw_reg_t; + +/** Type of saradc_int_st register + * register description + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** saradc_thres1_low_int_st : RO; bitpos: [26]; default: 0; + * Need add description + */ + uint32_t saradc_thres1_low_int_st:1; + /** saradc_thres0_low_int_st : RO; bitpos: [27]; default: 0; + * Need add description + */ + uint32_t saradc_thres0_low_int_st:1; + /** saradc_thres1_high_int_st : RO; bitpos: [28]; default: 0; + * Need add description + */ + uint32_t saradc_thres1_high_int_st:1; + /** saradc_thres0_high_int_st : RO; bitpos: [29]; default: 0; + * Need add description + */ + uint32_t saradc_thres0_high_int_st:1; + /** saradc2_done_int_st : RO; bitpos: [30]; default: 0; + * Need add description + */ + uint32_t saradc2_done_int_st:1; + /** saradc1_done_int_st : RO; bitpos: [31]; default: 0; + * Need add description + */ + uint32_t saradc1_done_int_st:1; + }; + uint32_t val; +} apb_saradc_int_st_reg_t; + +/** Type of saradc_int_clr register + * register description + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** saradc_thres1_low_int_clr : WO; bitpos: [26]; default: 0; + * Need add description + */ + uint32_t saradc_thres1_low_int_clr:1; + /** saradc_thres0_low_int_clr : WO; bitpos: [27]; default: 0; + * Need add description + */ + uint32_t saradc_thres0_low_int_clr:1; + /** saradc_thres1_high_int_clr : WO; bitpos: [28]; default: 0; + * Need add description + */ + uint32_t saradc_thres1_high_int_clr:1; + /** saradc_thres0_high_int_clr : WO; bitpos: [29]; default: 0; + * Need add description + */ + uint32_t saradc_thres0_high_int_clr:1; + /** saradc2_done_int_clr : WO; bitpos: [30]; default: 0; + * Need add description + */ + uint32_t saradc2_done_int_clr:1; + /** saradc1_done_int_clr : WO; bitpos: [31]; default: 0; + * Need add description + */ + uint32_t saradc1_done_int_clr:1; + }; + uint32_t val; +} apb_saradc_int_clr_reg_t; + +/** Type of saradc_dma_conf register + * register description + */ +typedef union { + struct { + /** saradc_apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255; + * the dma_in_suc_eof gen when sample cnt = spi_eof_num + */ + uint32_t saradc_apb_adc_eof_num:16; + uint32_t reserved_16:14; + /** saradc_apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0; + * reset_apb_adc_state + */ + uint32_t saradc_apb_adc_reset_fsm:1; + /** saradc_apb_adc_trans : R/W; bitpos: [31]; default: 0; + * enable apb_adc use spi_dma + */ + uint32_t saradc_apb_adc_trans:1; + }; + uint32_t val; +} apb_saradc_dma_conf_reg_t; + +/** Type of saradc_apb_adc_clkm_conf register + * register description + */ +typedef union { + struct { + /** saradc_reg_clkm_div_num : R/W; bitpos: [7:0]; default: 4; + * Integral I2S clock divider value + */ + uint32_t saradc_reg_clkm_div_num:8; + /** saradc_reg_clkm_div_b : R/W; bitpos: [13:8]; default: 0; + * Fractional clock divider numerator value + */ + uint32_t saradc_reg_clkm_div_b:6; + /** saradc_reg_clkm_div_a : R/W; bitpos: [19:14]; default: 0; + * Fractional clock divider denominator value + */ + uint32_t saradc_reg_clkm_div_a:6; + /** saradc_clk_en : R/W; bitpos: [20]; default: 0; + * Need add description + */ + uint32_t saradc_clk_en:1; + /** saradc_reg_clk_sel : R/W; bitpos: [22:21]; default: 0; + * Set this bit to enable clk_apll + */ + uint32_t saradc_reg_clk_sel:2; + uint32_t reserved_23:9; + }; + uint32_t val; +} apb_saradc_apb_adc_clkm_conf_reg_t; + +/** Type of saradc_apb_tsens_ctrl register + * register description + */ +typedef union { + struct { + /** saradc_reg_tsens_out : RO; bitpos: [7:0]; default: 0; + * Need add description + */ + uint32_t saradc_reg_tsens_out:8; + uint32_t reserved_8:5; + /** saradc_reg_tsens_in_inv : R/W; bitpos: [13]; default: 0; + * Need add description + */ + uint32_t saradc_reg_tsens_in_inv:1; + /** saradc_reg_tsens_clk_div : R/W; bitpos: [21:14]; default: 6; + * Need add description + */ + uint32_t saradc_reg_tsens_clk_div:8; + /** saradc_reg_tsens_pu : R/W; bitpos: [22]; default: 0; + * Need add description + */ + uint32_t saradc_reg_tsens_pu:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} apb_saradc_apb_tsens_ctrl_reg_t; + +/** Type of saradc_apb_tsens_ctrl2 register + * register description + */ +typedef union { + struct { + /** saradc_reg_tsens_xpd_wait : R/W; bitpos: [11:0]; default: 2; + * Need add description + */ + uint32_t saradc_reg_tsens_xpd_wait:12; + /** saradc_reg_tsens_xpd_force : R/W; bitpos: [13:12]; default: 0; + * Need add description + */ + uint32_t saradc_reg_tsens_xpd_force:2; + /** saradc_reg_tsens_clk_inv : R/W; bitpos: [14]; default: 1; + * Need add description + */ + uint32_t saradc_reg_tsens_clk_inv:1; + /** saradc_tsens_clk_sel : R/W; bitpos: [15]; default: 0; + * Need add description + */ + uint32_t saradc_tsens_clk_sel:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} apb_saradc_apb_tsens_ctrl2_reg_t; + +/** Type of saradc_cali register + * register description + */ +typedef union { + struct { + /** saradc_cali_cfg : R/W; bitpos: [16:0]; default: 32768; + * Need add description + */ + uint32_t saradc_cali_cfg:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_saradc_cali_reg_t; + +/** Type of saradc_apb_ctrl_date register + * register description + */ +typedef union { + struct { + /** saradc_date : R/W; bitpos: [31:0]; default: 34632208; + * Need add description + */ + uint32_t saradc_date:32; + }; + uint32_t val; +} apb_saradc_apb_ctrl_date_reg_t; + + +typedef struct { + volatile apb_saradc_ctrl_reg_t saradc_ctrl; + volatile apb_saradc_ctrl2_reg_t saradc_ctrl2; + volatile apb_saradc_filter_ctrl1_reg_t saradc_filter_ctrl1; + volatile apb_saradc_fsm_wait_reg_t saradc_fsm_wait; + volatile apb_saradc_sar1_status_reg_t saradc_sar1_status; + volatile apb_saradc_sar2_status_reg_t saradc_sar2_status; + volatile apb_saradc_sar_patt_tab1_reg_t saradc_sar_patt_tab1; + volatile apb_saradc_sar_patt_tab2_reg_t saradc_sar_patt_tab2; + volatile apb_saradc_onetime_sample_reg_t saradc_onetime_sample; + volatile apb_saradc_apb_adc_arb_ctrl_reg_t saradc_apb_adc_arb_ctrl; + volatile apb_saradc_filter_ctrl0_reg_t saradc_filter_ctrl0; + volatile apb_saradc1_data_status_reg_t saradc1_data_status; + volatile apb_saradc2_data_status_reg_t saradc2_data_status; + volatile apb_saradc_thres0_ctrl_reg_t saradc_thres0_ctrl; + volatile apb_saradc_thres1_ctrl_reg_t saradc_thres1_ctrl; + volatile apb_saradc_thres_ctrl_reg_t saradc_thres_ctrl; + volatile apb_saradc_int_ena_reg_t saradc_int_ena; + volatile apb_saradc_int_raw_reg_t saradc_int_raw; + volatile apb_saradc_int_st_reg_t saradc_int_st; + volatile apb_saradc_int_clr_reg_t saradc_int_clr; + volatile apb_saradc_dma_conf_reg_t saradc_dma_conf; + volatile apb_saradc_apb_adc_clkm_conf_reg_t saradc_apb_adc_clkm_conf; + volatile apb_saradc_apb_tsens_ctrl_reg_t saradc_apb_tsens_ctrl; + volatile apb_saradc_apb_tsens_ctrl2_reg_t saradc_apb_tsens_ctrl2; + volatile apb_saradc_cali_reg_t saradc_cali; + uint32_t reserved_064[230]; + volatile apb_saradc_apb_ctrl_date_reg_t saradc_apb_ctrl_date; +} apb_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(apb_dev_t) == 0x400, "Invalid size of apb_dev_t structure"); +#endif + #ifdef __cplusplus } #endif - - - -#endif /*_SOC_APB_SARADC_STRUCT_H_ */ diff --git a/components/soc/esp8684/include/soc/efuse_reg.h b/components/soc/esp8684/include/soc/efuse_reg.h index d94677ccdb..7b697079ef 100644 --- a/components/soc/esp8684/include/soc/efuse_reg.h +++ b/components/soc/esp8684/include/soc/efuse_reg.h @@ -1,813 +1,1065 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_EFUSE_REG_H_ -#define _SOC_EFUSE_REG_H_ - +#pragma once +#include +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) -/* EFUSE_PGM_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 0th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_0 0xFFFFFFFF -#define EFUSE_PGM_DATA_0_M ((EFUSE_PGM_DATA_0_V)<<(EFUSE_PGM_DATA_0_S)) -#define EFUSE_PGM_DATA_0_V 0xFFFFFFFF +/** EFUSE_PGM_DATA0_REG register + * Register 0 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_0_S 0 -#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) -/* EFUSE_PGM_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 1st 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_1 0xFFFFFFFF -#define EFUSE_PGM_DATA_1_M ((EFUSE_PGM_DATA_1_V)<<(EFUSE_PGM_DATA_1_S)) -#define EFUSE_PGM_DATA_1_V 0xFFFFFFFF +/** EFUSE_PGM_DATA1_REG register + * Register 1 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) +/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) +#define EFUSE_PGM_DATA_1_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_1_S 0 -#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) -/* EFUSE_PGM_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 2nd 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_2 0xFFFFFFFF -#define EFUSE_PGM_DATA_2_M ((EFUSE_PGM_DATA_2_V)<<(EFUSE_PGM_DATA_2_S)) -#define EFUSE_PGM_DATA_2_V 0xFFFFFFFF +/** EFUSE_PGM_DATA2_REG register + * Register 2 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) +/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) +#define EFUSE_PGM_DATA_2_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_2_S 0 -#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xC) -/* EFUSE_PGM_DATA_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 3rd 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_3 0xFFFFFFFF -#define EFUSE_PGM_DATA_3_M ((EFUSE_PGM_DATA_3_V)<<(EFUSE_PGM_DATA_3_S)) -#define EFUSE_PGM_DATA_3_V 0xFFFFFFFF +/** EFUSE_PGM_DATA3_REG register + * Register 3 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) +/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; + * The content of the 3rd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_3 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) +#define EFUSE_PGM_DATA_3_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_3_S 0 -#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) -/* EFUSE_PGM_DATA_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 4th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_4 0xFFFFFFFF -#define EFUSE_PGM_DATA_4_M ((EFUSE_PGM_DATA_4_V)<<(EFUSE_PGM_DATA_4_S)) -#define EFUSE_PGM_DATA_4_V 0xFFFFFFFF +/** EFUSE_PGM_DATA4_REG register + * Register 4 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) +/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; + * The content of the 4th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_4 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) +#define EFUSE_PGM_DATA_4_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_4_S 0 -#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) -/* EFUSE_PGM_DATA_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 5th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_5 0xFFFFFFFF -#define EFUSE_PGM_DATA_5_M ((EFUSE_PGM_DATA_5_V)<<(EFUSE_PGM_DATA_5_S)) -#define EFUSE_PGM_DATA_5_V 0xFFFFFFFF +/** EFUSE_PGM_DATA5_REG register + * Register 5 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) +/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; + * The content of the 5th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_5 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) +#define EFUSE_PGM_DATA_5_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_5_S 0 -#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) -/* EFUSE_PGM_DATA_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 6th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_6 0xFFFFFFFF -#define EFUSE_PGM_DATA_6_M ((EFUSE_PGM_DATA_6_V)<<(EFUSE_PGM_DATA_6_S)) -#define EFUSE_PGM_DATA_6_V 0xFFFFFFFF +/** EFUSE_PGM_DATA6_REG register + * Register 6 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) +/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; + * The content of the 6th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_6 0xFFFFFFFFU +#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) +#define EFUSE_PGM_DATA_6_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_6_S 0 -#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1C) -/* EFUSE_PGM_DATA_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 7th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_7 0xFFFFFFFF -#define EFUSE_PGM_DATA_7_M ((EFUSE_PGM_DATA_7_V)<<(EFUSE_PGM_DATA_7_S)) -#define EFUSE_PGM_DATA_7_V 0xFFFFFFFF +/** EFUSE_PGM_DATA7_REG register + * Register 7 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) +/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; + * The content of the 7th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_7 0xFFFFFFFFU +#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) +#define EFUSE_PGM_DATA_7_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_7_S 0 -#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) -/* EFUSE_PGM_RS_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 0th 32-bit RS code to be programmed..*/ -#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_0_M ((EFUSE_PGM_RS_DATA_0_V)<<(EFUSE_PGM_RS_DATA_0_S)) -#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE0_REG register + * Register 0 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) +/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_0_S 0 -#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) -/* EFUSE_PGM_RS_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 1st 32-bit RS code to be programmed..*/ -#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_1_M ((EFUSE_PGM_RS_DATA_1_V)<<(EFUSE_PGM_RS_DATA_1_S)) -#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE1_REG register + * Register 1 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) +/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) +#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_1_S 0 -#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) -/* EFUSE_PGM_RS_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 2nd 32-bit RS code to be programmed..*/ -#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_2_M ((EFUSE_PGM_RS_DATA_2_V)<<(EFUSE_PGM_RS_DATA_2_S)) -#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE2_REG register + * Register 2 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) +/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) +#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_2_S 0 -#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2C) -/* EFUSE_WR_DIS : RO ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: Disable programming of individual eFuses..*/ -#define EFUSE_WR_DIS 0x000000FF -#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) -#define EFUSE_WR_DIS_V 0xFF +/** EFUSE_RD_WR_DIS_REG register + * BLOCK0 data register 0. + */ +#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) +/** EFUSE_WR_DIS : RO; bitpos: [7:0]; default: 0; + * Disable programming of individual eFuses. + */ +#define EFUSE_WR_DIS 0x000000FFU +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0x000000FFU #define EFUSE_WR_DIS_S 0 -#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) -/* EFUSE_RPT4_RESERVED : RO ;bitpos:[31:22] ;default: 10'h0 ; */ -/*description: Reserved (used for four backups method)..*/ -#define EFUSE_RPT4_RESERVED 0x000003FF -#define EFUSE_RPT4_RESERVED_M ((EFUSE_RPT4_RESERVED_V)<<(EFUSE_RPT4_RESERVED_S)) -#define EFUSE_RPT4_RESERVED_V 0x3FF -#define EFUSE_RPT4_RESERVED_S 22 -/* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The bit be set to enable secure boot..*/ -#define EFUSE_SECURE_BOOT_EN (BIT(21)) -#define EFUSE_SECURE_BOOT_EN_M (BIT(21)) -#define EFUSE_SECURE_BOOT_EN_V 0x1 -#define EFUSE_SECURE_BOOT_EN_S 21 -/* EFUSE_FLASH_TPUW : RO ;bitpos:[20:17] ;default: 4'h0 ; */ -/*description: Configures flash waiting time after power-up, in unit of ms. If the value is les -s than 15, the waiting time is the configurable value. Otherwise, the waiting t -ime is twice the configurable value..*/ -#define EFUSE_FLASH_TPUW 0x0000000F -#define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) -#define EFUSE_FLASH_TPUW_V 0xF -#define EFUSE_FLASH_TPUW_S 17 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to enable secure UART download mode..*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(16)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(16)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 16 -/* EFUSE_DIS_DIRECT_BOOT : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This bit set means disable direct_boot mode..*/ -#define EFUSE_DIS_DIRECT_BOOT (BIT(15)) -#define EFUSE_DIS_DIRECT_BOOT_M (BIT(15)) -#define EFUSE_DIS_DIRECT_BOOT_V 0x1 -#define EFUSE_DIS_DIRECT_BOOT_S 15 -/* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7)..*/ -#define EFUSE_DIS_DOWNLOAD_MODE (BIT(14)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(14)) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MODE_S 14 -/* EFUSE_FORCE_SEND_RESUME : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to force ROM code to send a resume command during SPI boot..*/ -#define EFUSE_FORCE_SEND_RESUME (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_M (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_S 13 -/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: Set this bit to disable usb printing..*/ -#define EFUSE_UART_PRINT_CONTROL 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) -#define EFUSE_UART_PRINT_CONTROL_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_S 11 -/* EFUSE_XTS_KEY_LENGTH_256 : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwi -se, XTS_AES use 128-bit eFuse data in BLOCK3..*/ -#define EFUSE_XTS_KEY_LENGTH_256 (BIT(10)) -#define EFUSE_XTS_KEY_LENGTH_256_M (BIT(10)) -#define EFUSE_XTS_KEY_LENGTH_256_V 0x1 -#define EFUSE_XTS_KEY_LENGTH_256_S 10 -/* EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT : RO ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. e -ven number of 1: disable..*/ -#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT 0x00000007 -#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_M ((EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_V)<<(EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_S)) -#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_V 0x7 -#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_S 7 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The bit be set to disable manual encryption..*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(6)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(6)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 6 -/* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit be set to disable icache in download mode..*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(5)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(5)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_S 5 -/* EFUSE_DIS_PAD_JTAG : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to disable pad jtag..*/ -#define EFUSE_DIS_PAD_JTAG (BIT(4)) -#define EFUSE_DIS_PAD_JTAG_M (BIT(4)) -#define EFUSE_DIS_PAD_JTAG_V 0x1 -#define EFUSE_DIS_PAD_JTAG_S 4 -/* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1 -: 80000. 2: 160000. 3:320000..*/ -#define EFUSE_WDT_DELAY_SEL 0x00000003 -#define EFUSE_WDT_DELAY_SEL_M ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S)) -#define EFUSE_WDT_DELAY_SEL_V 0x3 +/** EFUSE_RD_REPEAT_DATA0_REG register + * BLOCK0 data register 1. + */ +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) +/** EFUSE_RD_DIS : RO; bitpos: [1:0]; default: 0; + * The bit be set to disable software read high/low 128-bit of BLK3. + */ +#define EFUSE_RD_DIS 0x00000003U +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x00000003U +#define EFUSE_RD_DIS_S 0 +/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [3:2]; default: 0; + * Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: + * 80000. 2: 160000. 3:320000. + */ +#define EFUSE_WDT_DELAY_SEL 0x00000003U +#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) +#define EFUSE_WDT_DELAY_SEL_V 0x00000003U #define EFUSE_WDT_DELAY_SEL_S 2 -/* EFUSE_KEY0_RD_DIS : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: The bit be set to disable software read high/low 128-bit of BLK3..*/ -#define EFUSE_KEY0_RD_DIS 0x00000003 -#define EFUSE_KEY0_RD_DIS_M ((EFUSE_KEY0_RD_DIS_V)<<(EFUSE_KEY0_RD_DIS_S)) -#define EFUSE_KEY0_RD_DIS_V 0x3 -#define EFUSE_KEY0_RD_DIS_S 0 +/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [4]; default: 0; + * Set this bit to disable pad jtag. + */ +#define EFUSE_DIS_PAD_JTAG (BIT(4)) +#define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) +#define EFUSE_DIS_PAD_JTAG_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_S 4 +/** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [5]; default: 0; + * The bit be set to disable icache in download mode. + */ +#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(5)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_M (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_ICACHE_S 5 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [6]; default: 0; + * The bit be set to disable manual encryption. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(6)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 6 +/** EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT : RO; bitpos: [9:7]; default: 0; + * These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even + * number of 1: disable. + */ +#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT 0x00000007U +#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_M (EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_V << EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_S) +#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_V 0x00000007U +#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_S 7 +/** EFUSE_XTS_KEY_LENGTH_256 : RO; bitpos: [10]; default: 0; + * The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise, + * XTS_AES use 128-bit eFuse data in BLOCK3. + */ +#define EFUSE_XTS_KEY_LENGTH_256 (BIT(10)) +#define EFUSE_XTS_KEY_LENGTH_256_M (EFUSE_XTS_KEY_LENGTH_256_V << EFUSE_XTS_KEY_LENGTH_256_S) +#define EFUSE_XTS_KEY_LENGTH_256_V 0x00000001U +#define EFUSE_XTS_KEY_LENGTH_256_S 10 +/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [12:11]; default: 0; + * Set this bit to disable usb printing. + */ +#define EFUSE_UART_PRINT_CONTROL 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) +#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_S 11 +/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0; + * Set this bit to force ROM code to send a resume command during SPI boot. + */ +#define EFUSE_FORCE_SEND_RESUME (BIT(13)) +#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) +#define EFUSE_FORCE_SEND_RESUME_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_S 13 +/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [14]; default: 0; + * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7). + */ +#define EFUSE_DIS_DOWNLOAD_MODE (BIT(14)) +#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MODE_S 14 +/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [15]; default: 0; + * This bit set means disable direct_boot mode. + */ +#define EFUSE_DIS_DIRECT_BOOT (BIT(15)) +#define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) +#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_S 15 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [16]; default: 0; + * Set this bit to enable secure UART download mode. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(16)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 16 +/** EFUSE_FLASH_TPUW : RO; bitpos: [20:17]; default: 0; + * Configures flash waiting time after power-up, in unit of ms. If the value is less + * than 15, the waiting time is the configurable value. Otherwise, the waiting time + * is twice the configurable value. + */ +#define EFUSE_FLASH_TPUW 0x0000000FU +#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) +#define EFUSE_FLASH_TPUW_V 0x0000000FU +#define EFUSE_FLASH_TPUW_S 17 +/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [21]; default: 0; + * The bit be set to enable secure boot. + */ +#define EFUSE_SECURE_BOOT_EN (BIT(21)) +#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) +#define EFUSE_SECURE_BOOT_EN_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_S 21 +/** EFUSE_RPT4_RESERVED : RO; bitpos: [31:22]; default: 0; + * Reserved (used for four backups method). + */ +#define EFUSE_RPT4_RESERVED 0x000003FFU +#define EFUSE_RPT4_RESERVED_M (EFUSE_RPT4_RESERVED_V << EFUSE_RPT4_RESERVED_S) +#define EFUSE_RPT4_RESERVED_V 0x000003FFU +#define EFUSE_RPT4_RESERVED_S 22 -#define EFUSE_RD_BLK1_DATA0_REG (DR_REG_EFUSE_BASE + 0x34) -/* EFUSE_SYSTEM_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the bits [0:31] of system data..*/ -#define EFUSE_SYSTEM_DATA0 0xFFFFFFFF -#define EFUSE_SYSTEM_DATA0_M ((EFUSE_SYSTEM_DATA0_V)<<(EFUSE_SYSTEM_DATA0_S)) -#define EFUSE_SYSTEM_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_BLK1_DATA0_REG register + * BLOCK1 data register 0. + */ +#define EFUSE_RD_BLK1_DATA0_REG (DR_REG_EFUSE_BASE + 0x34) +/** EFUSE_SYSTEM_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the bits [0:31] of system data. + */ +#define EFUSE_SYSTEM_DATA0 0xFFFFFFFFU +#define EFUSE_SYSTEM_DATA0_M (EFUSE_SYSTEM_DATA0_V << EFUSE_SYSTEM_DATA0_S) +#define EFUSE_SYSTEM_DATA0_V 0xFFFFFFFFU #define EFUSE_SYSTEM_DATA0_S 0 -#define EFUSE_RD_BLK1_DATA1_REG (DR_REG_EFUSE_BASE + 0x38) -/* EFUSE_SYSTEM_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the bits [32:63] of system data..*/ -#define EFUSE_SYSTEM_DATA1 0xFFFFFFFF -#define EFUSE_SYSTEM_DATA1_M ((EFUSE_SYSTEM_DATA1_V)<<(EFUSE_SYSTEM_DATA1_S)) -#define EFUSE_SYSTEM_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_BLK1_DATA1_REG register + * BLOCK1 data register 1. + */ +#define EFUSE_RD_BLK1_DATA1_REG (DR_REG_EFUSE_BASE + 0x38) +/** EFUSE_SYSTEM_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the bits [32:63] of system data. + */ +#define EFUSE_SYSTEM_DATA1 0xFFFFFFFFU +#define EFUSE_SYSTEM_DATA1_M (EFUSE_SYSTEM_DATA1_V << EFUSE_SYSTEM_DATA1_S) +#define EFUSE_SYSTEM_DATA1_V 0xFFFFFFFFU #define EFUSE_SYSTEM_DATA1_S 0 -#define EFUSE_RD_BLK1_DATA2_REG (DR_REG_EFUSE_BASE + 0x3C) -/* EFUSE_SYSTEM_DATA2 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Stores the bits [64:87] of system data..*/ -#define EFUSE_SYSTEM_DATA2 0x00FFFFFF -#define EFUSE_SYSTEM_DATA2_M ((EFUSE_SYSTEM_DATA2_V)<<(EFUSE_SYSTEM_DATA2_S)) -#define EFUSE_SYSTEM_DATA2_V 0xFFFFFF +/** EFUSE_RD_BLK1_DATA2_REG register + * BLOCK1 data register 2. + */ +#define EFUSE_RD_BLK1_DATA2_REG (DR_REG_EFUSE_BASE + 0x3c) +/** EFUSE_SYSTEM_DATA2 : RO; bitpos: [23:0]; default: 0; + * Stores the bits [64:87] of system data. + */ +#define EFUSE_SYSTEM_DATA2 0x00FFFFFFU +#define EFUSE_SYSTEM_DATA2_M (EFUSE_SYSTEM_DATA2_V << EFUSE_SYSTEM_DATA2_S) +#define EFUSE_SYSTEM_DATA2_V 0x00FFFFFFU #define EFUSE_SYSTEM_DATA2_S 0 -#define EFUSE_RD_BLK2_DATA0_REG (DR_REG_EFUSE_BASE + 0x40) -/* EFUSE_MAC_ID_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Store the bit [0:31] of MAC..*/ -#define EFUSE_MAC_ID_LOW 0xFFFFFFFF -#define EFUSE_MAC_ID_LOW_M ((EFUSE_MAC_ID_LOW_V)<<(EFUSE_MAC_ID_LOW_S)) -#define EFUSE_MAC_ID_LOW_V 0xFFFFFFFF -#define EFUSE_MAC_ID_LOW_S 0 +/** EFUSE_RD_BLK2_DATA0_REG register + * Register 0 of BLOCK2. + */ +#define EFUSE_RD_BLK2_DATA0_REG (DR_REG_EFUSE_BASE + 0x40) +/** EFUSE_BLK2_DATA0 : RO; bitpos: [31:0]; default: 0; + * Store the bit [0:31] of MAC. + */ +#define EFUSE_BLK2_DATA0 0xFFFFFFFFU +#define EFUSE_BLK2_DATA0_M (EFUSE_BLK2_DATA0_V << EFUSE_BLK2_DATA0_S) +#define EFUSE_BLK2_DATA0_V 0xFFFFFFFFU +#define EFUSE_BLK2_DATA0_S 0 -#define EFUSE_RD_BLK2_DATA1_REG (DR_REG_EFUSE_BASE + 0x44) -/* EFUSE_LDO_VOL_BIAS_CONFIG_LOW : RO ;bitpos:[31:29] ;default: 3'h0 ; */ -/*description: Store the bit [0:2] of ido configuration parameters..*/ -#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW 0x00000007 -#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW_M ((EFUSE_LDO_VOL_BIAS_CONFIG_LOW_V)<<(EFUSE_LDO_VOL_BIAS_CONFIG_LOW_S)) -#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW_V 0x7 -#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW_S 29 -/* EFUSE_RF_REF_I_BIAS_CONFIG : RO ;bitpos:[28:25] ;default: 4'h0 ; */ -/*description: Store rf configuration parameters..*/ -#define EFUSE_RF_REF_I_BIAS_CONFIG 0x0000000F -#define EFUSE_RF_REF_I_BIAS_CONFIG_M ((EFUSE_RF_REF_I_BIAS_CONFIG_V)<<(EFUSE_RF_REF_I_BIAS_CONFIG_S)) -#define EFUSE_RF_REF_I_BIAS_CONFIG_V 0xF -#define EFUSE_RF_REF_I_BIAS_CONFIG_S 25 -/* EFUSE_BLK2_EFUSE_VERSION : RO ;bitpos:[24:22] ;default: 3'h0 ; */ -/*description: Store efuse version..*/ -#define EFUSE_BLK2_EFUSE_VERSION 0x00000007 -#define EFUSE_BLK2_EFUSE_VERSION_M ((EFUSE_BLK2_EFUSE_VERSION_V)<<(EFUSE_BLK2_EFUSE_VERSION_S)) -#define EFUSE_BLK2_EFUSE_VERSION_V 0x7 -#define EFUSE_BLK2_EFUSE_VERSION_S 22 -/* EFUSE_PKG_VERSION : RO ;bitpos:[21:19] ;default: 3'h0 ; */ -/*description: Store package version..*/ -#define EFUSE_PKG_VERSION 0x00000007 -#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S)) -#define EFUSE_PKG_VERSION_V 0x7 -#define EFUSE_PKG_VERSION_S 19 -/* EFUSE_WAFER_VERSION : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: Store wafer version..*/ -#define EFUSE_WAFER_VERSION 0x00000007 -#define EFUSE_WAFER_VERSION_M ((EFUSE_WAFER_VERSION_V)<<(EFUSE_WAFER_VERSION_S)) -#define EFUSE_WAFER_VERSION_V 0x7 -#define EFUSE_WAFER_VERSION_S 16 -/* EFUSE_MAC_ID_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: Store the bit [31:47] of MAC..*/ -#define EFUSE_MAC_ID_HIGH 0x0000FFFF -#define EFUSE_MAC_ID_HIGH_M ((EFUSE_MAC_ID_HIGH_V)<<(EFUSE_MAC_ID_HIGH_S)) -#define EFUSE_MAC_ID_HIGH_V 0xFFFF +/** EFUSE_RD_BLK2_DATA1_REG register + * Register 1 of BLOCK2. + */ +#define EFUSE_RD_BLK2_DATA1_REG (DR_REG_EFUSE_BASE + 0x44) +/** EFUSE_MAC_ID_HIGH : RO; bitpos: [15:0]; default: 0; + * Store the bit [31:47] of MAC. + */ +#define EFUSE_MAC_ID_HIGH 0x0000FFFFU +#define EFUSE_MAC_ID_HIGH_M (EFUSE_MAC_ID_HIGH_V << EFUSE_MAC_ID_HIGH_S) +#define EFUSE_MAC_ID_HIGH_V 0x0000FFFFU #define EFUSE_MAC_ID_HIGH_S 0 +/** EFUSE_WAFER_VERSION : RO; bitpos: [18:16]; default: 0; + * Store wafer version. + */ +#define EFUSE_WAFER_VERSION 0x00000007U +#define EFUSE_WAFER_VERSION_M (EFUSE_WAFER_VERSION_V << EFUSE_WAFER_VERSION_S) +#define EFUSE_WAFER_VERSION_V 0x00000007U +#define EFUSE_WAFER_VERSION_S 16 +/** EFUSE_PKG_VERSION : RO; bitpos: [21:19]; default: 0; + * Store package version. + */ +#define EFUSE_PKG_VERSION 0x00000007U +#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) +#define EFUSE_PKG_VERSION_V 0x00000007U +#define EFUSE_PKG_VERSION_S 19 +/** EFUSE_BLK2_EFUSE_VERSION : RO; bitpos: [24:22]; default: 0; + * Store efuse version. + */ +#define EFUSE_BLK2_EFUSE_VERSION 0x00000007U +#define EFUSE_BLK2_EFUSE_VERSION_M (EFUSE_BLK2_EFUSE_VERSION_V << EFUSE_BLK2_EFUSE_VERSION_S) +#define EFUSE_BLK2_EFUSE_VERSION_V 0x00000007U +#define EFUSE_BLK2_EFUSE_VERSION_S 22 +/** EFUSE_RF_REF_I_BIAS_CONFIG : RO; bitpos: [28:25]; default: 0; + * Store rf configuration parameters. + */ +#define EFUSE_RF_REF_I_BIAS_CONFIG 0x0000000FU +#define EFUSE_RF_REF_I_BIAS_CONFIG_M (EFUSE_RF_REF_I_BIAS_CONFIG_V << EFUSE_RF_REF_I_BIAS_CONFIG_S) +#define EFUSE_RF_REF_I_BIAS_CONFIG_V 0x0000000FU +#define EFUSE_RF_REF_I_BIAS_CONFIG_S 25 +/** EFUSE_LDO_VOL_BIAS_CONFIG_LOW : RO; bitpos: [31:29]; default: 0; + * Store the bit [0:2] of ido configuration parameters. + */ +#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW 0x00000007U +#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW_M (EFUSE_LDO_VOL_BIAS_CONFIG_LOW_V << EFUSE_LDO_VOL_BIAS_CONFIG_LOW_S) +#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW_V 0x00000007U +#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW_S 29 -#define EFUSE_RD_BLK2_DATA2_REG (DR_REG_EFUSE_BASE + 0x48) -/* EFUSE_PVT_LOW : RO ;bitpos:[31:27] ;default: 5'h0 ; */ -/*description: Store the bit [0:4] of pvt..*/ -#define EFUSE_PVT_LOW 0x0000001F -#define EFUSE_PVT_LOW_M ((EFUSE_PVT_LOW_V)<<(EFUSE_PVT_LOW_S)) -#define EFUSE_PVT_LOW_V 0x1F -#define EFUSE_PVT_LOW_S 27 -/* EFUSE_LDO_VOL_BIAS_CONFIG_HIGH : RO ;bitpos:[26:0] ;default: 27'h0 ; */ -/*description: Store the bit [3:29] of ido configuration parameters..*/ -#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH 0x07FFFFFF -#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_M ((EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_V)<<(EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_S)) -#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_V 0x7FFFFFF +/** EFUSE_RD_BLK2_DATA2_REG register + * Register 2 of BLOCK2. + */ +#define EFUSE_RD_BLK2_DATA2_REG (DR_REG_EFUSE_BASE + 0x48) +/** EFUSE_LDO_VOL_BIAS_CONFIG_HIGH : RO; bitpos: [26:0]; default: 0; + * Store the bit [3:29] of ido configuration parameters. + */ +#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH 0x07FFFFFFU +#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_M (EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_V << EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_S) +#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_V 0x07FFFFFFU #define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_S 0 +/** EFUSE_PVT_LOW : RO; bitpos: [31:27]; default: 0; + * Store the bit [0:4] of pvt. + */ +#define EFUSE_PVT_LOW 0x0000001FU +#define EFUSE_PVT_LOW_M (EFUSE_PVT_LOW_V << EFUSE_PVT_LOW_S) +#define EFUSE_PVT_LOW_V 0x0000001FU +#define EFUSE_PVT_LOW_S 27 -#define EFUSE_RD_BLK2_DATA3_REG (DR_REG_EFUSE_BASE + 0x4C) -/* EFUSE_ADC_CALIBRATION_0 : RO ;bitpos:[31:10] ;default: 22'h0 ; */ -/*description: Store the bit [0:21] of ADC calibration data..*/ -#define EFUSE_ADC_CALIBRATION_0 0x003FFFFF -#define EFUSE_ADC_CALIBRATION_0_M ((EFUSE_ADC_CALIBRATION_0_V)<<(EFUSE_ADC_CALIBRATION_0_S)) -#define EFUSE_ADC_CALIBRATION_0_V 0x3FFFFF -#define EFUSE_ADC_CALIBRATION_0_S 10 -/* EFUSE_PVT_HIGH : RO ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: Store the bit [5:14] of pvt..*/ -#define EFUSE_PVT_HIGH 0x000003FF -#define EFUSE_PVT_HIGH_M ((EFUSE_PVT_HIGH_V)<<(EFUSE_PVT_HIGH_S)) -#define EFUSE_PVT_HIGH_V 0x3FF +/** EFUSE_RD_BLK2_DATA3_REG register + * Register 3 of BLOCK2. + */ +#define EFUSE_RD_BLK2_DATA3_REG (DR_REG_EFUSE_BASE + 0x4c) +/** EFUSE_PVT_HIGH : RO; bitpos: [9:0]; default: 0; + * Store the bit [5:14] of pvt. + */ +#define EFUSE_PVT_HIGH 0x000003FFU +#define EFUSE_PVT_HIGH_M (EFUSE_PVT_HIGH_V << EFUSE_PVT_HIGH_S) +#define EFUSE_PVT_HIGH_V 0x000003FFU #define EFUSE_PVT_HIGH_S 0 +/** EFUSE_ADC_CALIBRATION_0 : RO; bitpos: [31:10]; default: 0; + * Store the bit [0:21] of ADC calibration data. + */ +#define EFUSE_ADC_CALIBRATION_0 0x003FFFFFU +#define EFUSE_ADC_CALIBRATION_0_M (EFUSE_ADC_CALIBRATION_0_V << EFUSE_ADC_CALIBRATION_0_S) +#define EFUSE_ADC_CALIBRATION_0_V 0x003FFFFFU +#define EFUSE_ADC_CALIBRATION_0_S 10 -#define EFUSE_RD_BLK2_DATA4_REG (DR_REG_EFUSE_BASE + 0x50) -/* EFUSE_ADC_CALIBRATION_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Store the bit [22:53] of ADC calibration data..*/ -#define EFUSE_ADC_CALIBRATION_1 0xFFFFFFFF -#define EFUSE_ADC_CALIBRATION_1_M ((EFUSE_ADC_CALIBRATION_1_V)<<(EFUSE_ADC_CALIBRATION_1_S)) -#define EFUSE_ADC_CALIBRATION_1_V 0xFFFFFFFF +/** EFUSE_RD_BLK2_DATA4_REG register + * Register 4 of BLOCK2. + */ +#define EFUSE_RD_BLK2_DATA4_REG (DR_REG_EFUSE_BASE + 0x50) +/** EFUSE_ADC_CALIBRATION_1 : RO; bitpos: [31:0]; default: 0; + * Store the bit [22:53] of ADC calibration data. + */ +#define EFUSE_ADC_CALIBRATION_1 0xFFFFFFFFU +#define EFUSE_ADC_CALIBRATION_1_M (EFUSE_ADC_CALIBRATION_1_V << EFUSE_ADC_CALIBRATION_1_S) +#define EFUSE_ADC_CALIBRATION_1_V 0xFFFFFFFFU #define EFUSE_ADC_CALIBRATION_1_S 0 -#define EFUSE_RD_BLK2_DATA5_REG (DR_REG_EFUSE_BASE + 0x54) -/* EFUSE_ADC_CALIBRATION_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Store the bit [54:85] of ADC calibration data..*/ -#define EFUSE_ADC_CALIBRATION_2 0xFFFFFFFF -#define EFUSE_ADC_CALIBRATION_2_M ((EFUSE_ADC_CALIBRATION_2_V)<<(EFUSE_ADC_CALIBRATION_2_S)) -#define EFUSE_ADC_CALIBRATION_2_V 0xFFFFFFFF +/** EFUSE_RD_BLK2_DATA5_REG register + * Register 5 of BLOCK2. + */ +#define EFUSE_RD_BLK2_DATA5_REG (DR_REG_EFUSE_BASE + 0x54) +/** EFUSE_ADC_CALIBRATION_2 : RO; bitpos: [31:0]; default: 0; + * Store the bit [54:85] of ADC calibration data. + */ +#define EFUSE_ADC_CALIBRATION_2 0xFFFFFFFFU +#define EFUSE_ADC_CALIBRATION_2_M (EFUSE_ADC_CALIBRATION_2_V << EFUSE_ADC_CALIBRATION_2_S) +#define EFUSE_ADC_CALIBRATION_2_V 0xFFFFFFFFU #define EFUSE_ADC_CALIBRATION_2_S 0 -#define EFUSE_RD_BLK2_DATA6_REG (DR_REG_EFUSE_BASE + 0x58) -/* EFUSE_BLK2_RESERVED_DATA_0 : RO ;bitpos:[31:11] ;default: 21'h0 ; */ -/*description: Store the bit [0:20] of block2 reserved data..*/ -#define EFUSE_BLK2_RESERVED_DATA_0 0x001FFFFF -#define EFUSE_BLK2_RESERVED_DATA_0_M ((EFUSE_BLK2_RESERVED_DATA_0_V)<<(EFUSE_BLK2_RESERVED_DATA_0_S)) -#define EFUSE_BLK2_RESERVED_DATA_0_V 0x1FFFFF -#define EFUSE_BLK2_RESERVED_DATA_0_S 11 -/* EFUSE_ADC_CALIBRATION_3 : RO ;bitpos:[10:0] ;default: 11'h0 ; */ -/*description: Store the bit [86:96] of ADC calibration data..*/ -#define EFUSE_ADC_CALIBRATION_3 0x000007FF -#define EFUSE_ADC_CALIBRATION_3_M ((EFUSE_ADC_CALIBRATION_3_V)<<(EFUSE_ADC_CALIBRATION_3_S)) -#define EFUSE_ADC_CALIBRATION_3_V 0x7FF +/** EFUSE_RD_BLK2_DATA6_REG register + * Register 6 of BLOCK2. + */ +#define EFUSE_RD_BLK2_DATA6_REG (DR_REG_EFUSE_BASE + 0x58) +/** EFUSE_ADC_CALIBRATION_3 : RO; bitpos: [10:0]; default: 0; + * Store the bit [86:96] of ADC calibration data. + */ +#define EFUSE_ADC_CALIBRATION_3 0x000007FFU +#define EFUSE_ADC_CALIBRATION_3_M (EFUSE_ADC_CALIBRATION_3_V << EFUSE_ADC_CALIBRATION_3_S) +#define EFUSE_ADC_CALIBRATION_3_V 0x000007FFU #define EFUSE_ADC_CALIBRATION_3_S 0 +/** EFUSE_BLK2_RESERVED_DATA_0 : RO; bitpos: [31:11]; default: 0; + * Store the bit [0:20] of block2 reserved data. + */ +#define EFUSE_BLK2_RESERVED_DATA_0 0x001FFFFFU +#define EFUSE_BLK2_RESERVED_DATA_0_M (EFUSE_BLK2_RESERVED_DATA_0_V << EFUSE_BLK2_RESERVED_DATA_0_S) +#define EFUSE_BLK2_RESERVED_DATA_0_V 0x001FFFFFU +#define EFUSE_BLK2_RESERVED_DATA_0_S 11 -#define EFUSE_RD_BLK2_DATA7_REG (DR_REG_EFUSE_BASE + 0x5C) -/* EFUSE_BLK2_RESERVED_DATA_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Store the bit [21:52] of block2 reserved data..*/ -#define EFUSE_BLK2_RESERVED_DATA_1 0xFFFFFFFF -#define EFUSE_BLK2_RESERVED_DATA_1_M ((EFUSE_BLK2_RESERVED_DATA_1_V)<<(EFUSE_BLK2_RESERVED_DATA_1_S)) -#define EFUSE_BLK2_RESERVED_DATA_1_V 0xFFFFFFFF +/** EFUSE_RD_BLK2_DATA7_REG register + * Register 7 of BLOCK2. + */ +#define EFUSE_RD_BLK2_DATA7_REG (DR_REG_EFUSE_BASE + 0x5c) +/** EFUSE_BLK2_RESERVED_DATA_1 : RO; bitpos: [31:0]; default: 0; + * Store the bit [21:52] of block2 reserved data. + */ +#define EFUSE_BLK2_RESERVED_DATA_1 0xFFFFFFFFU +#define EFUSE_BLK2_RESERVED_DATA_1_M (EFUSE_BLK2_RESERVED_DATA_1_V << EFUSE_BLK2_RESERVED_DATA_1_S) +#define EFUSE_BLK2_RESERVED_DATA_1_V 0xFFFFFFFFU #define EFUSE_BLK2_RESERVED_DATA_1_S 0 -#define EFUSE_RD_BLK3_DATA0_REG (DR_REG_EFUSE_BASE + 0x60) -/* EFUSE_BLK3_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Store the first 32-bit of Block3..*/ -#define EFUSE_BLK3_DATA0 0xFFFFFFFF -#define EFUSE_BLK3_DATA0_M ((EFUSE_BLK3_DATA0_V)<<(EFUSE_BLK3_DATA0_S)) -#define EFUSE_BLK3_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_BLK3_DATA0_REG register + * Register 0 of BLOCK3. + */ +#define EFUSE_RD_BLK3_DATA0_REG (DR_REG_EFUSE_BASE + 0x60) +/** EFUSE_BLK3_DATA0 : RO; bitpos: [31:0]; default: 0; + * Store the first 32-bit of Block3. + */ +#define EFUSE_BLK3_DATA0 0xFFFFFFFFU +#define EFUSE_BLK3_DATA0_M (EFUSE_BLK3_DATA0_V << EFUSE_BLK3_DATA0_S) +#define EFUSE_BLK3_DATA0_V 0xFFFFFFFFU #define EFUSE_BLK3_DATA0_S 0 -#define EFUSE_RD_BLK3_DATA1_REG (DR_REG_EFUSE_BASE + 0x64) -/* EFUSE_BLK3_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Store the second 32-bit of Block3..*/ -#define EFUSE_BLK3_DATA1 0xFFFFFFFF -#define EFUSE_BLK3_DATA1_M ((EFUSE_BLK3_DATA1_V)<<(EFUSE_BLK3_DATA1_S)) -#define EFUSE_BLK3_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_BLK3_DATA1_REG register + * Register 1 of BLOCK3. + */ +#define EFUSE_RD_BLK3_DATA1_REG (DR_REG_EFUSE_BASE + 0x64) +/** EFUSE_BLK3_DATA1 : RO; bitpos: [31:0]; default: 0; + * Store the second 32-bit of Block3. + */ +#define EFUSE_BLK3_DATA1 0xFFFFFFFFU +#define EFUSE_BLK3_DATA1_M (EFUSE_BLK3_DATA1_V << EFUSE_BLK3_DATA1_S) +#define EFUSE_BLK3_DATA1_V 0xFFFFFFFFU #define EFUSE_BLK3_DATA1_S 0 -#define EFUSE_RD_BLK3_DATA2_REG (DR_REG_EFUSE_BASE + 0x68) -/* EFUSE_BLK3_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Store the third 32-bit of Block3..*/ -#define EFUSE_BLK3_DATA2 0xFFFFFFFF -#define EFUSE_BLK3_DATA2_M ((EFUSE_BLK3_DATA2_V)<<(EFUSE_BLK3_DATA2_S)) -#define EFUSE_BLK3_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_BLK3_DATA2_REG register + * Register 2 of BLOCK3. + */ +#define EFUSE_RD_BLK3_DATA2_REG (DR_REG_EFUSE_BASE + 0x68) +/** EFUSE_BLK3_DATA2 : RO; bitpos: [31:0]; default: 0; + * Store the third 32-bit of Block3. + */ +#define EFUSE_BLK3_DATA2 0xFFFFFFFFU +#define EFUSE_BLK3_DATA2_M (EFUSE_BLK3_DATA2_V << EFUSE_BLK3_DATA2_S) +#define EFUSE_BLK3_DATA2_V 0xFFFFFFFFU #define EFUSE_BLK3_DATA2_S 0 -#define EFUSE_RD_BLK3_DATA3_REG (DR_REG_EFUSE_BASE + 0x6C) -/* EFUSE_BLK3_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Store the fourth 32-bit of Block3..*/ -#define EFUSE_BLK3_DATA3 0xFFFFFFFF -#define EFUSE_BLK3_DATA3_M ((EFUSE_BLK3_DATA3_V)<<(EFUSE_BLK3_DATA3_S)) -#define EFUSE_BLK3_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_BLK3_DATA3_REG register + * Register 3 of BLOCK3. + */ +#define EFUSE_RD_BLK3_DATA3_REG (DR_REG_EFUSE_BASE + 0x6c) +/** EFUSE_BLK3_DATA3 : RO; bitpos: [31:0]; default: 0; + * Store the fourth 32-bit of Block3. + */ +#define EFUSE_BLK3_DATA3 0xFFFFFFFFU +#define EFUSE_BLK3_DATA3_M (EFUSE_BLK3_DATA3_V << EFUSE_BLK3_DATA3_S) +#define EFUSE_BLK3_DATA3_V 0xFFFFFFFFU #define EFUSE_BLK3_DATA3_S 0 -#define EFUSE_RD_BLK3_DATA4_REG (DR_REG_EFUSE_BASE + 0x70) -/* EFUSE_BLK3_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Store the fifth 32-bit of Block3..*/ -#define EFUSE_BLK3_DATA4 0xFFFFFFFF -#define EFUSE_BLK3_DATA4_M ((EFUSE_BLK3_DATA4_V)<<(EFUSE_BLK3_DATA4_S)) -#define EFUSE_BLK3_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_BLK3_DATA4_REG register + * Register 4 of BLOCK3. + */ +#define EFUSE_RD_BLK3_DATA4_REG (DR_REG_EFUSE_BASE + 0x70) +/** EFUSE_BLK3_DATA4 : RO; bitpos: [31:0]; default: 0; + * Store the fifth 32-bit of Block3. + */ +#define EFUSE_BLK3_DATA4 0xFFFFFFFFU +#define EFUSE_BLK3_DATA4_M (EFUSE_BLK3_DATA4_V << EFUSE_BLK3_DATA4_S) +#define EFUSE_BLK3_DATA4_V 0xFFFFFFFFU #define EFUSE_BLK3_DATA4_S 0 -#define EFUSE_RD_BLK3_DATA5_REG (DR_REG_EFUSE_BASE + 0x74) -/* EFUSE_BLK3_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Store the sixth 32-bit of Block3..*/ -#define EFUSE_BLK3_DATA5 0xFFFFFFFF -#define EFUSE_BLK3_DATA5_M ((EFUSE_BLK3_DATA5_V)<<(EFUSE_BLK3_DATA5_S)) -#define EFUSE_BLK3_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_BLK3_DATA5_REG register + * Register 5 of BLOCK3. + */ +#define EFUSE_RD_BLK3_DATA5_REG (DR_REG_EFUSE_BASE + 0x74) +/** EFUSE_BLK3_DATA5 : RO; bitpos: [31:0]; default: 0; + * Store the sixth 32-bit of Block3. + */ +#define EFUSE_BLK3_DATA5 0xFFFFFFFFU +#define EFUSE_BLK3_DATA5_M (EFUSE_BLK3_DATA5_V << EFUSE_BLK3_DATA5_S) +#define EFUSE_BLK3_DATA5_V 0xFFFFFFFFU #define EFUSE_BLK3_DATA5_S 0 -#define EFUSE_RD_BLK3_DATA6_REG (DR_REG_EFUSE_BASE + 0x78) -/* EFUSE_BLK3_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Store the seventh 32-bit of Block3..*/ -#define EFUSE_BLK3_DATA6 0xFFFFFFFF -#define EFUSE_BLK3_DATA6_M ((EFUSE_BLK3_DATA6_V)<<(EFUSE_BLK3_DATA6_S)) -#define EFUSE_BLK3_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_BLK3_DATA6_REG register + * Register 6 of BLOCK3. + */ +#define EFUSE_RD_BLK3_DATA6_REG (DR_REG_EFUSE_BASE + 0x78) +/** EFUSE_BLK3_DATA6 : RO; bitpos: [31:0]; default: 0; + * Store the seventh 32-bit of Block3. + */ +#define EFUSE_BLK3_DATA6 0xFFFFFFFFU +#define EFUSE_BLK3_DATA6_M (EFUSE_BLK3_DATA6_V << EFUSE_BLK3_DATA6_S) +#define EFUSE_BLK3_DATA6_V 0xFFFFFFFFU #define EFUSE_BLK3_DATA6_S 0 -#define EFUSE_RD_BLK3_DATA7_REG (DR_REG_EFUSE_BASE + 0x7C) -/* EFUSE_BLK3_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Store the eighth 32-bit of Block3..*/ -#define EFUSE_BLK3_DATA7 0xFFFFFFFF -#define EFUSE_BLK3_DATA7_M ((EFUSE_BLK3_DATA7_V)<<(EFUSE_BLK3_DATA7_S)) -#define EFUSE_BLK3_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_BLK3_DATA7_REG register + * Register 7 of BLOCK3. + */ +#define EFUSE_RD_BLK3_DATA7_REG (DR_REG_EFUSE_BASE + 0x7c) +/** EFUSE_BLK3_DATA7 : RO; bitpos: [31:0]; default: 0; + * Store the eighth 32-bit of Block3. + */ +#define EFUSE_BLK3_DATA7 0xFFFFFFFFU +#define EFUSE_BLK3_DATA7_M (EFUSE_BLK3_DATA7_V << EFUSE_BLK3_DATA7_S) +#define EFUSE_BLK3_DATA7_V 0xFFFFFFFFU #define EFUSE_BLK3_DATA7_S 0 -#define EFUSE_RD_REPEAT_ERR_REG (DR_REG_EFUSE_BASE + 0x80) -/* EFUSE_RPT4_RESERVED_ERR : RO ;bitpos:[31:22] ;default: 12'h0 ; */ -/*description: Reserved..*/ -#define EFUSE_RPT4_RESERVED_ERR 0x000003FF -#define EFUSE_RPT4_RESERVED_ERR_M ((EFUSE_RPT4_RESERVED_ERR_V)<<(EFUSE_RPT4_RESERVED_ERR_S)) -#define EFUSE_RPT4_RESERVED_ERR_V 0x3FF -#define EFUSE_RPT4_RESERVED_ERR_S 22 -/* EFUSE_SECURE_BOOT_EN_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: If any bit in this filed is 1, then it indicates a programming error..*/ -#define EFUSE_SECURE_BOOT_EN_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_EN_ERR_M (BIT(21)) -#define EFUSE_SECURE_BOOT_EN_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_EN_ERR_S 21 -/* EFUSE_FLASH_TPUW_ERR : RO ;bitpos:[20:17] ;default: 4'h0 ; */ -/*description: If any bit in this filed is 1, then it indicates a programming error..*/ -#define EFUSE_FLASH_TPUW_ERR 0x0000000F -#define EFUSE_FLASH_TPUW_ERR_M ((EFUSE_FLASH_TPUW_ERR_V)<<(EFUSE_FLASH_TPUW_ERR_S)) -#define EFUSE_FLASH_TPUW_ERR_V 0xF -#define EFUSE_FLASH_TPUW_ERR_S 17 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: If any bit in this filed is 1, then it indicates a programming error..*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(16)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (BIT(16)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 16 -/* EFUSE_DIS_DIRECT_BOOT_ERR : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: If any bit in this filed is 1, then it indicates a programming error..*/ -#define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(15)) -#define EFUSE_DIS_DIRECT_BOOT_ERR_M (BIT(15)) -#define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x1 -#define EFUSE_DIS_DIRECT_BOOT_ERR_S 15 -/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: If any bit in this filed is 1, then it indicates a programming error..*/ -#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(14)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (BIT(14)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 14 -/* EFUSE_FORCE_SEND_RESUME_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: If any bit in FORCE_SEND_RESUME is 1, then it indicates a programming error..*/ -#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_ERR_M (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_ERR_S 13 -/* EFUSE_UART_PRINT_CONTROL_ERR : RO ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error..*/ -#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_ERR_M ((EFUSE_UART_PRINT_CONTROL_ERR_V)<<(EFUSE_UART_PRINT_CONTROL_ERR_S)) -#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_ERR_S 11 -/* EFUSE_XTS_KEY_LENGTH_256_ERR : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: If any bit in XTS_KEY_LENGTH_256 is 1, then it indicates a programming error..*/ -#define EFUSE_XTS_KEY_LENGTH_256_ERR (BIT(10)) -#define EFUSE_XTS_KEY_LENGTH_256_ERR_M (BIT(10)) -#define EFUSE_XTS_KEY_LENGTH_256_ERR_V 0x1 -#define EFUSE_XTS_KEY_LENGTH_256_ERR_S 10 -/* EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR : RO ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: If any bit in SPI_BOOT_ENCRYPT_DECRYPT_CNT is 1, then it indicates a programming - error..*/ -#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR 0x00000007 -#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_M ((EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_V)<<(EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_S)) -#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_V 0x7 -#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_S 7 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: If any bit in DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming -error..*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(6)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (BIT(6)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 6 -/* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: If any bit in this filed is 1, then it indicates a programming error..*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(5)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (BIT(5)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 5 -/* EFUSE_DIS_PAD_JTAG_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error..*/ -#define EFUSE_DIS_PAD_JTAG_ERR (BIT(4)) -#define EFUSE_DIS_PAD_JTAG_ERR_M (BIT(4)) -#define EFUSE_DIS_PAD_JTAG_ERR_V 0x1 -#define EFUSE_DIS_PAD_JTAG_ERR_S 4 -/* EFUSE_WDT_DELAY_SEL_ERR : RO ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error..*/ -#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 -#define EFUSE_WDT_DELAY_SEL_ERR_M ((EFUSE_WDT_DELAY_SEL_ERR_V)<<(EFUSE_WDT_DELAY_SEL_ERR_S)) -#define EFUSE_WDT_DELAY_SEL_ERR_V 0x3 +/** EFUSE_RD_REPEAT_ERR_REG register + * Programming error record register 0 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR_REG (DR_REG_EFUSE_BASE + 0x80) +/** EFUSE_RD_DIS_ERR : RO; bitpos: [1:0]; default: 0; + * If any bit in RD_DIS is 1, then it indicates a programming error. + */ +#define EFUSE_RD_DIS_ERR 0x00000003U +#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) +#define EFUSE_RD_DIS_ERR_V 0x00000003U +#define EFUSE_RD_DIS_ERR_S 0 +/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [3:2]; default: 0; + * If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error. + */ +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U #define EFUSE_WDT_DELAY_SEL_ERR_S 2 -/* EFUSE_KEY0_RD_DIS_ERR : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: If any bit in RD_DIS is 1, then it indicates a programming error..*/ -#define EFUSE_KEY0_RD_DIS_ERR 0x00000003 -#define EFUSE_KEY0_RD_DIS_ERR_M ((EFUSE_KEY0_RD_DIS_ERR_V)<<(EFUSE_KEY0_RD_DIS_ERR_S)) -#define EFUSE_KEY0_RD_DIS_ERR_V 0x3 -#define EFUSE_KEY0_RD_DIS_ERR_S 0 +/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [4]; default: 0; + * If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_PAD_JTAG_ERR (BIT(4)) +#define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) +#define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_ERR_S 4 +/** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [5]; default: 0; + * If any bit in this filed is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(5)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 5 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [6]; default: 0; + * If any bit in DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming + * error. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(6)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 6 +/** EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR : RO; bitpos: [9:7]; default: 0; + * If any bit in SPI_BOOT_ENCRYPT_DECRYPT_CNT is 1, then it indicates a programming + * error. + */ +#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR 0x00000007U +#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_S) +#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_V 0x00000007U +#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_S 7 +/** EFUSE_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [10]; default: 0; + * If any bit in XTS_KEY_LENGTH_256 is 1, then it indicates a programming error. + */ +#define EFUSE_XTS_KEY_LENGTH_256_ERR (BIT(10)) +#define EFUSE_XTS_KEY_LENGTH_256_ERR_M (EFUSE_XTS_KEY_LENGTH_256_ERR_V << EFUSE_XTS_KEY_LENGTH_256_ERR_S) +#define EFUSE_XTS_KEY_LENGTH_256_ERR_V 0x00000001U +#define EFUSE_XTS_KEY_LENGTH_256_ERR_S 10 +/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [12:11]; default: 0; + * If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error. + */ +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_S 11 +/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0; + * If any bit in FORCE_SEND_RESUME is 1, then it indicates a programming error. + */ +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_ERR_S 13 +/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [14]; default: 0; + * If any bit in this filed is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(14)) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 14 +/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [15]; default: 0; + * If any bit in this filed is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(15)) +#define EFUSE_DIS_DIRECT_BOOT_ERR_M (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S) +#define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_ERR_S 15 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [16]; default: 0; + * If any bit in this filed is 1, then it indicates a programming error. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(16)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 16 +/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [20:17]; default: 0; + * If any bit in this filed is 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_TPUW_ERR 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) +#define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_S 17 +/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [21]; default: 0; + * If any bit in this filed is 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_ERR_S 21 +/** EFUSE_RPT4_RESERVED_ERR : RO; bitpos: [31:22]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED_ERR 0x000003FFU +#define EFUSE_RPT4_RESERVED_ERR_M (EFUSE_RPT4_RESERVED_ERR_V << EFUSE_RPT4_RESERVED_ERR_S) +#define EFUSE_RPT4_RESERVED_ERR_V 0x000003FFU +#define EFUSE_RPT4_RESERVED_ERR_S 22 -#define EFUSE_RD_RS_ERR_REG (DR_REG_EFUSE_BASE + 0x84) -/* EFUSE_BLK3_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the block3 data is reliable 1: Means that programmi -ng user data failed and the number of error bytes is over 6..*/ -#define EFUSE_BLK3_FAIL (BIT(11)) -#define EFUSE_BLK3_FAIL_M (BIT(11)) -#define EFUSE_BLK3_FAIL_V 0x1 -#define EFUSE_BLK3_FAIL_S 11 -/* EFUSE_BLK3_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes in block3..*/ -#define EFUSE_BLK3_ERR_NUM 0x00000007 -#define EFUSE_BLK3_ERR_NUM_M ((EFUSE_BLK3_ERR_NUM_V)<<(EFUSE_BLK3_ERR_NUM_S)) -#define EFUSE_BLK3_ERR_NUM_V 0x7 -#define EFUSE_BLK3_ERR_NUM_S 8 -/* EFUSE_BLK2_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of block2 is reliable 1: Means that progra -mming user data failed and the number of error bytes is over 6..*/ -#define EFUSE_BLK2_FAIL (BIT(7)) -#define EFUSE_BLK2_FAIL_M (BIT(7)) -#define EFUSE_BLK2_FAIL_V 0x1 -#define EFUSE_BLK2_FAIL_S 7 -/* EFUSE_BLK2_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes in block2..*/ -#define EFUSE_BLK2_ERR_NUM 0x00000007 -#define EFUSE_BLK2_ERR_NUM_M ((EFUSE_BLK2_ERR_NUM_V)<<(EFUSE_BLK2_ERR_NUM_S)) -#define EFUSE_BLK2_ERR_NUM_V 0x7 -#define EFUSE_BLK2_ERR_NUM_S 4 -/* EFUSE_BLK1_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of block1 is reliable 1: Means that progra -mming user data failed and the number of error bytes is over 6..*/ -#define EFUSE_BLK1_FAIL (BIT(3)) -#define EFUSE_BLK1_FAIL_M (BIT(3)) -#define EFUSE_BLK1_FAIL_V 0x1 -#define EFUSE_BLK1_FAIL_S 3 -/* EFUSE_BLK1_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes in block1..*/ -#define EFUSE_BLK1_ERR_NUM 0x00000007 -#define EFUSE_BLK1_ERR_NUM_M ((EFUSE_BLK1_ERR_NUM_V)<<(EFUSE_BLK1_ERR_NUM_S)) -#define EFUSE_BLK1_ERR_NUM_V 0x7 +/** EFUSE_RD_RS_ERR_REG register + * Programming error record register 0 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR_REG (DR_REG_EFUSE_BASE + 0x84) +/** EFUSE_BLK1_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes in block1. + */ +#define EFUSE_BLK1_ERR_NUM 0x00000007U +#define EFUSE_BLK1_ERR_NUM_M (EFUSE_BLK1_ERR_NUM_V << EFUSE_BLK1_ERR_NUM_S) +#define EFUSE_BLK1_ERR_NUM_V 0x00000007U #define EFUSE_BLK1_ERR_NUM_S 0 +/** EFUSE_BLK1_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of block1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_BLK1_FAIL (BIT(3)) +#define EFUSE_BLK1_FAIL_M (EFUSE_BLK1_FAIL_V << EFUSE_BLK1_FAIL_S) +#define EFUSE_BLK1_FAIL_V 0x00000001U +#define EFUSE_BLK1_FAIL_S 3 +/** EFUSE_BLK2_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes in block2. + */ +#define EFUSE_BLK2_ERR_NUM 0x00000007U +#define EFUSE_BLK2_ERR_NUM_M (EFUSE_BLK2_ERR_NUM_V << EFUSE_BLK2_ERR_NUM_S) +#define EFUSE_BLK2_ERR_NUM_V 0x00000007U +#define EFUSE_BLK2_ERR_NUM_S 4 +/** EFUSE_BLK2_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of block2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_BLK2_FAIL (BIT(7)) +#define EFUSE_BLK2_FAIL_M (EFUSE_BLK2_FAIL_V << EFUSE_BLK2_FAIL_S) +#define EFUSE_BLK2_FAIL_V 0x00000001U +#define EFUSE_BLK2_FAIL_S 7 +/** EFUSE_BLK3_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes in block3. + */ +#define EFUSE_BLK3_ERR_NUM 0x00000007U +#define EFUSE_BLK3_ERR_NUM_M (EFUSE_BLK3_ERR_NUM_V << EFUSE_BLK3_ERR_NUM_S) +#define EFUSE_BLK3_ERR_NUM_V 0x00000007U +#define EFUSE_BLK3_ERR_NUM_S 8 +/** EFUSE_BLK3_FAIL : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the block3 data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ +#define EFUSE_BLK3_FAIL (BIT(11)) +#define EFUSE_BLK3_FAIL_M (EFUSE_BLK3_FAIL_V << EFUSE_BLK3_FAIL_S) +#define EFUSE_BLK3_FAIL_V 0x00000001U +#define EFUSE_BLK3_FAIL_S 11 -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x88) -/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit and force to enable clock signal of eFuse memory..*/ -#define EFUSE_CLK_EN (BIT(16)) -#define EFUSE_CLK_EN_M (BIT(16)) -#define EFUSE_CLK_EN_V 0x1 -#define EFUSE_CLK_EN_S 16 -/* EFUSE_EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to force eFuse SRAM into working mode..*/ -#define EFUSE_EFUSE_MEM_FORCE_PU (BIT(2)) -#define EFUSE_EFUSE_MEM_FORCE_PU_M (BIT(2)) -#define EFUSE_EFUSE_MEM_FORCE_PU_V 0x1 -#define EFUSE_EFUSE_MEM_FORCE_PU_S 2 -/* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: Set this bit and force to activate clock signal of eFuse SRAM..*/ -#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_M (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_V 0x1 -#define EFUSE_MEM_CLK_FORCE_ON_S 1 -/* EFUSE_EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to force eFuse SRAM into power-saving mode..*/ +/** EFUSE_CLK_REG register + * eFuse clcok configuration register. + */ +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x88) +/** EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ #define EFUSE_EFUSE_MEM_FORCE_PD (BIT(0)) -#define EFUSE_EFUSE_MEM_FORCE_PD_M (BIT(0)) -#define EFUSE_EFUSE_MEM_FORCE_PD_V 0x1 +#define EFUSE_EFUSE_MEM_FORCE_PD_M (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S) +#define EFUSE_EFUSE_MEM_FORCE_PD_V 0x00000001U #define EFUSE_EFUSE_MEM_FORCE_PD_S 0 +/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U +#define EFUSE_MEM_CLK_FORCE_ON_S 1 +/** EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ +#define EFUSE_EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_EFUSE_MEM_FORCE_PU_M (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S) +#define EFUSE_EFUSE_MEM_FORCE_PU_V 0x00000001U +#define EFUSE_EFUSE_MEM_FORCE_PU_S 2 +/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; + * Set this bit and force to enable clock signal of eFuse memory. + */ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001U +#define EFUSE_CLK_EN_S 16 -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x8C) -/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command..*/ -#define EFUSE_OP_CODE 0x0000FFFF -#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) -#define EFUSE_OP_CODE_V 0xFFFF +/** EFUSE_CONF_REG register + * eFuse operation mode configuraiton register + */ +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x8c) +/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: Operate programming command 0x5AA5: Operate read command. + */ +#define EFUSE_OP_CODE 0x0000FFFFU +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFFU #define EFUSE_OP_CODE_S 0 -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x90) -/* EFUSE_BLK0_VALID_BIT_CNT : RO ;bitpos:[15:10] ;default: 8'h0 ; */ -/*description: Record the number of bit '1' in BLOCK0..*/ -#define EFUSE_BLK0_VALID_BIT_CNT 0x0000003F -#define EFUSE_BLK0_VALID_BIT_CNT_M ((EFUSE_BLK0_VALID_BIT_CNT_V)<<(EFUSE_BLK0_VALID_BIT_CNT_S)) -#define EFUSE_BLK0_VALID_BIT_CNT_V 0x3F -#define EFUSE_BLK0_VALID_BIT_CNT_S 10 -/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The value of OTP_VDDQ_IS_SW..*/ -#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_M (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_V 0x1 -#define EFUSE_OTP_VDDQ_IS_SW_S 9 -/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The value of OTP_PGENB_SW..*/ -#define EFUSE_OTP_PGENB_SW (BIT(8)) -#define EFUSE_OTP_PGENB_SW_M (BIT(8)) -#define EFUSE_OTP_PGENB_SW_V 0x1 -#define EFUSE_OTP_PGENB_SW_S 8 -/* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The value of OTP_CSB_SW..*/ -#define EFUSE_OTP_CSB_SW (BIT(7)) -#define EFUSE_OTP_CSB_SW_M (BIT(7)) -#define EFUSE_OTP_CSB_SW_V 0x1 -#define EFUSE_OTP_CSB_SW_S 7 -/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The value of OTP_STROBE_SW..*/ -#define EFUSE_OTP_STROBE_SW (BIT(6)) -#define EFUSE_OTP_STROBE_SW_M (BIT(6)) -#define EFUSE_OTP_STROBE_SW_V 0x1 -#define EFUSE_OTP_STROBE_SW_S 6 -/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The value of OTP_VDDQ_C_SYNC2..*/ -#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_M (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x1 -#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 -/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The value of OTP_LOAD_SW..*/ -#define EFUSE_OTP_LOAD_SW (BIT(4)) -#define EFUSE_OTP_LOAD_SW_M (BIT(4)) -#define EFUSE_OTP_LOAD_SW_V 0x1 -#define EFUSE_OTP_LOAD_SW_S 4 -/* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Indicates the state of the eFuse state machine..*/ -#define EFUSE_STATE 0x0000000F -#define EFUSE_STATE_M ((EFUSE_STATE_V)<<(EFUSE_STATE_S)) -#define EFUSE_STATE_V 0xF +/** EFUSE_STATUS_REG register + * eFuse status register. + */ +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x90) +/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ +#define EFUSE_STATE 0x0000000FU +#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) +#define EFUSE_STATE_V 0x0000000FU #define EFUSE_STATE_S 0 +/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) +#define EFUSE_OTP_LOAD_SW_V 0x00000001U +#define EFUSE_OTP_LOAD_SW_S 4 +/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 +/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) +#define EFUSE_OTP_STROBE_SW_V 0x00000001U +#define EFUSE_OTP_STROBE_SW_S 6 +/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) +#define EFUSE_OTP_CSB_SW_V 0x00000001U +#define EFUSE_OTP_CSB_SW_S 7 +/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) +#define EFUSE_OTP_PGENB_SW_V 0x00000001U +#define EFUSE_OTP_PGENB_SW_S 8 +/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U +#define EFUSE_OTP_VDDQ_IS_SW_S 9 +/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [15:10]; default: 0; + * Record the number of bit '1' in BLOCK0. + */ +#define EFUSE_BLK0_VALID_BIT_CNT 0x0000003FU +#define EFUSE_BLK0_VALID_BIT_CNT_M (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S) +#define EFUSE_BLK0_VALID_BIT_CNT_V 0x0000003FU +#define EFUSE_BLK0_VALID_BIT_CNT_S 10 -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x94) -/* EFUSE_BLK_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: The serial number of the block to be programmed. Value 0-3 corresponds to block -number 0-3, respectively..*/ -#define EFUSE_BLK_NUM 0x00000003 -#define EFUSE_BLK_NUM_M ((EFUSE_BLK_NUM_V)<<(EFUSE_BLK_NUM_S)) -#define EFUSE_BLK_NUM_V 0x3 -#define EFUSE_BLK_NUM_S 2 -/* EFUSE_PGM_CMD : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to send programming command..*/ -#define EFUSE_PGM_CMD (BIT(1)) -#define EFUSE_PGM_CMD_M (BIT(1)) -#define EFUSE_PGM_CMD_V 0x1 -#define EFUSE_PGM_CMD_S 1 -/* EFUSE_READ_CMD : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to send read command..*/ +/** EFUSE_CMD_REG register + * eFuse command register. + */ +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x94) +/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ #define EFUSE_READ_CMD (BIT(0)) -#define EFUSE_READ_CMD_M (BIT(0)) -#define EFUSE_READ_CMD_V 0x1 +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001U #define EFUSE_READ_CMD_S 0 +/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001U +#define EFUSE_PGM_CMD_S 1 +/** EFUSE_BLK_NUM : R/W; bitpos: [3:2]; default: 0; + * The serial number of the block to be programmed. Value 0-3 corresponds to block + * number 0-3, respectively. + */ +#define EFUSE_BLK_NUM 0x00000003U +#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) +#define EFUSE_BLK_NUM_V 0x00000003U +#define EFUSE_BLK_NUM_S 2 -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x98) -/* EFUSE_PGM_DONE_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw bit signal for pgm_done interrupt..*/ -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_V 0x1 -#define EFUSE_PGM_DONE_INT_RAW_S 1 -/* EFUSE_READ_DONE_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw bit signal for read_done interrupt..*/ +/** EFUSE_INT_RAW_REG register + * eFuse raw interrupt register. + */ +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x98) +/** EFUSE_READ_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ #define EFUSE_READ_DONE_INT_RAW (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_V 0x1 +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001U #define EFUSE_READ_DONE_INT_RAW_S 0 +/** EFUSE_PGM_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U +#define EFUSE_PGM_DONE_INT_RAW_S 1 -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x9C) -/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The status signal for pgm_done interrupt..*/ -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_V 0x1 -#define EFUSE_PGM_DONE_INT_ST_S 1 -/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The status signal for read_done interrupt..*/ +/** EFUSE_INT_ST_REG register + * eFuse interrupt status register. + */ +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x9c) +/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ #define EFUSE_READ_DONE_INT_ST (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_V 0x1 +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001U #define EFUSE_READ_DONE_INT_ST_S 0 +/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ST_S 1 -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x100) -/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The enable signal for pgm_done interrupt..*/ -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_V 0x1 -#define EFUSE_PGM_DONE_INT_ENA_S 1 -/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The enable signal for read_done interrupt..*/ +/** EFUSE_INT_ENA_REG register + * eFuse interrupt enable register. + */ +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x100) +/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ #define EFUSE_READ_DONE_INT_ENA (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_V 0x1 +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001U #define EFUSE_READ_DONE_INT_ENA_S 0 +/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ENA_S 1 -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x104) -/* EFUSE_PGM_DONE_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The clear signal for pgm_done interrupt..*/ -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_V 0x1 -#define EFUSE_PGM_DONE_INT_CLR_S 1 -/* EFUSE_READ_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The clear signal for read_done interrupt..*/ +/** EFUSE_INT_CLR_REG register + * eFuse interrupt clear register. + */ +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x104) +/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ #define EFUSE_READ_DONE_INT_CLR (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_V 0x1 +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001U #define EFUSE_READ_DONE_INT_CLR_S 0 +/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U +#define EFUSE_PGM_DONE_INT_CLR_S 1 -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x108) -/* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Reduces the power supply of the programming voltage..*/ -#define EFUSE_OE_CLR (BIT(17)) -#define EFUSE_OE_CLR_M (BIT(17)) -#define EFUSE_OE_CLR_V 0x1 -#define EFUSE_OE_CLR_S 17 -/* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */ -/*description: Controls the rising period of the programming voltage..*/ -#define EFUSE_DAC_NUM 0x000000FF -#define EFUSE_DAC_NUM_M ((EFUSE_DAC_NUM_V)<<(EFUSE_DAC_NUM_S)) -#define EFUSE_DAC_NUM_V 0xFF -#define EFUSE_DAC_NUM_S 9 -/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Don't care..*/ -#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_V 0x1 -#define EFUSE_DAC_CLK_PAD_SEL_S 8 -/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd28 ; */ -/*description: Controls the division factor of the rising clock of the programming voltage..*/ -#define EFUSE_DAC_CLK_DIV 0x000000FF -#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) -#define EFUSE_DAC_CLK_DIV_V 0xFF +/** EFUSE_DAC_CONF_REG register + * Controls the eFuse programming voltage. + */ +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x108) +/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming voltage. + */ +#define EFUSE_DAC_CLK_DIV 0x000000FFU +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FFU #define EFUSE_DAC_CLK_DIV_S 0 +/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; + * Don't care. + */ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U +#define EFUSE_DAC_CLK_PAD_SEL_S 8 +/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ +#define EFUSE_DAC_NUM 0x000000FFU +#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) +#define EFUSE_DAC_NUM_V 0x000000FFU +#define EFUSE_DAC_NUM_S 9 +/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) +#define EFUSE_OE_CLR_V 0x00000001U +#define EFUSE_OE_CLR_S 17 -#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x10C) -/* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'h12 ; */ -/*description: Configures the initial read time of eFuse..*/ -#define EFUSE_READ_INIT_NUM 0x000000FF -#define EFUSE_READ_INIT_NUM_M ((EFUSE_READ_INIT_NUM_V)<<(EFUSE_READ_INIT_NUM_S)) -#define EFUSE_READ_INIT_NUM_V 0xFF -#define EFUSE_READ_INIT_NUM_S 24 -/* EFUSE_TSUR_A : R/W ;bitpos:[23:16] ;default: 8'h1 ; */ -/*description: Configures setup time for efuse read..*/ -#define EFUSE_TSUR_A 0x000000FF -#define EFUSE_TSUR_A_M ((EFUSE_TSUR_A_V)<<(EFUSE_TSUR_A_S)) -#define EFUSE_TSUR_A_V 0xFF -#define EFUSE_TSUR_A_S 16 -/* EFUSE_TRD : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ -/*description: Configures pulse time for efuse read..*/ -#define EFUSE_TRD 0x000000FF -#define EFUSE_TRD_M ((EFUSE_TRD_V)<<(EFUSE_TRD_S)) -#define EFUSE_TRD_V 0xFF -#define EFUSE_TRD_S 8 -/* EFUSE_THR_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ -/*description: Configures hold time for efuse read..*/ -#define EFUSE_THR_A 0x000000FF -#define EFUSE_THR_A_M ((EFUSE_THR_A_V)<<(EFUSE_THR_A_S)) -#define EFUSE_THR_A_V 0xFF +/** EFUSE_RD_TIM_CONF_REG register + * Configures read timing parameters. + */ +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x10c) +/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; + * Configures hold time for efuse read. + */ +#define EFUSE_THR_A 0x000000FFU +#define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) +#define EFUSE_THR_A_V 0x000000FFU #define EFUSE_THR_A_S 0 +/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2; + * Configures pulse time for efuse read. + */ +#define EFUSE_TRD 0x000000FFU +#define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) +#define EFUSE_TRD_V 0x000000FFU +#define EFUSE_TRD_S 8 +/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; + * Configures setup time for efuse read. + */ +#define EFUSE_TSUR_A 0x000000FFU +#define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) +#define EFUSE_TSUR_A_V 0x000000FFU +#define EFUSE_TSUR_A_S 16 +/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; + * Configures the initial read time of eFuse. + */ +#define EFUSE_READ_INIT_NUM 0x000000FFU +#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) +#define EFUSE_READ_INIT_NUM_V 0x000000FFU +#define EFUSE_READ_INIT_NUM_S 24 -#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x110) -/* EFUSE_TPGM : R/W ;bitpos:[31:16] ;default: 16'hc8 ; */ -/*description: Configures pulse time for burning '1' bit..*/ -#define EFUSE_TPGM 0x0000FFFF -#define EFUSE_TPGM_M ((EFUSE_TPGM_V)<<(EFUSE_TPGM_S)) -#define EFUSE_TPGM_V 0xFFFF -#define EFUSE_TPGM_S 16 -/* EFUSE_TPGM_INACTIVE : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ -/*description: Configures pulse time for burning '0' bit..*/ -#define EFUSE_TPGM_INACTIVE 0x000000FF -#define EFUSE_TPGM_INACTIVE_M ((EFUSE_TPGM_INACTIVE_V)<<(EFUSE_TPGM_INACTIVE_S)) -#define EFUSE_TPGM_INACTIVE_V 0xFF -#define EFUSE_TPGM_INACTIVE_S 8 -/* EFUSE_THP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ -/*description: Configures hold time for efuse program..*/ -#define EFUSE_THP_A 0x000000FF -#define EFUSE_THP_A_M ((EFUSE_THP_A_V)<<(EFUSE_THP_A_S)) -#define EFUSE_THP_A_V 0xFF +/** EFUSE_WR_TIM_CONF0_REG register + * Configurarion register 0 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x110) +/** EFUSE_THP_A : R/W; bitpos: [7:0]; default: 1; + * Configures hold time for efuse program. + */ +#define EFUSE_THP_A 0x000000FFU +#define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) +#define EFUSE_THP_A_V 0x000000FFU #define EFUSE_THP_A_S 0 +/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [15:8]; default: 1; + * Configures pulse time for burning '0' bit. + */ +#define EFUSE_TPGM_INACTIVE 0x000000FFU +#define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) +#define EFUSE_TPGM_INACTIVE_V 0x000000FFU +#define EFUSE_TPGM_INACTIVE_S 8 +/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200; + * Configures pulse time for burning '1' bit. + */ +#define EFUSE_TPGM 0x0000FFFFU +#define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) +#define EFUSE_TPGM_V 0x0000FFFFU +#define EFUSE_TPGM_S 16 -#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x114) -/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h3000 ; */ -/*description: Configures the power up time for VDDQ..*/ -#define EFUSE_PWR_ON_NUM 0x0000FFFF -#define EFUSE_PWR_ON_NUM_M ((EFUSE_PWR_ON_NUM_V)<<(EFUSE_PWR_ON_NUM_S)) -#define EFUSE_PWR_ON_NUM_V 0xFFFF -#define EFUSE_PWR_ON_NUM_S 8 -/* EFUSE_TSUP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ -/*description: Configures setup time for efuse program..*/ -#define EFUSE_TSUP_A 0x000000FF -#define EFUSE_TSUP_A_M ((EFUSE_TSUP_A_V)<<(EFUSE_TSUP_A_S)) -#define EFUSE_TSUP_A_V 0xFF +/** EFUSE_WR_TIM_CONF1_REG register + * Configurarion register 1 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x114) +/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; + * Configures setup time for efuse program. + */ +#define EFUSE_TSUP_A 0x000000FFU +#define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) +#define EFUSE_TSUP_A_V 0x000000FFU #define EFUSE_TSUP_A_S 0 +/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 12288; + * Configures the power up time for VDDQ. + */ +#define EFUSE_PWR_ON_NUM 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) +#define EFUSE_PWR_ON_NUM_V 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_S 8 -#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x118) -/* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h190 ; */ -/*description: Configures the power outage time for VDDQ..*/ -#define EFUSE_PWR_OFF_NUM 0x0000FFFF -#define EFUSE_PWR_OFF_NUM_M ((EFUSE_PWR_OFF_NUM_V)<<(EFUSE_PWR_OFF_NUM_S)) -#define EFUSE_PWR_OFF_NUM_V 0xFFFF +/** EFUSE_WR_TIM_CONF2_REG register + * Configurarion register 2 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x118) +/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ +#define EFUSE_PWR_OFF_NUM 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) +#define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU #define EFUSE_PWR_OFF_NUM_S 0 -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) -/* EFUSE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2108190 ; */ -/*description: Stores eFuse version..*/ -#define EFUSE_DATE 0x0FFFFFFF -#define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) -#define EFUSE_DATE_V 0xFFFFFFF +/** EFUSE_DATE_REG register + * eFuse version register. + */ +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) +/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 34636176; + * Stores eFuse version. + */ +#define EFUSE_DATE 0x0FFFFFFFU +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0x0FFFFFFFU #define EFUSE_DATE_S 0 - #ifdef __cplusplus } #endif - - - -#endif /*_SOC_EFUSE_REG_H_ */ diff --git a/components/soc/esp8684/include/soc/efuse_struct.h b/components/soc/esp8684/include/soc/efuse_struct.h index fddb8c66a9..74751f5596 100644 --- a/components/soc/esp8684/include/soc/efuse_struct.h +++ b/components/soc/esp8684/include/soc/efuse_struct.h @@ -1,348 +1,1002 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_EFUSE_STRUCT_H_ -#define _SOC_EFUSE_STRUCT_H_ - +#pragma once +#include #ifdef __cplusplus extern "C" { #endif -typedef volatile struct efuse_dev_s { - uint32_t pgm_data0; - uint32_t pgm_data1; - uint32_t pgm_data2; - uint32_t pgm_data3; - uint32_t pgm_data4; - uint32_t pgm_data5; - uint32_t pgm_data6; - uint32_t pgm_data7; - uint32_t pgm_check_value0; - uint32_t pgm_check_value1; - uint32_t pgm_check_value2; - union { - struct { - uint32_t reg_wr_dis : 8; /*Disable programming of individual eFuses.*/ - uint32_t reserved8 : 24; /*Reserved.*/ - }; - uint32_t val; - } rd_wr_dis; - union { - struct { - uint32_t reg_rd_dis : 2; /*The bit be set to disable software read high/low 128-bit of BLK3.*/ - uint32_t reg_wdt_delay_sel : 2; /*Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/ - uint32_t reg_dis_pad_jtag : 1; /*Set this bit to disable pad jtag.*/ - uint32_t reg_dis_download_icache : 1; /*The bit be set to disable icache in download mode.*/ - uint32_t reg_dis_download_manual_encrypt: 1; /*The bit be set to disable manual encryption.*/ - uint32_t reg_spi_boot_encrypt_decrypt_cnt: 3; /*These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.*/ - uint32_t reg_xts_key_length_256 : 1; /*The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise, XTS_AES use 128-bit eFuse data in BLOCK3.*/ - uint32_t reg_uart_print_control : 2; /*Set this bit to disable usb printing.*/ - uint32_t reg_force_send_resume : 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/ - uint32_t reg_dis_download_mode : 1; /*Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7).*/ - uint32_t reg_dis_direct_boot : 1; /*This bit set means disable direct_boot mode.*/ - uint32_t reg_enable_security_download : 1; /*Set this bit to enable secure UART download mode.*/ - uint32_t reg_flash_tpuw : 4; /*Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value. Otherwise, the waiting time is twice the configurable value.*/ - uint32_t reg_secure_boot_en : 1; /*The bit be set to enable secure boot.*/ - uint32_t reg_rpt4_reserved : 10; /*Reserved (used for four backups method).*/ - }; - uint32_t val; - } rd_repeat_data0; - uint32_t rd_blk1_data0; - uint32_t rd_blk1_data1; - union { - struct { - uint32_t reg_system_data2 : 24; /*Stores the bits [64:87] of system data.*/ - uint32_t reserved24 : 8; /*Reserved.*/ - }; - uint32_t val; - } rd_blk1_data2; - uint32_t rd_blk2_data0; - union { - struct { - uint32_t reg_mac_id_high : 16; /*Store the bit [31:47] of MAC.*/ - uint32_t reg_wafer_version : 3; /*Store wafer version.*/ - uint32_t reg_pkg_version : 3; /*Store package version.*/ - uint32_t reg_blk2_efuse_version : 3; /*Store efuse version.*/ - uint32_t reg_rf_ref_i_bias_config : 4; /*Store rf configuration parameters.*/ - uint32_t reg_ldo_vol_bias_config_low : 3; /*Store the bit [0:2] of ido configuration parameters.*/ - }; - uint32_t val; - } rd_blk2_data1; - union { - struct { - uint32_t reg_ldo_vol_bias_config_high : 27; /*Store the bit [3:29] of ido configuration parameters.*/ - uint32_t reg_pvt_low : 5; /*Store the bit [0:4] of pvt.*/ - }; - uint32_t val; - } rd_blk2_data2; - union { - struct { - uint32_t reg_pvt_high : 10; /*Store the bit [5:14] of pvt.*/ - uint32_t reg_adc_calibration_0 : 22; /*Store the bit [0:21] of ADC calibration data.*/ - }; - uint32_t val; - } rd_blk2_data3; - uint32_t rd_blk2_data4; - uint32_t rd_blk2_data5; - union { - struct { - uint32_t reg_adc_calibration_3 : 11; /*Store the bit [86:96] of ADC calibration data.*/ - uint32_t reg_blk2_reserved_data_0 : 21; /*Store the bit [0:20] of block2 reserved data.*/ - }; - uint32_t val; - } rd_blk2_data6; - uint32_t rd_blk2_data7; - uint32_t rd_blk3_data0; - uint32_t rd_blk3_data1; - uint32_t rd_blk3_data2; - uint32_t rd_blk3_data3; - uint32_t rd_blk3_data4; - uint32_t rd_blk3_data5; - uint32_t rd_blk3_data6; - uint32_t rd_blk3_data7; - union { - struct { - uint32_t reg_rd_dis_err : 2; /*If any bit in RD_DIS is 1, then it indicates a programming error.*/ - uint32_t reg_wdt_delay_sel_err : 2; /*If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.*/ - uint32_t reg_dis_pad_jtag_err : 1; /*If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error.*/ - uint32_t reg_dis_download_icache : 1; /*If any bit in this filed is 1, then it indicates a programming error.*/ - uint32_t reg_dis_download_manual_encrypt_err: 1; /*If any bit in DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.*/ - uint32_t reg_spi_boot_encrypt_decrypt_cnt_err: 3; /*If any bit in SPI_BOOT_ENCRYPT_DECRYPT_CNT is 1, then it indicates a programming error.*/ - uint32_t reg_xts_key_length_256_err : 1; /*If any bit in XTS_KEY_LENGTH_256 is 1, then it indicates a programming error.*/ - uint32_t reg_uart_print_control_err : 2; /*If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.*/ - uint32_t reg_force_send_resume_err : 1; /*If any bit in FORCE_SEND_RESUME is 1, then it indicates a programming error.*/ - uint32_t reg_dis_download_mode_err : 1; /*If any bit in this filed is 1, then it indicates a programming error.*/ - uint32_t reg_dis_direct_boot_err : 1; /*If any bit in this filed is 1, then it indicates a programming error.*/ - uint32_t reg_enable_security_download_err: 1; /*If any bit in this filed is 1, then it indicates a programming error.*/ - uint32_t reg_flash_tpuw_err : 4; /*If any bit in this filed is 1, then it indicates a programming error.*/ - uint32_t reg_secure_boot_en_err : 1; /*If any bit in this filed is 1, then it indicates a programming error.*/ - uint32_t reg_rpt4_reserved_err : 10; /*Reserved.*/ - }; - uint32_t val; - } rd_repeat_err; - union { - struct { - uint32_t blk1_err_num : 3; /*The value of this signal means the number of error bytes in block1.*/ - uint32_t blk1_fail : 1; /*0: Means no failure and that the data of block1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t blk2_err_num : 3; /*The value of this signal means the number of error bytes in block2.*/ - uint32_t blk2_fail : 1; /*0: Means no failure and that the data of block2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t blk3_err_num : 3; /*The value of this signal means the number of error bytes in block3.*/ - uint32_t blk3_fail : 1; /*0: Means no failure and that the block3 data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t reserved12 : 20; /*Reserved.*/ - }; - uint32_t val; - } rd_rs_err; - union { - struct { - uint32_t reg_efuse_mem_force_pd : 1; /*Set this bit to force eFuse SRAM into power-saving mode.*/ - uint32_t reg_mem_clk_force_on : 1; /*Set this bit and force to activate clock signal of eFuse SRAM.*/ - uint32_t reg_efuse_mem_force_pu : 1; /*Set this bit to force eFuse SRAM into working mode.*/ - uint32_t reserved3 : 13; /*Reserved.*/ - uint32_t reg_clk_en : 1; /*Set this bit and force to enable clock signal of eFuse memory.*/ - uint32_t reserved17 : 15; /*Reserved.*/ - }; - uint32_t val; - } clk; - union { - struct { - uint32_t reg_op_code : 16; /*0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ - uint32_t reserved16 : 16; /*Reserved.*/ - }; - uint32_t val; - } conf; - union { - struct { - uint32_t reg_state : 4; /*Indicates the state of the eFuse state machine.*/ - uint32_t reg_otp_load_sw : 1; /*The value of OTP_LOAD_SW.*/ - uint32_t reg_otp_vddq_c_sync2 : 1; /*The value of OTP_VDDQ_C_SYNC2.*/ - uint32_t reg_otp_strobe_sw : 1; /*The value of OTP_STROBE_SW.*/ - uint32_t reg_otp_csb_sw : 1; /*The value of OTP_CSB_SW.*/ - uint32_t reg_otp_pgenb_sw : 1; /*The value of OTP_PGENB_SW.*/ - uint32_t reg_otp_vddq_is_sw : 1; /*The value of OTP_VDDQ_IS_SW.*/ - uint32_t reg_blk0_valid_bit_cnt : 6; /*Record the number of bit '1' in BLOCK0.*/ - uint32_t reserved16 : 16; /*Reserved.*/ - }; - uint32_t val; - } status; - union { - struct { - uint32_t reg_read_cmd : 1; /*Set this bit to send read command.*/ - uint32_t reg_pgm_cmd : 1; /*Set this bit to send programming command.*/ - uint32_t reg_blk_num : 2; /*The serial number of the block to be programmed. Value 0-3 corresponds to block number 0-3, respectively.*/ - uint32_t reserved4 : 28; /*Reserved.*/ - }; - uint32_t val; - } cmd; - union { - struct { - uint32_t reg_read_done_int_raw : 1; /*The raw bit signal for read_done interrupt.*/ - uint32_t reg_pgm_done_int_raw : 1; /*The raw bit signal for pgm_done interrupt.*/ - uint32_t reserved2 : 30; /*Reserved.*/ - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t reg_read_done_int_st : 1; /*The status signal for read_done interrupt.*/ - uint32_t reg_pgm_done_int_st : 1; /*The status signal for pgm_done interrupt.*/ - uint32_t reserved2 : 30; /*Reserved.*/ - }; - uint32_t val; - } int_st; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t reserved_fc; - union { - struct { - uint32_t reg_read_done_int_ena : 1; /*The enable signal for read_done interrupt.*/ - uint32_t reg_pgm_done_int_ena : 1; /*The enable signal for pgm_done interrupt.*/ - uint32_t reserved2 : 30; /*Reserved.*/ - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t reg_read_done_int_clr : 1; /*The clear signal for read_done interrupt.*/ - uint32_t reg_pgm_done_int_clr : 1; /*The clear signal for pgm_done interrupt.*/ - uint32_t reserved2 : 30; /*Reserved.*/ - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t reg_dac_clk_div : 8; /*Controls the division factor of the rising clock of the programming voltage.*/ - uint32_t reg_dac_clk_pad_sel : 1; /*Don't care.*/ - uint32_t reg_dac_num : 8; /*Controls the rising period of the programming voltage.*/ - uint32_t reg_oe_clr : 1; /*Reduces the power supply of the programming voltage.*/ - uint32_t reserved18 : 14; /*Reserved.*/ - }; - uint32_t val; - } dac_conf; - union { - struct { - uint32_t reg_thr_a : 8; /*Configures hold time for efuse read.*/ - uint32_t reg_trd : 8; /*Configures pulse time for efuse read.*/ - uint32_t reg_tsur_a : 8; /*Configures setup time for efuse read.*/ - uint32_t reg_read_init_num : 8; /*Configures the initial read time of eFuse.*/ - }; - uint32_t val; - } rd_tim_conf; - union { - struct { - uint32_t reg_thp_a : 8; /*Configures hold time for efuse program.*/ - uint32_t reg_tpgm_inactive : 8; /*Configures pulse time for burning '0' bit.*/ - uint32_t reg_tpgm : 16; /*Configures pulse time for burning '1' bit.*/ - }; - uint32_t val; - } wr_tim_conf0; - union { - struct { - uint32_t reg_tsup_a : 8; /*Configures setup time for efuse program.*/ - uint32_t reg_pwr_on_num : 16; /*Configures the power up time for VDDQ.*/ - uint32_t reserved24 : 8; /*Reserved.*/ - }; - uint32_t val; - } wr_tim_conf1; - union { - struct { - uint32_t reg_pwr_off_num : 16; /*Configures the power outage time for VDDQ.*/ - uint32_t reserved16 : 16; /*Reserved.*/ - }; - uint32_t val; - } wr_tim_conf2; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t reserved_140; - uint32_t reserved_144; - uint32_t reserved_148; - uint32_t reserved_14c; - uint32_t reserved_150; - uint32_t reserved_154; - uint32_t reserved_158; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; - uint32_t reserved_18c; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; - uint32_t reserved_1cc; - uint32_t reserved_1d0; - uint32_t reserved_1d4; - uint32_t reserved_1d8; - uint32_t reserved_1dc; - uint32_t reserved_1e0; - uint32_t reserved_1e4; - uint32_t reserved_1e8; - uint32_t reserved_1ec; - uint32_t reserved_1f0; - uint32_t reserved_1f4; - uint32_t reserved_1f8; - union { - struct { - uint32_t reg_efuse_date : 28; /*Stores eFuse version.*/ - uint32_t reserved28 : 4; /*Reserved.*/ - }; - uint32_t val; - } date; +/** Group: PGM Data Register */ +/** Type of pgm_data0 register + * Register 0 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data0_reg_t; + +/** Type of pgm_data1 register + * Register 1 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit data to be programmed. + */ + uint32_t pgm_data_1:32; + }; + uint32_t val; +} efuse_pgm_data1_reg_t; + +/** Type of pgm_data2 register + * Register 2 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit data to be programmed. + */ + uint32_t pgm_data_2:32; + }; + uint32_t val; +} efuse_pgm_data2_reg_t; + +/** Type of pgm_data3 register + * Register 3 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; + * The content of the 3rd 32-bit data to be programmed. + */ + uint32_t pgm_data_3:32; + }; + uint32_t val; +} efuse_pgm_data3_reg_t; + +/** Type of pgm_data4 register + * Register 4 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; + * The content of the 4th 32-bit data to be programmed. + */ + uint32_t pgm_data_4:32; + }; + uint32_t val; +} efuse_pgm_data4_reg_t; + +/** Type of pgm_data5 register + * Register 5 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; + * The content of the 5th 32-bit data to be programmed. + */ + uint32_t pgm_data_5:32; + }; + uint32_t val; +} efuse_pgm_data5_reg_t; + +/** Type of pgm_data6 register + * Register 6 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; + * The content of the 6th 32-bit data to be programmed. + */ + uint32_t pgm_data_6:32; + }; + uint32_t val; +} efuse_pgm_data6_reg_t; + +/** Type of pgm_data7 register + * Register 7 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; + * The content of the 7th 32-bit data to be programmed. + */ + uint32_t pgm_data_7:32; + }; + uint32_t val; +} efuse_pgm_data7_reg_t; + +/** Type of pgm_check_value0 register + * Register 0 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_0:32; + }; + uint32_t val; +} efuse_pgm_check_value0_reg_t; + +/** Type of pgm_check_value1 register + * Register 1 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_1:32; + }; + uint32_t val; +} efuse_pgm_check_value1_reg_t; + +/** Type of pgm_check_value2 register + * Register 2 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_2:32; + }; + uint32_t val; +} efuse_pgm_check_value2_reg_t; + + +/** Group: Read Data Register */ +/** Type of rd_wr_dis register + * BLOCK0 data register 0. + */ +typedef union { + struct { + /** wr_dis : RO; bitpos: [7:0]; default: 0; + * Disable programming of individual eFuses. + */ + uint32_t wr_dis:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} efuse_rd_wr_dis_reg_t; + +/** Type of rd_repeat_data0 register + * BLOCK0 data register 1. + */ +typedef union { + struct { + /** rd_dis : RO; bitpos: [1:0]; default: 0; + * The bit be set to disable software read high/low 128-bit of BLK3. + */ + uint32_t rd_dis:2; + /** wdt_delay_sel : RO; bitpos: [3:2]; default: 0; + * Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: + * 80000. 2: 160000. 3:320000. + */ + uint32_t wdt_delay_sel:2; + /** dis_pad_jtag : RO; bitpos: [4]; default: 0; + * Set this bit to disable pad jtag. + */ + uint32_t dis_pad_jtag:1; + /** dis_download_icache : RO; bitpos: [5]; default: 0; + * The bit be set to disable icache in download mode. + */ + uint32_t dis_download_icache:1; + /** dis_download_manual_encrypt : RO; bitpos: [6]; default: 0; + * The bit be set to disable manual encryption. + */ + uint32_t dis_download_manual_encrypt:1; + /** spi_boot_encrypt_decrypt_cnt : RO; bitpos: [9:7]; default: 0; + * These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even + * number of 1: disable. + */ + uint32_t spi_boot_encrypt_decrypt_cnt:3; + /** xts_key_length_256 : RO; bitpos: [10]; default: 0; + * The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise, + * XTS_AES use 128-bit eFuse data in BLOCK3. + */ + uint32_t xts_key_length_256:1; + /** uart_print_control : RO; bitpos: [12:11]; default: 0; + * Set this bit to disable usb printing. + */ + uint32_t uart_print_control:2; + /** force_send_resume : RO; bitpos: [13]; default: 0; + * Set this bit to force ROM code to send a resume command during SPI boot. + */ + uint32_t force_send_resume:1; + /** dis_download_mode : RO; bitpos: [14]; default: 0; + * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7). + */ + uint32_t dis_download_mode:1; + /** dis_direct_boot : RO; bitpos: [15]; default: 0; + * This bit set means disable direct_boot mode. + */ + uint32_t dis_direct_boot:1; + /** enable_security_download : RO; bitpos: [16]; default: 0; + * Set this bit to enable secure UART download mode. + */ + uint32_t enable_security_download:1; + /** flash_tpuw : RO; bitpos: [20:17]; default: 0; + * Configures flash waiting time after power-up, in unit of ms. If the value is less + * than 15, the waiting time is the configurable value. Otherwise, the waiting time + * is twice the configurable value. + */ + uint32_t flash_tpuw:4; + /** secure_boot_en : RO; bitpos: [21]; default: 0; + * The bit be set to enable secure boot. + */ + uint32_t secure_boot_en:1; + /** rpt4_reserved : RO; bitpos: [31:22]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved:10; + }; + uint32_t val; +} efuse_rd_repeat_data0_reg_t; + +/** Type of rd_blk1_data0 register + * BLOCK1 data register 0. + */ +typedef union { + struct { + /** system_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the bits [0:31] of system data. + */ + uint32_t system_data0:32; + }; + uint32_t val; +} efuse_rd_blk1_data0_reg_t; + +/** Type of rd_blk1_data1 register + * BLOCK1 data register 1. + */ +typedef union { + struct { + /** system_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the bits [32:63] of system data. + */ + uint32_t system_data1:32; + }; + uint32_t val; +} efuse_rd_blk1_data1_reg_t; + +/** Type of rd_blk1_data2 register + * BLOCK1 data register 2. + */ +typedef union { + struct { + /** system_data2 : RO; bitpos: [23:0]; default: 0; + * Stores the bits [64:87] of system data. + */ + uint32_t system_data2:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_rd_blk1_data2_reg_t; + +/** Type of rd_blk2_data0 register + * Register 0 of BLOCK2. + */ +typedef union { + struct { + /** blk2_data0 : RO; bitpos: [31:0]; default: 0; + * Store the bit [0:31] of MAC. + */ + uint32_t blk2_data0:32; + }; + uint32_t val; +} efuse_rd_blk2_data0_reg_t; + +/** Type of rd_blk2_data1 register + * Register 1 of BLOCK2. + */ +typedef union { + struct { + /** mac_id_high : RO; bitpos: [15:0]; default: 0; + * Store the bit [31:47] of MAC. + */ + uint32_t mac_id_high:16; + /** wafer_version : RO; bitpos: [18:16]; default: 0; + * Store wafer version. + */ + uint32_t wafer_version:3; + /** pkg_version : RO; bitpos: [21:19]; default: 0; + * Store package version. + */ + uint32_t pkg_version:3; + /** blk2_efuse_version : RO; bitpos: [24:22]; default: 0; + * Store efuse version. + */ + uint32_t blk2_efuse_version:3; + /** rf_ref_i_bias_config : RO; bitpos: [28:25]; default: 0; + * Store rf configuration parameters. + */ + uint32_t rf_ref_i_bias_config:4; + /** ldo_vol_bias_config_low : RO; bitpos: [31:29]; default: 0; + * Store the bit [0:2] of ido configuration parameters. + */ + uint32_t ldo_vol_bias_config_low:3; + }; + uint32_t val; +} efuse_rd_blk2_data1_reg_t; + +/** Type of rd_blk2_data2 register + * Register 2 of BLOCK2. + */ +typedef union { + struct { + /** ldo_vol_bias_config_high : RO; bitpos: [26:0]; default: 0; + * Store the bit [3:29] of ido configuration parameters. + */ + uint32_t ldo_vol_bias_config_high:27; + /** pvt_low : RO; bitpos: [31:27]; default: 0; + * Store the bit [0:4] of pvt. + */ + uint32_t pvt_low:5; + }; + uint32_t val; +} efuse_rd_blk2_data2_reg_t; + +/** Type of rd_blk2_data3 register + * Register 3 of BLOCK2. + */ +typedef union { + struct { + /** pvt_high : RO; bitpos: [9:0]; default: 0; + * Store the bit [5:14] of pvt. + */ + uint32_t pvt_high:10; + /** adc_calibration_0 : RO; bitpos: [31:10]; default: 0; + * Store the bit [0:21] of ADC calibration data. + */ + uint32_t adc_calibration_0:22; + }; + uint32_t val; +} efuse_rd_blk2_data3_reg_t; + +/** Type of rd_blk2_data4 register + * Register 4 of BLOCK2. + */ +typedef union { + struct { + /** adc_calibration_1 : RO; bitpos: [31:0]; default: 0; + * Store the bit [22:53] of ADC calibration data. + */ + uint32_t adc_calibration_1:32; + }; + uint32_t val; +} efuse_rd_blk2_data4_reg_t; + +/** Type of rd_blk2_data5 register + * Register 5 of BLOCK2. + */ +typedef union { + struct { + /** adc_calibration_2 : RO; bitpos: [31:0]; default: 0; + * Store the bit [54:85] of ADC calibration data. + */ + uint32_t adc_calibration_2:32; + }; + uint32_t val; +} efuse_rd_blk2_data5_reg_t; + +/** Type of rd_blk2_data6 register + * Register 6 of BLOCK2. + */ +typedef union { + struct { + /** adc_calibration_3 : RO; bitpos: [10:0]; default: 0; + * Store the bit [86:96] of ADC calibration data. + */ + uint32_t adc_calibration_3:11; + /** blk2_reserved_data_0 : RO; bitpos: [31:11]; default: 0; + * Store the bit [0:20] of block2 reserved data. + */ + uint32_t blk2_reserved_data_0:21; + }; + uint32_t val; +} efuse_rd_blk2_data6_reg_t; + +/** Type of rd_blk2_data7 register + * Register 7 of BLOCK2. + */ +typedef union { + struct { + /** blk2_reserved_data_1 : RO; bitpos: [31:0]; default: 0; + * Store the bit [21:52] of block2 reserved data. + */ + uint32_t blk2_reserved_data_1:32; + }; + uint32_t val; +} efuse_rd_blk2_data7_reg_t; + +/** Type of rd_blk3_data0 register + * Register 0 of BLOCK3. + */ +typedef union { + struct { + /** blk3_data0 : RO; bitpos: [31:0]; default: 0; + * Store the first 32-bit of Block3. + */ + uint32_t blk3_data0:32; + }; + uint32_t val; +} efuse_rd_blk3_data0_reg_t; + +/** Type of rd_blk3_data1 register + * Register 1 of BLOCK3. + */ +typedef union { + struct { + /** blk3_data1 : RO; bitpos: [31:0]; default: 0; + * Store the second 32-bit of Block3. + */ + uint32_t blk3_data1:32; + }; + uint32_t val; +} efuse_rd_blk3_data1_reg_t; + +/** Type of rd_blk3_data2 register + * Register 2 of BLOCK3. + */ +typedef union { + struct { + /** blk3_data2 : RO; bitpos: [31:0]; default: 0; + * Store the third 32-bit of Block3. + */ + uint32_t blk3_data2:32; + }; + uint32_t val; +} efuse_rd_blk3_data2_reg_t; + +/** Type of rd_blk3_data3 register + * Register 3 of BLOCK3. + */ +typedef union { + struct { + /** blk3_data3 : RO; bitpos: [31:0]; default: 0; + * Store the fourth 32-bit of Block3. + */ + uint32_t blk3_data3:32; + }; + uint32_t val; +} efuse_rd_blk3_data3_reg_t; + +/** Type of rd_blk3_data4 register + * Register 4 of BLOCK3. + */ +typedef union { + struct { + /** blk3_data4 : RO; bitpos: [31:0]; default: 0; + * Store the fifth 32-bit of Block3. + */ + uint32_t blk3_data4:32; + }; + uint32_t val; +} efuse_rd_blk3_data4_reg_t; + +/** Type of rd_blk3_data5 register + * Register 5 of BLOCK3. + */ +typedef union { + struct { + /** blk3_data5 : RO; bitpos: [31:0]; default: 0; + * Store the sixth 32-bit of Block3. + */ + uint32_t blk3_data5:32; + }; + uint32_t val; +} efuse_rd_blk3_data5_reg_t; + +/** Type of rd_blk3_data6 register + * Register 6 of BLOCK3. + */ +typedef union { + struct { + /** blk3_data6 : RO; bitpos: [31:0]; default: 0; + * Store the seventh 32-bit of Block3. + */ + uint32_t blk3_data6:32; + }; + uint32_t val; +} efuse_rd_blk3_data6_reg_t; + +/** Type of rd_blk3_data7 register + * Register 7 of BLOCK3. + */ +typedef union { + struct { + /** blk3_data7 : RO; bitpos: [31:0]; default: 0; + * Store the eighth 32-bit of Block3. + */ + uint32_t blk3_data7:32; + }; + uint32_t val; +} efuse_rd_blk3_data7_reg_t; + + +/** Group: Report Register */ +/** Type of rd_repeat_err register + * Programming error record register 0 of BLOCK0. + */ +typedef union { + struct { + /** rd_dis_err : RO; bitpos: [1:0]; default: 0; + * If any bit in RD_DIS is 1, then it indicates a programming error. + */ + uint32_t rd_dis_err:2; + /** wdt_delay_sel_err : RO; bitpos: [3:2]; default: 0; + * If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error. + */ + uint32_t wdt_delay_sel_err:2; + /** dis_pad_jtag_err : RO; bitpos: [4]; default: 0; + * If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error. + */ + uint32_t dis_pad_jtag_err:1; + /** dis_download_icache_err : RO; bitpos: [5]; default: 0; + * If any bit in this filed is 1, then it indicates a programming error. + */ + uint32_t dis_download_icache_err:1; + /** dis_download_manual_encrypt_err : RO; bitpos: [6]; default: 0; + * If any bit in DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming + * error. + */ + uint32_t dis_download_manual_encrypt_err:1; + /** spi_boot_encrypt_decrypt_cnt_err : RO; bitpos: [9:7]; default: 0; + * If any bit in SPI_BOOT_ENCRYPT_DECRYPT_CNT is 1, then it indicates a programming + * error. + */ + uint32_t spi_boot_encrypt_decrypt_cnt_err:3; + /** xts_key_length_256_err : RO; bitpos: [10]; default: 0; + * If any bit in XTS_KEY_LENGTH_256 is 1, then it indicates a programming error. + */ + uint32_t xts_key_length_256_err:1; + /** uart_print_control_err : RO; bitpos: [12:11]; default: 0; + * If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error. + */ + uint32_t uart_print_control_err:2; + /** force_send_resume_err : RO; bitpos: [13]; default: 0; + * If any bit in FORCE_SEND_RESUME is 1, then it indicates a programming error. + */ + uint32_t force_send_resume_err:1; + /** dis_download_mode_err : RO; bitpos: [14]; default: 0; + * If any bit in this filed is 1, then it indicates a programming error. + */ + uint32_t dis_download_mode_err:1; + /** dis_direct_boot_err : RO; bitpos: [15]; default: 0; + * If any bit in this filed is 1, then it indicates a programming error. + */ + uint32_t dis_direct_boot_err:1; + /** enable_security_download_err : RO; bitpos: [16]; default: 0; + * If any bit in this filed is 1, then it indicates a programming error. + */ + uint32_t enable_security_download_err:1; + /** flash_tpuw_err : RO; bitpos: [20:17]; default: 0; + * If any bit in this filed is 1, then it indicates a programming error. + */ + uint32_t flash_tpuw_err:4; + /** secure_boot_en_err : RO; bitpos: [21]; default: 0; + * If any bit in this filed is 1, then it indicates a programming error. + */ + uint32_t secure_boot_en_err:1; + /** rpt4_reserved_err : RO; bitpos: [31:22]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved_err:10; + }; + uint32_t val; +} efuse_rd_repeat_err_reg_t; + +/** Type of rd_rs_err register + * Programming error record register 0 of BLOCK1-10. + */ +typedef union { + struct { + /** blk1_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes in block1. + */ + uint32_t blk1_err_num:3; + /** blk1_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of block1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t blk1_fail:1; + /** blk2_err_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes in block2. + */ + uint32_t blk2_err_num:3; + /** blk2_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of block2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t blk2_fail:1; + /** blk3_err_num : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes in block3. + */ + uint32_t blk3_err_num:3; + /** blk3_fail : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the block3 data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ + uint32_t blk3_fail:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} efuse_rd_rs_err_reg_t; + + +/** Group: Configuration Register */ +/** Type of clk register + * eFuse clcok configuration register. + */ +typedef union { + struct { + /** efuse_mem_force_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ + uint32_t efuse_mem_force_pd:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ + uint32_t mem_clk_force_on:1; + /** efuse_mem_force_pu : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ + uint32_t efuse_mem_force_pu:1; + uint32_t reserved_3:13; + /** clk_en : R/W; bitpos: [16]; default: 0; + * Set this bit and force to enable clock signal of eFuse memory. + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} efuse_clk_reg_t; + +/** Type of conf register + * eFuse operation mode configuraiton register + */ +typedef union { + struct { + /** op_code : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: Operate programming command 0x5AA5: Operate read command. + */ + uint32_t op_code:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} efuse_conf_reg_t; + +/** Type of cmd register + * eFuse command register. + */ +typedef union { + struct { + /** read_cmd : R/W/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + uint32_t read_cmd:1; + /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + uint32_t pgm_cmd:1; + /** blk_num : R/W; bitpos: [3:2]; default: 0; + * The serial number of the block to be programmed. Value 0-3 corresponds to block + * number 0-3, respectively. + */ + uint32_t blk_num:2; + uint32_t reserved_4:28; + }; + uint32_t val; +} efuse_cmd_reg_t; + +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ +typedef union { + struct { + /** dac_clk_div : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming voltage. + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + uint32_t dac_clk_pad_sel:1; + /** dac_num : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + uint32_t dac_num:8; + /** oe_clr : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + uint32_t oe_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ +typedef union { + struct { + /** thr_a : R/W; bitpos: [7:0]; default: 1; + * Configures hold time for efuse read. + */ + uint32_t thr_a:8; + /** trd : R/W; bitpos: [15:8]; default: 2; + * Configures pulse time for efuse read. + */ + uint32_t trd:8; + /** tsur_a : R/W; bitpos: [23:16]; default: 1; + * Configures setup time for efuse read. + */ + uint32_t tsur_a:8; + /** read_init_num : R/W; bitpos: [31:24]; default: 18; + * Configures the initial read time of eFuse. + */ + uint32_t read_init_num:8; + }; + uint32_t val; +} efuse_rd_tim_conf_reg_t; + +/** Type of wr_tim_conf0 register + * Configurarion register 0 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** thp_a : R/W; bitpos: [7:0]; default: 1; + * Configures hold time for efuse program. + */ + uint32_t thp_a:8; + /** tpgm_inactive : R/W; bitpos: [15:8]; default: 1; + * Configures pulse time for burning '0' bit. + */ + uint32_t tpgm_inactive:8; + /** tpgm : R/W; bitpos: [31:16]; default: 200; + * Configures pulse time for burning '1' bit. + */ + uint32_t tpgm:16; + }; + uint32_t val; +} efuse_wr_tim_conf0_reg_t; + +/** Type of wr_tim_conf1 register + * Configurarion register 1 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** tsup_a : R/W; bitpos: [7:0]; default: 1; + * Configures setup time for efuse program. + */ + uint32_t tsup_a:8; + /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288; + * Configures the power up time for VDDQ. + */ + uint32_t pwr_on_num:16; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_wr_tim_conf1_reg_t; + +/** Type of wr_tim_conf2 register + * Configurarion register 2 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ + uint32_t pwr_off_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} efuse_wr_tim_conf2_reg_t; + + +/** Group: Status Register */ +/** Type of status register + * eFuse status register. + */ +typedef union { + struct { + /** state : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ + uint32_t state:4; + /** otp_load_sw : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ + uint32_t otp_load_sw:1; + /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ + uint32_t otp_vddq_c_sync2:1; + /** otp_strobe_sw : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ + uint32_t otp_strobe_sw:1; + /** otp_csb_sw : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ + uint32_t otp_csb_sw:1; + /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ + uint32_t otp_pgenb_sw:1; + /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ + uint32_t otp_vddq_is_sw:1; + /** blk0_valid_bit_cnt : RO; bitpos: [15:10]; default: 0; + * Record the number of bit '1' in BLOCK0. + */ + uint32_t blk0_valid_bit_cnt:6; + uint32_t reserved_16:16; + }; + uint32_t val; +} efuse_status_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * eFuse raw interrupt register. + */ +typedef union { + struct { + /** read_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ + uint32_t read_done_int_raw:1; + /** pgm_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_raw_reg_t; + +/** Type of int_st register + * eFuse interrupt status register. + */ +typedef union { + struct { + /** read_done_int_st : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ + uint32_t read_done_int_st:1; + /** pgm_done_int_st : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_st_reg_t; + +/** Type of int_ena register + * eFuse interrupt enable register. + */ +typedef union { + struct { + /** read_done_int_ena : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ + uint32_t read_done_int_ena:1; + /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_ena_reg_t; + +/** Type of int_clr register + * eFuse interrupt clear register. + */ +typedef union { + struct { + /** read_done_int_clr : WT; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ + uint32_t read_done_int_clr:1; + /** pgm_done_int_clr : WT; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_clr_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * eFuse version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 34636176; + * Stores eFuse version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} efuse_date_reg_t; + + +typedef struct { + volatile efuse_pgm_data0_reg_t pgm_data0; + volatile efuse_pgm_data1_reg_t pgm_data1; + volatile efuse_pgm_data2_reg_t pgm_data2; + volatile efuse_pgm_data3_reg_t pgm_data3; + volatile efuse_pgm_data4_reg_t pgm_data4; + volatile efuse_pgm_data5_reg_t pgm_data5; + volatile efuse_pgm_data6_reg_t pgm_data6; + volatile efuse_pgm_data7_reg_t pgm_data7; + volatile efuse_pgm_check_value0_reg_t pgm_check_value0; + volatile efuse_pgm_check_value1_reg_t pgm_check_value1; + volatile efuse_pgm_check_value2_reg_t pgm_check_value2; + volatile efuse_rd_wr_dis_reg_t rd_wr_dis; + volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; + volatile efuse_rd_blk1_data0_reg_t rd_blk1_data0; + volatile efuse_rd_blk1_data1_reg_t rd_blk1_data1; + volatile efuse_rd_blk1_data2_reg_t rd_blk1_data2; + volatile efuse_rd_blk2_data0_reg_t rd_blk2_data0; + volatile efuse_rd_blk2_data1_reg_t rd_blk2_data1; + volatile efuse_rd_blk2_data2_reg_t rd_blk2_data2; + volatile efuse_rd_blk2_data3_reg_t rd_blk2_data3; + volatile efuse_rd_blk2_data4_reg_t rd_blk2_data4; + volatile efuse_rd_blk2_data5_reg_t rd_blk2_data5; + volatile efuse_rd_blk2_data6_reg_t rd_blk2_data6; + volatile efuse_rd_blk2_data7_reg_t rd_blk2_data7; + volatile efuse_rd_blk3_data0_reg_t rd_blk3_data0; + volatile efuse_rd_blk3_data1_reg_t rd_blk3_data1; + volatile efuse_rd_blk3_data2_reg_t rd_blk3_data2; + volatile efuse_rd_blk3_data3_reg_t rd_blk3_data3; + volatile efuse_rd_blk3_data4_reg_t rd_blk3_data4; + volatile efuse_rd_blk3_data5_reg_t rd_blk3_data5; + volatile efuse_rd_blk3_data6_reg_t rd_blk3_data6; + volatile efuse_rd_blk3_data7_reg_t rd_blk3_data7; + volatile efuse_rd_repeat_err_reg_t rd_repeat_err; + volatile efuse_rd_rs_err_reg_t rd_rs_err; + volatile efuse_clk_reg_t clk; + volatile efuse_conf_reg_t conf; + volatile efuse_status_reg_t status; + volatile efuse_cmd_reg_t cmd; + volatile efuse_int_raw_reg_t int_raw; + volatile efuse_int_st_reg_t int_st; + uint32_t reserved_0a0[24]; + volatile efuse_int_ena_reg_t int_ena; + volatile efuse_int_clr_reg_t int_clr; + volatile efuse_dac_conf_reg_t dac_conf; + volatile efuse_rd_tim_conf_reg_t rd_tim_conf; + volatile efuse_wr_tim_conf0_reg_t wr_tim_conf0; + volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; + volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; + uint32_t reserved_11c[56]; + volatile efuse_date_reg_t date; } efuse_dev_t; -extern efuse_dev_t EFUSE; + + +#ifndef __cplusplus +_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); +#endif + #ifdef __cplusplus } #endif - - - -#endif /*_SOC_EFUSE_STRUCT_H_ */ diff --git a/components/soc/esp8684/include/soc/extmem_reg.h b/components/soc/esp8684/include/soc/extmem_reg.h index 6f3236c4fe..a58a7927d2 100644 --- a/components/soc/esp8684/include/soc/extmem_reg.h +++ b/components/soc/esp8684/include/soc/extmem_reg.h @@ -1,661 +1,850 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_EXTMEM_REG_H_ -#define _SOC_EXTMEM_REG_H_ - +#pragma once +#include +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -#define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0) -/* EXTMEM_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to activate the data cache. 0: disable, 1: enable.*/ +/** EXTMEM_ICACHE_CTRL_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0) +/** EXTMEM_ICACHE_ENABLE : R/W; bitpos: [0]; default: 0; + * The bit is used to activate the data cache. 0: disable, 1: enable + */ #define EXTMEM_ICACHE_ENABLE (BIT(0)) -#define EXTMEM_ICACHE_ENABLE_M (BIT(0)) -#define EXTMEM_ICACHE_ENABLE_V 0x1 +#define EXTMEM_ICACHE_ENABLE_M (EXTMEM_ICACHE_ENABLE_V << EXTMEM_ICACHE_ENABLE_S) +#define EXTMEM_ICACHE_ENABLE_V 0x00000001U #define EXTMEM_ICACHE_ENABLE_S 0 -#define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x4) -/* EXTMEM_ICACHE_SHUT_DBUS : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: The bit is used to disable core1 ibus, 0: enable, 1: disable.*/ -#define EXTMEM_ICACHE_SHUT_DBUS (BIT(1)) -#define EXTMEM_ICACHE_SHUT_DBUS_M (BIT(1)) -#define EXTMEM_ICACHE_SHUT_DBUS_V 0x1 -#define EXTMEM_ICACHE_SHUT_DBUS_S 1 -/* EXTMEM_ICACHE_SHUT_IBUS : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to disable core0 ibus, 0: enable, 1: disable.*/ +/** EXTMEM_ICACHE_CTRL1_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x4) +/** EXTMEM_ICACHE_SHUT_IBUS : R/W; bitpos: [0]; default: 1; + * The bit is used to disable core0 ibus, 0: enable, 1: disable + */ #define EXTMEM_ICACHE_SHUT_IBUS (BIT(0)) -#define EXTMEM_ICACHE_SHUT_IBUS_M (BIT(0)) -#define EXTMEM_ICACHE_SHUT_IBUS_V 0x1 +#define EXTMEM_ICACHE_SHUT_IBUS_M (EXTMEM_ICACHE_SHUT_IBUS_V << EXTMEM_ICACHE_SHUT_IBUS_S) +#define EXTMEM_ICACHE_SHUT_IBUS_V 0x00000001U #define EXTMEM_ICACHE_SHUT_IBUS_S 0 +/** EXTMEM_ICACHE_SHUT_DBUS : R/W; bitpos: [1]; default: 1; + * The bit is used to disable core1 ibus, 0: enable, 1: disable + */ +#define EXTMEM_ICACHE_SHUT_DBUS (BIT(1)) +#define EXTMEM_ICACHE_SHUT_DBUS_M (EXTMEM_ICACHE_SHUT_DBUS_V << EXTMEM_ICACHE_SHUT_DBUS_S) +#define EXTMEM_ICACHE_SHUT_DBUS_V 0x00000001U +#define EXTMEM_ICACHE_SHUT_DBUS_S 1 -#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x8) -/* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up.*/ -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU (BIT(2)) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M (BIT(2)) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V 0x1 -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S 2 -/* EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power d -own.*/ -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD (BIT(1)) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M (BIT(1)) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V 0x1 -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S 1 -/* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to close clock gating of icache tag memory. 1: close gating, 0: - open clock gating..*/ +/** EXTMEM_ICACHE_TAG_POWER_CTRL_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x8) +/** EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1; + * The bit is used to close clock gating of icache tag memory. 1: close gating, 0: + * open clock gating. + */ #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON (BIT(0)) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M (BIT(0)) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x1 +#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M (EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V << EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S) +#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x00000001U #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S 0 +/** EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; + * The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down + */ +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD (BIT(1)) +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M (EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V << EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S) +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V 0x00000001U +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S 1 +/** EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; + * The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up + */ +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU (BIT(2)) +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M (EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V << EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S) +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V 0x00000001U +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S 2 -#define EXTMEM_ICACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28) -/* EXTMEM_ICACHE_SYNC_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to indicate invalidate operation is finished..*/ -#define EXTMEM_ICACHE_SYNC_DONE (BIT(1)) -#define EXTMEM_ICACHE_SYNC_DONE_M (BIT(1)) -#define EXTMEM_ICACHE_SYNC_DONE_V 0x1 -#define EXTMEM_ICACHE_SYNC_DONE_S 1 -/* EXTMEM_ICACHE_INVALIDATE_ENA : R/W/SS ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a -fter invalidate operation done..*/ +/** EXTMEM_ICACHE_SYNC_CTRL_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_ICACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28) +/** EXTMEM_ICACHE_INVALIDATE_ENA : R/W/SS; bitpos: [0]; default: 1; + * The bit is used to enable invalidate operation. It will be cleared by hardware + * after invalidate operation done. + */ #define EXTMEM_ICACHE_INVALIDATE_ENA (BIT(0)) -#define EXTMEM_ICACHE_INVALIDATE_ENA_M (BIT(0)) -#define EXTMEM_ICACHE_INVALIDATE_ENA_V 0x1 +#define EXTMEM_ICACHE_INVALIDATE_ENA_M (EXTMEM_ICACHE_INVALIDATE_ENA_V << EXTMEM_ICACHE_INVALIDATE_ENA_S) +#define EXTMEM_ICACHE_INVALIDATE_ENA_V 0x00000001U #define EXTMEM_ICACHE_INVALIDATE_ENA_S 0 +/** EXTMEM_ICACHE_SYNC_DONE : RO; bitpos: [1]; default: 0; + * The bit is used to indicate invalidate operation is finished. + */ +#define EXTMEM_ICACHE_SYNC_DONE (BIT(1)) +#define EXTMEM_ICACHE_SYNC_DONE_M (EXTMEM_ICACHE_SYNC_DONE_V << EXTMEM_ICACHE_SYNC_DONE_S) +#define EXTMEM_ICACHE_SYNC_DONE_V 0x00000001U +#define EXTMEM_ICACHE_SYNC_DONE_S 1 -#define EXTMEM_ICACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x2C) -/* EXTMEM_ICACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address for clean operations. I -t should be combined with ICACHE_SYNC_SIZE_REG..*/ -#define EXTMEM_ICACHE_SYNC_ADDR 0xFFFFFFFF -#define EXTMEM_ICACHE_SYNC_ADDR_M ((EXTMEM_ICACHE_SYNC_ADDR_V)<<(EXTMEM_ICACHE_SYNC_ADDR_S)) -#define EXTMEM_ICACHE_SYNC_ADDR_V 0xFFFFFFFF +/** EXTMEM_ICACHE_SYNC_ADDR_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_ICACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x2c) +/** EXTMEM_ICACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0; + * The bits are used to configure the start virtual address for clean operations. It + * should be combined with ICACHE_SYNC_SIZE_REG. + */ +#define EXTMEM_ICACHE_SYNC_ADDR 0xFFFFFFFFU +#define EXTMEM_ICACHE_SYNC_ADDR_M (EXTMEM_ICACHE_SYNC_ADDR_V << EXTMEM_ICACHE_SYNC_ADDR_S) +#define EXTMEM_ICACHE_SYNC_ADDR_V 0xFFFFFFFFU #define EXTMEM_ICACHE_SYNC_ADDR_S 0 -#define EXTMEM_ICACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x30) -/* EXTMEM_ICACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */ -/*description: The bits are used to configure the length for sync operations. The bits are the -counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG..*/ -#define EXTMEM_ICACHE_SYNC_SIZE 0x007FFFFF -#define EXTMEM_ICACHE_SYNC_SIZE_M ((EXTMEM_ICACHE_SYNC_SIZE_V)<<(EXTMEM_ICACHE_SYNC_SIZE_S)) -#define EXTMEM_ICACHE_SYNC_SIZE_V 0x7FFFFF +/** EXTMEM_ICACHE_SYNC_SIZE_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_ICACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x30) +/** EXTMEM_ICACHE_SYNC_SIZE : R/W; bitpos: [22:0]; default: 0; + * The bits are used to configure the length for sync operations. The bits are the + * counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG. + */ +#define EXTMEM_ICACHE_SYNC_SIZE 0x007FFFFFU +#define EXTMEM_ICACHE_SYNC_SIZE_M (EXTMEM_ICACHE_SYNC_SIZE_V << EXTMEM_ICACHE_SYNC_SIZE_S) +#define EXTMEM_ICACHE_SYNC_SIZE_V 0x007FFFFFU #define EXTMEM_ICACHE_SYNC_SIZE_S 0 -#define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x54) -/* EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h42000000 ; */ -/*description: The bits are used to configure the start virtual address of ibus to access flash -. The register is used to give constraints to ibus access counter..*/ -#define EXTMEM_IBUS_TO_FLASH_START_VADDR 0xFFFFFFFF -#define EXTMEM_IBUS_TO_FLASH_START_VADDR_M ((EXTMEM_IBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_START_VADDR_S)) -#define EXTMEM_IBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF +/** EXTMEM_IBUS_TO_FLASH_START_VADDR_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x54) +/** EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W; bitpos: [31:0]; default: 1107296256; + * The bits are used to configure the start virtual address of ibus to access flash. + * The register is used to give constraints to ibus access counter. + */ +#define EXTMEM_IBUS_TO_FLASH_START_VADDR 0xFFFFFFFFU +#define EXTMEM_IBUS_TO_FLASH_START_VADDR_M (EXTMEM_IBUS_TO_FLASH_START_VADDR_V << EXTMEM_IBUS_TO_FLASH_START_VADDR_S) +#define EXTMEM_IBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFFU #define EXTMEM_IBUS_TO_FLASH_START_VADDR_S 0 -#define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x58) -/* EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h423fffff ; */ -/*description: The bits are used to configure the end virtual address of ibus to access flash. -The register is used to give constraints to ibus access counter..*/ -#define EXTMEM_IBUS_TO_FLASH_END_VADDR 0xFFFFFFFF -#define EXTMEM_IBUS_TO_FLASH_END_VADDR_M ((EXTMEM_IBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_END_VADDR_S)) -#define EXTMEM_IBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF +/** EXTMEM_IBUS_TO_FLASH_END_VADDR_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x58) +/** EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W; bitpos: [31:0]; default: 1111490559; + * The bits are used to configure the end virtual address of ibus to access flash. The + * register is used to give constraints to ibus access counter. + */ +#define EXTMEM_IBUS_TO_FLASH_END_VADDR 0xFFFFFFFFU +#define EXTMEM_IBUS_TO_FLASH_END_VADDR_M (EXTMEM_IBUS_TO_FLASH_END_VADDR_V << EXTMEM_IBUS_TO_FLASH_END_VADDR_S) +#define EXTMEM_IBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFFU #define EXTMEM_IBUS_TO_FLASH_END_VADDR_S 0 -#define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x5C) -/* EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3c000000 ; */ -/*description: The bits are used to configure the start virtual address of dbus to access flash -. The register is used to give constraints to dbus access counter..*/ -#define EXTMEM_DBUS_TO_FLASH_START_VADDR 0xFFFFFFFF -#define EXTMEM_DBUS_TO_FLASH_START_VADDR_M ((EXTMEM_DBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_START_VADDR_S)) -#define EXTMEM_DBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF +/** EXTMEM_DBUS_TO_FLASH_START_VADDR_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x5c) +/** EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W; bitpos: [31:0]; default: 1006632960; + * The bits are used to configure the start virtual address of dbus to access flash. + * The register is used to give constraints to dbus access counter. + */ +#define EXTMEM_DBUS_TO_FLASH_START_VADDR 0xFFFFFFFFU +#define EXTMEM_DBUS_TO_FLASH_START_VADDR_M (EXTMEM_DBUS_TO_FLASH_START_VADDR_V << EXTMEM_DBUS_TO_FLASH_START_VADDR_S) +#define EXTMEM_DBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFFU #define EXTMEM_DBUS_TO_FLASH_START_VADDR_S 0 -#define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x60) -/* EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3c3fffff ; */ -/*description: The bits are used to configure the end virtual address of dbus to access flash. -The register is used to give constraints to dbus access counter..*/ -#define EXTMEM_DBUS_TO_FLASH_END_VADDR 0xFFFFFFFF -#define EXTMEM_DBUS_TO_FLASH_END_VADDR_M ((EXTMEM_DBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_END_VADDR_S)) -#define EXTMEM_DBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF +/** EXTMEM_DBUS_TO_FLASH_END_VADDR_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x60) +/** EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W; bitpos: [31:0]; default: 1010827263; + * The bits are used to configure the end virtual address of dbus to access flash. The + * register is used to give constraints to dbus access counter. + */ +#define EXTMEM_DBUS_TO_FLASH_END_VADDR 0xFFFFFFFFU +#define EXTMEM_DBUS_TO_FLASH_END_VADDR_M (EXTMEM_DBUS_TO_FLASH_END_VADDR_V << EXTMEM_DBUS_TO_FLASH_END_VADDR_S) +#define EXTMEM_DBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFFU #define EXTMEM_DBUS_TO_FLASH_END_VADDR_S 0 -#define EXTMEM_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0x64) -/* EXTMEM_DBUS_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to clear dbus counter..*/ -#define EXTMEM_DBUS_ACS_CNT_CLR (BIT(1)) -#define EXTMEM_DBUS_ACS_CNT_CLR_M (BIT(1)) -#define EXTMEM_DBUS_ACS_CNT_CLR_V 0x1 -#define EXTMEM_DBUS_ACS_CNT_CLR_S 1 -/* EXTMEM_IBUS_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to clear ibus counter..*/ +/** EXTMEM_CACHE_ACS_CNT_CLR_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0x64) +/** EXTMEM_IBUS_ACS_CNT_CLR : WOD; bitpos: [0]; default: 0; + * The bit is used to clear ibus counter. + */ #define EXTMEM_IBUS_ACS_CNT_CLR (BIT(0)) -#define EXTMEM_IBUS_ACS_CNT_CLR_M (BIT(0)) -#define EXTMEM_IBUS_ACS_CNT_CLR_V 0x1 +#define EXTMEM_IBUS_ACS_CNT_CLR_M (EXTMEM_IBUS_ACS_CNT_CLR_V << EXTMEM_IBUS_ACS_CNT_CLR_S) +#define EXTMEM_IBUS_ACS_CNT_CLR_V 0x00000001U #define EXTMEM_IBUS_ACS_CNT_CLR_S 0 +/** EXTMEM_DBUS_ACS_CNT_CLR : WOD; bitpos: [1]; default: 0; + * The bit is used to clear dbus counter. + */ +#define EXTMEM_DBUS_ACS_CNT_CLR (BIT(1)) +#define EXTMEM_DBUS_ACS_CNT_CLR_M (EXTMEM_DBUS_ACS_CNT_CLR_V << EXTMEM_DBUS_ACS_CNT_CLR_S) +#define EXTMEM_DBUS_ACS_CNT_CLR_V 0x00000001U +#define EXTMEM_DBUS_ACS_CNT_CLR_S 1 -#define EXTMEM_CACHE_ILG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x78) -/* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by dbus counter overflow..*/ -#define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(8)) -#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M (BIT(8)) -#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V 0x1 -#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S 8 -/* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by ibus counter overflow..*/ -#define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(7)) -#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M (BIT(7)) -#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V 0x1 -#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S 7 -/* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by mmu entry fault..*/ -#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(5)) -#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M (BIT(5)) -#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V 0x1 -#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S 5 -/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by preload configurations fault..*/ -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x1 -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S 1 -/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by sync configurations fault..*/ +/** EXTMEM_CACHE_ILG_INT_ENA_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CACHE_ILG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x78) +/** EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W; bitpos: [0]; default: 0; + * The bit is used to enable interrupt by sync configurations fault. + */ #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA (BIT(0)) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M (BIT(0)) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V 0x1 +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M (EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V << EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S) +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V 0x00000001U #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S 0 +/** EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W; bitpos: [1]; default: 0; + * The bit is used to enable interrupt by preload configurations fault. + */ +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M (EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V << EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S) +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x00000001U +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S 1 +/** EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W; bitpos: [5]; default: 0; + * The bit is used to enable interrupt by mmu entry fault. + */ +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(5)) +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M (EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V << EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S) +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V 0x00000001U +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S 5 +/** EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W; bitpos: [7]; default: 0; + * The bit is used to enable interrupt by ibus counter overflow. + */ +#define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(7)) +#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M (EXTMEM_IBUS_CNT_OVF_INT_ENA_V << EXTMEM_IBUS_CNT_OVF_INT_ENA_S) +#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V 0x00000001U +#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S 7 +/** EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W; bitpos: [8]; default: 0; + * The bit is used to enable interrupt by dbus counter overflow. + */ +#define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(8)) +#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M (EXTMEM_DBUS_CNT_OVF_INT_ENA_V << EXTMEM_DBUS_CNT_OVF_INT_ENA_S) +#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V 0x00000001U +#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S 8 -#define EXTMEM_CACHE_ILG_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x7C) -/* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by dbus counter overflow..*/ -#define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(8)) -#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M (BIT(8)) -#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V 0x1 -#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S 8 -/* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by ibus counter overflow..*/ -#define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(7)) -#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M (BIT(7)) -#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x1 -#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 7 -/* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by mmu entry fault..*/ -#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR (BIT(5)) -#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M (BIT(5)) -#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V 0x1 -#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S 5 -/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by preload configurations fault..*/ -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x1 -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S 1 -/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by sync configurations fault..*/ +/** EXTMEM_CACHE_ILG_INT_CLR_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CACHE_ILG_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x7c) +/** EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD; bitpos: [0]; default: 0; + * The bit is used to clear interrupt by sync configurations fault. + */ #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR (BIT(0)) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M (BIT(0)) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V 0x1 +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M (EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V << EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S) +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V 0x00000001U #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S 0 +/** EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD; bitpos: [1]; default: 0; + * The bit is used to clear interrupt by preload configurations fault. + */ +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M (EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V << EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S) +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x00000001U +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S 1 +/** EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD; bitpos: [5]; default: 0; + * The bit is used to clear interrupt by mmu entry fault. + */ +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR (BIT(5)) +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M (EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V << EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S) +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V 0x00000001U +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S 5 +/** EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD; bitpos: [7]; default: 0; + * The bit is used to clear interrupt by ibus counter overflow. + */ +#define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(7)) +#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M (EXTMEM_IBUS_CNT_OVF_INT_CLR_V << EXTMEM_IBUS_CNT_OVF_INT_CLR_S) +#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x00000001U +#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 7 +/** EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD; bitpos: [8]; default: 0; + * The bit is used to clear interrupt by dbus counter overflow. + */ +#define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(8)) +#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M (EXTMEM_DBUS_CNT_OVF_INT_CLR_V << EXTMEM_DBUS_CNT_OVF_INT_CLR_S) +#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V 0x00000001U +#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S 8 -#define EXTMEM_CACHE_ILG_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x80) -/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by dbus access flash miss counter overflow -..*/ -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST (BIT(10)) -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M (BIT(10)) -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V 0x1 -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S 10 -/* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by dbus access flash/spiram counter overfl -ow..*/ -#define EXTMEM_DBUS_ACS_CNT_OVF_ST (BIT(9)) -#define EXTMEM_DBUS_ACS_CNT_OVF_ST_M (BIT(9)) -#define EXTMEM_DBUS_ACS_CNT_OVF_ST_V 0x1 -#define EXTMEM_DBUS_ACS_CNT_OVF_ST_S 9 -/* EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by ibus access flash/spiram miss counter o -verflow..*/ -#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST (BIT(8)) -#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M (BIT(8)) -#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V 0x1 -#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S 8 -/* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by ibus access flash/spiram counter overfl -ow..*/ -#define EXTMEM_IBUS_ACS_CNT_OVF_ST (BIT(7)) -#define EXTMEM_IBUS_ACS_CNT_OVF_ST_M (BIT(7)) -#define EXTMEM_IBUS_ACS_CNT_OVF_ST_V 0x1 -#define EXTMEM_IBUS_ACS_CNT_OVF_ST_S 7 -/* EXTMEM_MMU_ENTRY_FAULT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by mmu entry fault..*/ -#define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(5)) -#define EXTMEM_MMU_ENTRY_FAULT_ST_M (BIT(5)) -#define EXTMEM_MMU_ENTRY_FAULT_ST_V 0x1 -#define EXTMEM_MMU_ENTRY_FAULT_ST_S 5 -/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by preload configurations fault..*/ -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V 0x1 -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S 1 -/* EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by sync configurations fault..*/ +/** EXTMEM_CACHE_ILG_INT_ST_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CACHE_ILG_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x80) +/** EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO; bitpos: [0]; default: 0; + * The bit is used to indicate interrupt by sync configurations fault. + */ #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST (BIT(0)) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M (BIT(0)) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V 0x1 +#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M (EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V << EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S) +#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V 0x00000001U #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S 0 +/** EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO; bitpos: [1]; default: 0; + * The bit is used to indicate interrupt by preload configurations fault. + */ +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M (EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V << EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S) +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V 0x00000001U +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S 1 +/** EXTMEM_MMU_ENTRY_FAULT_ST : RO; bitpos: [5]; default: 0; + * The bit is used to indicate interrupt by mmu entry fault. + */ +#define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(5)) +#define EXTMEM_MMU_ENTRY_FAULT_ST_M (EXTMEM_MMU_ENTRY_FAULT_ST_V << EXTMEM_MMU_ENTRY_FAULT_ST_S) +#define EXTMEM_MMU_ENTRY_FAULT_ST_V 0x00000001U +#define EXTMEM_MMU_ENTRY_FAULT_ST_S 5 +/** EXTMEM_IBUS_ACS_CNT_OVF_ST : RO; bitpos: [7]; default: 0; + * The bit is used to indicate interrupt by ibus access flash/spiram counter overflow. + */ +#define EXTMEM_IBUS_ACS_CNT_OVF_ST (BIT(7)) +#define EXTMEM_IBUS_ACS_CNT_OVF_ST_M (EXTMEM_IBUS_ACS_CNT_OVF_ST_V << EXTMEM_IBUS_ACS_CNT_OVF_ST_S) +#define EXTMEM_IBUS_ACS_CNT_OVF_ST_V 0x00000001U +#define EXTMEM_IBUS_ACS_CNT_OVF_ST_S 7 +/** EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO; bitpos: [8]; default: 0; + * The bit is used to indicate interrupt by ibus access flash/spiram miss counter + * overflow. + */ +#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST (BIT(8)) +#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M (EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V << EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S) +#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V 0x00000001U +#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S 8 +/** EXTMEM_DBUS_ACS_CNT_OVF_ST : RO; bitpos: [9]; default: 0; + * The bit is used to indicate interrupt by dbus access flash/spiram counter overflow. + */ +#define EXTMEM_DBUS_ACS_CNT_OVF_ST (BIT(9)) +#define EXTMEM_DBUS_ACS_CNT_OVF_ST_M (EXTMEM_DBUS_ACS_CNT_OVF_ST_V << EXTMEM_DBUS_ACS_CNT_OVF_ST_S) +#define EXTMEM_DBUS_ACS_CNT_OVF_ST_V 0x00000001U +#define EXTMEM_DBUS_ACS_CNT_OVF_ST_S 9 +/** EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO; bitpos: [10]; default: 0; + * The bit is used to indicate interrupt by dbus access flash miss counter overflow. + */ +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST (BIT(10)) +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M (EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V << EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S) +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V 0x00000001U +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S 10 -#define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x84) -/* EXTMEM_CORE0_DBUS_WR_IC_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by dbus trying to write icache.*/ -#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA (BIT(5)) -#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_M (BIT(5)) -#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_V 0x1 -#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_S 5 -/* EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by authentication fail..*/ -#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA (BIT(4)) -#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M (BIT(4)) -#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V 0x1 -#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S 4 -/* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by cpu access icache while the corresponding - dbus is disabled which include speculative access..*/ -#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA (BIT(3)) -#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_M (BIT(3)) -#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_V 0x1 -#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_S 3 -/* EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by authentication fail..*/ -#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA (BIT(2)) -#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M (BIT(2)) -#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V 0x1 -#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S 2 -/* EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by ibus trying to write icache.*/ -#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA (BIT(1)) -#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M (BIT(1)) -#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V 0x1 -#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S 1 -/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by cpu access icache while the corresponding - ibus is disabled which include speculative access..*/ +/** EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x84) +/** EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W; bitpos: [0]; default: 0; + * The bit is used to enable interrupt by cpu access icache while the corresponding + * ibus is disabled which include speculative access. + */ #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA (BIT(0)) -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(0)) -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V 0x1 +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M (EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V << EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S) +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V 0x00000001U #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S 0 +/** EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W; bitpos: [1]; default: 0; + * The bit is used to enable interrupt by ibus trying to write icache + */ +#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA (BIT(1)) +#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M (EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V << EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S) +#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V 0x00000001U +#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S 1 +/** EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W; bitpos: [2]; default: 0; + * The bit is used to enable interrupt by authentication fail. + */ +#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA (BIT(2)) +#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M (EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V << EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S) +#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V 0x00000001U +#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S 2 +/** EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA : R/W; bitpos: [3]; default: 0; + * The bit is used to enable interrupt by cpu access icache while the corresponding + * dbus is disabled which include speculative access. + */ +#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA (BIT(3)) +#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_M (EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_V << EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_S) +#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_V 0x00000001U +#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_S 3 +/** EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt by authentication fail. + */ +#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA (BIT(4)) +#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M (EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V << EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S) +#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V 0x00000001U +#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S 4 +/** EXTMEM_CORE0_DBUS_WR_IC_INT_ENA : R/W; bitpos: [5]; default: 0; + * The bit is used to enable interrupt by dbus trying to write icache + */ +#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA (BIT(5)) +#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_M (EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_V << EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_S) +#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_V 0x00000001U +#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_S 5 -#define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x88) -/* EXTMEM_CORE0_DBUS_WR_IC_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by dbus trying to write icache.*/ -#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR (BIT(5)) -#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_M (BIT(5)) -#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_V 0x1 -#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_S 5 -/* EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by authentication fail..*/ -#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR (BIT(4)) -#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M (BIT(4)) -#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V 0x1 -#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S 4 -/* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by cpu access icache while the corresponding -dbus is disabled or icache is disabled which include speculative access..*/ -#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR (BIT(3)) -#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_M (BIT(3)) -#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_V 0x1 -#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_S 3 -/* EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by authentication fail..*/ -#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR (BIT(2)) -#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M (BIT(2)) -#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V 0x1 -#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S 2 -/* EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by ibus trying to write icache.*/ -#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR (BIT(1)) -#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M (BIT(1)) -#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V 0x1 -#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S 1 -/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by cpu access icache while the corresponding -ibus is disabled or icache is disabled which include speculative access..*/ +/** EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x88) +/** EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD; bitpos: [0]; default: 0; + * The bit is used to clear interrupt by cpu access icache while the corresponding + * ibus is disabled or icache is disabled which include speculative access. + */ #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M (BIT(0)) -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V 0x1 +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M (EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V << EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S) +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V 0x00000001U #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S 0 +/** EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD; bitpos: [1]; default: 0; + * The bit is used to clear interrupt by ibus trying to write icache + */ +#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR (BIT(1)) +#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M (EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V << EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S) +#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V 0x00000001U +#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S 1 +/** EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD; bitpos: [2]; default: 0; + * The bit is used to clear interrupt by authentication fail. + */ +#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR (BIT(2)) +#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M (EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V << EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S) +#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V 0x00000001U +#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S 2 +/** EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR : WOD; bitpos: [3]; default: 0; + * The bit is used to clear interrupt by cpu access icache while the corresponding + * dbus is disabled or icache is disabled which include speculative access. + */ +#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR (BIT(3)) +#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_M (EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_V << EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_S) +#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_V 0x00000001U +#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_S 3 +/** EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD; bitpos: [4]; default: 0; + * The bit is used to clear interrupt by authentication fail. + */ +#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR (BIT(4)) +#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M (EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V << EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S) +#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V 0x00000001U +#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S 4 +/** EXTMEM_CORE0_DBUS_WR_IC_INT_CLR : WOD; bitpos: [5]; default: 0; + * The bit is used to clear interrupt by dbus trying to write icache + */ +#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR (BIT(5)) +#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_M (EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_V << EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_S) +#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_V 0x00000001U +#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_S 5 -#define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x8C) -/* EXTMEM_CORE0_DBUS_WR_ICACHE_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by dbus trying to write icache.*/ -#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST (BIT(5)) -#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_M (BIT(5)) -#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_V 0x1 -#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_S 5 -/* EXTMEM_CORE0_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by authentication fail..*/ -#define EXTMEM_CORE0_DBUS_REJECT_ST (BIT(4)) -#define EXTMEM_CORE0_DBUS_REJECT_ST_M (BIT(4)) -#define EXTMEM_CORE0_DBUS_REJECT_ST_V 0x1 -#define EXTMEM_CORE0_DBUS_REJECT_ST_S 4 -/* EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by cpu access icache while the core0_dbus -is disabled or icache is disabled which include speculative access..*/ -#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST (BIT(3)) -#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_M (BIT(3)) -#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_V 0x1 -#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_S 3 -/* EXTMEM_CORE0_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by authentication fail..*/ -#define EXTMEM_CORE0_IBUS_REJECT_ST (BIT(2)) -#define EXTMEM_CORE0_IBUS_REJECT_ST_M (BIT(2)) -#define EXTMEM_CORE0_IBUS_REJECT_ST_V 0x1 -#define EXTMEM_CORE0_IBUS_REJECT_ST_S 2 -/* EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by ibus trying to write icache.*/ -#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST (BIT(1)) -#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M (BIT(1)) -#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V 0x1 -#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S 1 -/* EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by cpu access icache while the core0_ibus - is disabled or icache is disabled which include speculative access..*/ +/** EXTMEM_CORE0_ACS_CACHE_INT_ST_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x8c) +/** EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO; bitpos: [0]; default: 0; + * The bit is used to indicate interrupt by cpu access icache while the core0_ibus is + * disabled or icache is disabled which include speculative access. + */ #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST (BIT(0)) -#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M (BIT(0)) -#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V 0x1 +#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M (EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V << EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S) +#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V 0x00000001U #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S 0 +/** EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO; bitpos: [1]; default: 0; + * The bit is used to indicate interrupt by ibus trying to write icache + */ +#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST (BIT(1)) +#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M (EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V << EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S) +#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V 0x00000001U +#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S 1 +/** EXTMEM_CORE0_IBUS_REJECT_ST : RO; bitpos: [2]; default: 0; + * The bit is used to indicate interrupt by authentication fail. + */ +#define EXTMEM_CORE0_IBUS_REJECT_ST (BIT(2)) +#define EXTMEM_CORE0_IBUS_REJECT_ST_M (EXTMEM_CORE0_IBUS_REJECT_ST_V << EXTMEM_CORE0_IBUS_REJECT_ST_S) +#define EXTMEM_CORE0_IBUS_REJECT_ST_V 0x00000001U +#define EXTMEM_CORE0_IBUS_REJECT_ST_S 2 +/** EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST : RO; bitpos: [3]; default: 0; + * The bit is used to indicate interrupt by cpu access icache while the core0_dbus is + * disabled or icache is disabled which include speculative access. + */ +#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST (BIT(3)) +#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_M (EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_V << EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_S) +#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_V 0x00000001U +#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_S 3 +/** EXTMEM_CORE0_DBUS_REJECT_ST : RO; bitpos: [4]; default: 0; + * The bit is used to indicate interrupt by authentication fail. + */ +#define EXTMEM_CORE0_DBUS_REJECT_ST (BIT(4)) +#define EXTMEM_CORE0_DBUS_REJECT_ST_M (EXTMEM_CORE0_DBUS_REJECT_ST_V << EXTMEM_CORE0_DBUS_REJECT_ST_S) +#define EXTMEM_CORE0_DBUS_REJECT_ST_V 0x00000001U +#define EXTMEM_CORE0_DBUS_REJECT_ST_S 4 +/** EXTMEM_CORE0_DBUS_WR_ICACHE_ST : RO; bitpos: [5]; default: 0; + * The bit is used to indicate interrupt by dbus trying to write icache + */ +#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST (BIT(5)) +#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_M (EXTMEM_CORE0_DBUS_WR_ICACHE_ST_V << EXTMEM_CORE0_DBUS_WR_ICACHE_ST_S) +#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_V 0x00000001U +#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_S 5 -#define EXTMEM_CORE0_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x90) -/* EXTMEM_CORE0_DBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to indicate the world of CPU access dbus when authentication fai -l. 0: WORLD0, 1: WORLD1.*/ -#define EXTMEM_CORE0_DBUS_WORLD (BIT(3)) -#define EXTMEM_CORE0_DBUS_WORLD_M (BIT(3)) -#define EXTMEM_CORE0_DBUS_WORLD_V 0x1 -#define EXTMEM_CORE0_DBUS_WORLD_S 3 -/* EXTMEM_CORE0_DBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: The bits are used to indicate the attribute of CPU access dbus when authenticati -on fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/ -#define EXTMEM_CORE0_DBUS_ATTR 0x00000007 -#define EXTMEM_CORE0_DBUS_ATTR_M ((EXTMEM_CORE0_DBUS_ATTR_V)<<(EXTMEM_CORE0_DBUS_ATTR_S)) -#define EXTMEM_CORE0_DBUS_ATTR_V 0x7 +/** EXTMEM_CORE0_DBUS_REJECT_ST_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CORE0_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x90) +/** EXTMEM_CORE0_DBUS_ATTR : RO; bitpos: [2:0]; default: 0; + * The bits are used to indicate the attribute of CPU access dbus when authentication + * fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + */ +#define EXTMEM_CORE0_DBUS_ATTR 0x00000007U +#define EXTMEM_CORE0_DBUS_ATTR_M (EXTMEM_CORE0_DBUS_ATTR_V << EXTMEM_CORE0_DBUS_ATTR_S) +#define EXTMEM_CORE0_DBUS_ATTR_V 0x00000007U #define EXTMEM_CORE0_DBUS_ATTR_S 0 +/** EXTMEM_CORE0_DBUS_WORLD : RO; bitpos: [3]; default: 0; + * The bit is used to indicate the world of CPU access dbus when authentication fail. + * 0: WORLD0, 1: WORLD1 + */ +#define EXTMEM_CORE0_DBUS_WORLD (BIT(3)) +#define EXTMEM_CORE0_DBUS_WORLD_M (EXTMEM_CORE0_DBUS_WORLD_V << EXTMEM_CORE0_DBUS_WORLD_S) +#define EXTMEM_CORE0_DBUS_WORLD_V 0x00000001U +#define EXTMEM_CORE0_DBUS_WORLD_S 3 -#define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x94) -/* EXTMEM_CORE0_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: The bits are used to indicate the virtual address of CPU access dbus when authen -tication fail..*/ -#define EXTMEM_CORE0_DBUS_VADDR 0xFFFFFFFF -#define EXTMEM_CORE0_DBUS_VADDR_M ((EXTMEM_CORE0_DBUS_VADDR_V)<<(EXTMEM_CORE0_DBUS_VADDR_S)) -#define EXTMEM_CORE0_DBUS_VADDR_V 0xFFFFFFFF +/** EXTMEM_CORE0_DBUS_REJECT_VADDR_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x94) +/** EXTMEM_CORE0_DBUS_VADDR : RO; bitpos: [31:0]; default: 4294967295; + * The bits are used to indicate the virtual address of CPU access dbus when + * authentication fail. + */ +#define EXTMEM_CORE0_DBUS_VADDR 0xFFFFFFFFU +#define EXTMEM_CORE0_DBUS_VADDR_M (EXTMEM_CORE0_DBUS_VADDR_V << EXTMEM_CORE0_DBUS_VADDR_S) +#define EXTMEM_CORE0_DBUS_VADDR_V 0xFFFFFFFFU #define EXTMEM_CORE0_DBUS_VADDR_S 0 -#define EXTMEM_CORE0_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x98) -/* EXTMEM_CORE0_IBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to indicate the world of CPU access ibus when authentication fai -l. 0: WORLD0, 1: WORLD1.*/ -#define EXTMEM_CORE0_IBUS_WORLD (BIT(3)) -#define EXTMEM_CORE0_IBUS_WORLD_M (BIT(3)) -#define EXTMEM_CORE0_IBUS_WORLD_V 0x1 -#define EXTMEM_CORE0_IBUS_WORLD_S 3 -/* EXTMEM_CORE0_IBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: The bits are used to indicate the attribute of CPU access ibus when authenticati -on fail. 0: invalidate, 1: execute-able, 2: read-able.*/ -#define EXTMEM_CORE0_IBUS_ATTR 0x00000007 -#define EXTMEM_CORE0_IBUS_ATTR_M ((EXTMEM_CORE0_IBUS_ATTR_V)<<(EXTMEM_CORE0_IBUS_ATTR_S)) -#define EXTMEM_CORE0_IBUS_ATTR_V 0x7 +/** EXTMEM_CORE0_IBUS_REJECT_ST_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CORE0_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x98) +/** EXTMEM_CORE0_IBUS_ATTR : RO; bitpos: [2:0]; default: 0; + * The bits are used to indicate the attribute of CPU access ibus when authentication + * fail. 0: invalidate, 1: execute-able, 2: read-able + */ +#define EXTMEM_CORE0_IBUS_ATTR 0x00000007U +#define EXTMEM_CORE0_IBUS_ATTR_M (EXTMEM_CORE0_IBUS_ATTR_V << EXTMEM_CORE0_IBUS_ATTR_S) +#define EXTMEM_CORE0_IBUS_ATTR_V 0x00000007U #define EXTMEM_CORE0_IBUS_ATTR_S 0 +/** EXTMEM_CORE0_IBUS_WORLD : RO; bitpos: [3]; default: 0; + * The bit is used to indicate the world of CPU access ibus when authentication fail. + * 0: WORLD0, 1: WORLD1 + */ +#define EXTMEM_CORE0_IBUS_WORLD (BIT(3)) +#define EXTMEM_CORE0_IBUS_WORLD_M (EXTMEM_CORE0_IBUS_WORLD_V << EXTMEM_CORE0_IBUS_WORLD_S) +#define EXTMEM_CORE0_IBUS_WORLD_V 0x00000001U +#define EXTMEM_CORE0_IBUS_WORLD_S 3 -#define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x9C) -/* EXTMEM_CORE0_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: The bits are used to indicate the virtual address of CPU access ibus when authe -ntication fail..*/ -#define EXTMEM_CORE0_IBUS_VADDR 0xFFFFFFFF -#define EXTMEM_CORE0_IBUS_VADDR_M ((EXTMEM_CORE0_IBUS_VADDR_V)<<(EXTMEM_CORE0_IBUS_VADDR_S)) -#define EXTMEM_CORE0_IBUS_VADDR_V 0xFFFFFFFF +/** EXTMEM_CORE0_IBUS_REJECT_VADDR_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x9c) +/** EXTMEM_CORE0_IBUS_VADDR : RO; bitpos: [31:0]; default: 4294967295; + * The bits are used to indicate the virtual address of CPU access ibus when + * authentication fail. + */ +#define EXTMEM_CORE0_IBUS_VADDR 0xFFFFFFFFU +#define EXTMEM_CORE0_IBUS_VADDR_M (EXTMEM_CORE0_IBUS_VADDR_V << EXTMEM_CORE0_IBUS_VADDR_S) +#define EXTMEM_CORE0_IBUS_VADDR_V 0xFFFFFFFFU #define EXTMEM_CORE0_IBUS_VADDR_S 0 -#define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG (DR_REG_EXTMEM_BASE + 0xA0) -/* EXTMEM_CACHE_MMU_FAULT_CODE : RO ;bitpos:[13:10] ;default: 4'h0 ; */ -/*description: The right-most 3 bits are used to indicate the operations which cause mmu fault -occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss -evict recovery address, 5: load miss evict recovery address, 6: external dma tx, - 7: external dma rx. The most significant bit is used to indicate this operation - occurs in which one icache..*/ -#define EXTMEM_CACHE_MMU_FAULT_CODE 0x0000000F -#define EXTMEM_CACHE_MMU_FAULT_CODE_M ((EXTMEM_CACHE_MMU_FAULT_CODE_V)<<(EXTMEM_CACHE_MMU_FAULT_CODE_S)) -#define EXTMEM_CACHE_MMU_FAULT_CODE_V 0xF -#define EXTMEM_CACHE_MMU_FAULT_CODE_S 10 -/* EXTMEM_CACHE_MMU_FAULT_CONTENT : RO ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: The bits are used to indicate the content of mmu entry which cause mmu fault...*/ -#define EXTMEM_CACHE_MMU_FAULT_CONTENT 0x000000FF -#define EXTMEM_CACHE_MMU_FAULT_CONTENT_M ((EXTMEM_CACHE_MMU_FAULT_CONTENT_V)<<(EXTMEM_CACHE_MMU_FAULT_CONTENT_S)) -#define EXTMEM_CACHE_MMU_FAULT_CONTENT_V 0xFF +/** EXTMEM_CACHE_MMU_FAULT_CONTENT_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG (DR_REG_EXTMEM_BASE + 0xa0) +/** EXTMEM_CACHE_MMU_FAULT_CONTENT : RO; bitpos: [7:0]; default: 0; + * The bits are used to indicate the content of mmu entry which cause mmu fault.. + */ +#define EXTMEM_CACHE_MMU_FAULT_CONTENT 0x000000FFU +#define EXTMEM_CACHE_MMU_FAULT_CONTENT_M (EXTMEM_CACHE_MMU_FAULT_CONTENT_V << EXTMEM_CACHE_MMU_FAULT_CONTENT_S) +#define EXTMEM_CACHE_MMU_FAULT_CONTENT_V 0x000000FFU #define EXTMEM_CACHE_MMU_FAULT_CONTENT_S 0 +/** EXTMEM_CACHE_MMU_FAULT_CODE : RO; bitpos: [13:10]; default: 0; + * The right-most 3 bits are used to indicate the operations which cause mmu fault + * occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss + * evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: + * external dma rx. The most significant bit is used to indicate this operation occurs + * in which one icache. + */ +#define EXTMEM_CACHE_MMU_FAULT_CODE 0x0000000FU +#define EXTMEM_CACHE_MMU_FAULT_CODE_M (EXTMEM_CACHE_MMU_FAULT_CODE_V << EXTMEM_CACHE_MMU_FAULT_CODE_S) +#define EXTMEM_CACHE_MMU_FAULT_CODE_V 0x0000000FU +#define EXTMEM_CACHE_MMU_FAULT_CODE_S 10 -#define EXTMEM_CACHE_MMU_FAULT_VADDR_REG (DR_REG_EXTMEM_BASE + 0xA4) -/* EXTMEM_CACHE_MMU_FAULT_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to indicate the virtual address which cause mmu fault...*/ -#define EXTMEM_CACHE_MMU_FAULT_VADDR 0xFFFFFFFF -#define EXTMEM_CACHE_MMU_FAULT_VADDR_M ((EXTMEM_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_CACHE_MMU_FAULT_VADDR_S)) -#define EXTMEM_CACHE_MMU_FAULT_VADDR_V 0xFFFFFFFF +/** EXTMEM_CACHE_MMU_FAULT_VADDR_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CACHE_MMU_FAULT_VADDR_REG (DR_REG_EXTMEM_BASE + 0xa4) +/** EXTMEM_CACHE_MMU_FAULT_VADDR : RO; bitpos: [31:0]; default: 0; + * The bits are used to indicate the virtual address which cause mmu fault.. + */ +#define EXTMEM_CACHE_MMU_FAULT_VADDR 0xFFFFFFFFU +#define EXTMEM_CACHE_MMU_FAULT_VADDR_M (EXTMEM_CACHE_MMU_FAULT_VADDR_V << EXTMEM_CACHE_MMU_FAULT_VADDR_S) +#define EXTMEM_CACHE_MMU_FAULT_VADDR_V 0xFFFFFFFFU #define EXTMEM_CACHE_MMU_FAULT_VADDR_S 0 -#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0xA8) -/* EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable wrap around mode when read data from flash..*/ +/** EXTMEM_CACHE_WRAP_AROUND_CTRL_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0xa8) +/** EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W; bitpos: [0]; default: 0; + * The bit is used to enable wrap around mode when read data from flash. + */ #define EXTMEM_CACHE_FLASH_WRAP_AROUND (BIT(0)) -#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M (BIT(0)) -#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V 0x1 +#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M (EXTMEM_CACHE_FLASH_WRAP_AROUND_V << EXTMEM_CACHE_FLASH_WRAP_AROUND_S) +#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V 0x00000001U #define EXTMEM_CACHE_FLASH_WRAP_AROUND_S 0 -#define EXTMEM_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0xAC) -/* EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up.*/ -#define EXTMEM_CACHE_MMU_MEM_FORCE_PU (BIT(2)) -#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M (BIT(2)) -#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V 0x1 -#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S 2 -/* EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down.*/ -#define EXTMEM_CACHE_MMU_MEM_FORCE_PD (BIT(1)) -#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M (BIT(1)) -#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V 0x1 -#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S 1 -/* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to enable clock gating to save power when access mmu memory, 0: -enable, 1: disable.*/ +/** EXTMEM_CACHE_MMU_POWER_CTRL_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0xac) +/** EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1; + * The bit is used to enable clock gating to save power when access mmu memory, 0: + * enable, 1: disable + */ #define EXTMEM_CACHE_MMU_MEM_FORCE_ON (BIT(0)) -#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M (BIT(0)) -#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V 0x1 +#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M (EXTMEM_CACHE_MMU_MEM_FORCE_ON_V << EXTMEM_CACHE_MMU_MEM_FORCE_ON_S) +#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V 0x00000001U #define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S 0 +/** EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; + * The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down + */ +#define EXTMEM_CACHE_MMU_MEM_FORCE_PD (BIT(1)) +#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M (EXTMEM_CACHE_MMU_MEM_FORCE_PD_V << EXTMEM_CACHE_MMU_MEM_FORCE_PD_S) +#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V 0x00000001U +#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S 1 +/** EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; + * The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up + */ +#define EXTMEM_CACHE_MMU_MEM_FORCE_PU (BIT(2)) +#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M (EXTMEM_CACHE_MMU_MEM_FORCE_PU_V << EXTMEM_CACHE_MMU_MEM_FORCE_PU_S) +#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V 0x00000001U +#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S 2 -#define EXTMEM_CACHE_STATE_REG (DR_REG_EXTMEM_BASE + 0xB0) -/* EXTMEM_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h1 ; */ -/*description: The bit is used to indicate whether icache main fsm is in idle state or not. 1: - in idle state, 0: not in idle state.*/ -#define EXTMEM_ICACHE_STATE 0x00000FFF -#define EXTMEM_ICACHE_STATE_M ((EXTMEM_ICACHE_STATE_V)<<(EXTMEM_ICACHE_STATE_S)) -#define EXTMEM_ICACHE_STATE_V 0xFFF +/** EXTMEM_CACHE_STATE_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CACHE_STATE_REG (DR_REG_EXTMEM_BASE + 0xb0) +/** EXTMEM_ICACHE_STATE : RO; bitpos: [11:0]; default: 1; + * The bit is used to indicate whether icache main fsm is in idle state or not. 1: in + * idle state, 0: not in idle state + */ +#define EXTMEM_ICACHE_STATE 0x00000FFFU +#define EXTMEM_ICACHE_STATE_M (EXTMEM_ICACHE_STATE_V << EXTMEM_ICACHE_STATE_S) +#define EXTMEM_ICACHE_STATE_V 0x00000FFFU #define EXTMEM_ICACHE_STATE_S 0 -#define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG (DR_REG_EXTMEM_BASE + 0xB4) -/* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Reserved..*/ -#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT (BIT(1)) -#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M (BIT(1)) -#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V 0x1 -#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S 1 -/* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Reserved..*/ +/** EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG (DR_REG_EXTMEM_BASE + 0xb4) +/** EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W; bitpos: [0]; default: 0; + * Reserved. + */ #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT (BIT(0)) -#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M (BIT(0)) -#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V 0x1 +#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M (EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V << EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S) +#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V 0x00000001U #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S 0 +/** EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W; bitpos: [1]; default: 0; + * Reserved. + */ +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT (BIT(1)) +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M (EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V << EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S) +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V 0x00000001U +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S 1 -#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0xB8) -/* EXTMEM_CLK_FORCE_ON_CRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: The bit is used to close clock gating of external memory encrypt and decrypt clo -ck. 1: close gating, 0: open clock gating..*/ -#define EXTMEM_CLK_FORCE_ON_CRYPT (BIT(2)) -#define EXTMEM_CLK_FORCE_ON_CRYPT_M (BIT(2)) -#define EXTMEM_CLK_FORCE_ON_CRYPT_V 0x1 -#define EXTMEM_CLK_FORCE_ON_CRYPT_S 2 -/* EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: The bit is used to close clock gating of automatic crypt clock. 1: close gating, - 0: open clock gating..*/ -#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT (BIT(1)) -#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M (BIT(1)) -#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V 0x1 -#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S 1 -/* EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: - open clock gating..*/ +/** EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0xb8) +/** EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W; bitpos: [0]; default: 1; + * The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: + * open clock gating. + */ #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT (BIT(0)) -#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M (BIT(0)) -#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V 0x1 +#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M (EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V << EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S) +#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V 0x00000001U #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S 0 +/** EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W; bitpos: [1]; default: 1; + * The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: + * open clock gating. + */ +#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT (BIT(1)) +#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M (EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V << EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S) +#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V 0x00000001U +#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S 1 +/** EXTMEM_CLK_FORCE_ON_CRYPT : R/W; bitpos: [2]; default: 1; + * The bit is used to close clock gating of external memory encrypt and decrypt clock. + * 1: close gating, 0: open clock gating. + */ +#define EXTMEM_CLK_FORCE_ON_CRYPT (BIT(2)) +#define EXTMEM_CLK_FORCE_ON_CRYPT_M (EXTMEM_CLK_FORCE_ON_CRYPT_V << EXTMEM_CLK_FORCE_ON_CRYPT_S) +#define EXTMEM_CLK_FORCE_ON_CRYPT_V 0x00000001U +#define EXTMEM_CLK_FORCE_ON_CRYPT_S 2 -#define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0xBC) -/* EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to clear the interrupt by icache pre-load done..*/ -#define EXTMEM_ICACHE_PRELOAD_INT_CLR (BIT(2)) -#define EXTMEM_ICACHE_PRELOAD_INT_CLR_M (BIT(2)) -#define EXTMEM_ICACHE_PRELOAD_INT_CLR_V 0x1 -#define EXTMEM_ICACHE_PRELOAD_INT_CLR_S 2 -/* EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable the interrupt by icache pre-load done..*/ -#define EXTMEM_ICACHE_PRELOAD_INT_ENA (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_INT_ENA_M (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_INT_ENA_V 0x1 -#define EXTMEM_ICACHE_PRELOAD_INT_ENA_S 1 -/* EXTMEM_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to indicate the interrupt by icache pre-load done..*/ +/** EXTMEM_CACHE_PRELOAD_INT_CTRL_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0xbc) +/** EXTMEM_ICACHE_PRELOAD_INT_ST : RO; bitpos: [0]; default: 0; + * The bit is used to indicate the interrupt by icache pre-load done. + */ #define EXTMEM_ICACHE_PRELOAD_INT_ST (BIT(0)) -#define EXTMEM_ICACHE_PRELOAD_INT_ST_M (BIT(0)) -#define EXTMEM_ICACHE_PRELOAD_INT_ST_V 0x1 +#define EXTMEM_ICACHE_PRELOAD_INT_ST_M (EXTMEM_ICACHE_PRELOAD_INT_ST_V << EXTMEM_ICACHE_PRELOAD_INT_ST_S) +#define EXTMEM_ICACHE_PRELOAD_INT_ST_V 0x00000001U #define EXTMEM_ICACHE_PRELOAD_INT_ST_S 0 +/** EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W; bitpos: [1]; default: 0; + * The bit is used to enable the interrupt by icache pre-load done. + */ +#define EXTMEM_ICACHE_PRELOAD_INT_ENA (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_INT_ENA_M (EXTMEM_ICACHE_PRELOAD_INT_ENA_V << EXTMEM_ICACHE_PRELOAD_INT_ENA_S) +#define EXTMEM_ICACHE_PRELOAD_INT_ENA_V 0x00000001U +#define EXTMEM_ICACHE_PRELOAD_INT_ENA_S 1 +/** EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD; bitpos: [2]; default: 0; + * The bit is used to clear the interrupt by icache pre-load done. + */ +#define EXTMEM_ICACHE_PRELOAD_INT_CLR (BIT(2)) +#define EXTMEM_ICACHE_PRELOAD_INT_CLR_M (EXTMEM_ICACHE_PRELOAD_INT_CLR_V << EXTMEM_ICACHE_PRELOAD_INT_CLR_S) +#define EXTMEM_ICACHE_PRELOAD_INT_CLR_V 0x00000001U +#define EXTMEM_ICACHE_PRELOAD_INT_CLR_S 2 -#define EXTMEM_CACHE_SYNC_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0xC0) -/* EXTMEM_ICACHE_SYNC_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to clear the interrupt by icache sync done..*/ -#define EXTMEM_ICACHE_SYNC_INT_CLR (BIT(2)) -#define EXTMEM_ICACHE_SYNC_INT_CLR_M (BIT(2)) -#define EXTMEM_ICACHE_SYNC_INT_CLR_V 0x1 -#define EXTMEM_ICACHE_SYNC_INT_CLR_S 2 -/* EXTMEM_ICACHE_SYNC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable the interrupt by icache sync done..*/ -#define EXTMEM_ICACHE_SYNC_INT_ENA (BIT(1)) -#define EXTMEM_ICACHE_SYNC_INT_ENA_M (BIT(1)) -#define EXTMEM_ICACHE_SYNC_INT_ENA_V 0x1 -#define EXTMEM_ICACHE_SYNC_INT_ENA_S 1 -/* EXTMEM_ICACHE_SYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to indicate the interrupt by icache sync done..*/ +/** EXTMEM_CACHE_SYNC_INT_CTRL_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CACHE_SYNC_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0xc0) +/** EXTMEM_ICACHE_SYNC_INT_ST : RO; bitpos: [0]; default: 0; + * The bit is used to indicate the interrupt by icache sync done. + */ #define EXTMEM_ICACHE_SYNC_INT_ST (BIT(0)) -#define EXTMEM_ICACHE_SYNC_INT_ST_M (BIT(0)) -#define EXTMEM_ICACHE_SYNC_INT_ST_V 0x1 +#define EXTMEM_ICACHE_SYNC_INT_ST_M (EXTMEM_ICACHE_SYNC_INT_ST_V << EXTMEM_ICACHE_SYNC_INT_ST_S) +#define EXTMEM_ICACHE_SYNC_INT_ST_V 0x00000001U #define EXTMEM_ICACHE_SYNC_INT_ST_S 0 +/** EXTMEM_ICACHE_SYNC_INT_ENA : R/W; bitpos: [1]; default: 0; + * The bit is used to enable the interrupt by icache sync done. + */ +#define EXTMEM_ICACHE_SYNC_INT_ENA (BIT(1)) +#define EXTMEM_ICACHE_SYNC_INT_ENA_M (EXTMEM_ICACHE_SYNC_INT_ENA_V << EXTMEM_ICACHE_SYNC_INT_ENA_S) +#define EXTMEM_ICACHE_SYNC_INT_ENA_V 0x00000001U +#define EXTMEM_ICACHE_SYNC_INT_ENA_S 1 +/** EXTMEM_ICACHE_SYNC_INT_CLR : WOD; bitpos: [2]; default: 0; + * The bit is used to clear the interrupt by icache sync done. + */ +#define EXTMEM_ICACHE_SYNC_INT_CLR (BIT(2)) +#define EXTMEM_ICACHE_SYNC_INT_CLR_M (EXTMEM_ICACHE_SYNC_INT_CLR_V << EXTMEM_ICACHE_SYNC_INT_CLR_S) +#define EXTMEM_ICACHE_SYNC_INT_CLR_V 0x00000001U +#define EXTMEM_ICACHE_SYNC_INT_CLR_S 2 -#define EXTMEM_CACHE_MMU_OWNER_REG (DR_REG_EXTMEM_BASE + 0xC4) -/* EXTMEM_CACHE_MMU_OWNER : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus.*/ -#define EXTMEM_CACHE_MMU_OWNER 0x0000000F -#define EXTMEM_CACHE_MMU_OWNER_M ((EXTMEM_CACHE_MMU_OWNER_V)<<(EXTMEM_CACHE_MMU_OWNER_S)) -#define EXTMEM_CACHE_MMU_OWNER_V 0xF +/** EXTMEM_CACHE_MMU_OWNER_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CACHE_MMU_OWNER_REG (DR_REG_EXTMEM_BASE + 0xc4) +/** EXTMEM_CACHE_MMU_OWNER : R/W; bitpos: [3:0]; default: 0; + * The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus + */ +#define EXTMEM_CACHE_MMU_OWNER 0x0000000FU +#define EXTMEM_CACHE_MMU_OWNER_M (EXTMEM_CACHE_MMU_OWNER_V << EXTMEM_CACHE_MMU_OWNER_S) +#define EXTMEM_CACHE_MMU_OWNER_V 0x0000000FU #define EXTMEM_CACHE_MMU_OWNER_S 0 -#define EXTMEM_CACHE_CONF_MISC_REG (DR_REG_EXTMEM_BASE + 0xC8) -/* EXTMEM_CACHE_MMU_PAGE_SIZE : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: This bit is used to choose mmu page size. 2:64KB. 1. 32KB. 0: 16KB.*/ -#define EXTMEM_CACHE_MMU_PAGE_SIZE 0x00000003 -#define EXTMEM_CACHE_MMU_PAGE_SIZE_M ((EXTMEM_CACHE_MMU_PAGE_SIZE_V)<<(EXTMEM_CACHE_MMU_PAGE_SIZE_S)) -#define EXTMEM_CACHE_MMU_PAGE_SIZE_V 0x3 -#define EXTMEM_CACHE_MMU_PAGE_SIZE_S 3 -/* EXTMEM_CACHE_TRACE_ENA : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: The bit is used to enable cache trace function..*/ -#define EXTMEM_CACHE_TRACE_ENA (BIT(2)) -#define EXTMEM_CACHE_TRACE_ENA_M (BIT(2)) -#define EXTMEM_CACHE_TRACE_ENA_V 0x1 -#define EXTMEM_CACHE_TRACE_ENA_S 2 -/* EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: The bit is used to disable checking mmu entry fault by sync operation..*/ -#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT (BIT(1)) -#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M (BIT(1)) -#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V 0x1 -#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S 1 -/* EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to disable checking mmu entry fault by preload operation..*/ +/** EXTMEM_CACHE_CONF_MISC_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CACHE_CONF_MISC_REG (DR_REG_EXTMEM_BASE + 0xc8) +/** EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W; bitpos: [0]; default: 1; + * The bit is used to disable checking mmu entry fault by preload operation. + */ #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT (BIT(0)) -#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M (BIT(0)) -#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V 0x1 +#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M (EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V << EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S) +#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V 0x00000001U #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S 0 +/** EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W; bitpos: [1]; default: 1; + * The bit is used to disable checking mmu entry fault by sync operation. + */ +#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT (BIT(1)) +#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M (EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V << EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S) +#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V 0x00000001U +#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S 1 +/** EXTMEM_CACHE_TRACE_ENA : R/W; bitpos: [2]; default: 1; + * The bit is used to enable cache trace function. + */ +#define EXTMEM_CACHE_TRACE_ENA (BIT(2)) +#define EXTMEM_CACHE_TRACE_ENA_M (EXTMEM_CACHE_TRACE_ENA_V << EXTMEM_CACHE_TRACE_ENA_S) +#define EXTMEM_CACHE_TRACE_ENA_V 0x00000001U +#define EXTMEM_CACHE_TRACE_ENA_S 2 +/** EXTMEM_CACHE_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0; + * This bit is used to choose mmu page size. 2:64KB. 1. 32KB. 0: 16KB + */ +#define EXTMEM_CACHE_MMU_PAGE_SIZE 0x00000003U +#define EXTMEM_CACHE_MMU_PAGE_SIZE_M (EXTMEM_CACHE_MMU_PAGE_SIZE_V << EXTMEM_CACHE_MMU_PAGE_SIZE_S) +#define EXTMEM_CACHE_MMU_PAGE_SIZE_V 0x00000003U +#define EXTMEM_CACHE_MMU_PAGE_SIZE_S 3 -#define EXTMEM_ICACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0xCC) -/* EXTMEM_ICACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to indicate icache freeze success.*/ -#define EXTMEM_ICACHE_FREEZE_DONE (BIT(2)) -#define EXTMEM_ICACHE_FREEZE_DONE_M (BIT(2)) -#define EXTMEM_ICACHE_FREEZE_DONE_V 0x1 -#define EXTMEM_ICACHE_FREEZE_DONE_S 2 -/* EXTMEM_ICACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert -hit if CPU miss.*/ -#define EXTMEM_ICACHE_FREEZE_MODE (BIT(1)) -#define EXTMEM_ICACHE_FREEZE_MODE_M (BIT(1)) -#define EXTMEM_ICACHE_FREEZE_MODE_V 0x1 -#define EXTMEM_ICACHE_FREEZE_MODE_S 1 -/* EXTMEM_ICACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable icache freeze mode.*/ +/** EXTMEM_ICACHE_FREEZE_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_ICACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0xcc) +/** EXTMEM_ICACHE_FREEZE_ENA : R/W; bitpos: [0]; default: 0; + * The bit is used to enable icache freeze mode + */ #define EXTMEM_ICACHE_FREEZE_ENA (BIT(0)) -#define EXTMEM_ICACHE_FREEZE_ENA_M (BIT(0)) -#define EXTMEM_ICACHE_FREEZE_ENA_V 0x1 +#define EXTMEM_ICACHE_FREEZE_ENA_M (EXTMEM_ICACHE_FREEZE_ENA_V << EXTMEM_ICACHE_FREEZE_ENA_S) +#define EXTMEM_ICACHE_FREEZE_ENA_V 0x00000001U #define EXTMEM_ICACHE_FREEZE_ENA_S 0 +/** EXTMEM_ICACHE_FREEZE_MODE : R/W; bitpos: [1]; default: 0; + * The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit + * if CPU miss + */ +#define EXTMEM_ICACHE_FREEZE_MODE (BIT(1)) +#define EXTMEM_ICACHE_FREEZE_MODE_M (EXTMEM_ICACHE_FREEZE_MODE_V << EXTMEM_ICACHE_FREEZE_MODE_S) +#define EXTMEM_ICACHE_FREEZE_MODE_V 0x00000001U +#define EXTMEM_ICACHE_FREEZE_MODE_S 1 +/** EXTMEM_ICACHE_FREEZE_DONE : RO; bitpos: [2]; default: 0; + * The bit is used to indicate icache freeze success + */ +#define EXTMEM_ICACHE_FREEZE_DONE (BIT(2)) +#define EXTMEM_ICACHE_FREEZE_DONE_M (EXTMEM_ICACHE_FREEZE_DONE_V << EXTMEM_ICACHE_FREEZE_DONE_S) +#define EXTMEM_ICACHE_FREEZE_DONE_V 0x00000001U +#define EXTMEM_ICACHE_FREEZE_DONE_S 2 -#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0xD0) -/* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to activate icache atomic operation protection. In this case, sy -nc/lock operation can not interrupt miss-work. This feature does not work during - invalidateAll operation..*/ +/** EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0xd0) +/** EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W; bitpos: [0]; default: 1; + * The bit is used to activate icache atomic operation protection. In this case, + * sync/lock operation can not interrupt miss-work. This feature does not work during + * invalidateAll operation. + */ #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA (BIT(0)) -#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M (BIT(0)) -#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V 0x1 +#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M (EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V << EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S) +#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V 0x00000001U #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S 0 -#define EXTMEM_CACHE_REQUEST_REG (DR_REG_EXTMEM_BASE + 0xD4) -/* EXTMEM_CACHE_REQUEST_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to disable request recording which could cause performance issue.*/ +/** EXTMEM_CACHE_REQUEST_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CACHE_REQUEST_REG (DR_REG_EXTMEM_BASE + 0xd4) +/** EXTMEM_CACHE_REQUEST_BYPASS : R/W; bitpos: [0]; default: 0; + * The bit is used to disable request recording which could cause performance issue + */ #define EXTMEM_CACHE_REQUEST_BYPASS (BIT(0)) -#define EXTMEM_CACHE_REQUEST_BYPASS_M (BIT(0)) -#define EXTMEM_CACHE_REQUEST_BYPASS_V 0x1 +#define EXTMEM_CACHE_REQUEST_BYPASS_M (EXTMEM_CACHE_REQUEST_BYPASS_V << EXTMEM_CACHE_REQUEST_BYPASS_S) +#define EXTMEM_CACHE_REQUEST_BYPASS_V 0x00000001U #define EXTMEM_CACHE_REQUEST_BYPASS_S 0 -#define EXTMEM_CLOCK_GATE_REG (DR_REG_EXTMEM_BASE + 0x100) -/* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: clock gate enable..*/ +/** EXTMEM_CLOCK_GATE_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_CLOCK_GATE_REG (DR_REG_EXTMEM_BASE + 0x100) +/** EXTMEM_CLK_EN : R/W; bitpos: [0]; default: 1; + * clock gate enable. + */ #define EXTMEM_CLK_EN (BIT(0)) -#define EXTMEM_CLK_EN_M (BIT(0)) -#define EXTMEM_CLK_EN_V 0x1 +#define EXTMEM_CLK_EN_M (EXTMEM_CLK_EN_V << EXTMEM_CLK_EN_S) +#define EXTMEM_CLK_EN_V 0x00000001U #define EXTMEM_CLK_EN_S 0 -#define EXTMEM_REG_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC) -/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2107050 ; */ -/*description: version information.*/ -#define EXTMEM_DATE 0x0FFFFFFF -#define EXTMEM_DATE_M ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S)) -#define EXTMEM_DATE_V 0xFFFFFFF +/** EXTMEM_REG_DATE_REG register + * This description will be updated in the near future. + */ +#define EXTMEM_REG_DATE_REG (DR_REG_EXTMEM_BASE + 0x3fc) +/** EXTMEM_DATE : R/W; bitpos: [27:0]; default: 34631760; + * version information + */ +#define EXTMEM_DATE 0x0FFFFFFFU +#define EXTMEM_DATE_M (EXTMEM_DATE_V << EXTMEM_DATE_S) +#define EXTMEM_DATE_V 0x0FFFFFFFU #define EXTMEM_DATE_S 0 - #ifdef __cplusplus } #endif - - - -#endif /*_SOC_EXTMEM_REG_H_ */ diff --git a/components/soc/esp8684/include/soc/i2c_reg.h b/components/soc/esp8684/include/soc/i2c_reg.h index f520c99709..234331a0a0 100644 --- a/components/soc/esp8684/include/soc/i2c_reg.h +++ b/components/soc/esp8684/include/soc/i2c_reg.h @@ -1,9 +1,8 @@ -/* +/** * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ - #pragma once #include @@ -21,9 +20,9 @@ extern "C" { * This register is used to configure for how long SCL remains low in master mode, in * I2C module clock cycles. */ -#define I2C_SCL_LOW_PERIOD 0x000001FF +#define I2C_SCL_LOW_PERIOD 0x000001FFU #define I2C_SCL_LOW_PERIOD_M (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S) -#define I2C_SCL_LOW_PERIOD_V 0x000001FF +#define I2C_SCL_LOW_PERIOD_V 0x000001FFU #define I2C_SCL_LOW_PERIOD_S 0 /** I2C_CTR_REG register @@ -35,14 +34,14 @@ extern "C" { */ #define I2C_SDA_FORCE_OUT (BIT(0)) #define I2C_SDA_FORCE_OUT_M (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S) -#define I2C_SDA_FORCE_OUT_V 0x00000001 +#define I2C_SDA_FORCE_OUT_V 0x00000001U #define I2C_SDA_FORCE_OUT_S 0 /** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 1; * 0: direct output, 1: open drain output. */ #define I2C_SCL_FORCE_OUT (BIT(1)) #define I2C_SCL_FORCE_OUT_M (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S) -#define I2C_SCL_FORCE_OUT_V 0x00000001 +#define I2C_SCL_FORCE_OUT_V 0x00000001U #define I2C_SCL_FORCE_OUT_S 1 /** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; * This register is used to select the sample mode. @@ -51,7 +50,7 @@ extern "C" { */ #define I2C_SAMPLE_SCL_LEVEL (BIT(2)) #define I2C_SAMPLE_SCL_LEVEL_M (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S) -#define I2C_SAMPLE_SCL_LEVEL_V 0x00000001 +#define I2C_SAMPLE_SCL_LEVEL_V 0x00000001U #define I2C_SAMPLE_SCL_LEVEL_S 2 /** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; * This register is used to configure the ACK value that need to sent by master when @@ -59,7 +58,7 @@ extern "C" { */ #define I2C_RX_FULL_ACK_LEVEL (BIT(3)) #define I2C_RX_FULL_ACK_LEVEL_M (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S) -#define I2C_RX_FULL_ACK_LEVEL_V 0x00000001 +#define I2C_RX_FULL_ACK_LEVEL_V 0x00000001U #define I2C_RX_FULL_ACK_LEVEL_S 3 /** I2C_MS_MODE : R/W; bitpos: [4]; default: 0; * Set this bit to configure the module as an I2C Master. Clear this bit to configure @@ -68,14 +67,14 @@ extern "C" { */ #define I2C_MS_MODE (BIT(4)) #define I2C_MS_MODE_M (I2C_MS_MODE_V << I2C_MS_MODE_S) -#define I2C_MS_MODE_V 0x00000001 +#define I2C_MS_MODE_V 0x00000001U #define I2C_MS_MODE_S 4 /** I2C_TRANS_START : WT; bitpos: [5]; default: 0; * Set this bit to start sending the data in txfifo. */ #define I2C_TRANS_START (BIT(5)) #define I2C_TRANS_START_M (I2C_TRANS_START_V << I2C_TRANS_START_S) -#define I2C_TRANS_START_V 0x00000001 +#define I2C_TRANS_START_V 0x00000001U #define I2C_TRANS_START_S 5 /** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; * This bit is used to control the sending mode for data needing to be sent. @@ -84,7 +83,7 @@ extern "C" { */ #define I2C_TX_LSB_FIRST (BIT(6)) #define I2C_TX_LSB_FIRST_M (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S) -#define I2C_TX_LSB_FIRST_V 0x00000001 +#define I2C_TX_LSB_FIRST_V 0x00000001U #define I2C_TX_LSB_FIRST_S 6 /** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; * This bit is used to control the storage mode for received data. @@ -93,42 +92,42 @@ extern "C" { */ #define I2C_RX_LSB_FIRST (BIT(7)) #define I2C_RX_LSB_FIRST_M (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S) -#define I2C_RX_LSB_FIRST_V 0x00000001 +#define I2C_RX_LSB_FIRST_V 0x00000001U #define I2C_RX_LSB_FIRST_S 7 /** I2C_CLK_EN : R/W; bitpos: [8]; default: 0; * Reserved */ #define I2C_CLK_EN (BIT(8)) #define I2C_CLK_EN_M (I2C_CLK_EN_V << I2C_CLK_EN_S) -#define I2C_CLK_EN_V 0x00000001 +#define I2C_CLK_EN_V 0x00000001U #define I2C_CLK_EN_S 8 /** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; * This is the enable bit for arbitration_lost. */ #define I2C_ARBITRATION_EN (BIT(9)) #define I2C_ARBITRATION_EN_M (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S) -#define I2C_ARBITRATION_EN_V 0x00000001 +#define I2C_ARBITRATION_EN_V 0x00000001U #define I2C_ARBITRATION_EN_S 9 /** I2C_FSM_RST : WT; bitpos: [10]; default: 0; * This register is used to reset the scl FMS. */ #define I2C_FSM_RST (BIT(10)) #define I2C_FSM_RST_M (I2C_FSM_RST_V << I2C_FSM_RST_S) -#define I2C_FSM_RST_V 0x00000001 +#define I2C_FSM_RST_V 0x00000001U #define I2C_FSM_RST_S 10 /** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; * synchronization bit */ #define I2C_CONF_UPGATE (BIT(11)) #define I2C_CONF_UPGATE_M (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S) -#define I2C_CONF_UPGATE_V 0x00000001 +#define I2C_CONF_UPGATE_V 0x00000001U #define I2C_CONF_UPGATE_S 11 /** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0; * This is the enable bit for slave to send data automatically */ #define I2C_SLV_TX_AUTO_START_EN (BIT(12)) #define I2C_SLV_TX_AUTO_START_EN_M (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S) -#define I2C_SLV_TX_AUTO_START_EN_V 0x00000001 +#define I2C_SLV_TX_AUTO_START_EN_V 0x00000001U #define I2C_SLV_TX_AUTO_START_EN_S 12 /** I2C_SR_REG register @@ -140,52 +139,52 @@ extern "C" { */ #define I2C_RESP_REC (BIT(0)) #define I2C_RESP_REC_M (I2C_RESP_REC_V << I2C_RESP_REC_S) -#define I2C_RESP_REC_V 0x00000001 +#define I2C_RESP_REC_V 0x00000001U #define I2C_RESP_REC_S 0 /** I2C_ARB_LOST : RO; bitpos: [3]; default: 0; * When the I2C controller loses control of SCL line, this register changes to 1. */ #define I2C_ARB_LOST (BIT(3)) #define I2C_ARB_LOST_M (I2C_ARB_LOST_V << I2C_ARB_LOST_S) -#define I2C_ARB_LOST_V 0x00000001 +#define I2C_ARB_LOST_V 0x00000001U #define I2C_ARB_LOST_S 3 /** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; * 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. */ #define I2C_BUS_BUSY (BIT(4)) #define I2C_BUS_BUSY_M (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S) -#define I2C_BUS_BUSY_V 0x00000001 +#define I2C_BUS_BUSY_V 0x00000001U #define I2C_BUS_BUSY_S 4 /** I2C_RXFIFO_CNT : RO; bitpos: [12:8]; default: 0; * This field represents the amount of data needed to be sent. */ -#define I2C_RXFIFO_CNT 0x0000001F +#define I2C_RXFIFO_CNT 0x0000001FU #define I2C_RXFIFO_CNT_M (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S) -#define I2C_RXFIFO_CNT_V 0x0000001F +#define I2C_RXFIFO_CNT_V 0x0000001FU #define I2C_RXFIFO_CNT_S 8 /** I2C_TXFIFO_CNT : RO; bitpos: [22:18]; default: 0; * This field stores the amount of received data in RAM. */ -#define I2C_TXFIFO_CNT 0x0000001F +#define I2C_TXFIFO_CNT 0x0000001FU #define I2C_TXFIFO_CNT_M (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S) -#define I2C_TXFIFO_CNT_V 0x0000001F +#define I2C_TXFIFO_CNT_V 0x0000001FU #define I2C_TXFIFO_CNT_S 18 /** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; * This field indicates the states of the I2C module state machine. * 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: * Wait ACK */ -#define I2C_SCL_MAIN_STATE_LAST 0x00000007 +#define I2C_SCL_MAIN_STATE_LAST 0x00000007U #define I2C_SCL_MAIN_STATE_LAST_M (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S) -#define I2C_SCL_MAIN_STATE_LAST_V 0x00000007 +#define I2C_SCL_MAIN_STATE_LAST_V 0x00000007U #define I2C_SCL_MAIN_STATE_LAST_S 24 /** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; * This field indicates the states of the state machine used to produce SCL. * 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop */ -#define I2C_SCL_STATE_LAST 0x00000007 +#define I2C_SCL_STATE_LAST 0x00000007U #define I2C_SCL_STATE_LAST_M (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S) -#define I2C_SCL_STATE_LAST_V 0x00000007 +#define I2C_SCL_STATE_LAST_V 0x00000007U #define I2C_SCL_STATE_LAST_S 28 /** I2C_TO_REG register @@ -196,16 +195,16 @@ extern "C" { * This register is used to configure the timeout for receiving a data bit in APB * clock cycles. */ -#define I2C_TIME_OUT_VALUE 0x0000001F +#define I2C_TIME_OUT_VALUE 0x0000001FU #define I2C_TIME_OUT_VALUE_M (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S) -#define I2C_TIME_OUT_VALUE_V 0x0000001F +#define I2C_TIME_OUT_VALUE_V 0x0000001FU #define I2C_TIME_OUT_VALUE_S 0 /** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; * This is the enable bit for time out control. */ #define I2C_TIME_OUT_EN (BIT(5)) #define I2C_TIME_OUT_EN_M (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S) -#define I2C_TIME_OUT_EN_V 0x00000001 +#define I2C_TIME_OUT_EN_V 0x00000001U #define I2C_TIME_OUT_EN_S 5 /** I2C_FIFO_ST_REG register @@ -215,30 +214,30 @@ extern "C" { /** I2C_RXFIFO_RADDR : RO; bitpos: [3:0]; default: 0; * This is the offset address of the APB reading from rxfifo */ -#define I2C_RXFIFO_RADDR 0x0000000F +#define I2C_RXFIFO_RADDR 0x0000000FU #define I2C_RXFIFO_RADDR_M (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S) -#define I2C_RXFIFO_RADDR_V 0x0000000F +#define I2C_RXFIFO_RADDR_V 0x0000000FU #define I2C_RXFIFO_RADDR_S 0 /** I2C_RXFIFO_WADDR : RO; bitpos: [8:5]; default: 0; * This is the offset address of i2c module receiving data and writing to rxfifo. */ -#define I2C_RXFIFO_WADDR 0x0000000F +#define I2C_RXFIFO_WADDR 0x0000000FU #define I2C_RXFIFO_WADDR_M (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S) -#define I2C_RXFIFO_WADDR_V 0x0000000F +#define I2C_RXFIFO_WADDR_V 0x0000000FU #define I2C_RXFIFO_WADDR_S 5 /** I2C_TXFIFO_RADDR : RO; bitpos: [13:10]; default: 0; * This is the offset address of i2c module reading from txfifo. */ -#define I2C_TXFIFO_RADDR 0x0000000F +#define I2C_TXFIFO_RADDR 0x0000000FU #define I2C_TXFIFO_RADDR_M (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S) -#define I2C_TXFIFO_RADDR_V 0x0000000F +#define I2C_TXFIFO_RADDR_V 0x0000000FU #define I2C_TXFIFO_RADDR_S 10 /** I2C_TXFIFO_WADDR : RO; bitpos: [18:15]; default: 0; * This is the offset address of APB bus writing to txfifo. */ -#define I2C_TXFIFO_WADDR 0x0000000F +#define I2C_TXFIFO_WADDR 0x0000000FU #define I2C_TXFIFO_WADDR_M (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S) -#define I2C_TXFIFO_WADDR_V 0x0000000F +#define I2C_TXFIFO_WADDR_V 0x0000000FU #define I2C_TXFIFO_WADDR_S 15 /** I2C_FIFO_CONF_REG register @@ -250,39 +249,39 @@ extern "C" { * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than * reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. */ -#define I2C_RXFIFO_WM_THRHD 0x0000000F +#define I2C_RXFIFO_WM_THRHD 0x0000000FU #define I2C_RXFIFO_WM_THRHD_M (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S) -#define I2C_RXFIFO_WM_THRHD_V 0x0000000F +#define I2C_RXFIFO_WM_THRHD_V 0x0000000FU #define I2C_RXFIFO_WM_THRHD_S 0 /** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [8:5]; default: 2; * The water mark threshold of tx FIFO in nonfifo access mode. When * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than * reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. */ -#define I2C_TXFIFO_WM_THRHD 0x0000000F +#define I2C_TXFIFO_WM_THRHD 0x0000000FU #define I2C_TXFIFO_WM_THRHD_M (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S) -#define I2C_TXFIFO_WM_THRHD_V 0x0000000F +#define I2C_TXFIFO_WM_THRHD_V 0x0000000FU #define I2C_TXFIFO_WM_THRHD_S 5 /** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; * Set this bit to enable APB nonfifo access. */ #define I2C_NONFIFO_EN (BIT(10)) #define I2C_NONFIFO_EN_M (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S) -#define I2C_NONFIFO_EN_V 0x00000001 +#define I2C_NONFIFO_EN_V 0x00000001U #define I2C_NONFIFO_EN_S 10 /** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; * Set this bit to reset rx-fifo. */ #define I2C_RX_FIFO_RST (BIT(12)) #define I2C_RX_FIFO_RST_M (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S) -#define I2C_RX_FIFO_RST_V 0x00000001 +#define I2C_RX_FIFO_RST_V 0x00000001U #define I2C_RX_FIFO_RST_S 12 /** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; * Set this bit to reset tx-fifo. */ #define I2C_TX_FIFO_RST (BIT(13)) #define I2C_TX_FIFO_RST_M (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S) -#define I2C_TX_FIFO_RST_V 0x00000001 +#define I2C_TX_FIFO_RST_V 0x00000001U #define I2C_TX_FIFO_RST_S 13 /** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls @@ -290,7 +289,7 @@ extern "C" { */ #define I2C_FIFO_PRT_EN (BIT(14)) #define I2C_FIFO_PRT_EN_M (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S) -#define I2C_FIFO_PRT_EN_V 0x00000001 +#define I2C_FIFO_PRT_EN_V 0x00000001U #define I2C_FIFO_PRT_EN_S 14 /** I2C_DATA_REG register @@ -300,9 +299,9 @@ extern "C" { /** I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0; * The value of rx FIFO read data. */ -#define I2C_FIFO_RDATA 0x000000FF +#define I2C_FIFO_RDATA 0x000000FFU #define I2C_FIFO_RDATA_M (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S) -#define I2C_FIFO_RDATA_V 0x000000FF +#define I2C_FIFO_RDATA_V 0x000000FFU #define I2C_FIFO_RDATA_S 0 /** I2C_INT_RAW_REG register @@ -314,112 +313,112 @@ extern "C" { */ #define I2C_RXFIFO_WM_INT_RAW (BIT(0)) #define I2C_RXFIFO_WM_INT_RAW_M (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S) -#define I2C_RXFIFO_WM_INT_RAW_V 0x00000001 +#define I2C_RXFIFO_WM_INT_RAW_V 0x00000001U #define I2C_RXFIFO_WM_INT_RAW_S 0 /** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; * The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. */ #define I2C_TXFIFO_WM_INT_RAW (BIT(1)) #define I2C_TXFIFO_WM_INT_RAW_M (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S) -#define I2C_TXFIFO_WM_INT_RAW_V 0x00000001 +#define I2C_TXFIFO_WM_INT_RAW_V 0x00000001U #define I2C_TXFIFO_WM_INT_RAW_S 1 /** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; * The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. */ #define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) #define I2C_RXFIFO_OVF_INT_RAW_M (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S) -#define I2C_RXFIFO_OVF_INT_RAW_V 0x00000001 +#define I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U #define I2C_RXFIFO_OVF_INT_RAW_S 2 /** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. */ #define I2C_END_DETECT_INT_RAW (BIT(3)) #define I2C_END_DETECT_INT_RAW_M (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S) -#define I2C_END_DETECT_INT_RAW_V 0x00000001 +#define I2C_END_DETECT_INT_RAW_V 0x00000001U #define I2C_END_DETECT_INT_RAW_S 3 /** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. */ #define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) #define I2C_BYTE_TRANS_DONE_INT_RAW_M (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S) -#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001 +#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U #define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 /** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; * The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. */ #define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) #define I2C_ARBITRATION_LOST_INT_RAW_M (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S) -#define I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001 +#define I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U #define I2C_ARBITRATION_LOST_INT_RAW_S 5 /** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; * The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. */ #define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) #define I2C_MST_TXFIFO_UDF_INT_RAW_M (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S) -#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001 +#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U #define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 /** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; * The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. */ #define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) #define I2C_TRANS_COMPLETE_INT_RAW_M (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S) -#define I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001 +#define I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U #define I2C_TRANS_COMPLETE_INT_RAW_S 7 /** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; * The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. */ #define I2C_TIME_OUT_INT_RAW (BIT(8)) #define I2C_TIME_OUT_INT_RAW_M (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S) -#define I2C_TIME_OUT_INT_RAW_V 0x00000001 +#define I2C_TIME_OUT_INT_RAW_V 0x00000001U #define I2C_TIME_OUT_INT_RAW_S 8 /** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; * The raw interrupt bit for the I2C_TRANS_START_INT interrupt. */ #define I2C_TRANS_START_INT_RAW (BIT(9)) #define I2C_TRANS_START_INT_RAW_M (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S) -#define I2C_TRANS_START_INT_RAW_V 0x00000001 +#define I2C_TRANS_START_INT_RAW_V 0x00000001U #define I2C_TRANS_START_INT_RAW_S 9 /** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. */ #define I2C_NACK_INT_RAW (BIT(10)) #define I2C_NACK_INT_RAW_M (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S) -#define I2C_NACK_INT_RAW_V 0x00000001 +#define I2C_NACK_INT_RAW_V 0x00000001U #define I2C_NACK_INT_RAW_S 10 /** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; * The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. */ #define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) #define I2C_TXFIFO_OVF_INT_RAW_M (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S) -#define I2C_TXFIFO_OVF_INT_RAW_V 0x00000001 +#define I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U #define I2C_TXFIFO_OVF_INT_RAW_S 11 /** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; * The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. */ #define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) #define I2C_RXFIFO_UDF_INT_RAW_M (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S) -#define I2C_RXFIFO_UDF_INT_RAW_V 0x00000001 +#define I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U #define I2C_RXFIFO_UDF_INT_RAW_S 12 /** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; * The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. */ #define I2C_SCL_ST_TO_INT_RAW (BIT(13)) #define I2C_SCL_ST_TO_INT_RAW_M (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S) -#define I2C_SCL_ST_TO_INT_RAW_V 0x00000001 +#define I2C_SCL_ST_TO_INT_RAW_V 0x00000001U #define I2C_SCL_ST_TO_INT_RAW_S 13 /** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; * The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. */ #define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) #define I2C_SCL_MAIN_ST_TO_INT_RAW_M (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S) -#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001 +#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U #define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 /** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; * The raw interrupt bit for I2C_DET_START_INT interrupt. */ #define I2C_DET_START_INT_RAW (BIT(15)) #define I2C_DET_START_INT_RAW_M (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S) -#define I2C_DET_START_INT_RAW_V 0x00000001 +#define I2C_DET_START_INT_RAW_V 0x00000001U #define I2C_DET_START_INT_RAW_S 15 /** I2C_INT_CLR_REG register @@ -431,112 +430,112 @@ extern "C" { */ #define I2C_RXFIFO_WM_INT_CLR (BIT(0)) #define I2C_RXFIFO_WM_INT_CLR_M (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S) -#define I2C_RXFIFO_WM_INT_CLR_V 0x00000001 +#define I2C_RXFIFO_WM_INT_CLR_V 0x00000001U #define I2C_RXFIFO_WM_INT_CLR_S 0 /** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; * Set this bit to clear I2C_TXFIFO_WM_INT interrupt. */ #define I2C_TXFIFO_WM_INT_CLR (BIT(1)) #define I2C_TXFIFO_WM_INT_CLR_M (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S) -#define I2C_TXFIFO_WM_INT_CLR_V 0x00000001 +#define I2C_TXFIFO_WM_INT_CLR_V 0x00000001U #define I2C_TXFIFO_WM_INT_CLR_S 1 /** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; * Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. */ #define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) #define I2C_RXFIFO_OVF_INT_CLR_M (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S) -#define I2C_RXFIFO_OVF_INT_CLR_V 0x00000001 +#define I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U #define I2C_RXFIFO_OVF_INT_CLR_S 2 /** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; * Set this bit to clear the I2C_END_DETECT_INT interrupt. */ #define I2C_END_DETECT_INT_CLR (BIT(3)) #define I2C_END_DETECT_INT_CLR_M (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S) -#define I2C_END_DETECT_INT_CLR_V 0x00000001 +#define I2C_END_DETECT_INT_CLR_V 0x00000001U #define I2C_END_DETECT_INT_CLR_S 3 /** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; * Set this bit to clear the I2C_END_DETECT_INT interrupt. */ #define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) #define I2C_BYTE_TRANS_DONE_INT_CLR_M (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S) -#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001 +#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U #define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 /** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; * Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. */ #define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) #define I2C_ARBITRATION_LOST_INT_CLR_M (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S) -#define I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001 +#define I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U #define I2C_ARBITRATION_LOST_INT_CLR_S 5 /** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; * Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. */ #define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) #define I2C_MST_TXFIFO_UDF_INT_CLR_M (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S) -#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001 +#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U #define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 /** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; * Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. */ #define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) #define I2C_TRANS_COMPLETE_INT_CLR_M (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S) -#define I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001 +#define I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U #define I2C_TRANS_COMPLETE_INT_CLR_S 7 /** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; * Set this bit to clear the I2C_TIME_OUT_INT interrupt. */ #define I2C_TIME_OUT_INT_CLR (BIT(8)) #define I2C_TIME_OUT_INT_CLR_M (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S) -#define I2C_TIME_OUT_INT_CLR_V 0x00000001 +#define I2C_TIME_OUT_INT_CLR_V 0x00000001U #define I2C_TIME_OUT_INT_CLR_S 8 /** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; * Set this bit to clear the I2C_TRANS_START_INT interrupt. */ #define I2C_TRANS_START_INT_CLR (BIT(9)) #define I2C_TRANS_START_INT_CLR_M (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S) -#define I2C_TRANS_START_INT_CLR_V 0x00000001 +#define I2C_TRANS_START_INT_CLR_V 0x00000001U #define I2C_TRANS_START_INT_CLR_S 9 /** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. */ #define I2C_NACK_INT_CLR (BIT(10)) #define I2C_NACK_INT_CLR_M (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S) -#define I2C_NACK_INT_CLR_V 0x00000001 +#define I2C_NACK_INT_CLR_V 0x00000001U #define I2C_NACK_INT_CLR_S 10 /** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; * Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. */ #define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) #define I2C_TXFIFO_OVF_INT_CLR_M (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S) -#define I2C_TXFIFO_OVF_INT_CLR_V 0x00000001 +#define I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U #define I2C_TXFIFO_OVF_INT_CLR_S 11 /** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; * Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. */ #define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) #define I2C_RXFIFO_UDF_INT_CLR_M (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S) -#define I2C_RXFIFO_UDF_INT_CLR_V 0x00000001 +#define I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U #define I2C_RXFIFO_UDF_INT_CLR_S 12 /** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; * Set this bit to clear I2C_SCL_ST_TO_INT interrupt. */ #define I2C_SCL_ST_TO_INT_CLR (BIT(13)) #define I2C_SCL_ST_TO_INT_CLR_M (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S) -#define I2C_SCL_ST_TO_INT_CLR_V 0x00000001 +#define I2C_SCL_ST_TO_INT_CLR_V 0x00000001U #define I2C_SCL_ST_TO_INT_CLR_S 13 /** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; * Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. */ #define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) #define I2C_SCL_MAIN_ST_TO_INT_CLR_M (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S) -#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001 +#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U #define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 /** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; * Set this bit to clear I2C_DET_START_INT interrupt. */ #define I2C_DET_START_INT_CLR (BIT(15)) #define I2C_DET_START_INT_CLR_M (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S) -#define I2C_DET_START_INT_CLR_V 0x00000001 +#define I2C_DET_START_INT_CLR_V 0x00000001U #define I2C_DET_START_INT_CLR_S 15 /** I2C_INT_ENA_REG register @@ -548,112 +547,112 @@ extern "C" { */ #define I2C_RXFIFO_WM_INT_ENA (BIT(0)) #define I2C_RXFIFO_WM_INT_ENA_M (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S) -#define I2C_RXFIFO_WM_INT_ENA_V 0x00000001 +#define I2C_RXFIFO_WM_INT_ENA_V 0x00000001U #define I2C_RXFIFO_WM_INT_ENA_S 0 /** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; * The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. */ #define I2C_TXFIFO_WM_INT_ENA (BIT(1)) #define I2C_TXFIFO_WM_INT_ENA_M (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S) -#define I2C_TXFIFO_WM_INT_ENA_V 0x00000001 +#define I2C_TXFIFO_WM_INT_ENA_V 0x00000001U #define I2C_TXFIFO_WM_INT_ENA_S 1 /** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; * The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. */ #define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) #define I2C_RXFIFO_OVF_INT_ENA_M (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S) -#define I2C_RXFIFO_OVF_INT_ENA_V 0x00000001 +#define I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U #define I2C_RXFIFO_OVF_INT_ENA_S 2 /** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. */ #define I2C_END_DETECT_INT_ENA (BIT(3)) #define I2C_END_DETECT_INT_ENA_M (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S) -#define I2C_END_DETECT_INT_ENA_V 0x00000001 +#define I2C_END_DETECT_INT_ENA_V 0x00000001U #define I2C_END_DETECT_INT_ENA_S 3 /** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. */ #define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) #define I2C_BYTE_TRANS_DONE_INT_ENA_M (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S) -#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001 +#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U #define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 /** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; * The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. */ #define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) #define I2C_ARBITRATION_LOST_INT_ENA_M (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S) -#define I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001 +#define I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U #define I2C_ARBITRATION_LOST_INT_ENA_S 5 /** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; * The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. */ #define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) #define I2C_MST_TXFIFO_UDF_INT_ENA_M (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S) -#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001 +#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U #define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 /** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; * The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. */ #define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) #define I2C_TRANS_COMPLETE_INT_ENA_M (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S) -#define I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001 +#define I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U #define I2C_TRANS_COMPLETE_INT_ENA_S 7 /** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; * The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. */ #define I2C_TIME_OUT_INT_ENA (BIT(8)) #define I2C_TIME_OUT_INT_ENA_M (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S) -#define I2C_TIME_OUT_INT_ENA_V 0x00000001 +#define I2C_TIME_OUT_INT_ENA_V 0x00000001U #define I2C_TIME_OUT_INT_ENA_S 8 /** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; * The interrupt enable bit for the I2C_TRANS_START_INT interrupt. */ #define I2C_TRANS_START_INT_ENA (BIT(9)) #define I2C_TRANS_START_INT_ENA_M (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S) -#define I2C_TRANS_START_INT_ENA_V 0x00000001 +#define I2C_TRANS_START_INT_ENA_V 0x00000001U #define I2C_TRANS_START_INT_ENA_S 9 /** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. */ #define I2C_NACK_INT_ENA (BIT(10)) #define I2C_NACK_INT_ENA_M (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S) -#define I2C_NACK_INT_ENA_V 0x00000001 +#define I2C_NACK_INT_ENA_V 0x00000001U #define I2C_NACK_INT_ENA_S 10 /** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; * The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. */ #define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) #define I2C_TXFIFO_OVF_INT_ENA_M (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S) -#define I2C_TXFIFO_OVF_INT_ENA_V 0x00000001 +#define I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U #define I2C_TXFIFO_OVF_INT_ENA_S 11 /** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; * The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. */ #define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) #define I2C_RXFIFO_UDF_INT_ENA_M (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S) -#define I2C_RXFIFO_UDF_INT_ENA_V 0x00000001 +#define I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U #define I2C_RXFIFO_UDF_INT_ENA_S 12 /** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; * The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. */ #define I2C_SCL_ST_TO_INT_ENA (BIT(13)) #define I2C_SCL_ST_TO_INT_ENA_M (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S) -#define I2C_SCL_ST_TO_INT_ENA_V 0x00000001 +#define I2C_SCL_ST_TO_INT_ENA_V 0x00000001U #define I2C_SCL_ST_TO_INT_ENA_S 13 /** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; * The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. */ #define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) #define I2C_SCL_MAIN_ST_TO_INT_ENA_M (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S) -#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001 +#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U #define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 /** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; * The interrupt enable bit for I2C_DET_START_INT interrupt. */ #define I2C_DET_START_INT_ENA (BIT(15)) #define I2C_DET_START_INT_ENA_M (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S) -#define I2C_DET_START_INT_ENA_V 0x00000001 +#define I2C_DET_START_INT_ENA_V 0x00000001U #define I2C_DET_START_INT_ENA_S 15 /** I2C_INT_STATUS_REG register @@ -665,112 +664,112 @@ extern "C" { */ #define I2C_RXFIFO_WM_INT_ST (BIT(0)) #define I2C_RXFIFO_WM_INT_ST_M (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S) -#define I2C_RXFIFO_WM_INT_ST_V 0x00000001 +#define I2C_RXFIFO_WM_INT_ST_V 0x00000001U #define I2C_RXFIFO_WM_INT_ST_S 0 /** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; * The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. */ #define I2C_TXFIFO_WM_INT_ST (BIT(1)) #define I2C_TXFIFO_WM_INT_ST_M (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S) -#define I2C_TXFIFO_WM_INT_ST_V 0x00000001 +#define I2C_TXFIFO_WM_INT_ST_V 0x00000001U #define I2C_TXFIFO_WM_INT_ST_S 1 /** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; * The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. */ #define I2C_RXFIFO_OVF_INT_ST (BIT(2)) #define I2C_RXFIFO_OVF_INT_ST_M (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S) -#define I2C_RXFIFO_OVF_INT_ST_V 0x00000001 +#define I2C_RXFIFO_OVF_INT_ST_V 0x00000001U #define I2C_RXFIFO_OVF_INT_ST_S 2 /** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. */ #define I2C_END_DETECT_INT_ST (BIT(3)) #define I2C_END_DETECT_INT_ST_M (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S) -#define I2C_END_DETECT_INT_ST_V 0x00000001 +#define I2C_END_DETECT_INT_ST_V 0x00000001U #define I2C_END_DETECT_INT_ST_S 3 /** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. */ #define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) #define I2C_BYTE_TRANS_DONE_INT_ST_M (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S) -#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001 +#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U #define I2C_BYTE_TRANS_DONE_INT_ST_S 4 /** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; * The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. */ #define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) #define I2C_ARBITRATION_LOST_INT_ST_M (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S) -#define I2C_ARBITRATION_LOST_INT_ST_V 0x00000001 +#define I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U #define I2C_ARBITRATION_LOST_INT_ST_S 5 /** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; * The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. */ #define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) #define I2C_MST_TXFIFO_UDF_INT_ST_M (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S) -#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001 +#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U #define I2C_MST_TXFIFO_UDF_INT_ST_S 6 /** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; * The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. */ #define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) #define I2C_TRANS_COMPLETE_INT_ST_M (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S) -#define I2C_TRANS_COMPLETE_INT_ST_V 0x00000001 +#define I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U #define I2C_TRANS_COMPLETE_INT_ST_S 7 /** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; * The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. */ #define I2C_TIME_OUT_INT_ST (BIT(8)) #define I2C_TIME_OUT_INT_ST_M (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S) -#define I2C_TIME_OUT_INT_ST_V 0x00000001 +#define I2C_TIME_OUT_INT_ST_V 0x00000001U #define I2C_TIME_OUT_INT_ST_S 8 /** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; * The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. */ #define I2C_TRANS_START_INT_ST (BIT(9)) #define I2C_TRANS_START_INT_ST_M (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S) -#define I2C_TRANS_START_INT_ST_V 0x00000001 +#define I2C_TRANS_START_INT_ST_V 0x00000001U #define I2C_TRANS_START_INT_ST_S 9 /** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. */ #define I2C_NACK_INT_ST (BIT(10)) #define I2C_NACK_INT_ST_M (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S) -#define I2C_NACK_INT_ST_V 0x00000001 +#define I2C_NACK_INT_ST_V 0x00000001U #define I2C_NACK_INT_ST_S 10 /** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; * The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. */ #define I2C_TXFIFO_OVF_INT_ST (BIT(11)) #define I2C_TXFIFO_OVF_INT_ST_M (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S) -#define I2C_TXFIFO_OVF_INT_ST_V 0x00000001 +#define I2C_TXFIFO_OVF_INT_ST_V 0x00000001U #define I2C_TXFIFO_OVF_INT_ST_S 11 /** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; * The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. */ #define I2C_RXFIFO_UDF_INT_ST (BIT(12)) #define I2C_RXFIFO_UDF_INT_ST_M (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S) -#define I2C_RXFIFO_UDF_INT_ST_V 0x00000001 +#define I2C_RXFIFO_UDF_INT_ST_V 0x00000001U #define I2C_RXFIFO_UDF_INT_ST_S 12 /** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; * The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. */ #define I2C_SCL_ST_TO_INT_ST (BIT(13)) #define I2C_SCL_ST_TO_INT_ST_M (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S) -#define I2C_SCL_ST_TO_INT_ST_V 0x00000001 +#define I2C_SCL_ST_TO_INT_ST_V 0x00000001U #define I2C_SCL_ST_TO_INT_ST_S 13 /** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; * The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. */ #define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) #define I2C_SCL_MAIN_ST_TO_INT_ST_M (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S) -#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001 +#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U #define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 /** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; * The masked interrupt status bit for I2C_DET_START_INT interrupt. */ #define I2C_DET_START_INT_ST (BIT(15)) #define I2C_DET_START_INT_ST_M (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S) -#define I2C_DET_START_INT_ST_V 0x00000001 +#define I2C_DET_START_INT_ST_V 0x00000001U #define I2C_DET_START_INT_ST_S 15 /** I2C_SDA_HOLD_REG register @@ -781,9 +780,9 @@ extern "C" { * This register is used to configure the time to hold the data after the negative * edge of SCL, in I2C module clock cycles. */ -#define I2C_SDA_HOLD_TIME 0x000001FF +#define I2C_SDA_HOLD_TIME 0x000001FFU #define I2C_SDA_HOLD_TIME_M (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S) -#define I2C_SDA_HOLD_TIME_V 0x000001FF +#define I2C_SDA_HOLD_TIME_V 0x000001FFU #define I2C_SDA_HOLD_TIME_S 0 /** I2C_SDA_SAMPLE_REG register @@ -794,9 +793,9 @@ extern "C" { * This register is used to configure for how long SDA is sampled, in I2C module clock * cycles. */ -#define I2C_SDA_SAMPLE_TIME 0x000001FF +#define I2C_SDA_SAMPLE_TIME 0x000001FFU #define I2C_SDA_SAMPLE_TIME_M (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S) -#define I2C_SDA_SAMPLE_TIME_V 0x000001FF +#define I2C_SDA_SAMPLE_TIME_V 0x000001FFU #define I2C_SDA_SAMPLE_TIME_S 0 /** I2C_SCL_HIGH_PERIOD_REG register @@ -807,17 +806,17 @@ extern "C" { * This register is used to configure for how long SCL setup to high level and remains * high in master mode, in I2C module clock cycles. */ -#define I2C_SCL_HIGH_PERIOD 0x000001FF +#define I2C_SCL_HIGH_PERIOD 0x000001FFU #define I2C_SCL_HIGH_PERIOD_M (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S) -#define I2C_SCL_HIGH_PERIOD_V 0x000001FF +#define I2C_SCL_HIGH_PERIOD_V 0x000001FFU #define I2C_SCL_HIGH_PERIOD_S 0 /** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; * This register is used to configure for the SCL_FSM's waiting period for SCL high * level in master mode, in I2C module clock cycles. */ -#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007F +#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU #define I2C_SCL_WAIT_HIGH_PERIOD_M (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S) -#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007F +#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU #define I2C_SCL_WAIT_HIGH_PERIOD_S 9 /** I2C_SCL_START_HOLD_REG register @@ -829,9 +828,9 @@ extern "C" { * of SDA and the negative edge of SCL for a START condition, in I2C module clock * cycles. */ -#define I2C_SCL_START_HOLD_TIME 0x000001FF +#define I2C_SCL_START_HOLD_TIME 0x000001FFU #define I2C_SCL_START_HOLD_TIME_M (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S) -#define I2C_SCL_START_HOLD_TIME_V 0x000001FF +#define I2C_SCL_START_HOLD_TIME_V 0x000001FFU #define I2C_SCL_START_HOLD_TIME_S 0 /** I2C_SCL_RSTART_SETUP_REG register @@ -844,9 +843,9 @@ extern "C" { * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module * clock cycles. */ -#define I2C_SCL_RSTART_SETUP_TIME 0x000001FF +#define I2C_SCL_RSTART_SETUP_TIME 0x000001FFU #define I2C_SCL_RSTART_SETUP_TIME_M (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S) -#define I2C_SCL_RSTART_SETUP_TIME_V 0x000001FF +#define I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU #define I2C_SCL_RSTART_SETUP_TIME_S 0 /** I2C_SCL_STOP_HOLD_REG register @@ -858,9 +857,9 @@ extern "C" { * This register is used to configure the delay after the STOP condition, * in I2C module clock cycles. */ -#define I2C_SCL_STOP_HOLD_TIME 0x000001FF +#define I2C_SCL_STOP_HOLD_TIME 0x000001FFU #define I2C_SCL_STOP_HOLD_TIME_M (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S) -#define I2C_SCL_STOP_HOLD_TIME_V 0x000001FF +#define I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU #define I2C_SCL_STOP_HOLD_TIME_S 0 /** I2C_SCL_STOP_SETUP_REG register @@ -872,9 +871,9 @@ extern "C" { * This register is used to configure the time between the positive edge * of SCL and the positive edge of SDA, in I2C module clock cycles. */ -#define I2C_SCL_STOP_SETUP_TIME 0x000001FF +#define I2C_SCL_STOP_SETUP_TIME 0x000001FFU #define I2C_SCL_STOP_SETUP_TIME_M (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S) -#define I2C_SCL_STOP_SETUP_TIME_V 0x000001FF +#define I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU #define I2C_SCL_STOP_SETUP_TIME_S 0 /** I2C_FILTER_CFG_REG register @@ -885,31 +884,31 @@ extern "C" { * When a pulse on the SCL input has smaller width than this register value * in I2C module clock cycles, the I2C controller will ignore that pulse. */ -#define I2C_SCL_FILTER_THRES 0x0000000F +#define I2C_SCL_FILTER_THRES 0x0000000FU #define I2C_SCL_FILTER_THRES_M (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S) -#define I2C_SCL_FILTER_THRES_V 0x0000000F +#define I2C_SCL_FILTER_THRES_V 0x0000000FU #define I2C_SCL_FILTER_THRES_S 0 /** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; * When a pulse on the SDA input has smaller width than this register value * in I2C module clock cycles, the I2C controller will ignore that pulse. */ -#define I2C_SDA_FILTER_THRES 0x0000000F +#define I2C_SDA_FILTER_THRES 0x0000000FU #define I2C_SDA_FILTER_THRES_M (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S) -#define I2C_SDA_FILTER_THRES_V 0x0000000F +#define I2C_SDA_FILTER_THRES_V 0x0000000FU #define I2C_SDA_FILTER_THRES_S 4 /** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; * This is the filter enable bit for SCL. */ #define I2C_SCL_FILTER_EN (BIT(8)) #define I2C_SCL_FILTER_EN_M (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S) -#define I2C_SCL_FILTER_EN_V 0x00000001 +#define I2C_SCL_FILTER_EN_V 0x00000001U #define I2C_SCL_FILTER_EN_S 8 /** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; * This is the filter enable bit for SDA. */ #define I2C_SDA_FILTER_EN (BIT(9)) #define I2C_SDA_FILTER_EN_M (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S) -#define I2C_SDA_FILTER_EN_V 0x00000001 +#define I2C_SDA_FILTER_EN_V 0x00000001U #define I2C_SDA_FILTER_EN_S 9 /** I2C_CLK_CONF_REG register @@ -919,37 +918,37 @@ extern "C" { /** I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; * the integral part of the fractional divisor for i2c module */ -#define I2C_SCLK_DIV_NUM 0x000000FF +#define I2C_SCLK_DIV_NUM 0x000000FFU #define I2C_SCLK_DIV_NUM_M (I2C_SCLK_DIV_NUM_V << I2C_SCLK_DIV_NUM_S) -#define I2C_SCLK_DIV_NUM_V 0x000000FF +#define I2C_SCLK_DIV_NUM_V 0x000000FFU #define I2C_SCLK_DIV_NUM_S 0 /** I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; * the numerator of the fractional part of the fractional divisor for i2c module */ -#define I2C_SCLK_DIV_A 0x0000003F +#define I2C_SCLK_DIV_A 0x0000003FU #define I2C_SCLK_DIV_A_M (I2C_SCLK_DIV_A_V << I2C_SCLK_DIV_A_S) -#define I2C_SCLK_DIV_A_V 0x0000003F +#define I2C_SCLK_DIV_A_V 0x0000003FU #define I2C_SCLK_DIV_A_S 8 /** I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; * the denominator of the fractional part of the fractional divisor for i2c module */ -#define I2C_SCLK_DIV_B 0x0000003F +#define I2C_SCLK_DIV_B 0x0000003FU #define I2C_SCLK_DIV_B_M (I2C_SCLK_DIV_B_V << I2C_SCLK_DIV_B_S) -#define I2C_SCLK_DIV_B_V 0x0000003F +#define I2C_SCLK_DIV_B_V 0x0000003FU #define I2C_SCLK_DIV_B_S 14 /** I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. */ #define I2C_SCLK_SEL (BIT(20)) #define I2C_SCLK_SEL_M (I2C_SCLK_SEL_V << I2C_SCLK_SEL_S) -#define I2C_SCLK_SEL_V 0x00000001 +#define I2C_SCLK_SEL_V 0x00000001U #define I2C_SCLK_SEL_S 20 /** I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; * The clock switch for i2c module */ #define I2C_SCLK_ACTIVE (BIT(21)) #define I2C_SCLK_ACTIVE_M (I2C_SCLK_ACTIVE_V << I2C_SCLK_ACTIVE_S) -#define I2C_SCLK_ACTIVE_V 0x00000001 +#define I2C_SCLK_ACTIVE_V 0x00000001U #define I2C_SCLK_ACTIVE_S 21 /** I2C_COMD0_REG register @@ -964,9 +963,9 @@ extern "C" { * structure for more * Information. */ -#define I2C_COMMAND0 0x00003FFF +#define I2C_COMMAND0 0x00003FFFU #define I2C_COMMAND0_M (I2C_COMMAND0_V << I2C_COMMAND0_S) -#define I2C_COMMAND0_V 0x00003FFF +#define I2C_COMMAND0_V 0x00003FFFU #define I2C_COMMAND0_S 0 /** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 0 is done in I2C Master mode, this bit changes to high @@ -974,7 +973,7 @@ extern "C" { */ #define I2C_COMMAND0_DONE (BIT(31)) #define I2C_COMMAND0_DONE_M (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S) -#define I2C_COMMAND0_DONE_V 0x00000001 +#define I2C_COMMAND0_DONE_V 0x00000001U #define I2C_COMMAND0_DONE_S 31 /** I2C_COMD1_REG register @@ -989,9 +988,9 @@ extern "C" { * structure for more * Information. */ -#define I2C_COMMAND1 0x00003FFF +#define I2C_COMMAND1 0x00003FFFU #define I2C_COMMAND1_M (I2C_COMMAND1_V << I2C_COMMAND1_S) -#define I2C_COMMAND1_V 0x00003FFF +#define I2C_COMMAND1_V 0x00003FFFU #define I2C_COMMAND1_S 0 /** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 1 is done in I2C Master mode, this bit changes to high @@ -999,7 +998,7 @@ extern "C" { */ #define I2C_COMMAND1_DONE (BIT(31)) #define I2C_COMMAND1_DONE_M (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S) -#define I2C_COMMAND1_DONE_V 0x00000001 +#define I2C_COMMAND1_DONE_V 0x00000001U #define I2C_COMMAND1_DONE_S 31 /** I2C_COMD2_REG register @@ -1014,9 +1013,9 @@ extern "C" { * structure for more * Information. */ -#define I2C_COMMAND2 0x00003FFF +#define I2C_COMMAND2 0x00003FFFU #define I2C_COMMAND2_M (I2C_COMMAND2_V << I2C_COMMAND2_S) -#define I2C_COMMAND2_V 0x00003FFF +#define I2C_COMMAND2_V 0x00003FFFU #define I2C_COMMAND2_S 0 /** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 2 is done in I2C Master mode, this bit changes to high @@ -1024,7 +1023,7 @@ extern "C" { */ #define I2C_COMMAND2_DONE (BIT(31)) #define I2C_COMMAND2_DONE_M (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S) -#define I2C_COMMAND2_DONE_V 0x00000001 +#define I2C_COMMAND2_DONE_V 0x00000001U #define I2C_COMMAND2_DONE_S 31 /** I2C_COMD3_REG register @@ -1039,9 +1038,9 @@ extern "C" { * structure for more * Information. */ -#define I2C_COMMAND3 0x00003FFF +#define I2C_COMMAND3 0x00003FFFU #define I2C_COMMAND3_M (I2C_COMMAND3_V << I2C_COMMAND3_S) -#define I2C_COMMAND3_V 0x00003FFF +#define I2C_COMMAND3_V 0x00003FFFU #define I2C_COMMAND3_S 0 /** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 3 is done in I2C Master mode, this bit changes to high @@ -1049,7 +1048,7 @@ extern "C" { */ #define I2C_COMMAND3_DONE (BIT(31)) #define I2C_COMMAND3_DONE_M (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S) -#define I2C_COMMAND3_DONE_V 0x00000001 +#define I2C_COMMAND3_DONE_V 0x00000001U #define I2C_COMMAND3_DONE_S 31 /** I2C_COMD4_REG register @@ -1064,9 +1063,9 @@ extern "C" { * structure for more * Information. */ -#define I2C_COMMAND4 0x00003FFF +#define I2C_COMMAND4 0x00003FFFU #define I2C_COMMAND4_M (I2C_COMMAND4_V << I2C_COMMAND4_S) -#define I2C_COMMAND4_V 0x00003FFF +#define I2C_COMMAND4_V 0x00003FFFU #define I2C_COMMAND4_S 0 /** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 4 is done in I2C Master mode, this bit changes to high @@ -1074,7 +1073,7 @@ extern "C" { */ #define I2C_COMMAND4_DONE (BIT(31)) #define I2C_COMMAND4_DONE_M (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S) -#define I2C_COMMAND4_DONE_V 0x00000001 +#define I2C_COMMAND4_DONE_V 0x00000001U #define I2C_COMMAND4_DONE_S 31 /** I2C_COMD5_REG register @@ -1089,16 +1088,16 @@ extern "C" { * structure for more * Information. */ -#define I2C_COMMAND5 0x00003FFF +#define I2C_COMMAND5 0x00003FFFU #define I2C_COMMAND5_M (I2C_COMMAND5_V << I2C_COMMAND5_S) -#define I2C_COMMAND5_V 0x00003FFF +#define I2C_COMMAND5_V 0x00003FFFU #define I2C_COMMAND5_S 0 /** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 5 is done in I2C Master mode, this bit changes to high level. */ #define I2C_COMMAND5_DONE (BIT(31)) #define I2C_COMMAND5_DONE_M (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S) -#define I2C_COMMAND5_DONE_V 0x00000001 +#define I2C_COMMAND5_DONE_V 0x00000001U #define I2C_COMMAND5_DONE_S 31 /** I2C_COMD6_REG register @@ -1113,16 +1112,16 @@ extern "C" { * structure for more * Information. */ -#define I2C_COMMAND6 0x00003FFF +#define I2C_COMMAND6 0x00003FFFU #define I2C_COMMAND6_M (I2C_COMMAND6_V << I2C_COMMAND6_S) -#define I2C_COMMAND6_V 0x00003FFF +#define I2C_COMMAND6_V 0x00003FFFU #define I2C_COMMAND6_S 0 /** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 6 is done in I2C Master mode, this bit changes to high level. */ #define I2C_COMMAND6_DONE (BIT(31)) #define I2C_COMMAND6_DONE_M (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S) -#define I2C_COMMAND6_DONE_V 0x00000001 +#define I2C_COMMAND6_DONE_V 0x00000001U #define I2C_COMMAND6_DONE_S 31 /** I2C_COMD7_REG register @@ -1137,16 +1136,16 @@ extern "C" { * structure for more * Information. */ -#define I2C_COMMAND7 0x00003FFF +#define I2C_COMMAND7 0x00003FFFU #define I2C_COMMAND7_M (I2C_COMMAND7_V << I2C_COMMAND7_S) -#define I2C_COMMAND7_V 0x00003FFF +#define I2C_COMMAND7_V 0x00003FFFU #define I2C_COMMAND7_S 0 /** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 7 is done in I2C Master mode, this bit changes to high level. */ #define I2C_COMMAND7_DONE (BIT(31)) #define I2C_COMMAND7_DONE_M (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S) -#define I2C_COMMAND7_DONE_V 0x00000001 +#define I2C_COMMAND7_DONE_V 0x00000001U #define I2C_COMMAND7_DONE_S 31 /** I2C_SCL_ST_TIME_OUT_REG register @@ -1156,9 +1155,9 @@ extern "C" { /** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 */ -#define I2C_SCL_ST_TO_I2C 0x0000001F +#define I2C_SCL_ST_TO_I2C 0x0000001FU #define I2C_SCL_ST_TO_I2C_M (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S) -#define I2C_SCL_ST_TO_I2C_V 0x0000001F +#define I2C_SCL_ST_TO_I2C_V 0x0000001FU #define I2C_SCL_ST_TO_I2C_S 0 /** I2C_SCL_MAIN_ST_TIME_OUT_REG register @@ -1169,9 +1168,9 @@ extern "C" { * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more * than 23 */ -#define I2C_SCL_MAIN_ST_TO_I2C 0x0000001F +#define I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU #define I2C_SCL_MAIN_ST_TO_I2C_M (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S) -#define I2C_SCL_MAIN_ST_TO_I2C_V 0x0000001F +#define I2C_SCL_MAIN_ST_TO_I2C_V 0x0000001FU #define I2C_SCL_MAIN_ST_TO_I2C_S 0 /** I2C_SCL_SP_CONF_REG register @@ -1184,15 +1183,15 @@ extern "C" { */ #define I2C_SCL_RST_SLV_EN (BIT(0)) #define I2C_SCL_RST_SLV_EN_M (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S) -#define I2C_SCL_RST_SLV_EN_V 0x00000001 +#define I2C_SCL_RST_SLV_EN_V 0x00000001U #define I2C_SCL_RST_SLV_EN_S 0 /** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; * Configure the pulses of SCL generated in I2C master mode. Valid when * reg_scl_rst_slv_en is 1. */ -#define I2C_SCL_RST_SLV_NUM 0x0000001F +#define I2C_SCL_RST_SLV_NUM 0x0000001FU #define I2C_SCL_RST_SLV_NUM_M (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S) -#define I2C_SCL_RST_SLV_NUM_V 0x0000001F +#define I2C_SCL_RST_SLV_NUM_V 0x0000001FU #define I2C_SCL_RST_SLV_NUM_S 1 /** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power @@ -1200,7 +1199,7 @@ extern "C" { */ #define I2C_SCL_PD_EN (BIT(6)) #define I2C_SCL_PD_EN_M (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S) -#define I2C_SCL_PD_EN_V 0x00000001 +#define I2C_SCL_PD_EN_V 0x00000001U #define I2C_SCL_PD_EN_S 6 /** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power @@ -1208,7 +1207,7 @@ extern "C" { */ #define I2C_SDA_PD_EN (BIT(7)) #define I2C_SDA_PD_EN_M (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S) -#define I2C_SDA_PD_EN_V 0x00000001 +#define I2C_SDA_PD_EN_V 0x00000001U #define I2C_SDA_PD_EN_S 7 /** I2C_DATE_REG register @@ -1218,9 +1217,9 @@ extern "C" { /** I2C_DATE : R/W; bitpos: [31:0]; default: 34628163; * This is the the version register. */ -#define I2C_DATE 0xFFFFFFFF +#define I2C_DATE 0xFFFFFFFFU #define I2C_DATE_M (I2C_DATE_V << I2C_DATE_S) -#define I2C_DATE_V 0xFFFFFFFF +#define I2C_DATE_V 0xFFFFFFFFU #define I2C_DATE_S 0 /** I2C_TXFIFO_START_ADDR_REG register @@ -1230,9 +1229,9 @@ extern "C" { /** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; * This is the I2C txfifo first address. */ -#define I2C_TXFIFO_START_ADDR 0xFFFFFFFF +#define I2C_TXFIFO_START_ADDR 0xFFFFFFFFU #define I2C_TXFIFO_START_ADDR_M (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S) -#define I2C_TXFIFO_START_ADDR_V 0xFFFFFFFF +#define I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU #define I2C_TXFIFO_START_ADDR_S 0 /** I2C_RXFIFO_START_ADDR_REG register @@ -1242,9 +1241,9 @@ extern "C" { /** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; * This is the I2C rxfifo first address. */ -#define I2C_RXFIFO_START_ADDR 0xFFFFFFFF +#define I2C_RXFIFO_START_ADDR 0xFFFFFFFFU #define I2C_RXFIFO_START_ADDR_M (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S) -#define I2C_RXFIFO_START_ADDR_V 0xFFFFFFFF +#define I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU #define I2C_RXFIFO_START_ADDR_S 0 #ifdef __cplusplus diff --git a/components/soc/esp8684/include/soc/interrupt_core0_reg.h b/components/soc/esp8684/include/soc/interrupt_core0_reg.h index 5df4bdb3b7..b1a9500b06 100644 --- a/components/soc/esp8684/include/soc/interrupt_core0_reg.h +++ b/components/soc/esp8684/include/soc/interrupt_core0_reg.h @@ -1,696 +1,1026 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_INTERRUPT_CORE0_REG_H_ -#define _SOC_INTERRUPT_CORE0_REG_H_ - +#pragma once +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE - -#define INTERRUPT_CORE0_WIFI_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0) -/* INTERRUPT_CORE0_WIFI_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_WIFI_MAC_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_WIFI_MAC_INT_MAP_M ((INTERRUPT_CORE0_WIFI_MAC_INT_MAP_V)<<(INTERRUPT_CORE0_WIFI_MAC_INT_MAP_S)) -#define INTERRUPT_CORE0_WIFI_MAC_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_WIFI_MAC_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_WIFI_MAC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0) +/** INTERRUPT_CORE0_WIFI_MAC_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_WIFI_MAC_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_WIFI_MAC_INT_MAP_M (INTERRUPT_CORE0_WIFI_MAC_INT_MAP_V << INTERRUPT_CORE0_WIFI_MAC_INT_MAP_S) +#define INTERRUPT_CORE0_WIFI_MAC_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_WIFI_MAC_INT_MAP_S 0 -#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4) -/* INTERRUPT_CORE0_WIFI_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP 0x0000001F -#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_M ((INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V)<<(INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S)) -#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V 0x1F +/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x4) +/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP 0x0000001FU +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_M (INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V << INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S) +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V 0x0000001FU #define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S 0 -#define INTERRUPT_CORE0_WIFI_PWR_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8) -/* INTERRUPT_CORE0_WIFI_PWR_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_WIFI_PWR_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_WIFI_PWR_INT_MAP_M ((INTERRUPT_CORE0_WIFI_PWR_INT_MAP_V)<<(INTERRUPT_CORE0_WIFI_PWR_INT_MAP_S)) -#define INTERRUPT_CORE0_WIFI_PWR_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_WIFI_PWR_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_WIFI_PWR_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x8) +/** INTERRUPT_CORE0_WIFI_PWR_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_WIFI_PWR_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_WIFI_PWR_INT_MAP_M (INTERRUPT_CORE0_WIFI_PWR_INT_MAP_V << INTERRUPT_CORE0_WIFI_PWR_INT_MAP_S) +#define INTERRUPT_CORE0_WIFI_PWR_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_WIFI_PWR_INT_MAP_S 0 -#define INTERRUPT_CORE0_WIFI_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xC) -/* INTERRUPT_CORE0_WIFI_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_WIFI_BB_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_WIFI_BB_INT_MAP_M ((INTERRUPT_CORE0_WIFI_BB_INT_MAP_V)<<(INTERRUPT_CORE0_WIFI_BB_INT_MAP_S)) -#define INTERRUPT_CORE0_WIFI_BB_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_WIFI_BB_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_WIFI_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xc) +/** INTERRUPT_CORE0_WIFI_BB_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_WIFI_BB_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_WIFI_BB_INT_MAP_M (INTERRUPT_CORE0_WIFI_BB_INT_MAP_V << INTERRUPT_CORE0_WIFI_BB_INT_MAP_S) +#define INTERRUPT_CORE0_WIFI_BB_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_WIFI_BB_INT_MAP_S 0 -#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10) -/* INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_BT_MAC_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M ((INTERRUPT_CORE0_BT_MAC_INT_MAP_V)<<(INTERRUPT_CORE0_BT_MAC_INT_MAP_S)) -#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_BT_MAC_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x10) +/** INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_BT_MAC_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M (INTERRUPT_CORE0_BT_MAC_INT_MAP_V << INTERRUPT_CORE0_BT_MAC_INT_MAP_S) +#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_BT_MAC_INT_MAP_S 0 -#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14) -/* INTERRUPT_CORE0_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_BT_BB_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_BT_BB_INT_MAP_M ((INTERRUPT_CORE0_BT_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BT_BB_INT_MAP_S)) -#define INTERRUPT_CORE0_BT_BB_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_BT_BB_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x14) +/** INTERRUPT_CORE0_BT_BB_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_BT_BB_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_BT_BB_INT_MAP_M (INTERRUPT_CORE0_BT_BB_INT_MAP_V << INTERRUPT_CORE0_BT_BB_INT_MAP_S) +#define INTERRUPT_CORE0_BT_BB_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_BT_BB_INT_MAP_S 0 -#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18) -/* INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000001F -#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M ((INTERRUPT_CORE0_BT_BB_NMI_MAP_V)<<(INTERRUPT_CORE0_BT_BB_NMI_MAP_S)) -#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x1F +/** INTERRUPT_CORE0_BT_BB_NMI_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x18) +/** INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000001FU +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M (INTERRUPT_CORE0_BT_BB_NMI_MAP_V << INTERRUPT_CORE0_BT_BB_NMI_MAP_S) +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x0000001FU #define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0 -#define INTERRUPT_CORE0_LP_TIMER_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1C) -/* INTERRUPT_CORE0_LP_TIMER_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_LP_TIMER_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_LP_TIMER_INT_MAP_M ((INTERRUPT_CORE0_LP_TIMER_INT_MAP_V)<<(INTERRUPT_CORE0_LP_TIMER_INT_MAP_S)) -#define INTERRUPT_CORE0_LP_TIMER_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_LP_TIMER_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_LP_TIMER_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x1c) +/** INTERRUPT_CORE0_LP_TIMER_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_LP_TIMER_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_LP_TIMER_INT_MAP_M (INTERRUPT_CORE0_LP_TIMER_INT_MAP_V << INTERRUPT_CORE0_LP_TIMER_INT_MAP_S) +#define INTERRUPT_CORE0_LP_TIMER_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_LP_TIMER_INT_MAP_S 0 -#define INTERRUPT_CORE0_COEX_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20) -/* INTERRUPT_CORE0_COEX_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_COEX_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_COEX_INT_MAP_M ((INTERRUPT_CORE0_COEX_INT_MAP_V)<<(INTERRUPT_CORE0_COEX_INT_MAP_S)) -#define INTERRUPT_CORE0_COEX_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_COEX_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_COEX_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x20) +/** INTERRUPT_CORE0_COEX_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_COEX_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_COEX_INT_MAP_M (INTERRUPT_CORE0_COEX_INT_MAP_V << INTERRUPT_CORE0_COEX_INT_MAP_S) +#define INTERRUPT_CORE0_COEX_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_COEX_INT_MAP_S 0 -#define INTERRUPT_CORE0_BLE_TIMER_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24) -/* INTERRUPT_CORE0_BLE_TIMER_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_BLE_TIMER_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_BLE_TIMER_INT_MAP_M ((INTERRUPT_CORE0_BLE_TIMER_INT_MAP_V)<<(INTERRUPT_CORE0_BLE_TIMER_INT_MAP_S)) -#define INTERRUPT_CORE0_BLE_TIMER_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_BLE_TIMER_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_BLE_TIMER_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x24) +/** INTERRUPT_CORE0_BLE_TIMER_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_BLE_TIMER_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_BLE_TIMER_INT_MAP_M (INTERRUPT_CORE0_BLE_TIMER_INT_MAP_V << INTERRUPT_CORE0_BLE_TIMER_INT_MAP_S) +#define INTERRUPT_CORE0_BLE_TIMER_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_BLE_TIMER_INT_MAP_S 0 -#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28) -/* INTERRUPT_CORE0_BLE_SEC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_BLE_SEC_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_M ((INTERRUPT_CORE0_BLE_SEC_INT_MAP_V)<<(INTERRUPT_CORE0_BLE_SEC_INT_MAP_S)) -#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_BLE_SEC_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x28) +/** INTERRUPT_CORE0_BLE_SEC_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_BLE_SEC_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_M (INTERRUPT_CORE0_BLE_SEC_INT_MAP_V << INTERRUPT_CORE0_BLE_SEC_INT_MAP_S) +#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_BLE_SEC_INT_MAP_S 0 -#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2C) -/* INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_I2C_MST_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M ((INTERRUPT_CORE0_I2C_MST_INT_MAP_V)<<(INTERRUPT_CORE0_I2C_MST_INT_MAP_S)) -#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_I2C_MST_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x2c) +/** INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_I2C_MST_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M (INTERRUPT_CORE0_I2C_MST_INT_MAP_V << INTERRUPT_CORE0_I2C_MST_INT_MAP_S) +#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_I2C_MST_INT_MAP_S 0 -#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30) -/* INTERRUPT_CORE0_APB_CTRL_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_M ((INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V)<<(INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S)) -#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V 0x1F +/** INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x30) +/** INTERRUPT_CORE0_APB_CTRL_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP 0x0000001FU +#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_M (INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V << INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S) +#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V 0x0000001FU #define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S 0 -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34) -/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001F -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S)) -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x1F +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_BASE + 0x34) +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x0000001FU #define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0 -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38) -/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S)) -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x38) +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x0000001FU #define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 -#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3C) -/* INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_SPI_INTR_1_MAP 0x0000001F -#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M ((INTERRUPT_CORE0_SPI_INTR_1_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_1_MAP_S)) -#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V 0x1F +/** INTERRUPT_CORE0_SPI_INTR_1_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x3c) +/** INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_SPI_INTR_1_MAP 0x0000001FU +#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M (INTERRUPT_CORE0_SPI_INTR_1_MAP_V << INTERRUPT_CORE0_SPI_INTR_1_MAP_S) +#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V 0x0000001FU #define INTERRUPT_CORE0_SPI_INTR_1_MAP_S 0 -#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40) -/* INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_SPI_INTR_2_MAP 0x0000001F -#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M ((INTERRUPT_CORE0_SPI_INTR_2_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_2_MAP_S)) -#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V 0x1F +/** INTERRUPT_CORE0_SPI_INTR_2_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x40) +/** INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_SPI_INTR_2_MAP 0x0000001FU +#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M (INTERRUPT_CORE0_SPI_INTR_2_MAP_V << INTERRUPT_CORE0_SPI_INTR_2_MAP_S) +#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V 0x0000001FU #define INTERRUPT_CORE0_SPI_INTR_2_MAP_S 0 -#define INTERRUPT_CORE0_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44) -/* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_UART_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_UART_INTR_MAP_M ((INTERRUPT_CORE0_UART_INTR_MAP_V)<<(INTERRUPT_CORE0_UART_INTR_MAP_S)) -#define INTERRUPT_CORE0_UART_INTR_MAP_V 0x1F +/** INTERRUPT_CORE0_UART_INTR_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_UART_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x44) +/** INTERRUPT_CORE0_UART_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_UART_INTR_MAP 0x0000001FU +#define INTERRUPT_CORE0_UART_INTR_MAP_M (INTERRUPT_CORE0_UART_INTR_MAP_V << INTERRUPT_CORE0_UART_INTR_MAP_S) +#define INTERRUPT_CORE0_UART_INTR_MAP_V 0x0000001FU #define INTERRUPT_CORE0_UART_INTR_MAP_S 0 -#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48) -/* INTERRUPT_CORE0_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_UART1_INTR_MAP_M ((INTERRUPT_CORE0_UART1_INTR_MAP_V)<<(INTERRUPT_CORE0_UART1_INTR_MAP_S)) -#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x1F +/** INTERRUPT_CORE0_UART1_INTR_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x48) +/** INTERRUPT_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000001FU +#define INTERRUPT_CORE0_UART1_INTR_MAP_M (INTERRUPT_CORE0_UART1_INTR_MAP_V << INTERRUPT_CORE0_UART1_INTR_MAP_S) +#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x0000001FU #define INTERRUPT_CORE0_UART1_INTR_MAP_S 0 -#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4C) -/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_LEDC_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_LEDC_INT_MAP_M ((INTERRUPT_CORE0_LEDC_INT_MAP_V)<<(INTERRUPT_CORE0_LEDC_INT_MAP_S)) -#define INTERRUPT_CORE0_LEDC_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_LEDC_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x4c) +/** INTERRUPT_CORE0_LEDC_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_LEDC_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_LEDC_INT_MAP_M (INTERRUPT_CORE0_LEDC_INT_MAP_V << INTERRUPT_CORE0_LEDC_INT_MAP_S) +#define INTERRUPT_CORE0_LEDC_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_LEDC_INT_MAP_S 0 -#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50) -/* INTERRUPT_CORE0_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_EFUSE_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_EFUSE_INT_MAP_M ((INTERRUPT_CORE0_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE0_EFUSE_INT_MAP_S)) -#define INTERRUPT_CORE0_EFUSE_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_EFUSE_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x50) +/** INTERRUPT_CORE0_EFUSE_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_EFUSE_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_EFUSE_INT_MAP_M (INTERRUPT_CORE0_EFUSE_INT_MAP_V << INTERRUPT_CORE0_EFUSE_INT_MAP_S) +#define INTERRUPT_CORE0_EFUSE_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_EFUSE_INT_MAP_S 0 -#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54) -/* INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M ((INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V)<<(INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S)) -#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V 0x1F +/** INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x54) +/** INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP 0x0000001FU +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M (INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V << INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S) +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V 0x0000001FU #define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S 0 -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58) -/* INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M ((INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S)) -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x1F +/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x58) +/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000001FU +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M (INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V << INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x0000001FU #define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0 -#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5C) -/* INTERRUPT_CORE0_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_TG_T0_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_TG_T0_INT_MAP_M ((INTERRUPT_CORE0_TG_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T0_INT_MAP_S)) -#define INTERRUPT_CORE0_TG_T0_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_TG_T0_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x5c) +/** INTERRUPT_CORE0_TG_T0_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_TG_T0_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_TG_T0_INT_MAP_M (INTERRUPT_CORE0_TG_T0_INT_MAP_V << INTERRUPT_CORE0_TG_T0_INT_MAP_S) +#define INTERRUPT_CORE0_TG_T0_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_TG_T0_INT_MAP_S 0 -#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60) -/* INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_TG_WDT_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG_WDT_INT_MAP_S)) -#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_TG_WDT_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x60) +/** INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_TG_WDT_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M (INTERRUPT_CORE0_TG_WDT_INT_MAP_V << INTERRUPT_CORE0_TG_WDT_INT_MAP_S) +#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_TG_WDT_INT_MAP_S 0 -#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64) -/* INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CACHE_IA_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M ((INTERRUPT_CORE0_CACHE_IA_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_IA_INT_MAP_S)) -#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x64) +/** INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M (INTERRUPT_CORE0_CACHE_IA_INT_MAP_V << INTERRUPT_CORE0_CACHE_IA_INT_MAP_S) +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S 0 -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68) -/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S)) -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x68) +/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S 0 -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6C) -/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S)) -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x6c) +/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S 0 -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70) -/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S)) -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x70) +/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S 0 -#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74) -/* INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M ((INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V)<<(INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S)) -#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V 0x1F +/** INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x74) +/** INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP 0x0000001FU +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M (INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V << INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S) +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V 0x0000001FU #define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S 0 -#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78) -/* INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S)) -#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x78) +/** INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M (INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V << INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S) +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S 0 -#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7C) -/* INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S)) -#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x7c) +/** INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M (INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V << INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S) +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S 0 -#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80) -/* INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_APB_ADC_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M ((INTERRUPT_CORE0_APB_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_APB_ADC_INT_MAP_S)) -#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_APB_ADC_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x80) +/** INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_APB_ADC_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M (INTERRUPT_CORE0_APB_ADC_INT_MAP_V << INTERRUPT_CORE0_APB_ADC_INT_MAP_S) +#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_APB_ADC_INT_MAP_S 0 -#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84) -/* INTERRUPT_CORE0_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_DMA_CH0_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH0_INT_MAP_S)) -#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x84) +/** INTERRUPT_CORE0_DMA_CH0_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_DMA_CH0_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_M (INTERRUPT_CORE0_DMA_CH0_INT_MAP_V << INTERRUPT_CORE0_DMA_CH0_INT_MAP_S) +#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_DMA_CH0_INT_MAP_S 0 -#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88) -/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_SHA_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_SHA_INT_MAP_M ((INTERRUPT_CORE0_SHA_INT_MAP_V)<<(INTERRUPT_CORE0_SHA_INT_MAP_S)) -#define INTERRUPT_CORE0_SHA_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_SHA_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x88) +/** INTERRUPT_CORE0_SHA_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_SHA_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_SHA_INT_MAP_M (INTERRUPT_CORE0_SHA_INT_MAP_V << INTERRUPT_CORE0_SHA_INT_MAP_S) +#define INTERRUPT_CORE0_SHA_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_SHA_INT_MAP_S 0 -#define INTERRUPT_CORE0_ECC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8C) -/* INTERRUPT_CORE0_ECC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_ECC_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_ECC_INT_MAP_M ((INTERRUPT_CORE0_ECC_INT_MAP_V)<<(INTERRUPT_CORE0_ECC_INT_MAP_S)) -#define INTERRUPT_CORE0_ECC_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_ECC_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_ECC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x8c) +/** INTERRUPT_CORE0_ECC_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_ECC_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_ECC_INT_MAP_M (INTERRUPT_CORE0_ECC_INT_MAP_V << INTERRUPT_CORE0_ECC_INT_MAP_S) +#define INTERRUPT_CORE0_ECC_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_ECC_INT_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90) -/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)) -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x1F +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_BASE + 0x90) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x0000001FU #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94) -/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)) -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x1F +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x94) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x0000001FU #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98) -/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)) -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x1F +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x98) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x0000001FU #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9C) -/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)) -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x1F +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_BASE + 0x9c) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x0000001FU #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0 -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xA0) -/* INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M ((INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V)<<(INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S)) -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x1F +/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xa0) +/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001FU +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M (INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S) +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x0000001FU #define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0 -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xA4) -/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S)) -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F +/** INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xa4) +/** INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W; bitpos: [4:0]; + * default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001FU +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M (INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V << INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S) +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x0000001FU #define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0 -#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xA8) -/* INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M ((INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S)) -#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V 0x1F +/** INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG register + * register description + */ +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xa8) +/** INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP 0x0000001FU +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M (INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V << INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S) +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V 0x0000001FU #define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S 0 -#define INTERRUPT_CORE0_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xAC) -/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFF -#define INTERRUPT_CORE0_INTR_STATUS_0_M ((INTERRUPT_CORE0_INTR_STATUS_0_V)<<(INTERRUPT_CORE0_INTR_STATUS_0_S)) -#define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFF +/** INTERRUPT_CORE0_INTR_STATUS_REG_0_REG register + * register description + */ +#define INTERRUPT_CORE0_INTR_STATUS_REG_0_REG (DR_REG_INTERRUPT_BASE + 0xac) +/** INTERRUPT_CORE0_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFFU +#define INTERRUPT_CORE0_INTR_STATUS_0_M (INTERRUPT_CORE0_INTR_STATUS_0_V << INTERRUPT_CORE0_INTR_STATUS_0_S) +#define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFFU #define INTERRUPT_CORE0_INTR_STATUS_0_S 0 -#define INTERRUPT_CORE0_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xB0) -/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFF -#define INTERRUPT_CORE0_INTR_STATUS_1_M ((INTERRUPT_CORE0_INTR_STATUS_1_V)<<(INTERRUPT_CORE0_INTR_STATUS_1_S)) -#define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFF +/** INTERRUPT_CORE0_INTR_STATUS_REG_1_REG register + * register description + */ +#define INTERRUPT_CORE0_INTR_STATUS_REG_1_REG (DR_REG_INTERRUPT_BASE + 0xb0) +/** INTERRUPT_CORE0_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFFU +#define INTERRUPT_CORE0_INTR_STATUS_1_M (INTERRUPT_CORE0_INTR_STATUS_1_V << INTERRUPT_CORE0_INTR_STATUS_1_S) +#define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFFU #define INTERRUPT_CORE0_INTR_STATUS_1_S 0 -#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xB4) -/* INTERRUPT_CORE0_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CLK_EN (BIT(0)) -#define INTERRUPT_CORE0_CLK_EN_M (BIT(0)) -#define INTERRUPT_CORE0_CLK_EN_V 0x1 -#define INTERRUPT_CORE0_CLK_EN_S 0 +/** INTERRUPT_CORE0_CLOCK_GATE_REG register + * register description + */ +#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_BASE + 0xb4) +/** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1; + * Need add description + */ +#define INTERRUPT_CORE0_REG_CLK_EN (BIT(0)) +#define INTERRUPT_CORE0_REG_CLK_EN_M (INTERRUPT_CORE0_REG_CLK_EN_V << INTERRUPT_CORE0_REG_CLK_EN_S) +#define INTERRUPT_CORE0_REG_CLK_EN_V 0x00000001U +#define INTERRUPT_CORE0_REG_CLK_EN_S 0 -#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xB8) -/* INTERRUPT_CORE0_CPU_INT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_INT_ENABLE 0xFFFFFFFF -#define INTERRUPT_CORE0_CPU_INT_ENABLE_M ((INTERRUPT_CORE0_CPU_INT_ENABLE_V)<<(INTERRUPT_CORE0_CPU_INT_ENABLE_S)) -#define INTERRUPT_CORE0_CPU_INT_ENABLE_V 0xFFFFFFFF +/** INTERRUPT_CORE0_CPU_INT_ENABLE_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTERRUPT_BASE + 0xb8) +/** INTERRUPT_CORE0_CPU_INT_ENABLE : R/W; bitpos: [31:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_INT_ENABLE 0xFFFFFFFFU +#define INTERRUPT_CORE0_CPU_INT_ENABLE_M (INTERRUPT_CORE0_CPU_INT_ENABLE_V << INTERRUPT_CORE0_CPU_INT_ENABLE_S) +#define INTERRUPT_CORE0_CPU_INT_ENABLE_V 0xFFFFFFFFU #define INTERRUPT_CORE0_CPU_INT_ENABLE_S 0 -#define INTERRUPT_CORE0_CPU_INT_TYPE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xBC) -/* INTERRUPT_CORE0_CPU_INT_TYPE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_INT_TYPE 0xFFFFFFFF -#define INTERRUPT_CORE0_CPU_INT_TYPE_M ((INTERRUPT_CORE0_CPU_INT_TYPE_V)<<(INTERRUPT_CORE0_CPU_INT_TYPE_S)) -#define INTERRUPT_CORE0_CPU_INT_TYPE_V 0xFFFFFFFF +/** INTERRUPT_CORE0_CPU_INT_TYPE_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_TYPE_REG (DR_REG_INTERRUPT_BASE + 0xbc) +/** INTERRUPT_CORE0_CPU_INT_TYPE : R/W; bitpos: [31:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_INT_TYPE 0xFFFFFFFFU +#define INTERRUPT_CORE0_CPU_INT_TYPE_M (INTERRUPT_CORE0_CPU_INT_TYPE_V << INTERRUPT_CORE0_CPU_INT_TYPE_S) +#define INTERRUPT_CORE0_CPU_INT_TYPE_V 0xFFFFFFFFU #define INTERRUPT_CORE0_CPU_INT_TYPE_S 0 -#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xC0) -/* INTERRUPT_CORE0_CPU_INT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_INT_CLEAR 0xFFFFFFFF -#define INTERRUPT_CORE0_CPU_INT_CLEAR_M ((INTERRUPT_CORE0_CPU_INT_CLEAR_V)<<(INTERRUPT_CORE0_CPU_INT_CLEAR_S)) -#define INTERRUPT_CORE0_CPU_INT_CLEAR_V 0xFFFFFFFF +/** INTERRUPT_CORE0_CPU_INT_CLEAR_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTERRUPT_BASE + 0xc0) +/** INTERRUPT_CORE0_CPU_INT_CLEAR : R/W; bitpos: [31:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_INT_CLEAR 0xFFFFFFFFU +#define INTERRUPT_CORE0_CPU_INT_CLEAR_M (INTERRUPT_CORE0_CPU_INT_CLEAR_V << INTERRUPT_CORE0_CPU_INT_CLEAR_S) +#define INTERRUPT_CORE0_CPU_INT_CLEAR_V 0xFFFFFFFFU #define INTERRUPT_CORE0_CPU_INT_CLEAR_S 0 -#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xC4) -/* INTERRUPT_CORE0_CPU_INT_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS 0xFFFFFFFF -#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_M ((INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V)<<(INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S)) -#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V 0xFFFFFFFF +/** INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTERRUPT_BASE + 0xc4) +/** INTERRUPT_CORE0_CPU_INT_EIP_STATUS : RO; bitpos: [31:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS 0xFFFFFFFFU +#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_M (INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V << INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S) +#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V 0xFFFFFFFFU #define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xC8) -/* INTERRUPT_CORE0_CPU_PRI_0_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_0_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_0_MAP_M ((INTERRUPT_CORE0_CPU_PRI_0_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_0_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_0_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_0_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTERRUPT_BASE + 0xc8) +/** INTERRUPT_CORE0_CPU_PRI_0_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_0_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_0_MAP_M (INTERRUPT_CORE0_CPU_PRI_0_MAP_V << INTERRUPT_CORE0_CPU_PRI_0_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_0_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_0_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xCC) -/* INTERRUPT_CORE0_CPU_PRI_1_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_1_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_1_MAP_M ((INTERRUPT_CORE0_CPU_PRI_1_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_1_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_1_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_1_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTERRUPT_BASE + 0xcc) +/** INTERRUPT_CORE0_CPU_PRI_1_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_1_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_1_MAP_M (INTERRUPT_CORE0_CPU_PRI_1_MAP_V << INTERRUPT_CORE0_CPU_PRI_1_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_1_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_1_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xD0) -/* INTERRUPT_CORE0_CPU_PRI_2_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_2_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_2_MAP_M ((INTERRUPT_CORE0_CPU_PRI_2_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_2_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_2_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_2_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTERRUPT_BASE + 0xd0) +/** INTERRUPT_CORE0_CPU_PRI_2_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_2_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_2_MAP_M (INTERRUPT_CORE0_CPU_PRI_2_MAP_V << INTERRUPT_CORE0_CPU_PRI_2_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_2_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_2_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xD4) -/* INTERRUPT_CORE0_CPU_PRI_3_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_3_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_3_MAP_M ((INTERRUPT_CORE0_CPU_PRI_3_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_3_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_3_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_3_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTERRUPT_BASE + 0xd4) +/** INTERRUPT_CORE0_CPU_PRI_3_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_3_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_3_MAP_M (INTERRUPT_CORE0_CPU_PRI_3_MAP_V << INTERRUPT_CORE0_CPU_PRI_3_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_3_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_3_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xD8) -/* INTERRUPT_CORE0_CPU_PRI_4_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_4_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_4_MAP_M ((INTERRUPT_CORE0_CPU_PRI_4_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_4_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_4_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_4_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTERRUPT_BASE + 0xd8) +/** INTERRUPT_CORE0_CPU_PRI_4_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_4_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_4_MAP_M (INTERRUPT_CORE0_CPU_PRI_4_MAP_V << INTERRUPT_CORE0_CPU_PRI_4_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_4_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_4_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xDC) -/* INTERRUPT_CORE0_CPU_PRI_5_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_5_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_5_MAP_M ((INTERRUPT_CORE0_CPU_PRI_5_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_5_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_5_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_5_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTERRUPT_BASE + 0xdc) +/** INTERRUPT_CORE0_CPU_PRI_5_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_5_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_5_MAP_M (INTERRUPT_CORE0_CPU_PRI_5_MAP_V << INTERRUPT_CORE0_CPU_PRI_5_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_5_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_5_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xE0) -/* INTERRUPT_CORE0_CPU_PRI_6_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_6_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_6_MAP_M ((INTERRUPT_CORE0_CPU_PRI_6_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_6_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_6_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_6_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTERRUPT_BASE + 0xe0) +/** INTERRUPT_CORE0_CPU_PRI_6_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_6_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_6_MAP_M (INTERRUPT_CORE0_CPU_PRI_6_MAP_V << INTERRUPT_CORE0_CPU_PRI_6_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_6_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_6_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xE4) -/* INTERRUPT_CORE0_CPU_PRI_7_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_7_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_7_MAP_M ((INTERRUPT_CORE0_CPU_PRI_7_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_7_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_7_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_7_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTERRUPT_BASE + 0xe4) +/** INTERRUPT_CORE0_CPU_PRI_7_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_7_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_7_MAP_M (INTERRUPT_CORE0_CPU_PRI_7_MAP_V << INTERRUPT_CORE0_CPU_PRI_7_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_7_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_7_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xE8) -/* INTERRUPT_CORE0_CPU_PRI_8_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_8_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_8_MAP_M ((INTERRUPT_CORE0_CPU_PRI_8_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_8_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_8_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_8_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTERRUPT_BASE + 0xe8) +/** INTERRUPT_CORE0_CPU_PRI_8_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_8_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_8_MAP_M (INTERRUPT_CORE0_CPU_PRI_8_MAP_V << INTERRUPT_CORE0_CPU_PRI_8_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_8_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_8_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xEC) -/* INTERRUPT_CORE0_CPU_PRI_9_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_9_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_9_MAP_M ((INTERRUPT_CORE0_CPU_PRI_9_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_9_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_9_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_9_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTERRUPT_BASE + 0xec) +/** INTERRUPT_CORE0_CPU_PRI_9_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_9_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_9_MAP_M (INTERRUPT_CORE0_CPU_PRI_9_MAP_V << INTERRUPT_CORE0_CPU_PRI_9_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_9_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_9_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xF0) -/* INTERRUPT_CORE0_CPU_PRI_10_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_10_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_10_MAP_M ((INTERRUPT_CORE0_CPU_PRI_10_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_10_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_10_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_10_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTERRUPT_BASE + 0xf0) +/** INTERRUPT_CORE0_CPU_PRI_10_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_10_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_10_MAP_M (INTERRUPT_CORE0_CPU_PRI_10_MAP_V << INTERRUPT_CORE0_CPU_PRI_10_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_10_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_10_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xF4) -/* INTERRUPT_CORE0_CPU_PRI_11_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_11_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_11_MAP_M ((INTERRUPT_CORE0_CPU_PRI_11_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_11_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_11_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_11_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTERRUPT_BASE + 0xf4) +/** INTERRUPT_CORE0_CPU_PRI_11_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_11_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_11_MAP_M (INTERRUPT_CORE0_CPU_PRI_11_MAP_V << INTERRUPT_CORE0_CPU_PRI_11_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_11_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_11_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xF8) -/* INTERRUPT_CORE0_CPU_PRI_12_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_12_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_12_MAP_M ((INTERRUPT_CORE0_CPU_PRI_12_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_12_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_12_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_12_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTERRUPT_BASE + 0xf8) +/** INTERRUPT_CORE0_CPU_PRI_12_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_12_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_12_MAP_M (INTERRUPT_CORE0_CPU_PRI_12_MAP_V << INTERRUPT_CORE0_CPU_PRI_12_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_12_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_12_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xFC) -/* INTERRUPT_CORE0_CPU_PRI_13_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_13_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_13_MAP_M ((INTERRUPT_CORE0_CPU_PRI_13_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_13_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_13_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_13_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTERRUPT_BASE + 0xfc) +/** INTERRUPT_CORE0_CPU_PRI_13_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_13_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_13_MAP_M (INTERRUPT_CORE0_CPU_PRI_13_MAP_V << INTERRUPT_CORE0_CPU_PRI_13_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_13_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_13_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) -/* INTERRUPT_CORE0_CPU_PRI_14_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_14_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_14_MAP_M ((INTERRUPT_CORE0_CPU_PRI_14_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_14_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_14_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_14_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTERRUPT_BASE + 0x100) +/** INTERRUPT_CORE0_CPU_PRI_14_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_14_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_14_MAP_M (INTERRUPT_CORE0_CPU_PRI_14_MAP_V << INTERRUPT_CORE0_CPU_PRI_14_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_14_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_14_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104) -/* INTERRUPT_CORE0_CPU_PRI_15_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_15_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_15_MAP_M ((INTERRUPT_CORE0_CPU_PRI_15_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_15_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_15_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_15_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTERRUPT_BASE + 0x104) +/** INTERRUPT_CORE0_CPU_PRI_15_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_15_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_15_MAP_M (INTERRUPT_CORE0_CPU_PRI_15_MAP_V << INTERRUPT_CORE0_CPU_PRI_15_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_15_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_15_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108) -/* INTERRUPT_CORE0_CPU_PRI_16_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_16_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_16_MAP_M ((INTERRUPT_CORE0_CPU_PRI_16_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_16_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_16_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_16_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTERRUPT_BASE + 0x108) +/** INTERRUPT_CORE0_CPU_PRI_16_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_16_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_16_MAP_M (INTERRUPT_CORE0_CPU_PRI_16_MAP_V << INTERRUPT_CORE0_CPU_PRI_16_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_16_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_16_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10C) -/* INTERRUPT_CORE0_CPU_PRI_17_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_17_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_17_MAP_M ((INTERRUPT_CORE0_CPU_PRI_17_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_17_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_17_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_17_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTERRUPT_BASE + 0x10c) +/** INTERRUPT_CORE0_CPU_PRI_17_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_17_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_17_MAP_M (INTERRUPT_CORE0_CPU_PRI_17_MAP_V << INTERRUPT_CORE0_CPU_PRI_17_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_17_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_17_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110) -/* INTERRUPT_CORE0_CPU_PRI_18_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_18_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_18_MAP_M ((INTERRUPT_CORE0_CPU_PRI_18_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_18_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_18_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_18_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTERRUPT_BASE + 0x110) +/** INTERRUPT_CORE0_CPU_PRI_18_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_18_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_18_MAP_M (INTERRUPT_CORE0_CPU_PRI_18_MAP_V << INTERRUPT_CORE0_CPU_PRI_18_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_18_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_18_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114) -/* INTERRUPT_CORE0_CPU_PRI_19_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_19_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_19_MAP_M ((INTERRUPT_CORE0_CPU_PRI_19_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_19_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_19_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_19_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTERRUPT_BASE + 0x114) +/** INTERRUPT_CORE0_CPU_PRI_19_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_19_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_19_MAP_M (INTERRUPT_CORE0_CPU_PRI_19_MAP_V << INTERRUPT_CORE0_CPU_PRI_19_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_19_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_19_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118) -/* INTERRUPT_CORE0_CPU_PRI_20_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_20_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_20_MAP_M ((INTERRUPT_CORE0_CPU_PRI_20_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_20_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_20_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_20_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTERRUPT_BASE + 0x118) +/** INTERRUPT_CORE0_CPU_PRI_20_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_20_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_20_MAP_M (INTERRUPT_CORE0_CPU_PRI_20_MAP_V << INTERRUPT_CORE0_CPU_PRI_20_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_20_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_20_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11C) -/* INTERRUPT_CORE0_CPU_PRI_21_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_21_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_21_MAP_M ((INTERRUPT_CORE0_CPU_PRI_21_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_21_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_21_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_21_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTERRUPT_BASE + 0x11c) +/** INTERRUPT_CORE0_CPU_PRI_21_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_21_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_21_MAP_M (INTERRUPT_CORE0_CPU_PRI_21_MAP_V << INTERRUPT_CORE0_CPU_PRI_21_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_21_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_21_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120) -/* INTERRUPT_CORE0_CPU_PRI_22_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_22_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_22_MAP_M ((INTERRUPT_CORE0_CPU_PRI_22_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_22_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_22_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_22_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTERRUPT_BASE + 0x120) +/** INTERRUPT_CORE0_CPU_PRI_22_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_22_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_22_MAP_M (INTERRUPT_CORE0_CPU_PRI_22_MAP_V << INTERRUPT_CORE0_CPU_PRI_22_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_22_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_22_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124) -/* INTERRUPT_CORE0_CPU_PRI_23_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_23_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_23_MAP_M ((INTERRUPT_CORE0_CPU_PRI_23_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_23_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_23_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_23_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTERRUPT_BASE + 0x124) +/** INTERRUPT_CORE0_CPU_PRI_23_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_23_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_23_MAP_M (INTERRUPT_CORE0_CPU_PRI_23_MAP_V << INTERRUPT_CORE0_CPU_PRI_23_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_23_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_23_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128) -/* INTERRUPT_CORE0_CPU_PRI_24_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_24_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_24_MAP_M ((INTERRUPT_CORE0_CPU_PRI_24_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_24_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_24_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_24_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTERRUPT_BASE + 0x128) +/** INTERRUPT_CORE0_CPU_PRI_24_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_24_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_24_MAP_M (INTERRUPT_CORE0_CPU_PRI_24_MAP_V << INTERRUPT_CORE0_CPU_PRI_24_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_24_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_24_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12C) -/* INTERRUPT_CORE0_CPU_PRI_25_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_25_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_25_MAP_M ((INTERRUPT_CORE0_CPU_PRI_25_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_25_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_25_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_25_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTERRUPT_BASE + 0x12c) +/** INTERRUPT_CORE0_CPU_PRI_25_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_25_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_25_MAP_M (INTERRUPT_CORE0_CPU_PRI_25_MAP_V << INTERRUPT_CORE0_CPU_PRI_25_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_25_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_25_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130) -/* INTERRUPT_CORE0_CPU_PRI_26_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_26_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_26_MAP_M ((INTERRUPT_CORE0_CPU_PRI_26_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_26_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_26_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_26_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTERRUPT_BASE + 0x130) +/** INTERRUPT_CORE0_CPU_PRI_26_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_26_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_26_MAP_M (INTERRUPT_CORE0_CPU_PRI_26_MAP_V << INTERRUPT_CORE0_CPU_PRI_26_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_26_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_26_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134) -/* INTERRUPT_CORE0_CPU_PRI_27_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_27_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_27_MAP_M ((INTERRUPT_CORE0_CPU_PRI_27_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_27_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_27_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_27_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTERRUPT_BASE + 0x134) +/** INTERRUPT_CORE0_CPU_PRI_27_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_27_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_27_MAP_M (INTERRUPT_CORE0_CPU_PRI_27_MAP_V << INTERRUPT_CORE0_CPU_PRI_27_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_27_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_27_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138) -/* INTERRUPT_CORE0_CPU_PRI_28_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_28_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_28_MAP_M ((INTERRUPT_CORE0_CPU_PRI_28_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_28_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_28_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_28_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTERRUPT_BASE + 0x138) +/** INTERRUPT_CORE0_CPU_PRI_28_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_28_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_28_MAP_M (INTERRUPT_CORE0_CPU_PRI_28_MAP_V << INTERRUPT_CORE0_CPU_PRI_28_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_28_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_28_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13C) -/* INTERRUPT_CORE0_CPU_PRI_29_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_29_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_29_MAP_M ((INTERRUPT_CORE0_CPU_PRI_29_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_29_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_29_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_29_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTERRUPT_BASE + 0x13c) +/** INTERRUPT_CORE0_CPU_PRI_29_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_29_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_29_MAP_M (INTERRUPT_CORE0_CPU_PRI_29_MAP_V << INTERRUPT_CORE0_CPU_PRI_29_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_29_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_29_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140) -/* INTERRUPT_CORE0_CPU_PRI_30_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_30_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_30_MAP_M ((INTERRUPT_CORE0_CPU_PRI_30_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_30_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_30_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_30_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTERRUPT_BASE + 0x140) +/** INTERRUPT_CORE0_CPU_PRI_30_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_30_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_30_MAP_M (INTERRUPT_CORE0_CPU_PRI_30_MAP_V << INTERRUPT_CORE0_CPU_PRI_30_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_30_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_30_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144) -/* INTERRUPT_CORE0_CPU_PRI_31_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_PRI_31_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_31_MAP_M ((INTERRUPT_CORE0_CPU_PRI_31_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_31_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_31_MAP_V 0xF +/** INTERRUPT_CORE0_CPU_INT_PRI_31_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTERRUPT_BASE + 0x144) +/** INTERRUPT_CORE0_CPU_PRI_31_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_PRI_31_MAP 0x0000000FU +#define INTERRUPT_CORE0_CPU_PRI_31_MAP_M (INTERRUPT_CORE0_CPU_PRI_31_MAP_V << INTERRUPT_CORE0_CPU_PRI_31_MAP_S) +#define INTERRUPT_CORE0_CPU_PRI_31_MAP_V 0x0000000FU #define INTERRUPT_CORE0_CPU_PRI_31_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_THRESH_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148) -/* INTERRUPT_CORE0_CPU_INT_THRESH : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_CPU_INT_THRESH 0x0000000F -#define INTERRUPT_CORE0_CPU_INT_THRESH_M ((INTERRUPT_CORE0_CPU_INT_THRESH_V)<<(INTERRUPT_CORE0_CPU_INT_THRESH_S)) -#define INTERRUPT_CORE0_CPU_INT_THRESH_V 0xF +/** INTERRUPT_CORE0_CPU_INT_THRESH_REG register + * register description + */ +#define INTERRUPT_CORE0_CPU_INT_THRESH_REG (DR_REG_INTERRUPT_BASE + 0x148) +/** INTERRUPT_CORE0_CPU_INT_THRESH : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTERRUPT_CORE0_CPU_INT_THRESH 0x0000000FU +#define INTERRUPT_CORE0_CPU_INT_THRESH_M (INTERRUPT_CORE0_CPU_INT_THRESH_V << INTERRUPT_CORE0_CPU_INT_THRESH_S) +#define INTERRUPT_CORE0_CPU_INT_THRESH_V 0x0000000FU #define INTERRUPT_CORE0_CPU_INT_THRESH_S 0 -#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC) -/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2108190 ; */ -/*description: Need add description.*/ -#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFF -#define INTERRUPT_CORE0_INTERRUPT_DATE_M ((INTERRUPT_CORE0_INTERRUPT_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_DATE_S)) -#define INTERRUPT_CORE0_INTERRUPT_DATE_V 0xFFFFFFF -#define INTERRUPT_CORE0_INTERRUPT_DATE_S 0 +/** INTERRUPT_CORE0_INTERRUPT_REG_DATE_REG register + * register description + */ +#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_BASE + 0x7fc) +/** INTERRUPT_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 34636176; + * Need add description + */ +#define INTERRUPT_CORE0_INTERRUPT_REG_DATE 0x0FFFFFFFU +#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_M (INTERRUPT_CORE0_INTERRUPT_REG_DATE_V << INTERRUPT_CORE0_INTERRUPT_REG_DATE_S) +#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_V 0x0FFFFFFFU +#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_S 0 #define INTC_INT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4) + #ifdef __cplusplus } #endif - - - -#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */ diff --git a/components/soc/esp8684/include/soc/periph_defs.h b/components/soc/esp8684/include/soc/periph_defs.h index 0b1a6efc88..17a58a8f71 100644 --- a/components/soc/esp8684/include/soc/periph_defs.h +++ b/components/soc/esp8684/include/soc/periph_defs.h @@ -14,26 +14,20 @@ typedef enum { PERIPH_LEDC_MODULE = 0, PERIPH_UART0_MODULE, PERIPH_UART1_MODULE, - PERIPH_USB_DEVICE_MODULE, PERIPH_I2C0_MODULE, PERIPH_TIMG0_MODULE, PERIPH_TIMG1_MODULE, //No timg1 on esp8684, please remove TODO: IDF-3825 PERIPH_UHCI0_MODULE, - PERIPH_RMT_MODULE, PERIPH_SPI_MODULE, //SPI1 PERIPH_SPI2_MODULE, //SPI2 - PERIPH_TWAI_MODULE, PERIPH_RNG_MODULE, PERIPH_WIFI_MODULE, PERIPH_BT_MODULE, PERIPH_WIFI_BT_COMMON_MODULE, PERIPH_BT_BASEBAND_MODULE, PERIPH_BT_LC_MODULE, - PERIPH_RSA_MODULE, PERIPH_AES_MODULE, PERIPH_SHA_MODULE, - PERIPH_HMAC_MODULE, - PERIPH_DS_MODULE, PERIPH_GDMA_MODULE, PERIPH_SYSTIMER_MODULE, PERIPH_SARADC_MODULE, diff --git a/components/soc/esp8684/include/soc/rtc.h b/components/soc/esp8684/include/soc/rtc.h index 6fd177c442..99859a3641 100644 --- a/components/soc/esp8684/include/soc/rtc.h +++ b/components/soc/esp8684/include/soc/rtc.h @@ -588,7 +588,6 @@ typedef struct { uint32_t dig_fpu : 1; //!< Set to 1 to power UP digital part in sleep uint32_t rtc_fpu : 1; //!< Set to 1 to power UP RTC memories in sleep uint32_t cpu_fpu : 1; //!< Set to 1 to power UP digital memories and CPU in sleep - uint32_t i2s_fpu : 1; //!< Set to 1 to power UP I2S in sleep uint32_t bb_fpu : 1; //!< Set to 1 to power UP WiFi in sleep uint32_t nrx_fpu : 1; //!< Set to 1 to power UP WiFi in sleep uint32_t fe_fpu : 1; //!< Set to 1 to power UP WiFi in sleep @@ -603,7 +602,6 @@ typedef struct { .dig_fpu = (val), \ .rtc_fpu = (val), \ .cpu_fpu = (val), \ - .i2s_fpu = (val), \ .bb_fpu = (val), \ .nrx_fpu = (val), \ .fe_fpu = (val), \ diff --git a/components/soc/esp8684/include/soc/rtc_i2c_reg.h b/components/soc/esp8684/include/soc/rtc_i2c_reg.h deleted file mode 100644 index 50ce570198..0000000000 --- a/components/soc/esp8684/include/soc/rtc_i2c_reg.h +++ /dev/null @@ -1,676 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_RTC_I2C_REG_H_ -#define _SOC_RTC_I2C_REG_H_ - - -#ifdef __cplusplus -extern "C" { -#endif -#include "soc.h" -#define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0000) -/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */ -/*description: time period that scl = 0*/ -#define RTC_I2C_SCL_LOW_PERIOD 0x000FFFFF -#define RTC_I2C_SCL_LOW_PERIOD_M ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S)) -#define RTC_I2C_SCL_LOW_PERIOD_V 0xFFFFF -#define RTC_I2C_SCL_LOW_PERIOD_S 0 - -#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x0004) -/* RTC_I2C_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: rtc i2c reg clk gating*/ -#define RTC_I2C_CLK_EN (BIT(31)) -#define RTC_I2C_CLK_EN_M (BIT(31)) -#define RTC_I2C_CLK_EN_V 0x1 -#define RTC_I2C_CLK_EN_S 31 -/* RTC_I2C_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: rtc i2c sw reset*/ -#define RTC_I2C_RESET (BIT(30)) -#define RTC_I2C_RESET_M (BIT(30)) -#define RTC_I2C_RESET_V 0x1 -#define RTC_I2C_RESET_S 30 -/* RTC_I2C_CTRL_CLK_GATE_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define RTC_I2C_CTRL_CLK_GATE_EN (BIT(29)) -#define RTC_I2C_CTRL_CLK_GATE_EN_M (BIT(29)) -#define RTC_I2C_CTRL_CLK_GATE_EN_V 0x1 -#define RTC_I2C_CTRL_CLK_GATE_EN_S 29 -/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: receive lsb first*/ -#define RTC_I2C_RX_LSB_FIRST (BIT(5)) -#define RTC_I2C_RX_LSB_FIRST_M (BIT(5)) -#define RTC_I2C_RX_LSB_FIRST_V 0x1 -#define RTC_I2C_RX_LSB_FIRST_S 5 -/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: transit lsb first*/ -#define RTC_I2C_TX_LSB_FIRST (BIT(4)) -#define RTC_I2C_TX_LSB_FIRST_M (BIT(4)) -#define RTC_I2C_TX_LSB_FIRST_V 0x1 -#define RTC_I2C_TX_LSB_FIRST_S 4 -/* RTC_I2C_TRANS_START : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: force start*/ -#define RTC_I2C_TRANS_START (BIT(3)) -#define RTC_I2C_TRANS_START_M (BIT(3)) -#define RTC_I2C_TRANS_START_V 0x1 -#define RTC_I2C_TRANS_START_S 3 -/* RTC_I2C_MS_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: 1=master 0=slave*/ -#define RTC_I2C_MS_MODE (BIT(2)) -#define RTC_I2C_MS_MODE_M (BIT(2)) -#define RTC_I2C_MS_MODE_V 0x1 -#define RTC_I2C_MS_MODE_S 2 -/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: 1=push pull 0=open drain*/ -#define RTC_I2C_SCL_FORCE_OUT (BIT(1)) -#define RTC_I2C_SCL_FORCE_OUT_M (BIT(1)) -#define RTC_I2C_SCL_FORCE_OUT_V 0x1 -#define RTC_I2C_SCL_FORCE_OUT_S 1 -/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: 1=push pull 0=open drain*/ -#define RTC_I2C_SDA_FORCE_OUT (BIT(0)) -#define RTC_I2C_SDA_FORCE_OUT_M (BIT(0)) -#define RTC_I2C_SDA_FORCE_OUT_V 0x1 -#define RTC_I2C_SDA_FORCE_OUT_S 0 - -#define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x0008) -/* RTC_I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ -/*description: scl last status*/ -#define RTC_I2C_SCL_STATE_LAST 0x00000007 -#define RTC_I2C_SCL_STATE_LAST_M ((RTC_I2C_SCL_STATE_LAST_V)<<(RTC_I2C_SCL_STATE_LAST_S)) -#define RTC_I2C_SCL_STATE_LAST_V 0x7 -#define RTC_I2C_SCL_STATE_LAST_S 28 -/* RTC_I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ -/*description: i2c last main status*/ -#define RTC_I2C_SCL_MAIN_STATE_LAST 0x00000007 -#define RTC_I2C_SCL_MAIN_STATE_LAST_M ((RTC_I2C_SCL_MAIN_STATE_LAST_V)<<(RTC_I2C_SCL_MAIN_STATE_LAST_S)) -#define RTC_I2C_SCL_MAIN_STATE_LAST_V 0x7 -#define RTC_I2C_SCL_MAIN_STATE_LAST_S 24 -/* RTC_I2C_SHIFT : RO ;bitpos:[23:16] ;default: 8'b0 ; */ -/*description: shifter content*/ -#define RTC_I2C_SHIFT 0x000000FF -#define RTC_I2C_SHIFT_M ((RTC_I2C_SHIFT_V)<<(RTC_I2C_SHIFT_S)) -#define RTC_I2C_SHIFT_V 0xFF -#define RTC_I2C_SHIFT_S 16 -/* RTC_I2C_OP_CNT : RO ;bitpos:[7:6] ;default: 2'b0 ; */ -/*description: which operation is working*/ -#define RTC_I2C_OP_CNT 0x00000003 -#define RTC_I2C_OP_CNT_M ((RTC_I2C_OP_CNT_V)<<(RTC_I2C_OP_CNT_S)) -#define RTC_I2C_OP_CNT_V 0x3 -#define RTC_I2C_OP_CNT_S 6 -/* RTC_I2C_BYTE_TRANS : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: One byte transit done*/ -#define RTC_I2C_BYTE_TRANS (BIT(5)) -#define RTC_I2C_BYTE_TRANS_M (BIT(5)) -#define RTC_I2C_BYTE_TRANS_V 0x1 -#define RTC_I2C_BYTE_TRANS_S 5 -/* RTC_I2C_SLAVE_ADDRESSED : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: slave reg sub address*/ -#define RTC_I2C_SLAVE_ADDRESSED (BIT(4)) -#define RTC_I2C_SLAVE_ADDRESSED_M (BIT(4)) -#define RTC_I2C_SLAVE_ADDRESSED_V 0x1 -#define RTC_I2C_SLAVE_ADDRESSED_S 4 -/* RTC_I2C_BUS_BUSY : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: bus is busy*/ -#define RTC_I2C_BUS_BUSY (BIT(3)) -#define RTC_I2C_BUS_BUSY_M (BIT(3)) -#define RTC_I2C_BUS_BUSY_V 0x1 -#define RTC_I2C_BUS_BUSY_S 3 -/* RTC_I2C_ARB_LOST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: arbitration is lost*/ -#define RTC_I2C_ARB_LOST (BIT(2)) -#define RTC_I2C_ARB_LOST_M (BIT(2)) -#define RTC_I2C_ARB_LOST_V 0x1 -#define RTC_I2C_ARB_LOST_S 2 -/* RTC_I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: slave read or write*/ -#define RTC_I2C_SLAVE_RW (BIT(1)) -#define RTC_I2C_SLAVE_RW_M (BIT(1)) -#define RTC_I2C_SLAVE_RW_V 0x1 -#define RTC_I2C_SLAVE_RW_S 1 -/* RTC_I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: ack response*/ -#define RTC_I2C_ACK_REC (BIT(0)) -#define RTC_I2C_ACK_REC_M (BIT(0)) -#define RTC_I2C_ACK_REC_V 0x1 -#define RTC_I2C_ACK_REC_S 0 - -#define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0x000c) -/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'h10000 ; */ -/*description: time out threshold*/ -#define RTC_I2C_TIMEOUT 0x000FFFFF -#define RTC_I2C_TIMEOUT_M ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S)) -#define RTC_I2C_TIMEOUT_V 0xFFFFF -#define RTC_I2C_TIMEOUT_S 0 - -#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x0010) -/* RTC_I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: i2c 10bit mode enable*/ -#define RTC_I2C_ADDR_10BIT_EN (BIT(31)) -#define RTC_I2C_ADDR_10BIT_EN_M (BIT(31)) -#define RTC_I2C_ADDR_10BIT_EN_V 0x1 -#define RTC_I2C_ADDR_10BIT_EN_S 31 -/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ -/*description: slave address*/ -#define RTC_I2C_SLAVE_ADDR 0x00007FFF -#define RTC_I2C_SLAVE_ADDR_M ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S)) -#define RTC_I2C_SLAVE_ADDR_V 0x7FFF -#define RTC_I2C_SLAVE_ADDR_S 0 - -#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x0014) -/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */ -/*description: time period that scl = 1*/ -#define RTC_I2C_SCL_HIGH_PERIOD 0x000FFFFF -#define RTC_I2C_SCL_HIGH_PERIOD_M ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S)) -#define RTC_I2C_SCL_HIGH_PERIOD_V 0xFFFFF -#define RTC_I2C_SCL_HIGH_PERIOD_S 0 - -#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x0018) -/* RTC_I2C_SDA_DUTY_NUM : R/W ;bitpos:[19:0] ;default: 20'h10 ; */ -/*description: time period for SDA to toggle after SCL goes low*/ -#define RTC_I2C_SDA_DUTY_NUM 0x000FFFFF -#define RTC_I2C_SDA_DUTY_NUM_M ((RTC_I2C_SDA_DUTY_NUM_V)<<(RTC_I2C_SDA_DUTY_NUM_S)) -#define RTC_I2C_SDA_DUTY_NUM_V 0xFFFFF -#define RTC_I2C_SDA_DUTY_NUM_S 0 - -#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x001c) -/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */ -/*description: time period for SCL to toggle after I2C start is triggered*/ -#define RTC_I2C_SCL_START_PERIOD 0x000FFFFF -#define RTC_I2C_SCL_START_PERIOD_M ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S)) -#define RTC_I2C_SCL_START_PERIOD_V 0xFFFFF -#define RTC_I2C_SCL_START_PERIOD_S 0 - -#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0020) -/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */ -/*description: time period for SCL to stop after I2C end is triggered*/ -#define RTC_I2C_SCL_STOP_PERIOD 0x000FFFFF -#define RTC_I2C_SCL_STOP_PERIOD_M ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S)) -#define RTC_I2C_SCL_STOP_PERIOD_V 0xFFFFF -#define RTC_I2C_SCL_STOP_PERIOD_S 0 - -#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x0024) -/* RTC_I2C_DETECT_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: clear detect start interrupt*/ -#define RTC_I2C_DETECT_START_INT_CLR (BIT(8)) -#define RTC_I2C_DETECT_START_INT_CLR_M (BIT(8)) -#define RTC_I2C_DETECT_START_INT_CLR_V 0x1 -#define RTC_I2C_DETECT_START_INT_CLR_S 8 -/* RTC_I2C_TX_DATA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: clear transit load data complete interrupt*/ -#define RTC_I2C_TX_DATA_INT_CLR (BIT(7)) -#define RTC_I2C_TX_DATA_INT_CLR_M (BIT(7)) -#define RTC_I2C_TX_DATA_INT_CLR_V 0x1 -#define RTC_I2C_TX_DATA_INT_CLR_S 7 -/* RTC_I2C_RX_DATA_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: clear receive data interrupt*/ -#define RTC_I2C_RX_DATA_INT_CLR (BIT(6)) -#define RTC_I2C_RX_DATA_INT_CLR_M (BIT(6)) -#define RTC_I2C_RX_DATA_INT_CLR_V 0x1 -#define RTC_I2C_RX_DATA_INT_CLR_S 6 -/* RTC_I2C_ACK_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: clear ack error interrupt*/ -#define RTC_I2C_ACK_ERR_INT_CLR (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_CLR_M (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_CLR_V 0x1 -#define RTC_I2C_ACK_ERR_INT_CLR_S 5 -/* RTC_I2C_TIMEOUT_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: clear time out interrupt*/ -#define RTC_I2C_TIMEOUT_INT_CLR (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_CLR_M (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_CLR_V 0x1 -#define RTC_I2C_TIMEOUT_INT_CLR_S 4 -/* RTC_I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: clear transit complete interrupt*/ -#define RTC_I2C_TRANS_COMPLETE_INT_CLR (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V 0x1 -#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S 3 -/* RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: clear master transit complete interrupt*/ -#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1 -#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S 2 -/* RTC_I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: clear arbitration lost interrupt*/ -#define RTC_I2C_ARBITRATION_LOST_INT_CLR (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V 0x1 -#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S 1 -/* RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: clear slave transit complete interrupt*/ -#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1 -#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S 0 - -#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x0028) -/* RTC_I2C_DETECT_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: detect start interrupt raw*/ -#define RTC_I2C_DETECT_START_INT_RAW (BIT(8)) -#define RTC_I2C_DETECT_START_INT_RAW_M (BIT(8)) -#define RTC_I2C_DETECT_START_INT_RAW_V 0x1 -#define RTC_I2C_DETECT_START_INT_RAW_S 8 -/* RTC_I2C_TX_DATA_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: transit data interrupt raw*/ -#define RTC_I2C_TX_DATA_INT_RAW (BIT(7)) -#define RTC_I2C_TX_DATA_INT_RAW_M (BIT(7)) -#define RTC_I2C_TX_DATA_INT_RAW_V 0x1 -#define RTC_I2C_TX_DATA_INT_RAW_S 7 -/* RTC_I2C_RX_DATA_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: receive data interrupt raw*/ -#define RTC_I2C_RX_DATA_INT_RAW (BIT(6)) -#define RTC_I2C_RX_DATA_INT_RAW_M (BIT(6)) -#define RTC_I2C_RX_DATA_INT_RAW_V 0x1 -#define RTC_I2C_RX_DATA_INT_RAW_S 6 -/* RTC_I2C_ACK_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: ack error interrupt raw*/ -#define RTC_I2C_ACK_ERR_INT_RAW (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_RAW_M (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_RAW_V 0x1 -#define RTC_I2C_ACK_ERR_INT_RAW_S 5 -/* RTC_I2C_TIMEOUT_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: time out interrupt raw*/ -#define RTC_I2C_TIMEOUT_INT_RAW (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_RAW_M (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_RAW_V 0x1 -#define RTC_I2C_TIMEOUT_INT_RAW_S 4 -/* RTC_I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: transit complete interrupt raw*/ -#define RTC_I2C_TRANS_COMPLETE_INT_RAW (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V 0x1 -#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S 3 -/* RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: master transit complete interrupt raw*/ -#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1 -#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S 2 -/* RTC_I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: arbitration lost interrupt raw*/ -#define RTC_I2C_ARBITRATION_LOST_INT_RAW (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V 0x1 -#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S 1 -/* RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: slave transit complete interrupt raw*/ -#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1 -#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S 0 - -#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x002c) -/* RTC_I2C_DETECT_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: detect start interrupt state*/ -#define RTC_I2C_DETECT_START_INT_ST (BIT(8)) -#define RTC_I2C_DETECT_START_INT_ST_M (BIT(8)) -#define RTC_I2C_DETECT_START_INT_ST_V 0x1 -#define RTC_I2C_DETECT_START_INT_ST_S 8 -/* RTC_I2C_TX_DATA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: transit data interrupt state*/ -#define RTC_I2C_TX_DATA_INT_ST (BIT(7)) -#define RTC_I2C_TX_DATA_INT_ST_M (BIT(7)) -#define RTC_I2C_TX_DATA_INT_ST_V 0x1 -#define RTC_I2C_TX_DATA_INT_ST_S 7 -/* RTC_I2C_RX_DATA_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: receive data interrupt state*/ -#define RTC_I2C_RX_DATA_INT_ST (BIT(6)) -#define RTC_I2C_RX_DATA_INT_ST_M (BIT(6)) -#define RTC_I2C_RX_DATA_INT_ST_V 0x1 -#define RTC_I2C_RX_DATA_INT_ST_S 6 -/* RTC_I2C_ACK_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: ack error interrupt state*/ -#define RTC_I2C_ACK_ERR_INT_ST (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_ST_M (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_ST_V 0x1 -#define RTC_I2C_ACK_ERR_INT_ST_S 5 -/* RTC_I2C_TIMEOUT_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: time out interrupt state*/ -#define RTC_I2C_TIMEOUT_INT_ST (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_ST_M (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_ST_V 0x1 -#define RTC_I2C_TIMEOUT_INT_ST_S 4 -/* RTC_I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: transit complete interrupt state*/ -#define RTC_I2C_TRANS_COMPLETE_INT_ST (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_ST_M (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_ST_V 0x1 -#define RTC_I2C_TRANS_COMPLETE_INT_ST_S 3 -/* RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: master transit complete interrupt state*/ -#define RTC_I2C_MASTER_TRAN_COMP_INT_ST (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V 0x1 -#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S 2 -/* RTC_I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: arbitration lost interrupt state*/ -#define RTC_I2C_ARBITRATION_LOST_INT_ST (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_ST_M (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_ST_V 0x1 -#define RTC_I2C_ARBITRATION_LOST_INT_ST_S 1 -/* RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: slave transit complete interrupt state*/ -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1 -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S 0 - -#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_I2C_BASE + 0x0030) -/* RTC_I2C_DETECT_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: enable detect start interrupt*/ -#define RTC_I2C_DETECT_START_INT_ENA (BIT(8)) -#define RTC_I2C_DETECT_START_INT_ENA_M (BIT(8)) -#define RTC_I2C_DETECT_START_INT_ENA_V 0x1 -#define RTC_I2C_DETECT_START_INT_ENA_S 8 -/* RTC_I2C_TX_DATA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: enable transit data interrupt*/ -#define RTC_I2C_TX_DATA_INT_ENA (BIT(7)) -#define RTC_I2C_TX_DATA_INT_ENA_M (BIT(7)) -#define RTC_I2C_TX_DATA_INT_ENA_V 0x1 -#define RTC_I2C_TX_DATA_INT_ENA_S 7 -/* RTC_I2C_RX_DATA_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: enable receive data interrupt*/ -#define RTC_I2C_RX_DATA_INT_ENA (BIT(6)) -#define RTC_I2C_RX_DATA_INT_ENA_M (BIT(6)) -#define RTC_I2C_RX_DATA_INT_ENA_V 0x1 -#define RTC_I2C_RX_DATA_INT_ENA_S 6 -/* RTC_I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: enable eack error interrupt*/ -#define RTC_I2C_ACK_ERR_INT_ENA (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_ENA_M (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_ENA_V 0x1 -#define RTC_I2C_ACK_ERR_INT_ENA_S 5 -/* RTC_I2C_TIMEOUT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: enable time out interrupt*/ -#define RTC_I2C_TIMEOUT_INT_ENA (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_ENA_M (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_ENA_V 0x1 -#define RTC_I2C_TIMEOUT_INT_ENA_S 4 -/* RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: enable transit complete interrupt*/ -#define RTC_I2C_TRANS_COMPLETE_INT_ENA (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V 0x1 -#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S 3 -/* RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: enable master transit complete interrupt*/ -#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1 -#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S 2 -/* RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: enable arbitration lost interrupt*/ -#define RTC_I2C_ARBITRATION_LOST_INT_ENA (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V 0x1 -#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S 1 -/* RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: enable slave transit complete interrupt*/ -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1 -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S 0 - -#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x0034) -/* RTC_I2C_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: i2c done*/ -#define RTC_I2C_DONE (BIT(31)) -#define RTC_I2C_DONE_M (BIT(31)) -#define RTC_I2C_DONE_V 0x1 -#define RTC_I2C_DONE_S 31 -/* RTC_I2C_SLAVE_TX_DATA : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: data sent by slave*/ -#define RTC_I2C_SLAVE_TX_DATA 0x000000FF -#define RTC_I2C_SLAVE_TX_DATA_M ((RTC_I2C_SLAVE_TX_DATA_V)<<(RTC_I2C_SLAVE_TX_DATA_S)) -#define RTC_I2C_SLAVE_TX_DATA_V 0xFF -#define RTC_I2C_SLAVE_TX_DATA_S 8 -/* RTC_I2C_RDATA : RO ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: data received*/ -#define RTC_I2C_RDATA 0x000000FF -#define RTC_I2C_RDATA_M ((RTC_I2C_RDATA_V)<<(RTC_I2C_RDATA_S)) -#define RTC_I2C_RDATA_V 0xFF -#define RTC_I2C_RDATA_S 0 - -#define RTC_I2C_CMD0_REG (DR_REG_RTC_I2C_BASE + 0x0038) -/* RTC_I2C_COMMAND0_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command0_done*/ -#define RTC_I2C_COMMAND0_DONE (BIT(31)) -#define RTC_I2C_COMMAND0_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND0_DONE_V 0x1 -#define RTC_I2C_COMMAND0_DONE_S 31 -/* RTC_I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */ -/*description: command0*/ -#define RTC_I2C_COMMAND0 0x00003FFF -#define RTC_I2C_COMMAND0_M ((RTC_I2C_COMMAND0_V)<<(RTC_I2C_COMMAND0_S)) -#define RTC_I2C_COMMAND0_V 0x3FFF -#define RTC_I2C_COMMAND0_S 0 - -#define RTC_I2C_CMD1_REG (DR_REG_RTC_I2C_BASE + 0x003c) -/* RTC_I2C_COMMAND1_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command1_done*/ -#define RTC_I2C_COMMAND1_DONE (BIT(31)) -#define RTC_I2C_COMMAND1_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND1_DONE_V 0x1 -#define RTC_I2C_COMMAND1_DONE_S 31 -/* RTC_I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ -/*description: command1*/ -#define RTC_I2C_COMMAND1 0x00003FFF -#define RTC_I2C_COMMAND1_M ((RTC_I2C_COMMAND1_V)<<(RTC_I2C_COMMAND1_S)) -#define RTC_I2C_COMMAND1_V 0x3FFF -#define RTC_I2C_COMMAND1_S 0 - -#define RTC_I2C_CMD2_REG (DR_REG_RTC_I2C_BASE + 0x0040) -/* RTC_I2C_COMMAND2_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command2_done*/ -#define RTC_I2C_COMMAND2_DONE (BIT(31)) -#define RTC_I2C_COMMAND2_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND2_DONE_V 0x1 -#define RTC_I2C_COMMAND2_DONE_S 31 -/* RTC_I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'h0902 ; */ -/*description: command2*/ -#define RTC_I2C_COMMAND2 0x00003FFF -#define RTC_I2C_COMMAND2_M ((RTC_I2C_COMMAND2_V)<<(RTC_I2C_COMMAND2_S)) -#define RTC_I2C_COMMAND2_V 0x3FFF -#define RTC_I2C_COMMAND2_S 0 - -#define RTC_I2C_CMD3_REG (DR_REG_RTC_I2C_BASE + 0x0044) -/* RTC_I2C_COMMAND3_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command3_done*/ -#define RTC_I2C_COMMAND3_DONE (BIT(31)) -#define RTC_I2C_COMMAND3_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND3_DONE_V 0x1 -#define RTC_I2C_COMMAND3_DONE_S 31 -/* RTC_I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */ -/*description: command3*/ -#define RTC_I2C_COMMAND3 0x00003FFF -#define RTC_I2C_COMMAND3_M ((RTC_I2C_COMMAND3_V)<<(RTC_I2C_COMMAND3_S)) -#define RTC_I2C_COMMAND3_V 0x3FFF -#define RTC_I2C_COMMAND3_S 0 - -#define RTC_I2C_CMD4_REG (DR_REG_RTC_I2C_BASE + 0x0048) -/* RTC_I2C_COMMAND4_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command4_done*/ -#define RTC_I2C_COMMAND4_DONE (BIT(31)) -#define RTC_I2C_COMMAND4_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND4_DONE_V 0x1 -#define RTC_I2C_COMMAND4_DONE_S 31 -/* RTC_I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */ -/*description: command4*/ -#define RTC_I2C_COMMAND4 0x00003FFF -#define RTC_I2C_COMMAND4_M ((RTC_I2C_COMMAND4_V)<<(RTC_I2C_COMMAND4_S)) -#define RTC_I2C_COMMAND4_V 0x3FFF -#define RTC_I2C_COMMAND4_S 0 - -#define RTC_I2C_CMD5_REG (DR_REG_RTC_I2C_BASE + 0x004c) -/* RTC_I2C_COMMAND5_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command5_done*/ -#define RTC_I2C_COMMAND5_DONE (BIT(31)) -#define RTC_I2C_COMMAND5_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND5_DONE_V 0x1 -#define RTC_I2C_COMMAND5_DONE_S 31 -/* RTC_I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */ -/*description: command5*/ -#define RTC_I2C_COMMAND5 0x00003FFF -#define RTC_I2C_COMMAND5_M ((RTC_I2C_COMMAND5_V)<<(RTC_I2C_COMMAND5_S)) -#define RTC_I2C_COMMAND5_V 0x3FFF -#define RTC_I2C_COMMAND5_S 0 - -#define RTC_I2C_CMD6_REG (DR_REG_RTC_I2C_BASE + 0x0050) -/* RTC_I2C_COMMAND6_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command6_done*/ -#define RTC_I2C_COMMAND6_DONE (BIT(31)) -#define RTC_I2C_COMMAND6_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND6_DONE_V 0x1 -#define RTC_I2C_COMMAND6_DONE_S 31 -/* RTC_I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ -/*description: command6*/ -#define RTC_I2C_COMMAND6 0x00003FFF -#define RTC_I2C_COMMAND6_M ((RTC_I2C_COMMAND6_V)<<(RTC_I2C_COMMAND6_S)) -#define RTC_I2C_COMMAND6_V 0x3FFF -#define RTC_I2C_COMMAND6_S 0 - -#define RTC_I2C_CMD7_REG (DR_REG_RTC_I2C_BASE + 0x0054) -/* RTC_I2C_COMMAND7_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command7_done*/ -#define RTC_I2C_COMMAND7_DONE (BIT(31)) -#define RTC_I2C_COMMAND7_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND7_DONE_V 0x1 -#define RTC_I2C_COMMAND7_DONE_S 31 -/* RTC_I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'h0904 ; */ -/*description: command7*/ -#define RTC_I2C_COMMAND7 0x00003FFF -#define RTC_I2C_COMMAND7_M ((RTC_I2C_COMMAND7_V)<<(RTC_I2C_COMMAND7_S)) -#define RTC_I2C_COMMAND7_V 0x3FFF -#define RTC_I2C_COMMAND7_S 0 - -#define RTC_I2C_CMD8_REG (DR_REG_RTC_I2C_BASE + 0x0058) -/* RTC_I2C_COMMAND8_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command8_done*/ -#define RTC_I2C_COMMAND8_DONE (BIT(31)) -#define RTC_I2C_COMMAND8_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND8_DONE_V 0x1 -#define RTC_I2C_COMMAND8_DONE_S 31 -/* RTC_I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ -/*description: command8*/ -#define RTC_I2C_COMMAND8 0x00003FFF -#define RTC_I2C_COMMAND8_M ((RTC_I2C_COMMAND8_V)<<(RTC_I2C_COMMAND8_S)) -#define RTC_I2C_COMMAND8_V 0x3FFF -#define RTC_I2C_COMMAND8_S 0 - -#define RTC_I2C_CMD9_REG (DR_REG_RTC_I2C_BASE + 0x005c) -/* RTC_I2C_COMMAND9_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command9_done*/ -#define RTC_I2C_COMMAND9_DONE (BIT(31)) -#define RTC_I2C_COMMAND9_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND9_DONE_V 0x1 -#define RTC_I2C_COMMAND9_DONE_S 31 -/* RTC_I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */ -/*description: command9*/ -#define RTC_I2C_COMMAND9 0x00003FFF -#define RTC_I2C_COMMAND9_M ((RTC_I2C_COMMAND9_V)<<(RTC_I2C_COMMAND9_S)) -#define RTC_I2C_COMMAND9_V 0x3FFF -#define RTC_I2C_COMMAND9_S 0 - -#define RTC_I2C_CMD10_REG (DR_REG_RTC_I2C_BASE + 0x0060) -/* RTC_I2C_COMMAND10_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command10_done*/ -#define RTC_I2C_COMMAND10_DONE (BIT(31)) -#define RTC_I2C_COMMAND10_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND10_DONE_V 0x1 -#define RTC_I2C_COMMAND10_DONE_S 31 -/* RTC_I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */ -/*description: command10*/ -#define RTC_I2C_COMMAND10 0x00003FFF -#define RTC_I2C_COMMAND10_M ((RTC_I2C_COMMAND10_V)<<(RTC_I2C_COMMAND10_S)) -#define RTC_I2C_COMMAND10_V 0x3FFF -#define RTC_I2C_COMMAND10_S 0 - -#define RTC_I2C_CMD11_REG (DR_REG_RTC_I2C_BASE + 0x0064) -/* RTC_I2C_COMMAND11_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command11_done*/ -#define RTC_I2C_COMMAND11_DONE (BIT(31)) -#define RTC_I2C_COMMAND11_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND11_DONE_V 0x1 -#define RTC_I2C_COMMAND11_DONE_S 31 -/* RTC_I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */ -/*description: command11*/ -#define RTC_I2C_COMMAND11 0x00003FFF -#define RTC_I2C_COMMAND11_M ((RTC_I2C_COMMAND11_V)<<(RTC_I2C_COMMAND11_S)) -#define RTC_I2C_COMMAND11_V 0x3FFF -#define RTC_I2C_COMMAND11_S 0 - -#define RTC_I2C_CMD12_REG (DR_REG_RTC_I2C_BASE + 0x0068) -/* RTC_I2C_COMMAND12_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command12_done*/ -#define RTC_I2C_COMMAND12_DONE (BIT(31)) -#define RTC_I2C_COMMAND12_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND12_DONE_V 0x1 -#define RTC_I2C_COMMAND12_DONE_S 31 -/* RTC_I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */ -/*description: command12*/ -#define RTC_I2C_COMMAND12 0x00003FFF -#define RTC_I2C_COMMAND12_M ((RTC_I2C_COMMAND12_V)<<(RTC_I2C_COMMAND12_S)) -#define RTC_I2C_COMMAND12_V 0x3FFF -#define RTC_I2C_COMMAND12_S 0 - -#define RTC_I2C_CMD13_REG (DR_REG_RTC_I2C_BASE + 0x006c) -/* RTC_I2C_COMMAND13_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command13_done*/ -#define RTC_I2C_COMMAND13_DONE (BIT(31)) -#define RTC_I2C_COMMAND13_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND13_DONE_V 0x1 -#define RTC_I2C_COMMAND13_DONE_S 31 -/* RTC_I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ -/*description: command13*/ -#define RTC_I2C_COMMAND13 0x00003FFF -#define RTC_I2C_COMMAND13_M ((RTC_I2C_COMMAND13_V)<<(RTC_I2C_COMMAND13_S)) -#define RTC_I2C_COMMAND13_V 0x3FFF -#define RTC_I2C_COMMAND13_S 0 - -#define RTC_I2C_CMD14_REG (DR_REG_RTC_I2C_BASE + 0x0070) -/* RTC_I2C_COMMAND14_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command14_done*/ -#define RTC_I2C_COMMAND14_DONE (BIT(31)) -#define RTC_I2C_COMMAND14_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND14_DONE_V 0x1 -#define RTC_I2C_COMMAND14_DONE_S 31 -/* RTC_I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ -/*description: command14*/ -#define RTC_I2C_COMMAND14 0x00003FFF -#define RTC_I2C_COMMAND14_M ((RTC_I2C_COMMAND14_V)<<(RTC_I2C_COMMAND14_S)) -#define RTC_I2C_COMMAND14_V 0x3FFF -#define RTC_I2C_COMMAND14_S 0 - -#define RTC_I2C_CMD15_REG (DR_REG_RTC_I2C_BASE + 0x0074) -/* RTC_I2C_COMMAND15_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command15_done*/ -#define RTC_I2C_COMMAND15_DONE (BIT(31)) -#define RTC_I2C_COMMAND15_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND15_DONE_V 0x1 -#define RTC_I2C_COMMAND15_DONE_S 31 -/* RTC_I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ -/*description: command15*/ -#define RTC_I2C_COMMAND15 0x00003FFF -#define RTC_I2C_COMMAND15_M ((RTC_I2C_COMMAND15_V)<<(RTC_I2C_COMMAND15_S)) -#define RTC_I2C_COMMAND15_V 0x3FFF -#define RTC_I2C_COMMAND15_S 0 - -#define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0x00FC) -/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905310 ; */ -/*description: */ -#define RTC_I2C_DATE 0x0FFFFFFF -#define RTC_I2C_DATE_M ((RTC_I2C_DATE_V)<<(RTC_I2C_DATE_S)) -#define RTC_I2C_DATE_V 0xFFFFFFF -#define RTC_I2C_DATE_S 0 - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_RTC_I2C_REG_H_ */ diff --git a/components/soc/esp8684/include/soc/rtc_i2c_struct.h b/components/soc/esp8684/include/soc/rtc_i2c_struct.h deleted file mode 100644 index 28987a1f9c..0000000000 --- a/components/soc/esp8684/include/soc/rtc_i2c_struct.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_RTC_I2C_STRUCT_H_ -#define _SOC_RTC_I2C_STRUCT_H_ -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct rtc_i2c_dev_s{ - union { - struct { - uint32_t period: 20; /*time period that scl = 0*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } scl_low; - union { - struct { - uint32_t sda_force_out: 1; /*1=push pull 0=open drain*/ - uint32_t scl_force_out: 1; /*1=push pull 0=open drain*/ - uint32_t ms_mode: 1; /*1=master 0=slave*/ - uint32_t trans_start: 1; /*force start*/ - uint32_t tx_lsb_first: 1; /*transit lsb first*/ - uint32_t rx_lsb_first: 1; /*receive lsb first*/ - uint32_t reserved6: 23; - uint32_t i2c_ctrl_clk_gate_en: 1; - uint32_t i2c_reset: 1; /*rtc i2c sw reset*/ - uint32_t i2cclk_en: 1; /*rtc i2c reg clk gating*/ - }; - uint32_t val; - } ctrl; - union { - struct { - uint32_t ack_rec: 1; /*ack response*/ - uint32_t slave_rw: 1; /*slave read or write*/ - uint32_t arb_lost: 1; /*arbitration is lost*/ - uint32_t bus_busy: 1; /*bus is busy*/ - uint32_t slave_addressed: 1; /*slave reg sub address*/ - uint32_t byte_trans: 1; /*One byte transit done*/ - uint32_t op_cnt: 2; /*which operation is working*/ - uint32_t reserved8: 8; - uint32_t shift: 8; /*shifter content*/ - uint32_t scl_main_state_last: 3; /*i2c last main status*/ - uint32_t reserved27: 1; - uint32_t scl_state_last: 3; /*scl last status*/ - uint32_t reserved31: 1; - }; - uint32_t val; - } status; - union { - struct { - uint32_t time_out: 20; /*time out threshold*/ - uint32_t reserved20:12; - }; - uint32_t val; - } timeout; - union { - struct { - uint32_t addr: 15; /*slave address*/ - uint32_t reserved15: 16; - uint32_t en_10bit: 1; /*i2c 10bit mode enable*/ - }; - uint32_t val; - } slave_addr; - union { - struct { - uint32_t period: 20; /*time period that scl = 1*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } scl_high; - union { - struct { - uint32_t sda_duty_num:20; /*time period for SDA to toggle after SCL goes low*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } sda_duty; - union { - struct { - uint32_t scl_start_period:20; /*time period for SCL to toggle after I2C start is triggered*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } scl_start_period; - union { - struct { - uint32_t scl_stop_period:20; /*time period for SCL to stop after I2C end is triggered*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } scl_stop_period; - union { - struct { - uint32_t slave_tran_comp: 1; /*clear slave transit complete interrupt*/ - uint32_t arbitration_lost: 1; /*clear arbitration lost interrupt*/ - uint32_t master_tran_comp: 1; /*clear master transit complete interrupt*/ - uint32_t trans_complete: 1; /*clear transit complete interrupt*/ - uint32_t time_out: 1; /*clear time out interrupt*/ - uint32_t ack_err: 1; /*clear ack error interrupt*/ - uint32_t rx_data: 1; /*clear receive data interrupt*/ - uint32_t tx_data: 1; /*clear transit load data complete interrupt*/ - uint32_t detect_start: 1; /*clear detect start interrupt*/ - uint32_t reserved9: 23; - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t slave_tran_comp: 1; /*slave transit complete interrupt raw*/ - uint32_t arbitration_lost: 1; /*arbitration lost interrupt raw*/ - uint32_t master_tran_comp: 1; /*master transit complete interrupt raw*/ - uint32_t trans_complete: 1; /*transit complete interrupt raw*/ - uint32_t time_out: 1; /*time out interrupt raw*/ - uint32_t ack_err: 1; /*ack error interrupt raw*/ - uint32_t rx_data: 1; /*receive data interrupt raw*/ - uint32_t tx_data: 1; /*transit data interrupt raw*/ - uint32_t detect_start: 1; /*detect start interrupt raw*/ - uint32_t reserved9: 23; - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t slave_tran_comp: 1; /*slave transit complete interrupt state*/ - uint32_t arbitration_lost: 1; /*arbitration lost interrupt state*/ - uint32_t master_tran_comp: 1; /*master transit complete interrupt state*/ - uint32_t trans_complete: 1; /*transit complete interrupt state*/ - uint32_t time_out: 1; /*time out interrupt state*/ - uint32_t ack_err: 1; /*ack error interrupt state*/ - uint32_t rx_data: 1; /*receive data interrupt state*/ - uint32_t tx_data: 1; /*transit data interrupt state*/ - uint32_t detect_start: 1; /*detect start interrupt state*/ - uint32_t reserved9: 23; - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t slave_tran_comp: 1; /*enable slave transit complete interrupt*/ - uint32_t arbitration_lost: 1; /*enable arbitration lost interrupt*/ - uint32_t master_tran_comp: 1; /*enable master transit complete interrupt*/ - uint32_t trans_complete: 1; /*enable transit complete interrupt*/ - uint32_t time_out: 1; /*enable time out interrupt*/ - uint32_t ack_err: 1; /*enable eack error interrupt*/ - uint32_t rx_data: 1; /*enable receive data interrupt*/ - uint32_t tx_data: 1; /*enable transit data interrupt*/ - uint32_t detect_start: 1; /*enable detect start interrupt*/ - uint32_t reserved9: 23; - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t i2c_rdata: 8; /*data received*/ - uint32_t slave_tx_data: 8; /*data sent by slave*/ - uint32_t reserved16: 15; - uint32_t i2c_done: 1; /*i2c done*/ - }; - uint32_t val; - } fifo_data; - union { - struct { - uint32_t command0: 14; /*command0*/ - uint32_t reserved14: 17; - uint32_t done: 1; /*command0_done*/ - }; - uint32_t val; - } command[16]; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - union { - struct { - uint32_t i2c_date: 28; - uint32_t reserved28: 4; - }; - uint32_t val; - } date; -} rtc_i2c_dev_t; -extern rtc_i2c_dev_t RTC_I2C; -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_RTC_I2C_STRUCT_H_ */ diff --git a/components/soc/esp8684/include/soc/sensitive_reg.h b/components/soc/esp8684/include/soc/sensitive_reg.h index e09819a3ad..e3de172e73 100644 --- a/components/soc/esp8684/include/soc/sensitive_reg.h +++ b/components/soc/esp8684/include/soc/sensitive_reg.h @@ -1,214 +1,290 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_SENSITIVE_REG_H_ -#define _SOC_SENSITIVE_REG_H_ - +#pragma once +#include +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -#define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x0) -/* SENSITIVE_ROM_TABLE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Need add description.*/ +/** SENSITIVE_ROM_TABLE_LOCK_REG register + * register description + */ +#define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x0) +/** SENSITIVE_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0; + * Need add description + */ #define SENSITIVE_ROM_TABLE_LOCK (BIT(0)) -#define SENSITIVE_ROM_TABLE_LOCK_M (BIT(0)) -#define SENSITIVE_ROM_TABLE_LOCK_V 0x1 +#define SENSITIVE_ROM_TABLE_LOCK_M (SENSITIVE_ROM_TABLE_LOCK_V << SENSITIVE_ROM_TABLE_LOCK_S) +#define SENSITIVE_ROM_TABLE_LOCK_V 0x00000001U #define SENSITIVE_ROM_TABLE_LOCK_S 0 -#define SENSITIVE_ROM_TABLE_REG (DR_REG_SENSITIVE_BASE + 0x4) -/* SENSITIVE_ROM_TABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: Need add description.*/ -#define SENSITIVE_ROM_TABLE 0xFFFFFFFF -#define SENSITIVE_ROM_TABLE_M ((SENSITIVE_ROM_TABLE_V)<<(SENSITIVE_ROM_TABLE_S)) -#define SENSITIVE_ROM_TABLE_V 0xFFFFFFFF +/** SENSITIVE_ROM_TABLE_REG register + * register description + */ +#define SENSITIVE_ROM_TABLE_REG (DR_REG_SENSITIVE_BASE + 0x4) +/** SENSITIVE_ROM_TABLE : R/W; bitpos: [31:0]; default: 0; + * Need add description + */ +#define SENSITIVE_ROM_TABLE 0xFFFFFFFFU +#define SENSITIVE_ROM_TABLE_M (SENSITIVE_ROM_TABLE_V << SENSITIVE_ROM_TABLE_S) +#define SENSITIVE_ROM_TABLE_V 0xFFFFFFFFU #define SENSITIVE_ROM_TABLE_S 0 -#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x8) -/* SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Need add description.*/ +/** SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG register + * register description + */ +#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x8) +/** SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W; bitpos: [0]; default: 0; + * Need add description + */ #define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK (BIT(0)) -#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M (BIT(0)) -#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V 0x1 +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M (SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V << SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V 0x00000001U #define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S 0 -#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0xC) -/* SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Need add description.*/ +/** SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG register + * register description + */ +#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0xc) +/** SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W; bitpos: [0]; default: 1; + * Need add description + */ #define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST (BIT(0)) -#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M (BIT(0)) -#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V 0x1 +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M (SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V << SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V 0x00000001U #define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S 0 -#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG (DR_REG_SENSITIVE_BASE + 0x10) -/* SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Need add description.*/ +/** SENSITIVE_INTERNAL_SRAM_USAGE_0_REG register + * register description + */ +#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG (DR_REG_SENSITIVE_BASE + 0x10) +/** SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W; bitpos: [0]; default: 0; + * Need add description + */ #define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK (BIT(0)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M (BIT(0)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V 0x1 +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M (SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V << SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S) +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V 0x00000001U #define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S 0 -#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG (DR_REG_SENSITIVE_BASE + 0x14) -/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM : R/W ;bitpos:[3:1] ;default: 3'b111 ; */ -/*description: Need add description.*/ -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM 0x00000007 -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_M ((SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V 0x7 -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S 1 -/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Need add description.*/ +/** SENSITIVE_INTERNAL_SRAM_USAGE_1_REG register + * register description + */ +#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG (DR_REG_SENSITIVE_BASE + 0x14) +/** SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE : R/W; bitpos: [0]; default: 1; + * Need add description + */ #define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE (BIT(0)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_M (BIT(0)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V 0x1 +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_M (SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V << SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_S) +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V 0x00000001U #define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_S 0 +/** SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM : R/W; bitpos: [3:1]; default: 7; + * Need add description + */ +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM 0x00000007U +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_M (SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V << SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S) +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V 0x00000007U +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S 1 -#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG (DR_REG_SENSITIVE_BASE + 0x18) -/* SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Need add description.*/ -#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP (BIT(3)) -#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_M (BIT(3)) -#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V 0x1 -#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S 3 -/* SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: Need add description.*/ -#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM 0x00000007 -#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_M ((SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V 0x7 +/** SENSITIVE_INTERNAL_SRAM_USAGE_3_REG register + * register description + */ +#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG (DR_REG_SENSITIVE_BASE + 0x18) +/** SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM : R/W; bitpos: [2:0]; default: 0; + * Need add description + */ +#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM 0x00000007U +#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_M (SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V << SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S) +#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V 0x00000007U #define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S 0 +/** SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP : R/W; bitpos: [3]; default: 0; + * Need add description + */ +#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP (BIT(3)) +#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_M (SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V << SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S) +#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V 0x00000001U +#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S 3 -#define SENSITIVE_CACHE_TAG_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x1C) -/* SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Need add description.*/ +/** SENSITIVE_CACHE_TAG_ACCESS_0_REG register + * register description + */ +#define SENSITIVE_CACHE_TAG_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x1c) +/** SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W; bitpos: [0]; default: 0; + * Need add description + */ #define SENSITIVE_CACHE_TAG_ACCESS_LOCK (BIT(0)) -#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M (BIT(0)) -#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V 0x1 +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M (SENSITIVE_CACHE_TAG_ACCESS_LOCK_V << SENSITIVE_CACHE_TAG_ACCESS_LOCK_S) +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V 0x00000001U #define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S 0 -#define SENSITIVE_CACHE_TAG_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x20) -/* SENSITIVE_PRO_D_TAG_WR_ACS : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: Need add description.*/ -#define SENSITIVE_PRO_D_TAG_WR_ACS (BIT(3)) -#define SENSITIVE_PRO_D_TAG_WR_ACS_M (BIT(3)) -#define SENSITIVE_PRO_D_TAG_WR_ACS_V 0x1 -#define SENSITIVE_PRO_D_TAG_WR_ACS_S 3 -/* SENSITIVE_PRO_D_TAG_RD_ACS : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: Need add description.*/ -#define SENSITIVE_PRO_D_TAG_RD_ACS (BIT(2)) -#define SENSITIVE_PRO_D_TAG_RD_ACS_M (BIT(2)) -#define SENSITIVE_PRO_D_TAG_RD_ACS_V 0x1 -#define SENSITIVE_PRO_D_TAG_RD_ACS_S 2 -/* SENSITIVE_PRO_I_TAG_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: Need add description.*/ -#define SENSITIVE_PRO_I_TAG_WR_ACS (BIT(1)) -#define SENSITIVE_PRO_I_TAG_WR_ACS_M (BIT(1)) -#define SENSITIVE_PRO_I_TAG_WR_ACS_V 0x1 -#define SENSITIVE_PRO_I_TAG_WR_ACS_S 1 -/* SENSITIVE_PRO_I_TAG_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Need add description.*/ +/** SENSITIVE_CACHE_TAG_ACCESS_1_REG register + * register description + */ +#define SENSITIVE_CACHE_TAG_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x20) +/** SENSITIVE_PRO_I_TAG_RD_ACS : R/W; bitpos: [0]; default: 1; + * Need add description + */ #define SENSITIVE_PRO_I_TAG_RD_ACS (BIT(0)) -#define SENSITIVE_PRO_I_TAG_RD_ACS_M (BIT(0)) -#define SENSITIVE_PRO_I_TAG_RD_ACS_V 0x1 +#define SENSITIVE_PRO_I_TAG_RD_ACS_M (SENSITIVE_PRO_I_TAG_RD_ACS_V << SENSITIVE_PRO_I_TAG_RD_ACS_S) +#define SENSITIVE_PRO_I_TAG_RD_ACS_V 0x00000001U #define SENSITIVE_PRO_I_TAG_RD_ACS_S 0 +/** SENSITIVE_PRO_I_TAG_WR_ACS : R/W; bitpos: [1]; default: 1; + * Need add description + */ +#define SENSITIVE_PRO_I_TAG_WR_ACS (BIT(1)) +#define SENSITIVE_PRO_I_TAG_WR_ACS_M (SENSITIVE_PRO_I_TAG_WR_ACS_V << SENSITIVE_PRO_I_TAG_WR_ACS_S) +#define SENSITIVE_PRO_I_TAG_WR_ACS_V 0x00000001U +#define SENSITIVE_PRO_I_TAG_WR_ACS_S 1 +/** SENSITIVE_PRO_D_TAG_RD_ACS : R/W; bitpos: [2]; default: 1; + * Need add description + */ +#define SENSITIVE_PRO_D_TAG_RD_ACS (BIT(2)) +#define SENSITIVE_PRO_D_TAG_RD_ACS_M (SENSITIVE_PRO_D_TAG_RD_ACS_V << SENSITIVE_PRO_D_TAG_RD_ACS_S) +#define SENSITIVE_PRO_D_TAG_RD_ACS_V 0x00000001U +#define SENSITIVE_PRO_D_TAG_RD_ACS_S 2 +/** SENSITIVE_PRO_D_TAG_WR_ACS : R/W; bitpos: [3]; default: 1; + * Need add description + */ +#define SENSITIVE_PRO_D_TAG_WR_ACS (BIT(3)) +#define SENSITIVE_PRO_D_TAG_WR_ACS_M (SENSITIVE_PRO_D_TAG_WR_ACS_V << SENSITIVE_PRO_D_TAG_WR_ACS_S) +#define SENSITIVE_PRO_D_TAG_WR_ACS_V 0x00000001U +#define SENSITIVE_PRO_D_TAG_WR_ACS_S 3 -#define SENSITIVE_CACHE_MMU_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x24) -/* SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Need add description.*/ +/** SENSITIVE_CACHE_MMU_ACCESS_0_REG register + * register description + */ +#define SENSITIVE_CACHE_MMU_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x24) +/** SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W; bitpos: [0]; default: 0; + * Need add description + */ #define SENSITIVE_CACHE_MMU_ACCESS_LOCK (BIT(0)) -#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M (BIT(0)) -#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V 0x1 +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M (SENSITIVE_CACHE_MMU_ACCESS_LOCK_V << SENSITIVE_CACHE_MMU_ACCESS_LOCK_S) +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V 0x00000001U #define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S 0 -#define SENSITIVE_CACHE_MMU_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x28) -/* SENSITIVE_PRO_MMU_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: Need add description.*/ -#define SENSITIVE_PRO_MMU_WR_ACS (BIT(1)) -#define SENSITIVE_PRO_MMU_WR_ACS_M (BIT(1)) -#define SENSITIVE_PRO_MMU_WR_ACS_V 0x1 -#define SENSITIVE_PRO_MMU_WR_ACS_S 1 -/* SENSITIVE_PRO_MMU_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Need add description.*/ +/** SENSITIVE_CACHE_MMU_ACCESS_1_REG register + * register description + */ +#define SENSITIVE_CACHE_MMU_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x28) +/** SENSITIVE_PRO_MMU_RD_ACS : R/W; bitpos: [0]; default: 1; + * Need add description + */ #define SENSITIVE_PRO_MMU_RD_ACS (BIT(0)) -#define SENSITIVE_PRO_MMU_RD_ACS_M (BIT(0)) -#define SENSITIVE_PRO_MMU_RD_ACS_V 0x1 +#define SENSITIVE_PRO_MMU_RD_ACS_M (SENSITIVE_PRO_MMU_RD_ACS_V << SENSITIVE_PRO_MMU_RD_ACS_S) +#define SENSITIVE_PRO_MMU_RD_ACS_V 0x00000001U #define SENSITIVE_PRO_MMU_RD_ACS_S 0 +/** SENSITIVE_PRO_MMU_WR_ACS : R/W; bitpos: [1]; default: 1; + * Need add description + */ +#define SENSITIVE_PRO_MMU_WR_ACS (BIT(1)) +#define SENSITIVE_PRO_MMU_WR_ACS_M (SENSITIVE_PRO_MMU_WR_ACS_V << SENSITIVE_PRO_MMU_WR_ACS_S) +#define SENSITIVE_PRO_MMU_WR_ACS_V 0x00000001U +#define SENSITIVE_PRO_MMU_WR_ACS_S 1 -#define SENSITIVE_PIF_ACCESS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x2C) -/* SENSITIVE_PIF_ACCESS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Need add description.*/ +/** SENSITIVE_PIF_ACCESS_MONITOR_0_REG register + * register description + */ +#define SENSITIVE_PIF_ACCESS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x2c) +/** SENSITIVE_PIF_ACCESS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0; + * Need add description + */ #define SENSITIVE_PIF_ACCESS_MONITOR_LOCK (BIT(0)) -#define SENSITIVE_PIF_ACCESS_MONITOR_LOCK_M (BIT(0)) -#define SENSITIVE_PIF_ACCESS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_PIF_ACCESS_MONITOR_LOCK_M (SENSITIVE_PIF_ACCESS_MONITOR_LOCK_V << SENSITIVE_PIF_ACCESS_MONITOR_LOCK_S) +#define SENSITIVE_PIF_ACCESS_MONITOR_LOCK_V 0x00000001U #define SENSITIVE_PIF_ACCESS_MONITOR_LOCK_S 0 -#define SENSITIVE_PIF_ACCESS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x30) -/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: Need add description.*/ -#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN (BIT(1)) -#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_M (BIT(1)) -#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_V 0x1 -#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_S 1 -/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Need add description.*/ +/** SENSITIVE_PIF_ACCESS_MONITOR_1_REG register + * register description + */ +#define SENSITIVE_PIF_ACCESS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x30) +/** SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR : R/W; bitpos: [0]; default: 1; + * Need add description + */ #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_M (BIT(0)) -#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_V 0x1 +#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_M (SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_V << SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_S) +#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_V 0x00000001U #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_S 0 +/** SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN : R/W; bitpos: [1]; default: 1; + * Need add description + */ +#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN (BIT(1)) +#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_M (SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_V << SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_S) +#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_V 0x00000001U +#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_S 1 -#define SENSITIVE_PIF_ACCESS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x34) -/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */ -/*description: Need add description.*/ -#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE 0x00000003 -#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S)) -#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V 0x3 -#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S 1 -/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Need add description.*/ +/** SENSITIVE_PIF_ACCESS_MONITOR_2_REG register + * register description + */ +#define SENSITIVE_PIF_ACCESS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x34) +/** SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR : RO; bitpos: [0]; default: 0; + * Need add description + */ #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_M (BIT(0)) -#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_V 0x1 +#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_M (SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_V << SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_S) +#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_V 0x00000001U #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_S 0 +/** SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO; bitpos: [2:1]; + * default: 0; + * Need add description + */ +#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE 0x00000003U +#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M (SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V << SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S) +#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V 0x00000003U +#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S 1 -#define SENSITIVE_PIF_ACCESS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x38) -/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: Need add description.*/ -#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xFFFFFFFF -#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M ((SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S)) -#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF +/** SENSITIVE_PIF_ACCESS_MONITOR_3_REG register + * register description + */ +#define SENSITIVE_PIF_ACCESS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x38) +/** SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO; bitpos: [31:0]; + * default: 0; + * Need add description + */ +#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xFFFFFFFFU +#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M (SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V << SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S) +#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V 0xFFFFFFFFU #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S 0 -#define SENSITIVE_XTS_AES_KEY_UPDATE_REG (DR_REG_SENSITIVE_BASE + 0x3C) -/* SENSITIVE_XTS_AES_KEY_UPDATE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to update xts_aes key.*/ +/** SENSITIVE_XTS_AES_KEY_UPDATE_REG register + * register description + */ +#define SENSITIVE_XTS_AES_KEY_UPDATE_REG (DR_REG_SENSITIVE_BASE + 0x3c) +/** SENSITIVE_XTS_AES_KEY_UPDATE : R/W; bitpos: [0]; default: 0; + * Set this bit to update xts_aes key + */ #define SENSITIVE_XTS_AES_KEY_UPDATE (BIT(0)) -#define SENSITIVE_XTS_AES_KEY_UPDATE_M (BIT(0)) -#define SENSITIVE_XTS_AES_KEY_UPDATE_V 0x1 +#define SENSITIVE_XTS_AES_KEY_UPDATE_M (SENSITIVE_XTS_AES_KEY_UPDATE_V << SENSITIVE_XTS_AES_KEY_UPDATE_S) +#define SENSITIVE_XTS_AES_KEY_UPDATE_V 0x00000001U #define SENSITIVE_XTS_AES_KEY_UPDATE_S 0 -#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x40) -/* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Need add description.*/ +/** SENSITIVE_CLOCK_GATE_REG register + * register description + */ +#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x40) +/** SENSITIVE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Need add description + */ #define SENSITIVE_CLK_EN (BIT(0)) -#define SENSITIVE_CLK_EN_M (BIT(0)) -#define SENSITIVE_CLK_EN_V 0x1 +#define SENSITIVE_CLK_EN_M (SENSITIVE_CLK_EN_V << SENSITIVE_CLK_EN_S) +#define SENSITIVE_CLK_EN_V 0x00000001U #define SENSITIVE_CLK_EN_S 0 -#define SENSITIVE_DATE_REG (DR_REG_SENSITIVE_BASE + 0xFFC) -/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2106301 ; */ -/*description: Need add description.*/ -#define SENSITIVE_DATE 0x0FFFFFFF -#define SENSITIVE_DATE_M ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S)) -#define SENSITIVE_DATE_V 0xFFFFFFF -#define SENSITIVE_DATE_S 0 - +/** SENSITIVE_SENSITIVE_REG_DATE_REG register + * register description + */ +#define SENSITIVE_SENSITIVE_REG_DATE_REG (DR_REG_SENSITIVE_BASE + 0xffc) +/** SENSITIVE_SENSITIVE_REG_DATE : R/W; bitpos: [27:0]; default: 34628353; + * Need add description + */ +#define SENSITIVE_SENSITIVE_REG_DATE 0x0FFFFFFFU +#define SENSITIVE_SENSITIVE_REG_DATE_M (SENSITIVE_SENSITIVE_REG_DATE_V << SENSITIVE_SENSITIVE_REG_DATE_S) +#define SENSITIVE_SENSITIVE_REG_DATE_V 0x0FFFFFFFU +#define SENSITIVE_SENSITIVE_REG_DATE_S 0 #ifdef __cplusplus } #endif - - - -#endif /*_SOC_SENSITIVE_REG_H_ */ diff --git a/components/soc/esp8684/include/soc/sensitive_struct.h b/components/soc/esp8684/include/soc/sensitive_struct.h index cb14d54049..1105743a95 100644 --- a/components/soc/esp8684/include/soc/sensitive_struct.h +++ b/components/soc/esp8684/include/soc/sensitive_struct.h @@ -1,1152 +1,326 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_SENSITIVE_STRUCT_H_ -#define _SOC_SENSITIVE_STRUCT_H_ - +#pragma once +#include #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -typedef volatile struct sensitive_dev_s{ - union { - struct { - uint32_t rom_table_lock : 1; /*Need add description*/ - uint32_t reserved1 : 31; /*Reserved*/ - }; - uint32_t val; - } rom_table_lock; - uint32_t rom_table; - union { - struct { - uint32_t apb_peripheral_access_lock : 1; /*Need add description*/ - uint32_t reserved1 : 31; /*Reserved*/ - }; - uint32_t val; - } apb_peripheral_access_0; - union { - struct { - uint32_t apb_peripheral_access_split_burst: 1; /*Need add description*/ - uint32_t reserved1 : 31; /*Reserved*/ - }; - uint32_t val; - } apb_peripheral_access_1; - union { - struct { - uint32_t internal_sram_usage_lock : 1; /*Need add description*/ - uint32_t reserved1 : 31; /*Reserved*/ - }; - uint32_t val; - } internal_sram_usage_0; - union { - struct { - uint32_t internal_sram_usage_cpu_cache : 1; /*Need add description*/ - uint32_t internal_sram_usage_cpu_sram : 3; /*Need add description*/ - uint32_t reserved4 : 28; /*Reserved*/ - }; - uint32_t val; - } internal_sram_usage_1; - union { - struct { - uint32_t internal_sram_usage_mac_dump_sram: 3; /*Need add description*/ - uint32_t internal_sram_alloc_mac_dump : 1; /*Need add description*/ - uint32_t reserved4 : 28; /*Reserved*/ - }; - uint32_t val; - } internal_sram_usage_3; - union { - struct { - uint32_t cache_tag_access_lock : 1; /*Need add description*/ - uint32_t reserved1 : 31; /*Reserved*/ - }; - uint32_t val; - } cache_tag_access_0; - union { - struct { - uint32_t pro_i_tag_rd_acs : 1; /*Need add description*/ - uint32_t pro_i_tag_wr_acs : 1; /*Need add description*/ - uint32_t pro_d_tag_rd_acs : 1; /*Need add description*/ - uint32_t pro_d_tag_wr_acs : 1; /*Need add description*/ - uint32_t reserved4 : 28; /*Reserved*/ - }; - uint32_t val; - } cache_tag_access_1; - union { - struct { - uint32_t cache_mmu_access_lock : 1; /*Need add description*/ - uint32_t reserved1 : 31; /*Reserved*/ - }; - uint32_t val; - } cache_mmu_access_0; - union { - struct { - uint32_t pro_mmu_rd_acs : 1; /*Need add description*/ - uint32_t pro_mmu_wr_acs : 1; /*Need add description*/ - uint32_t reserved2 : 30; /*Reserved*/ - }; - uint32_t val; - } cache_mmu_access_1; - union { - struct { - uint32_t pif_access_monitor_lock : 1; /*Need add description*/ - uint32_t reserved1 : 31; /*Reserved*/ - }; - uint32_t val; - } pif_access_monitor_0; - union { - struct { - uint32_t pif_access_monitor_nonword_violate_clr: 1; /*Need add description*/ - uint32_t pif_access_monitor_nonword_violate_en: 1; /*Need add description*/ - uint32_t reserved2 : 30; /*Reserved*/ - }; - uint32_t val; - } pif_access_monitor_1; - union { - struct { - uint32_t pif_access_monitor_nonword_violate_intr: 1; /*Need add description*/ - uint32_t pif_access_monitor_nonword_violate_status_hsize: 2; /*Need add description*/ - uint32_t reserved3 : 29; /*Reserved*/ - }; - uint32_t val; - } pif_access_monitor_2; - uint32_t pif_access_monitor_3; - union { - struct { - uint32_t xts_aes_key_update : 1; /*Set this bit to update xts_aes key*/ - uint32_t reserved1 : 31; /*Reserved*/ - }; - uint32_t val; - } xts_aes_key_update; - union { - struct { - uint32_t clk_en : 1; /*Need add description*/ - uint32_t reserved1 : 31; /*Reserved*/ - }; - uint32_t val; - } clock_gate; - uint32_t reserved_44; - uint32_t reserved_48; - uint32_t reserved_4c; - uint32_t reserved_50; - uint32_t reserved_54; - uint32_t reserved_58; - uint32_t reserved_5c; - uint32_t reserved_60; - uint32_t reserved_64; - uint32_t reserved_68; - uint32_t reserved_6c; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t reserved_fc; - uint32_t reserved_100; - uint32_t reserved_104; - uint32_t reserved_108; - uint32_t reserved_10c; - uint32_t reserved_110; - uint32_t reserved_114; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t reserved_140; - uint32_t reserved_144; - uint32_t reserved_148; - uint32_t reserved_14c; - uint32_t reserved_150; - uint32_t reserved_154; - uint32_t reserved_158; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; - uint32_t reserved_18c; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; - uint32_t reserved_1cc; - uint32_t reserved_1d0; - uint32_t reserved_1d4; - uint32_t reserved_1d8; - uint32_t reserved_1dc; - uint32_t reserved_1e0; - uint32_t reserved_1e4; - uint32_t reserved_1e8; - uint32_t reserved_1ec; - uint32_t reserved_1f0; - uint32_t reserved_1f4; - uint32_t reserved_1f8; - uint32_t reserved_1fc; - uint32_t reserved_200; - uint32_t reserved_204; - uint32_t reserved_208; - uint32_t reserved_20c; - uint32_t reserved_210; - uint32_t reserved_214; - uint32_t reserved_218; - uint32_t reserved_21c; - uint32_t reserved_220; - uint32_t reserved_224; - uint32_t reserved_228; - uint32_t reserved_22c; - uint32_t reserved_230; - uint32_t reserved_234; - uint32_t reserved_238; - uint32_t reserved_23c; - uint32_t reserved_240; - uint32_t reserved_244; - uint32_t reserved_248; - uint32_t reserved_24c; - uint32_t reserved_250; - uint32_t reserved_254; - uint32_t reserved_258; - uint32_t reserved_25c; - uint32_t reserved_260; - uint32_t reserved_264; - uint32_t reserved_268; - uint32_t reserved_26c; - uint32_t reserved_270; - uint32_t reserved_274; - uint32_t reserved_278; - uint32_t reserved_27c; - uint32_t reserved_280; - uint32_t reserved_284; - uint32_t reserved_288; - uint32_t reserved_28c; - uint32_t reserved_290; - uint32_t reserved_294; - uint32_t reserved_298; - uint32_t reserved_29c; - uint32_t reserved_2a0; - uint32_t reserved_2a4; - uint32_t reserved_2a8; - uint32_t reserved_2ac; - uint32_t reserved_2b0; - uint32_t reserved_2b4; - uint32_t reserved_2b8; - uint32_t reserved_2bc; - uint32_t reserved_2c0; - uint32_t reserved_2c4; - uint32_t reserved_2c8; - uint32_t reserved_2cc; - uint32_t reserved_2d0; - uint32_t reserved_2d4; - uint32_t reserved_2d8; - uint32_t reserved_2dc; - uint32_t reserved_2e0; - uint32_t reserved_2e4; - uint32_t reserved_2e8; - uint32_t reserved_2ec; - uint32_t reserved_2f0; - uint32_t reserved_2f4; - uint32_t reserved_2f8; - uint32_t reserved_2fc; - uint32_t reserved_300; - uint32_t reserved_304; - uint32_t reserved_308; - uint32_t reserved_30c; - uint32_t reserved_310; - uint32_t reserved_314; - uint32_t reserved_318; - uint32_t reserved_31c; - uint32_t reserved_320; - uint32_t reserved_324; - uint32_t reserved_328; - uint32_t reserved_32c; - uint32_t reserved_330; - uint32_t reserved_334; - uint32_t reserved_338; - uint32_t reserved_33c; - uint32_t reserved_340; - uint32_t reserved_344; - uint32_t reserved_348; - uint32_t reserved_34c; - uint32_t reserved_350; - uint32_t reserved_354; - uint32_t reserved_358; - uint32_t reserved_35c; - uint32_t reserved_360; - uint32_t reserved_364; - uint32_t reserved_368; - uint32_t reserved_36c; - uint32_t reserved_370; - uint32_t reserved_374; - uint32_t reserved_378; - uint32_t reserved_37c; - uint32_t reserved_380; - uint32_t reserved_384; - uint32_t reserved_388; - uint32_t reserved_38c; - uint32_t reserved_390; - uint32_t reserved_394; - uint32_t reserved_398; - uint32_t reserved_39c; - uint32_t reserved_3a0; - uint32_t reserved_3a4; - uint32_t reserved_3a8; - uint32_t reserved_3ac; - uint32_t reserved_3b0; - uint32_t reserved_3b4; - uint32_t reserved_3b8; - uint32_t reserved_3bc; - uint32_t reserved_3c0; - uint32_t reserved_3c4; - uint32_t reserved_3c8; - uint32_t reserved_3cc; - uint32_t reserved_3d0; - uint32_t reserved_3d4; - uint32_t reserved_3d8; - uint32_t reserved_3dc; - uint32_t reserved_3e0; - uint32_t reserved_3e4; - uint32_t reserved_3e8; - uint32_t reserved_3ec; - uint32_t reserved_3f0; - uint32_t reserved_3f4; - uint32_t reserved_3f8; - uint32_t reserved_3fc; - uint32_t reserved_400; - uint32_t reserved_404; - uint32_t reserved_408; - uint32_t reserved_40c; - uint32_t reserved_410; - uint32_t reserved_414; - uint32_t reserved_418; - uint32_t reserved_41c; - uint32_t reserved_420; - uint32_t reserved_424; - uint32_t reserved_428; - uint32_t reserved_42c; - uint32_t reserved_430; - uint32_t reserved_434; - uint32_t reserved_438; - uint32_t reserved_43c; - uint32_t reserved_440; - uint32_t reserved_444; - uint32_t reserved_448; - uint32_t reserved_44c; - uint32_t reserved_450; - uint32_t reserved_454; - uint32_t reserved_458; - uint32_t reserved_45c; - uint32_t reserved_460; - uint32_t reserved_464; - uint32_t reserved_468; - uint32_t reserved_46c; - uint32_t reserved_470; - uint32_t reserved_474; - uint32_t reserved_478; - uint32_t reserved_47c; - uint32_t reserved_480; - uint32_t reserved_484; - uint32_t reserved_488; - uint32_t reserved_48c; - uint32_t reserved_490; - uint32_t reserved_494; - uint32_t reserved_498; - uint32_t reserved_49c; - uint32_t reserved_4a0; - uint32_t reserved_4a4; - uint32_t reserved_4a8; - uint32_t reserved_4ac; - uint32_t reserved_4b0; - uint32_t reserved_4b4; - uint32_t reserved_4b8; - uint32_t reserved_4bc; - uint32_t reserved_4c0; - uint32_t reserved_4c4; - uint32_t reserved_4c8; - uint32_t reserved_4cc; - uint32_t reserved_4d0; - uint32_t reserved_4d4; - uint32_t reserved_4d8; - uint32_t reserved_4dc; - uint32_t reserved_4e0; - uint32_t reserved_4e4; - uint32_t reserved_4e8; - uint32_t reserved_4ec; - uint32_t reserved_4f0; - uint32_t reserved_4f4; - uint32_t reserved_4f8; - uint32_t reserved_4fc; - uint32_t reserved_500; - uint32_t reserved_504; - uint32_t reserved_508; - uint32_t reserved_50c; - uint32_t reserved_510; - uint32_t reserved_514; - uint32_t reserved_518; - uint32_t reserved_51c; - uint32_t reserved_520; - uint32_t reserved_524; - uint32_t reserved_528; - uint32_t reserved_52c; - uint32_t reserved_530; - uint32_t reserved_534; - uint32_t reserved_538; - uint32_t reserved_53c; - uint32_t reserved_540; - uint32_t reserved_544; - uint32_t reserved_548; - uint32_t reserved_54c; - uint32_t reserved_550; - uint32_t reserved_554; - uint32_t reserved_558; - uint32_t reserved_55c; - uint32_t reserved_560; - uint32_t reserved_564; - uint32_t reserved_568; - uint32_t reserved_56c; - uint32_t reserved_570; - uint32_t reserved_574; - uint32_t reserved_578; - uint32_t reserved_57c; - uint32_t reserved_580; - uint32_t reserved_584; - uint32_t reserved_588; - uint32_t reserved_58c; - uint32_t reserved_590; - uint32_t reserved_594; - uint32_t reserved_598; - uint32_t reserved_59c; - uint32_t reserved_5a0; - uint32_t reserved_5a4; - uint32_t reserved_5a8; - uint32_t reserved_5ac; - uint32_t reserved_5b0; - uint32_t reserved_5b4; - uint32_t reserved_5b8; - uint32_t reserved_5bc; - uint32_t reserved_5c0; - uint32_t reserved_5c4; - uint32_t reserved_5c8; - uint32_t reserved_5cc; - uint32_t reserved_5d0; - uint32_t reserved_5d4; - uint32_t reserved_5d8; - uint32_t reserved_5dc; - uint32_t reserved_5e0; - uint32_t reserved_5e4; - uint32_t reserved_5e8; - uint32_t reserved_5ec; - uint32_t reserved_5f0; - uint32_t reserved_5f4; - uint32_t reserved_5f8; - uint32_t reserved_5fc; - uint32_t reserved_600; - uint32_t reserved_604; - uint32_t reserved_608; - uint32_t reserved_60c; - uint32_t reserved_610; - uint32_t reserved_614; - uint32_t reserved_618; - uint32_t reserved_61c; - uint32_t reserved_620; - uint32_t reserved_624; - uint32_t reserved_628; - uint32_t reserved_62c; - uint32_t reserved_630; - uint32_t reserved_634; - uint32_t reserved_638; - uint32_t reserved_63c; - uint32_t reserved_640; - uint32_t reserved_644; - uint32_t reserved_648; - uint32_t reserved_64c; - uint32_t reserved_650; - uint32_t reserved_654; - uint32_t reserved_658; - uint32_t reserved_65c; - uint32_t reserved_660; - uint32_t reserved_664; - uint32_t reserved_668; - uint32_t reserved_66c; - uint32_t reserved_670; - uint32_t reserved_674; - uint32_t reserved_678; - uint32_t reserved_67c; - uint32_t reserved_680; - uint32_t reserved_684; - uint32_t reserved_688; - uint32_t reserved_68c; - uint32_t reserved_690; - uint32_t reserved_694; - uint32_t reserved_698; - uint32_t reserved_69c; - uint32_t reserved_6a0; - uint32_t reserved_6a4; - uint32_t reserved_6a8; - uint32_t reserved_6ac; - uint32_t reserved_6b0; - uint32_t reserved_6b4; - uint32_t reserved_6b8; - uint32_t reserved_6bc; - uint32_t reserved_6c0; - uint32_t reserved_6c4; - uint32_t reserved_6c8; - uint32_t reserved_6cc; - uint32_t reserved_6d0; - uint32_t reserved_6d4; - uint32_t reserved_6d8; - uint32_t reserved_6dc; - uint32_t reserved_6e0; - uint32_t reserved_6e4; - uint32_t reserved_6e8; - uint32_t reserved_6ec; - uint32_t reserved_6f0; - uint32_t reserved_6f4; - uint32_t reserved_6f8; - uint32_t reserved_6fc; - uint32_t reserved_700; - uint32_t reserved_704; - uint32_t reserved_708; - uint32_t reserved_70c; - uint32_t reserved_710; - uint32_t reserved_714; - uint32_t reserved_718; - uint32_t reserved_71c; - uint32_t reserved_720; - uint32_t reserved_724; - uint32_t reserved_728; - uint32_t reserved_72c; - uint32_t reserved_730; - uint32_t reserved_734; - uint32_t reserved_738; - uint32_t reserved_73c; - uint32_t reserved_740; - uint32_t reserved_744; - uint32_t reserved_748; - uint32_t reserved_74c; - uint32_t reserved_750; - uint32_t reserved_754; - uint32_t reserved_758; - uint32_t reserved_75c; - uint32_t reserved_760; - uint32_t reserved_764; - uint32_t reserved_768; - uint32_t reserved_76c; - uint32_t reserved_770; - uint32_t reserved_774; - uint32_t reserved_778; - uint32_t reserved_77c; - uint32_t reserved_780; - uint32_t reserved_784; - uint32_t reserved_788; - uint32_t reserved_78c; - uint32_t reserved_790; - uint32_t reserved_794; - uint32_t reserved_798; - uint32_t reserved_79c; - uint32_t reserved_7a0; - uint32_t reserved_7a4; - uint32_t reserved_7a8; - uint32_t reserved_7ac; - uint32_t reserved_7b0; - uint32_t reserved_7b4; - uint32_t reserved_7b8; - uint32_t reserved_7bc; - uint32_t reserved_7c0; - uint32_t reserved_7c4; - uint32_t reserved_7c8; - uint32_t reserved_7cc; - uint32_t reserved_7d0; - uint32_t reserved_7d4; - uint32_t reserved_7d8; - uint32_t reserved_7dc; - uint32_t reserved_7e0; - uint32_t reserved_7e4; - uint32_t reserved_7e8; - uint32_t reserved_7ec; - uint32_t reserved_7f0; - uint32_t reserved_7f4; - uint32_t reserved_7f8; - uint32_t reserved_7fc; - uint32_t reserved_800; - uint32_t reserved_804; - uint32_t reserved_808; - uint32_t reserved_80c; - uint32_t reserved_810; - uint32_t reserved_814; - uint32_t reserved_818; - uint32_t reserved_81c; - uint32_t reserved_820; - uint32_t reserved_824; - uint32_t reserved_828; - uint32_t reserved_82c; - uint32_t reserved_830; - uint32_t reserved_834; - uint32_t reserved_838; - uint32_t reserved_83c; - uint32_t reserved_840; - uint32_t reserved_844; - uint32_t reserved_848; - uint32_t reserved_84c; - uint32_t reserved_850; - uint32_t reserved_854; - uint32_t reserved_858; - uint32_t reserved_85c; - uint32_t reserved_860; - uint32_t reserved_864; - uint32_t reserved_868; - uint32_t reserved_86c; - uint32_t reserved_870; - uint32_t reserved_874; - uint32_t reserved_878; - uint32_t reserved_87c; - uint32_t reserved_880; - uint32_t reserved_884; - uint32_t reserved_888; - uint32_t reserved_88c; - uint32_t reserved_890; - uint32_t reserved_894; - uint32_t reserved_898; - uint32_t reserved_89c; - uint32_t reserved_8a0; - uint32_t reserved_8a4; - uint32_t reserved_8a8; - uint32_t reserved_8ac; - uint32_t reserved_8b0; - uint32_t reserved_8b4; - uint32_t reserved_8b8; - uint32_t reserved_8bc; - uint32_t reserved_8c0; - uint32_t reserved_8c4; - uint32_t reserved_8c8; - uint32_t reserved_8cc; - uint32_t reserved_8d0; - uint32_t reserved_8d4; - uint32_t reserved_8d8; - uint32_t reserved_8dc; - uint32_t reserved_8e0; - uint32_t reserved_8e4; - uint32_t reserved_8e8; - uint32_t reserved_8ec; - uint32_t reserved_8f0; - uint32_t reserved_8f4; - uint32_t reserved_8f8; - uint32_t reserved_8fc; - uint32_t reserved_900; - uint32_t reserved_904; - uint32_t reserved_908; - uint32_t reserved_90c; - uint32_t reserved_910; - uint32_t reserved_914; - uint32_t reserved_918; - uint32_t reserved_91c; - uint32_t reserved_920; - uint32_t reserved_924; - uint32_t reserved_928; - uint32_t reserved_92c; - uint32_t reserved_930; - uint32_t reserved_934; - uint32_t reserved_938; - uint32_t reserved_93c; - uint32_t reserved_940; - uint32_t reserved_944; - uint32_t reserved_948; - uint32_t reserved_94c; - uint32_t reserved_950; - uint32_t reserved_954; - uint32_t reserved_958; - uint32_t reserved_95c; - uint32_t reserved_960; - uint32_t reserved_964; - uint32_t reserved_968; - uint32_t reserved_96c; - uint32_t reserved_970; - uint32_t reserved_974; - uint32_t reserved_978; - uint32_t reserved_97c; - uint32_t reserved_980; - uint32_t reserved_984; - uint32_t reserved_988; - uint32_t reserved_98c; - uint32_t reserved_990; - uint32_t reserved_994; - uint32_t reserved_998; - uint32_t reserved_99c; - uint32_t reserved_9a0; - uint32_t reserved_9a4; - uint32_t reserved_9a8; - uint32_t reserved_9ac; - uint32_t reserved_9b0; - uint32_t reserved_9b4; - uint32_t reserved_9b8; - uint32_t reserved_9bc; - uint32_t reserved_9c0; - uint32_t reserved_9c4; - uint32_t reserved_9c8; - uint32_t reserved_9cc; - uint32_t reserved_9d0; - uint32_t reserved_9d4; - uint32_t reserved_9d8; - uint32_t reserved_9dc; - uint32_t reserved_9e0; - uint32_t reserved_9e4; - uint32_t reserved_9e8; - uint32_t reserved_9ec; - uint32_t reserved_9f0; - uint32_t reserved_9f4; - uint32_t reserved_9f8; - uint32_t reserved_9fc; - uint32_t reserved_a00; - uint32_t reserved_a04; - uint32_t reserved_a08; - uint32_t reserved_a0c; - uint32_t reserved_a10; - uint32_t reserved_a14; - uint32_t reserved_a18; - uint32_t reserved_a1c; - uint32_t reserved_a20; - uint32_t reserved_a24; - uint32_t reserved_a28; - uint32_t reserved_a2c; - uint32_t reserved_a30; - uint32_t reserved_a34; - uint32_t reserved_a38; - uint32_t reserved_a3c; - uint32_t reserved_a40; - uint32_t reserved_a44; - uint32_t reserved_a48; - uint32_t reserved_a4c; - uint32_t reserved_a50; - uint32_t reserved_a54; - uint32_t reserved_a58; - uint32_t reserved_a5c; - uint32_t reserved_a60; - uint32_t reserved_a64; - uint32_t reserved_a68; - uint32_t reserved_a6c; - uint32_t reserved_a70; - uint32_t reserved_a74; - uint32_t reserved_a78; - uint32_t reserved_a7c; - uint32_t reserved_a80; - uint32_t reserved_a84; - uint32_t reserved_a88; - uint32_t reserved_a8c; - uint32_t reserved_a90; - uint32_t reserved_a94; - uint32_t reserved_a98; - uint32_t reserved_a9c; - uint32_t reserved_aa0; - uint32_t reserved_aa4; - uint32_t reserved_aa8; - uint32_t reserved_aac; - uint32_t reserved_ab0; - uint32_t reserved_ab4; - uint32_t reserved_ab8; - uint32_t reserved_abc; - uint32_t reserved_ac0; - uint32_t reserved_ac4; - uint32_t reserved_ac8; - uint32_t reserved_acc; - uint32_t reserved_ad0; - uint32_t reserved_ad4; - uint32_t reserved_ad8; - uint32_t reserved_adc; - uint32_t reserved_ae0; - uint32_t reserved_ae4; - uint32_t reserved_ae8; - uint32_t reserved_aec; - uint32_t reserved_af0; - uint32_t reserved_af4; - uint32_t reserved_af8; - uint32_t reserved_afc; - uint32_t reserved_b00; - uint32_t reserved_b04; - uint32_t reserved_b08; - uint32_t reserved_b0c; - uint32_t reserved_b10; - uint32_t reserved_b14; - uint32_t reserved_b18; - uint32_t reserved_b1c; - uint32_t reserved_b20; - uint32_t reserved_b24; - uint32_t reserved_b28; - uint32_t reserved_b2c; - uint32_t reserved_b30; - uint32_t reserved_b34; - uint32_t reserved_b38; - uint32_t reserved_b3c; - uint32_t reserved_b40; - uint32_t reserved_b44; - uint32_t reserved_b48; - uint32_t reserved_b4c; - uint32_t reserved_b50; - uint32_t reserved_b54; - uint32_t reserved_b58; - uint32_t reserved_b5c; - uint32_t reserved_b60; - uint32_t reserved_b64; - uint32_t reserved_b68; - uint32_t reserved_b6c; - uint32_t reserved_b70; - uint32_t reserved_b74; - uint32_t reserved_b78; - uint32_t reserved_b7c; - uint32_t reserved_b80; - uint32_t reserved_b84; - uint32_t reserved_b88; - uint32_t reserved_b8c; - uint32_t reserved_b90; - uint32_t reserved_b94; - uint32_t reserved_b98; - uint32_t reserved_b9c; - uint32_t reserved_ba0; - uint32_t reserved_ba4; - uint32_t reserved_ba8; - uint32_t reserved_bac; - uint32_t reserved_bb0; - uint32_t reserved_bb4; - uint32_t reserved_bb8; - uint32_t reserved_bbc; - uint32_t reserved_bc0; - uint32_t reserved_bc4; - uint32_t reserved_bc8; - uint32_t reserved_bcc; - uint32_t reserved_bd0; - uint32_t reserved_bd4; - uint32_t reserved_bd8; - uint32_t reserved_bdc; - uint32_t reserved_be0; - uint32_t reserved_be4; - uint32_t reserved_be8; - uint32_t reserved_bec; - uint32_t reserved_bf0; - uint32_t reserved_bf4; - uint32_t reserved_bf8; - uint32_t reserved_bfc; - uint32_t reserved_c00; - uint32_t reserved_c04; - uint32_t reserved_c08; - uint32_t reserved_c0c; - uint32_t reserved_c10; - uint32_t reserved_c14; - uint32_t reserved_c18; - uint32_t reserved_c1c; - uint32_t reserved_c20; - uint32_t reserved_c24; - uint32_t reserved_c28; - uint32_t reserved_c2c; - uint32_t reserved_c30; - uint32_t reserved_c34; - uint32_t reserved_c38; - uint32_t reserved_c3c; - uint32_t reserved_c40; - uint32_t reserved_c44; - uint32_t reserved_c48; - uint32_t reserved_c4c; - uint32_t reserved_c50; - uint32_t reserved_c54; - uint32_t reserved_c58; - uint32_t reserved_c5c; - uint32_t reserved_c60; - uint32_t reserved_c64; - uint32_t reserved_c68; - uint32_t reserved_c6c; - uint32_t reserved_c70; - uint32_t reserved_c74; - uint32_t reserved_c78; - uint32_t reserved_c7c; - uint32_t reserved_c80; - uint32_t reserved_c84; - uint32_t reserved_c88; - uint32_t reserved_c8c; - uint32_t reserved_c90; - uint32_t reserved_c94; - uint32_t reserved_c98; - uint32_t reserved_c9c; - uint32_t reserved_ca0; - uint32_t reserved_ca4; - uint32_t reserved_ca8; - uint32_t reserved_cac; - uint32_t reserved_cb0; - uint32_t reserved_cb4; - uint32_t reserved_cb8; - uint32_t reserved_cbc; - uint32_t reserved_cc0; - uint32_t reserved_cc4; - uint32_t reserved_cc8; - uint32_t reserved_ccc; - uint32_t reserved_cd0; - uint32_t reserved_cd4; - uint32_t reserved_cd8; - uint32_t reserved_cdc; - uint32_t reserved_ce0; - uint32_t reserved_ce4; - uint32_t reserved_ce8; - uint32_t reserved_cec; - uint32_t reserved_cf0; - uint32_t reserved_cf4; - uint32_t reserved_cf8; - uint32_t reserved_cfc; - uint32_t reserved_d00; - uint32_t reserved_d04; - uint32_t reserved_d08; - uint32_t reserved_d0c; - uint32_t reserved_d10; - uint32_t reserved_d14; - uint32_t reserved_d18; - uint32_t reserved_d1c; - uint32_t reserved_d20; - uint32_t reserved_d24; - uint32_t reserved_d28; - uint32_t reserved_d2c; - uint32_t reserved_d30; - uint32_t reserved_d34; - uint32_t reserved_d38; - uint32_t reserved_d3c; - uint32_t reserved_d40; - uint32_t reserved_d44; - uint32_t reserved_d48; - uint32_t reserved_d4c; - uint32_t reserved_d50; - uint32_t reserved_d54; - uint32_t reserved_d58; - uint32_t reserved_d5c; - uint32_t reserved_d60; - uint32_t reserved_d64; - uint32_t reserved_d68; - uint32_t reserved_d6c; - uint32_t reserved_d70; - uint32_t reserved_d74; - uint32_t reserved_d78; - uint32_t reserved_d7c; - uint32_t reserved_d80; - uint32_t reserved_d84; - uint32_t reserved_d88; - uint32_t reserved_d8c; - uint32_t reserved_d90; - uint32_t reserved_d94; - uint32_t reserved_d98; - uint32_t reserved_d9c; - uint32_t reserved_da0; - uint32_t reserved_da4; - uint32_t reserved_da8; - uint32_t reserved_dac; - uint32_t reserved_db0; - uint32_t reserved_db4; - uint32_t reserved_db8; - uint32_t reserved_dbc; - uint32_t reserved_dc0; - uint32_t reserved_dc4; - uint32_t reserved_dc8; - uint32_t reserved_dcc; - uint32_t reserved_dd0; - uint32_t reserved_dd4; - uint32_t reserved_dd8; - uint32_t reserved_ddc; - uint32_t reserved_de0; - uint32_t reserved_de4; - uint32_t reserved_de8; - uint32_t reserved_dec; - uint32_t reserved_df0; - uint32_t reserved_df4; - uint32_t reserved_df8; - uint32_t reserved_dfc; - uint32_t reserved_e00; - uint32_t reserved_e04; - uint32_t reserved_e08; - uint32_t reserved_e0c; - uint32_t reserved_e10; - uint32_t reserved_e14; - uint32_t reserved_e18; - uint32_t reserved_e1c; - uint32_t reserved_e20; - uint32_t reserved_e24; - uint32_t reserved_e28; - uint32_t reserved_e2c; - uint32_t reserved_e30; - uint32_t reserved_e34; - uint32_t reserved_e38; - uint32_t reserved_e3c; - uint32_t reserved_e40; - uint32_t reserved_e44; - uint32_t reserved_e48; - uint32_t reserved_e4c; - uint32_t reserved_e50; - uint32_t reserved_e54; - uint32_t reserved_e58; - uint32_t reserved_e5c; - uint32_t reserved_e60; - uint32_t reserved_e64; - uint32_t reserved_e68; - uint32_t reserved_e6c; - uint32_t reserved_e70; - uint32_t reserved_e74; - uint32_t reserved_e78; - uint32_t reserved_e7c; - uint32_t reserved_e80; - uint32_t reserved_e84; - uint32_t reserved_e88; - uint32_t reserved_e8c; - uint32_t reserved_e90; - uint32_t reserved_e94; - uint32_t reserved_e98; - uint32_t reserved_e9c; - uint32_t reserved_ea0; - uint32_t reserved_ea4; - uint32_t reserved_ea8; - uint32_t reserved_eac; - uint32_t reserved_eb0; - uint32_t reserved_eb4; - uint32_t reserved_eb8; - uint32_t reserved_ebc; - uint32_t reserved_ec0; - uint32_t reserved_ec4; - uint32_t reserved_ec8; - uint32_t reserved_ecc; - uint32_t reserved_ed0; - uint32_t reserved_ed4; - uint32_t reserved_ed8; - uint32_t reserved_edc; - uint32_t reserved_ee0; - uint32_t reserved_ee4; - uint32_t reserved_ee8; - uint32_t reserved_eec; - uint32_t reserved_ef0; - uint32_t reserved_ef4; - uint32_t reserved_ef8; - uint32_t reserved_efc; - uint32_t reserved_f00; - uint32_t reserved_f04; - uint32_t reserved_f08; - uint32_t reserved_f0c; - uint32_t reserved_f10; - uint32_t reserved_f14; - uint32_t reserved_f18; - uint32_t reserved_f1c; - uint32_t reserved_f20; - uint32_t reserved_f24; - uint32_t reserved_f28; - uint32_t reserved_f2c; - uint32_t reserved_f30; - uint32_t reserved_f34; - uint32_t reserved_f38; - uint32_t reserved_f3c; - uint32_t reserved_f40; - uint32_t reserved_f44; - uint32_t reserved_f48; - uint32_t reserved_f4c; - uint32_t reserved_f50; - uint32_t reserved_f54; - uint32_t reserved_f58; - uint32_t reserved_f5c; - uint32_t reserved_f60; - uint32_t reserved_f64; - uint32_t reserved_f68; - uint32_t reserved_f6c; - uint32_t reserved_f70; - uint32_t reserved_f74; - uint32_t reserved_f78; - uint32_t reserved_f7c; - uint32_t reserved_f80; - uint32_t reserved_f84; - uint32_t reserved_f88; - uint32_t reserved_f8c; - uint32_t reserved_f90; - uint32_t reserved_f94; - uint32_t reserved_f98; - uint32_t reserved_f9c; - uint32_t reserved_fa0; - uint32_t reserved_fa4; - uint32_t reserved_fa8; - uint32_t reserved_fac; - uint32_t reserved_fb0; - uint32_t reserved_fb4; - uint32_t reserved_fb8; - uint32_t reserved_fbc; - uint32_t reserved_fc0; - uint32_t reserved_fc4; - uint32_t reserved_fc8; - uint32_t reserved_fcc; - uint32_t reserved_fd0; - uint32_t reserved_fd4; - uint32_t reserved_fd8; - uint32_t reserved_fdc; - uint32_t reserved_fe0; - uint32_t reserved_fe4; - uint32_t reserved_fe8; - uint32_t reserved_fec; - uint32_t reserved_ff0; - uint32_t reserved_ff4; - uint32_t reserved_ff8; - union { - struct { - uint32_t sensitive_date : 28; /*Need add description*/ - uint32_t reserved28 : 4; /*Reserved*/ - }; - uint32_t val; - } date; +/** Group: Configuration Registers */ +/** Type of rom_table_lock register + * register description + */ +typedef union { + struct { + /** rom_table_lock : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t rom_table_lock:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sensitive_rom_table_lock_reg_t; + +/** Type of rom_table register + * register description + */ +typedef union { + struct { + /** rom_table : R/W; bitpos: [31:0]; default: 0; + * Need add description + */ + uint32_t rom_table:32; + }; + uint32_t val; +} sensitive_rom_table_reg_t; + +/** Type of apb_peripheral_access_0 register + * register description + */ +typedef union { + struct { + /** apb_peripheral_access_lock : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t apb_peripheral_access_lock:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sensitive_apb_peripheral_access_0_reg_t; + +/** Type of apb_peripheral_access_1 register + * register description + */ +typedef union { + struct { + /** apb_peripheral_access_split_burst : R/W; bitpos: [0]; default: 1; + * Need add description + */ + uint32_t apb_peripheral_access_split_burst:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sensitive_apb_peripheral_access_1_reg_t; + +/** Type of internal_sram_usage_0 register + * register description + */ +typedef union { + struct { + /** internal_sram_usage_lock : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t internal_sram_usage_lock:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sensitive_internal_sram_usage_0_reg_t; + +/** Type of internal_sram_usage_1 register + * register description + */ +typedef union { + struct { + /** internal_sram_usage_cpu_cache : R/W; bitpos: [0]; default: 1; + * Need add description + */ + uint32_t internal_sram_usage_cpu_cache:1; + /** internal_sram_usage_cpu_sram : R/W; bitpos: [3:1]; default: 7; + * Need add description + */ + uint32_t internal_sram_usage_cpu_sram:3; + uint32_t reserved_4:28; + }; + uint32_t val; +} sensitive_internal_sram_usage_1_reg_t; + +/** Type of internal_sram_usage_3 register + * register description + */ +typedef union { + struct { + /** internal_sram_usage_mac_dump_sram : R/W; bitpos: [2:0]; default: 0; + * Need add description + */ + uint32_t internal_sram_usage_mac_dump_sram:3; + /** internal_sram_alloc_mac_dump : R/W; bitpos: [3]; default: 0; + * Need add description + */ + uint32_t internal_sram_alloc_mac_dump:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} sensitive_internal_sram_usage_3_reg_t; + +/** Type of cache_tag_access_0 register + * register description + */ +typedef union { + struct { + /** cache_tag_access_lock : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t cache_tag_access_lock:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sensitive_cache_tag_access_0_reg_t; + +/** Type of cache_tag_access_1 register + * register description + */ +typedef union { + struct { + /** pro_i_tag_rd_acs : R/W; bitpos: [0]; default: 1; + * Need add description + */ + uint32_t pro_i_tag_rd_acs:1; + /** pro_i_tag_wr_acs : R/W; bitpos: [1]; default: 1; + * Need add description + */ + uint32_t pro_i_tag_wr_acs:1; + /** pro_d_tag_rd_acs : R/W; bitpos: [2]; default: 1; + * Need add description + */ + uint32_t pro_d_tag_rd_acs:1; + /** pro_d_tag_wr_acs : R/W; bitpos: [3]; default: 1; + * Need add description + */ + uint32_t pro_d_tag_wr_acs:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} sensitive_cache_tag_access_1_reg_t; + +/** Type of cache_mmu_access_0 register + * register description + */ +typedef union { + struct { + /** cache_mmu_access_lock : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t cache_mmu_access_lock:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sensitive_cache_mmu_access_0_reg_t; + +/** Type of cache_mmu_access_1 register + * register description + */ +typedef union { + struct { + /** pro_mmu_rd_acs : R/W; bitpos: [0]; default: 1; + * Need add description + */ + uint32_t pro_mmu_rd_acs:1; + /** pro_mmu_wr_acs : R/W; bitpos: [1]; default: 1; + * Need add description + */ + uint32_t pro_mmu_wr_acs:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} sensitive_cache_mmu_access_1_reg_t; + +/** Type of pif_access_monitor_0 register + * register description + */ +typedef union { + struct { + /** pif_access_monitor_lock : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t pif_access_monitor_lock:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sensitive_pif_access_monitor_0_reg_t; + +/** Type of pif_access_monitor_1 register + * register description + */ +typedef union { + struct { + /** pif_access_monitor_nonword_violate_clr : R/W; bitpos: [0]; default: 1; + * Need add description + */ + uint32_t pif_access_monitor_nonword_violate_clr:1; + /** pif_access_monitor_nonword_violate_en : R/W; bitpos: [1]; default: 1; + * Need add description + */ + uint32_t pif_access_monitor_nonword_violate_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} sensitive_pif_access_monitor_1_reg_t; + +/** Type of pif_access_monitor_2 register + * register description + */ +typedef union { + struct { + /** pif_access_monitor_nonword_violate_intr : RO; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t pif_access_monitor_nonword_violate_intr:1; + /** pif_access_monitor_nonword_violate_status_hsize : RO; bitpos: [2:1]; default: 0; + * Need add description + */ + uint32_t pif_access_monitor_nonword_violate_status_hsize:2; + uint32_t reserved_3:29; + }; + uint32_t val; +} sensitive_pif_access_monitor_2_reg_t; + +/** Type of pif_access_monitor_3 register + * register description + */ +typedef union { + struct { + /** pif_access_monitor_nonword_violate_status_haddr : RO; bitpos: [31:0]; default: 0; + * Need add description + */ + uint32_t pif_access_monitor_nonword_violate_status_haddr:32; + }; + uint32_t val; +} sensitive_pif_access_monitor_3_reg_t; + +/** Type of xts_aes_key_update register + * register description + */ +typedef union { + struct { + /** xts_aes_key_update : R/W; bitpos: [0]; default: 0; + * Set this bit to update xts_aes key + */ + uint32_t xts_aes_key_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sensitive_xts_aes_key_update_reg_t; + +/** Type of clock_gate register + * register description + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Need add description + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sensitive_clock_gate_reg_t; + +/** Type of sensitive_reg_date register + * register description + */ +typedef union { + struct { + /** sensitive_reg_date : R/W; bitpos: [27:0]; default: 34628353; + * Need add description + */ + uint32_t sensitive_reg_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} sensitive_sensitive_reg_date_reg_t; + + +typedef struct { + volatile sensitive_rom_table_lock_reg_t rom_table_lock; + volatile sensitive_rom_table_reg_t rom_table; + volatile sensitive_apb_peripheral_access_0_reg_t apb_peripheral_access_0; + volatile sensitive_apb_peripheral_access_1_reg_t apb_peripheral_access_1; + volatile sensitive_internal_sram_usage_0_reg_t internal_sram_usage_0; + volatile sensitive_internal_sram_usage_1_reg_t internal_sram_usage_1; + volatile sensitive_internal_sram_usage_3_reg_t internal_sram_usage_3; + volatile sensitive_cache_tag_access_0_reg_t cache_tag_access_0; + volatile sensitive_cache_tag_access_1_reg_t cache_tag_access_1; + volatile sensitive_cache_mmu_access_0_reg_t cache_mmu_access_0; + volatile sensitive_cache_mmu_access_1_reg_t cache_mmu_access_1; + volatile sensitive_pif_access_monitor_0_reg_t pif_access_monitor_0; + volatile sensitive_pif_access_monitor_1_reg_t pif_access_monitor_1; + volatile sensitive_pif_access_monitor_2_reg_t pif_access_monitor_2; + volatile sensitive_pif_access_monitor_3_reg_t pif_access_monitor_3; + volatile sensitive_xts_aes_key_update_reg_t xts_aes_key_update; + volatile sensitive_clock_gate_reg_t clock_gate; + uint32_t reserved_044[1006]; + volatile sensitive_sensitive_reg_date_reg_t sensitive_reg_date; } sensitive_dev_t; -extern sensitive_dev_t SENSITIVE; + + +#ifndef __cplusplus +_Static_assert(sizeof(sensitive_dev_t) == 0x1000, "Invalid size of sensitive_dev_t structure"); +#endif + #ifdef __cplusplus } #endif - - - -#endif /*_SOC_SENSITIVE_STRUCT_H_ */ diff --git a/components/soc/esp8684/include/soc/soc.h b/components/soc/esp8684/include/soc/soc.h index c66349dc96..1a28265110 100644 --- a/components/soc/esp8684/include/soc/soc.h +++ b/components/soc/esp8684/include/soc/soc.h @@ -12,8 +12,6 @@ #include "esp_bit_defs.h" #endif -#include "sdkconfig.h" - #define PRO_CPU_NUM (0) #define DR_REG_SYSTEM_BASE 0x600c0000 #define DR_REG_SENSITIVE_BASE 0x600c1000 diff --git a/components/soc/esp8684/include/soc/soc_caps.h b/components/soc/esp8684/include/soc/soc_caps.h index 31682e7794..4e433b22e9 100644 --- a/components/soc/esp8684/include/soc/soc_caps.h +++ b/components/soc/esp8684/include/soc/soc_caps.h @@ -110,9 +110,6 @@ #define SOC_I2C_SUPPORT_XTAL (1) #define SOC_I2C_SUPPORT_RTC (1) -/*-------------------------- I2S CAPS ----------------------------------------*/ -// TODO IDF-3896 - /*-------------------------- LEDC CAPS ---------------------------------------*/ #define SOC_LEDC_SUPPORT_XTAL_CLOCK (1) #define SOC_LEDC_CHANNEL_NUM (6) @@ -125,18 +122,6 @@ #define SOC_MPU_REGION_RO_SUPPORTED 0 #define SOC_MPU_REGION_WO_SUPPORTED 0 -/*--------------------------- RMT CAPS ---------------------------------------*/ -#define SOC_RMT_GROUPS (1U) /*!< One RMT group */ -#define SOC_RMT_TX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Transmit */ -#define SOC_RMT_RX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Receive */ -#define SOC_RMT_CHANNELS_PER_GROUP (4) /*!< Total 4 channels */ -#define SOC_RMT_MEM_WORDS_PER_CHANNEL (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */ -#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */ -#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */ -#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */ -#define SOC_RMT_SUPPORT_TX_SYNCHRO (1) /*!< Support coordinate a group of TX channels to start simultaneously */ -#define SOC_RMT_SUPPORT_XTAL (1) /*!< Support set XTAL clock as the RMT clock source */ - /*-------------------------- RTC CAPS --------------------------------------*/ #define SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128) #define SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM (108) @@ -222,9 +207,6 @@ /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ #define SOC_TOUCH_SENSOR_NUM (0U) /*! No touch sensors on ESP8684 */ -/*-------------------------- TWAI CAPS ---------------------------------------*/ -// TODO IDF-3897 - /*-------------------------- Flash Encryption CAPS----------------------------*/ #define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32) diff --git a/components/soc/esp8684/include/soc/spi_mem_reg.h b/components/soc/esp8684/include/soc/spi_mem_reg.h index 7ec9405277..649eeecf1c 100644 --- a/components/soc/esp8684/include/soc/spi_mem_reg.h +++ b/components/soc/esp8684/include/soc/spi_mem_reg.h @@ -7,10 +7,10 @@ #define _SOC_SPI_MEM_REG_H_ +#include "soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" #define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0) /* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ diff --git a/components/soc/esp8684/include/soc/system_reg.h b/components/soc/esp8684/include/soc/system_reg.h index e90cf56989..9a9c931749 100644 --- a/components/soc/esp8684/include/soc/system_reg.h +++ b/components/soc/esp8684/include/soc/system_reg.h @@ -1,722 +1,939 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_SYSTEM_REG_H_ -#define _SOC_SYSTEM_REG_H_ - +#pragma once +#include +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x0) -/* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set 1 to open dedicated_gpio module clk.*/ -#define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7)) -#define SYSTEM_CLK_EN_DEDICATED_GPIO_M (BIT(7)) -#define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x1 -#define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7 -/* SYSTEM_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set 1 to open assist_debug module clock.*/ +/** SYSTEM_CPU_PERI_CLK_EN_REG register + * cpu_peripheral clock gating register + */ +#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x0) +/** SYSTEM_CLK_EN_ASSIST_DEBUG : R/W; bitpos: [6]; default: 0; + * Set 1 to open assist_debug module clock + */ #define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6)) -#define SYSTEM_CLK_EN_ASSIST_DEBUG_M (BIT(6)) -#define SYSTEM_CLK_EN_ASSIST_DEBUG_V 0x1 +#define SYSTEM_CLK_EN_ASSIST_DEBUG_M (SYSTEM_CLK_EN_ASSIST_DEBUG_V << SYSTEM_CLK_EN_ASSIST_DEBUG_S) +#define SYSTEM_CLK_EN_ASSIST_DEBUG_V 0x00000001U #define SYSTEM_CLK_EN_ASSIST_DEBUG_S 6 +/** SYSTEM_CLK_EN_DEDICATED_GPIO : R/W; bitpos: [7]; default: 0; + * Set 1 to open dedicated_gpio module clk + */ +#define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_M (SYSTEM_CLK_EN_DEDICATED_GPIO_V << SYSTEM_CLK_EN_DEDICATED_GPIO_S) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x00000001U +#define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7 -#define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x4) -/* SYSTEM_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: Set 1 to let dedicated_gpio module reset.*/ -#define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7)) -#define SYSTEM_RST_EN_DEDICATED_GPIO_M (BIT(7)) -#define SYSTEM_RST_EN_DEDICATED_GPIO_V 0x1 -#define SYSTEM_RST_EN_DEDICATED_GPIO_S 7 -/* SYSTEM_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: Set 1 to let assist_debug module reset.*/ +/** SYSTEM_CPU_PERI_RST_EN_REG register + * cpu_peripheral reset register + */ +#define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x4) +/** SYSTEM_RST_EN_ASSIST_DEBUG : R/W; bitpos: [6]; default: 1; + * Set 1 to let assist_debug module reset + */ #define SYSTEM_RST_EN_ASSIST_DEBUG (BIT(6)) -#define SYSTEM_RST_EN_ASSIST_DEBUG_M (BIT(6)) -#define SYSTEM_RST_EN_ASSIST_DEBUG_V 0x1 +#define SYSTEM_RST_EN_ASSIST_DEBUG_M (SYSTEM_RST_EN_ASSIST_DEBUG_V << SYSTEM_RST_EN_ASSIST_DEBUG_S) +#define SYSTEM_RST_EN_ASSIST_DEBUG_V 0x00000001U #define SYSTEM_RST_EN_ASSIST_DEBUG_S 6 +/** SYSTEM_RST_EN_DEDICATED_GPIO : R/W; bitpos: [7]; default: 1; + * Set 1 to let dedicated_gpio module reset + */ +#define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_RST_EN_DEDICATED_GPIO_M (SYSTEM_RST_EN_DEDICATED_GPIO_V << SYSTEM_RST_EN_DEDICATED_GPIO_S) +#define SYSTEM_RST_EN_DEDICATED_GPIO_V 0x00000001U +#define SYSTEM_RST_EN_DEDICATED_GPIO_S 7 -#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x8) -/* SYSTEM_CPU_WAITI_DELAY_NUM : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: This field used to set delay cycle when cpu enter waiti mode, after delay waiti_ -clk will close.*/ -#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000F -#define SYSTEM_CPU_WAITI_DELAY_NUM_M ((SYSTEM_CPU_WAITI_DELAY_NUM_V)<<(SYSTEM_CPU_WAITI_DELAY_NUM_S)) -#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0xF -#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4 -/* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: Set 1 to force cpu_waiti_clk enable..*/ -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3)) -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (BIT(3)) -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x1 -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3 -/* SYSTEM_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: This field used to sel pll frequent..*/ -#define SYSTEM_PLL_FREQ_SEL (BIT(2)) -#define SYSTEM_PLL_FREQ_SEL_M (BIT(2)) -#define SYSTEM_PLL_FREQ_SEL_V 0x1 -#define SYSTEM_PLL_FREQ_SEL_S 2 -/* SYSTEM_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: This field used to sel cpu clock frequent..*/ -#define SYSTEM_CPUPERIOD_SEL 0x00000003 -#define SYSTEM_CPUPERIOD_SEL_M ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S)) -#define SYSTEM_CPUPERIOD_SEL_V 0x3 +/** SYSTEM_CPU_PER_CONF_REG register + * cpu clock config register + */ +#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x8) +/** SYSTEM_CPUPERIOD_SEL : R/W; bitpos: [1:0]; default: 0; + * This field used to sel cpu clock frequent. + */ +#define SYSTEM_CPUPERIOD_SEL 0x00000003U +#define SYSTEM_CPUPERIOD_SEL_M (SYSTEM_CPUPERIOD_SEL_V << SYSTEM_CPUPERIOD_SEL_S) +#define SYSTEM_CPUPERIOD_SEL_V 0x00000003U #define SYSTEM_CPUPERIOD_SEL_S 0 +/** SYSTEM_PLL_FREQ_SEL : R/W; bitpos: [2]; default: 1; + * This field used to sel pll frequent. + */ +#define SYSTEM_PLL_FREQ_SEL (BIT(2)) +#define SYSTEM_PLL_FREQ_SEL_M (SYSTEM_PLL_FREQ_SEL_V << SYSTEM_PLL_FREQ_SEL_S) +#define SYSTEM_PLL_FREQ_SEL_V 0x00000001U +#define SYSTEM_PLL_FREQ_SEL_S 2 +/** SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; + * Set 1 to force cpu_waiti_clk enable. + */ +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (SYSTEM_CPU_WAIT_MODE_FORCE_ON_V << SYSTEM_CPU_WAIT_MODE_FORCE_ON_S) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x00000001U +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3 +/** SYSTEM_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0; + * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk + * will close + */ +#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000FU +#define SYSTEM_CPU_WAITI_DELAY_NUM_M (SYSTEM_CPU_WAITI_DELAY_NUM_V << SYSTEM_CPU_WAITI_DELAY_NUM_S) +#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0x0000000FU +#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4 -#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0xC) -/* SYSTEM_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Set 1 to mask memory power down..*/ +/** SYSTEM_MEM_PD_MASK_REG register + * memory power down mask register + */ +#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0xc) +/** SYSTEM_LSLP_MEM_PD_MASK : R/W; bitpos: [0]; default: 1; + * Set 1 to mask memory power down. + */ #define SYSTEM_LSLP_MEM_PD_MASK (BIT(0)) -#define SYSTEM_LSLP_MEM_PD_MASK_M (BIT(0)) -#define SYSTEM_LSLP_MEM_PD_MASK_V 0x1 +#define SYSTEM_LSLP_MEM_PD_MASK_M (SYSTEM_LSLP_MEM_PD_MASK_V << SYSTEM_LSLP_MEM_PD_MASK_S) +#define SYSTEM_LSLP_MEM_PD_MASK_V 0x00000001U #define SYSTEM_LSLP_MEM_PD_MASK_S 0 -#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x10) -/* SYSTEM_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: Set 1 to enable ADC2_ARB clock.*/ -#define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) -#define SYSTEM_ADC2_ARB_CLK_EN_M (BIT(30)) -#define SYSTEM_ADC2_ARB_CLK_EN_V 0x1 -#define SYSTEM_ADC2_ARB_CLK_EN_S 30 -/* SYSTEM_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: Set 1 to enable SYSTEMTIMER clock.*/ -#define SYSTEM_SYSTIMER_CLK_EN (BIT(29)) -#define SYSTEM_SYSTIMER_CLK_EN_M (BIT(29)) -#define SYSTEM_SYSTIMER_CLK_EN_V 0x1 -#define SYSTEM_SYSTIMER_CLK_EN_S 29 -/* SYSTEM_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: Set 1 to enable APB_SARADC clock.*/ -#define SYSTEM_APB_SARADC_CLK_EN (BIT(28)) -#define SYSTEM_APB_SARADC_CLK_EN_M (BIT(28)) -#define SYSTEM_APB_SARADC_CLK_EN_V 0x1 -#define SYSTEM_APB_SARADC_CLK_EN_S 28 -/* SYSTEM_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: Set 1 to enable UART_MEM clock.*/ -#define SYSTEM_UART_MEM_CLK_EN (BIT(24)) -#define SYSTEM_UART_MEM_CLK_EN_M (BIT(24)) -#define SYSTEM_UART_MEM_CLK_EN_V 0x1 -#define SYSTEM_UART_MEM_CLK_EN_S 24 -/* SYSTEM_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: Set 1 to enable TIMERGROUP clock.*/ -#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13)) -#define SYSTEM_TIMERGROUP_CLK_EN_M (BIT(13)) -#define SYSTEM_TIMERGROUP_CLK_EN_V 0x1 -#define SYSTEM_TIMERGROUP_CLK_EN_S 13 -/* SYSTEM_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set 1 to enable LEDC clock.*/ -#define SYSTEM_LEDC_CLK_EN (BIT(11)) -#define SYSTEM_LEDC_CLK_EN_M (BIT(11)) -#define SYSTEM_LEDC_CLK_EN_V 0x1 -#define SYSTEM_LEDC_CLK_EN_S 11 -/* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set 1 to enable I2C_EXT0 clock.*/ -#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7)) -#define SYSTEM_I2C_EXT0_CLK_EN_M (BIT(7)) -#define SYSTEM_I2C_EXT0_CLK_EN_V 0x1 -#define SYSTEM_I2C_EXT0_CLK_EN_S 7 -/* SYSTEM_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: Set 1 to enable SPI2 clock.*/ -#define SYSTEM_SPI2_CLK_EN (BIT(6)) -#define SYSTEM_SPI2_CLK_EN_M (BIT(6)) -#define SYSTEM_SPI2_CLK_EN_V 0x1 -#define SYSTEM_SPI2_CLK_EN_S 6 -/* SYSTEM_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: Set 1 to enable UART1 clock.*/ -#define SYSTEM_UART1_CLK_EN (BIT(5)) -#define SYSTEM_UART1_CLK_EN_M (BIT(5)) -#define SYSTEM_UART1_CLK_EN_V 0x1 -#define SYSTEM_UART1_CLK_EN_S 5 -/* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: Set 1 to enable UART clock.*/ -#define SYSTEM_UART_CLK_EN (BIT(2)) -#define SYSTEM_UART_CLK_EN_M (BIT(2)) -#define SYSTEM_UART_CLK_EN_V 0x1 -#define SYSTEM_UART_CLK_EN_S 2 -/* SYSTEM_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: Set 1 to enable SPI01 clock.*/ +/** SYSTEM_PERIP_CLK_EN0_REG register + * peripheral clock gating register + */ +#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x10) +/** SYSTEM_SPI01_CLK_EN : R/W; bitpos: [1]; default: 1; + * Set 1 to enable SPI01 clock + */ #define SYSTEM_SPI01_CLK_EN (BIT(1)) -#define SYSTEM_SPI01_CLK_EN_M (BIT(1)) -#define SYSTEM_SPI01_CLK_EN_V 0x1 +#define SYSTEM_SPI01_CLK_EN_M (SYSTEM_SPI01_CLK_EN_V << SYSTEM_SPI01_CLK_EN_S) +#define SYSTEM_SPI01_CLK_EN_V 0x00000001U #define SYSTEM_SPI01_CLK_EN_S 1 +/** SYSTEM_UART_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable UART clock + */ +#define SYSTEM_UART_CLK_EN (BIT(2)) +#define SYSTEM_UART_CLK_EN_M (SYSTEM_UART_CLK_EN_V << SYSTEM_UART_CLK_EN_S) +#define SYSTEM_UART_CLK_EN_V 0x00000001U +#define SYSTEM_UART_CLK_EN_S 2 +/** SYSTEM_UART1_CLK_EN : R/W; bitpos: [5]; default: 1; + * Set 1 to enable UART1 clock + */ +#define SYSTEM_UART1_CLK_EN (BIT(5)) +#define SYSTEM_UART1_CLK_EN_M (SYSTEM_UART1_CLK_EN_V << SYSTEM_UART1_CLK_EN_S) +#define SYSTEM_UART1_CLK_EN_V 0x00000001U +#define SYSTEM_UART1_CLK_EN_S 5 +/** SYSTEM_SPI2_CLK_EN : R/W; bitpos: [6]; default: 1; + * Set 1 to enable SPI2 clock + */ +#define SYSTEM_SPI2_CLK_EN (BIT(6)) +#define SYSTEM_SPI2_CLK_EN_M (SYSTEM_SPI2_CLK_EN_V << SYSTEM_SPI2_CLK_EN_S) +#define SYSTEM_SPI2_CLK_EN_V 0x00000001U +#define SYSTEM_SPI2_CLK_EN_S 6 +/** SYSTEM_I2C_EXT0_CLK_EN : R/W; bitpos: [7]; default: 0; + * Set 1 to enable I2C_EXT0 clock + */ +#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7)) +#define SYSTEM_I2C_EXT0_CLK_EN_M (SYSTEM_I2C_EXT0_CLK_EN_V << SYSTEM_I2C_EXT0_CLK_EN_S) +#define SYSTEM_I2C_EXT0_CLK_EN_V 0x00000001U +#define SYSTEM_I2C_EXT0_CLK_EN_S 7 +/** SYSTEM_LEDC_CLK_EN : R/W; bitpos: [11]; default: 0; + * Set 1 to enable LEDC clock + */ +#define SYSTEM_LEDC_CLK_EN (BIT(11)) +#define SYSTEM_LEDC_CLK_EN_M (SYSTEM_LEDC_CLK_EN_V << SYSTEM_LEDC_CLK_EN_S) +#define SYSTEM_LEDC_CLK_EN_V 0x00000001U +#define SYSTEM_LEDC_CLK_EN_S 11 +/** SYSTEM_TIMERGROUP_CLK_EN : R/W; bitpos: [13]; default: 1; + * Set 1 to enable TIMERGROUP clock + */ +#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13)) +#define SYSTEM_TIMERGROUP_CLK_EN_M (SYSTEM_TIMERGROUP_CLK_EN_V << SYSTEM_TIMERGROUP_CLK_EN_S) +#define SYSTEM_TIMERGROUP_CLK_EN_V 0x00000001U +#define SYSTEM_TIMERGROUP_CLK_EN_S 13 +/** SYSTEM_UART_MEM_CLK_EN : R/W; bitpos: [24]; default: 1; + * Set 1 to enable UART_MEM clock + */ +#define SYSTEM_UART_MEM_CLK_EN (BIT(24)) +#define SYSTEM_UART_MEM_CLK_EN_M (SYSTEM_UART_MEM_CLK_EN_V << SYSTEM_UART_MEM_CLK_EN_S) +#define SYSTEM_UART_MEM_CLK_EN_V 0x00000001U +#define SYSTEM_UART_MEM_CLK_EN_S 24 +/** SYSTEM_APB_SARADC_CLK_EN : R/W; bitpos: [28]; default: 1; + * Set 1 to enable APB_SARADC clock + */ +#define SYSTEM_APB_SARADC_CLK_EN (BIT(28)) +#define SYSTEM_APB_SARADC_CLK_EN_M (SYSTEM_APB_SARADC_CLK_EN_V << SYSTEM_APB_SARADC_CLK_EN_S) +#define SYSTEM_APB_SARADC_CLK_EN_V 0x00000001U +#define SYSTEM_APB_SARADC_CLK_EN_S 28 +/** SYSTEM_SYSTIMER_CLK_EN : R/W; bitpos: [29]; default: 1; + * Set 1 to enable SYSTEMTIMER clock + */ +#define SYSTEM_SYSTIMER_CLK_EN (BIT(29)) +#define SYSTEM_SYSTIMER_CLK_EN_M (SYSTEM_SYSTIMER_CLK_EN_V << SYSTEM_SYSTIMER_CLK_EN_S) +#define SYSTEM_SYSTIMER_CLK_EN_V 0x00000001U +#define SYSTEM_SYSTIMER_CLK_EN_S 29 +/** SYSTEM_ADC2_ARB_CLK_EN : R/W; bitpos: [30]; default: 1; + * Set 1 to enable ADC2_ARB clock + */ +#define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) +#define SYSTEM_ADC2_ARB_CLK_EN_M (SYSTEM_ADC2_ARB_CLK_EN_V << SYSTEM_ADC2_ARB_CLK_EN_S) +#define SYSTEM_ADC2_ARB_CLK_EN_V 0x00000001U +#define SYSTEM_ADC2_ARB_CLK_EN_S 30 -#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x14) -/* SYSTEM_TSENS_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set 1 to enable TSENS clock.*/ -#define SYSTEM_TSENS_CLK_EN (BIT(10)) -#define SYSTEM_TSENS_CLK_EN_M (BIT(10)) -#define SYSTEM_TSENS_CLK_EN_V 0x1 -#define SYSTEM_TSENS_CLK_EN_S 10 -/* SYSTEM_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set 1 to enable DMA clock.*/ -#define SYSTEM_DMA_CLK_EN (BIT(6)) -#define SYSTEM_DMA_CLK_EN_M (BIT(6)) -#define SYSTEM_DMA_CLK_EN_V 0x1 -#define SYSTEM_DMA_CLK_EN_S 6 -/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set 1 to enable SHA clock.*/ -#define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2)) -#define SYSTEM_CRYPTO_SHA_CLK_EN_M (BIT(2)) -#define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x1 -#define SYSTEM_CRYPTO_SHA_CLK_EN_S 2 -/* SYSTEM_CRYPTO_ECC_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set 1 to enable ECC clock.*/ +/** SYSTEM_PERIP_CLK_EN1_REG register + * peripheral clock gating register + */ +#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x14) +/** SYSTEM_CRYPTO_ECC_CLK_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to enable ECC clock + */ #define SYSTEM_CRYPTO_ECC_CLK_EN (BIT(1)) -#define SYSTEM_CRYPTO_ECC_CLK_EN_M (BIT(1)) -#define SYSTEM_CRYPTO_ECC_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_ECC_CLK_EN_M (SYSTEM_CRYPTO_ECC_CLK_EN_V << SYSTEM_CRYPTO_ECC_CLK_EN_S) +#define SYSTEM_CRYPTO_ECC_CLK_EN_V 0x00000001U #define SYSTEM_CRYPTO_ECC_CLK_EN_S 1 +/** SYSTEM_CRYPTO_SHA_CLK_EN : R/W; bitpos: [2]; default: 0; + * Set 1 to enable SHA clock + */ +#define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2)) +#define SYSTEM_CRYPTO_SHA_CLK_EN_M (SYSTEM_CRYPTO_SHA_CLK_EN_V << SYSTEM_CRYPTO_SHA_CLK_EN_S) +#define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x00000001U +#define SYSTEM_CRYPTO_SHA_CLK_EN_S 2 +/** SYSTEM_DMA_CLK_EN : R/W; bitpos: [6]; default: 0; + * Set 1 to enable DMA clock + */ +#define SYSTEM_DMA_CLK_EN (BIT(6)) +#define SYSTEM_DMA_CLK_EN_M (SYSTEM_DMA_CLK_EN_V << SYSTEM_DMA_CLK_EN_S) +#define SYSTEM_DMA_CLK_EN_V 0x00000001U +#define SYSTEM_DMA_CLK_EN_S 6 +/** SYSTEM_TSENS_CLK_EN : R/W; bitpos: [10]; default: 0; + * Set 1 to enable TSENS clock + */ +#define SYSTEM_TSENS_CLK_EN (BIT(10)) +#define SYSTEM_TSENS_CLK_EN_M (SYSTEM_TSENS_CLK_EN_V << SYSTEM_TSENS_CLK_EN_S) +#define SYSTEM_TSENS_CLK_EN_V 0x00000001U +#define SYSTEM_TSENS_CLK_EN_S 10 -#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x18) -/* SYSTEM_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set 1 to let ADC2_ARB reset.*/ -#define SYSTEM_ADC2_ARB_RST (BIT(30)) -#define SYSTEM_ADC2_ARB_RST_M (BIT(30)) -#define SYSTEM_ADC2_ARB_RST_V 0x1 -#define SYSTEM_ADC2_ARB_RST_S 30 -/* SYSTEM_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set 1 to let SYSTIMER reset.*/ -#define SYSTEM_SYSTIMER_RST (BIT(29)) -#define SYSTEM_SYSTIMER_RST_M (BIT(29)) -#define SYSTEM_SYSTIMER_RST_V 0x1 -#define SYSTEM_SYSTIMER_RST_S 29 -/* SYSTEM_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Set 1 to let APB_SARADC reset.*/ -#define SYSTEM_APB_SARADC_RST (BIT(28)) -#define SYSTEM_APB_SARADC_RST_M (BIT(28)) -#define SYSTEM_APB_SARADC_RST_V 0x1 -#define SYSTEM_APB_SARADC_RST_S 28 -/* SYSTEM_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: Set 1 to let UART_MEM reset.*/ -#define SYSTEM_UART_MEM_RST (BIT(24)) -#define SYSTEM_UART_MEM_RST_M (BIT(24)) -#define SYSTEM_UART_MEM_RST_V 0x1 -#define SYSTEM_UART_MEM_RST_S 24 -/* SYSTEM_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set 1 to let TIMERGROUP reset.*/ -#define SYSTEM_TIMERGROUP_RST (BIT(13)) -#define SYSTEM_TIMERGROUP_RST_M (BIT(13)) -#define SYSTEM_TIMERGROUP_RST_V 0x1 -#define SYSTEM_TIMERGROUP_RST_S 13 -/* SYSTEM_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set 1 to let LEDC reset.*/ -#define SYSTEM_LEDC_RST (BIT(11)) -#define SYSTEM_LEDC_RST_M (BIT(11)) -#define SYSTEM_LEDC_RST_V 0x1 -#define SYSTEM_LEDC_RST_S 11 -/* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set 1 to let I2C_EXT0 reset.*/ -#define SYSTEM_I2C_EXT0_RST (BIT(7)) -#define SYSTEM_I2C_EXT0_RST_M (BIT(7)) -#define SYSTEM_I2C_EXT0_RST_V 0x1 -#define SYSTEM_I2C_EXT0_RST_S 7 -/* SYSTEM_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set 1 to let SPI2 reset.*/ -#define SYSTEM_SPI2_RST (BIT(6)) -#define SYSTEM_SPI2_RST_M (BIT(6)) -#define SYSTEM_SPI2_RST_V 0x1 -#define SYSTEM_SPI2_RST_S 6 -/* SYSTEM_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set 1 to let UART1 reset.*/ -#define SYSTEM_UART1_RST (BIT(5)) -#define SYSTEM_UART1_RST_M (BIT(5)) -#define SYSTEM_UART1_RST_V 0x1 -#define SYSTEM_UART1_RST_S 5 -/* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set 1 to let UART reset.*/ -#define SYSTEM_UART_RST (BIT(2)) -#define SYSTEM_UART_RST_M (BIT(2)) -#define SYSTEM_UART_RST_V 0x1 -#define SYSTEM_UART_RST_S 2 -/* SYSTEM_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set 1 to let SPI01 reset.*/ +/** SYSTEM_PERIP_RST_EN0_REG register + * reserved + */ +#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x18) +/** SYSTEM_SPI01_RST : R/W; bitpos: [1]; default: 0; + * Set 1 to let SPI01 reset + */ #define SYSTEM_SPI01_RST (BIT(1)) -#define SYSTEM_SPI01_RST_M (BIT(1)) -#define SYSTEM_SPI01_RST_V 0x1 +#define SYSTEM_SPI01_RST_M (SYSTEM_SPI01_RST_V << SYSTEM_SPI01_RST_S) +#define SYSTEM_SPI01_RST_V 0x00000001U #define SYSTEM_SPI01_RST_S 1 +/** SYSTEM_UART_RST : R/W; bitpos: [2]; default: 0; + * Set 1 to let UART reset + */ +#define SYSTEM_UART_RST (BIT(2)) +#define SYSTEM_UART_RST_M (SYSTEM_UART_RST_V << SYSTEM_UART_RST_S) +#define SYSTEM_UART_RST_V 0x00000001U +#define SYSTEM_UART_RST_S 2 +/** SYSTEM_UART1_RST : R/W; bitpos: [5]; default: 0; + * Set 1 to let UART1 reset + */ +#define SYSTEM_UART1_RST (BIT(5)) +#define SYSTEM_UART1_RST_M (SYSTEM_UART1_RST_V << SYSTEM_UART1_RST_S) +#define SYSTEM_UART1_RST_V 0x00000001U +#define SYSTEM_UART1_RST_S 5 +/** SYSTEM_SPI2_RST : R/W; bitpos: [6]; default: 0; + * Set 1 to let SPI2 reset + */ +#define SYSTEM_SPI2_RST (BIT(6)) +#define SYSTEM_SPI2_RST_M (SYSTEM_SPI2_RST_V << SYSTEM_SPI2_RST_S) +#define SYSTEM_SPI2_RST_V 0x00000001U +#define SYSTEM_SPI2_RST_S 6 +/** SYSTEM_I2C_EXT0_RST : R/W; bitpos: [7]; default: 0; + * Set 1 to let I2C_EXT0 reset + */ +#define SYSTEM_I2C_EXT0_RST (BIT(7)) +#define SYSTEM_I2C_EXT0_RST_M (SYSTEM_I2C_EXT0_RST_V << SYSTEM_I2C_EXT0_RST_S) +#define SYSTEM_I2C_EXT0_RST_V 0x00000001U +#define SYSTEM_I2C_EXT0_RST_S 7 +/** SYSTEM_LEDC_RST : R/W; bitpos: [11]; default: 0; + * Set 1 to let LEDC reset + */ +#define SYSTEM_LEDC_RST (BIT(11)) +#define SYSTEM_LEDC_RST_M (SYSTEM_LEDC_RST_V << SYSTEM_LEDC_RST_S) +#define SYSTEM_LEDC_RST_V 0x00000001U +#define SYSTEM_LEDC_RST_S 11 +/** SYSTEM_TIMERGROUP_RST : R/W; bitpos: [13]; default: 0; + * Set 1 to let TIMERGROUP reset + */ +#define SYSTEM_TIMERGROUP_RST (BIT(13)) +#define SYSTEM_TIMERGROUP_RST_M (SYSTEM_TIMERGROUP_RST_V << SYSTEM_TIMERGROUP_RST_S) +#define SYSTEM_TIMERGROUP_RST_V 0x00000001U +#define SYSTEM_TIMERGROUP_RST_S 13 +/** SYSTEM_UART_MEM_RST : R/W; bitpos: [24]; default: 0; + * Set 1 to let UART_MEM reset + */ +#define SYSTEM_UART_MEM_RST (BIT(24)) +#define SYSTEM_UART_MEM_RST_M (SYSTEM_UART_MEM_RST_V << SYSTEM_UART_MEM_RST_S) +#define SYSTEM_UART_MEM_RST_V 0x00000001U +#define SYSTEM_UART_MEM_RST_S 24 +/** SYSTEM_APB_SARADC_RST : R/W; bitpos: [28]; default: 0; + * Set 1 to let APB_SARADC reset + */ +#define SYSTEM_APB_SARADC_RST (BIT(28)) +#define SYSTEM_APB_SARADC_RST_M (SYSTEM_APB_SARADC_RST_V << SYSTEM_APB_SARADC_RST_S) +#define SYSTEM_APB_SARADC_RST_V 0x00000001U +#define SYSTEM_APB_SARADC_RST_S 28 +/** SYSTEM_SYSTIMER_RST : R/W; bitpos: [29]; default: 0; + * Set 1 to let SYSTIMER reset + */ +#define SYSTEM_SYSTIMER_RST (BIT(29)) +#define SYSTEM_SYSTIMER_RST_M (SYSTEM_SYSTIMER_RST_V << SYSTEM_SYSTIMER_RST_S) +#define SYSTEM_SYSTIMER_RST_V 0x00000001U +#define SYSTEM_SYSTIMER_RST_S 29 +/** SYSTEM_ADC2_ARB_RST : R/W; bitpos: [30]; default: 0; + * Set 1 to let ADC2_ARB reset + */ +#define SYSTEM_ADC2_ARB_RST (BIT(30)) +#define SYSTEM_ADC2_ARB_RST_M (SYSTEM_ADC2_ARB_RST_V << SYSTEM_ADC2_ARB_RST_S) +#define SYSTEM_ADC2_ARB_RST_V 0x00000001U +#define SYSTEM_ADC2_ARB_RST_S 30 -#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x1C) -/* SYSTEM_TSENS_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set 1 to let TSENS reset.*/ -#define SYSTEM_TSENS_RST (BIT(10)) -#define SYSTEM_TSENS_RST_M (BIT(10)) -#define SYSTEM_TSENS_RST_V 0x1 -#define SYSTEM_TSENS_RST_S 10 -/* SYSTEM_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: Set 1 to let DMA reset.*/ -#define SYSTEM_DMA_RST (BIT(6)) -#define SYSTEM_DMA_RST_M (BIT(6)) -#define SYSTEM_DMA_RST_V 0x1 -#define SYSTEM_DMA_RST_S 6 -/* SYSTEM_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: Set 1 to let CRYPTO_SHA reset.*/ -#define SYSTEM_CRYPTO_SHA_RST (BIT(2)) -#define SYSTEM_CRYPTO_SHA_RST_M (BIT(2)) -#define SYSTEM_CRYPTO_SHA_RST_V 0x1 -#define SYSTEM_CRYPTO_SHA_RST_S 2 -/* SYSTEM_CRYPTO_ECC_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: Set 1 to let CRYPTO_ECC reset.*/ +/** SYSTEM_PERIP_RST_EN1_REG register + * peripheral reset register + */ +#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x1c) +/** SYSTEM_CRYPTO_ECC_RST : R/W; bitpos: [1]; default: 1; + * Set 1 to let CRYPTO_ECC reset + */ #define SYSTEM_CRYPTO_ECC_RST (BIT(1)) -#define SYSTEM_CRYPTO_ECC_RST_M (BIT(1)) -#define SYSTEM_CRYPTO_ECC_RST_V 0x1 +#define SYSTEM_CRYPTO_ECC_RST_M (SYSTEM_CRYPTO_ECC_RST_V << SYSTEM_CRYPTO_ECC_RST_S) +#define SYSTEM_CRYPTO_ECC_RST_V 0x00000001U #define SYSTEM_CRYPTO_ECC_RST_S 1 +/** SYSTEM_CRYPTO_SHA_RST : R/W; bitpos: [2]; default: 1; + * Set 1 to let CRYPTO_SHA reset + */ +#define SYSTEM_CRYPTO_SHA_RST (BIT(2)) +#define SYSTEM_CRYPTO_SHA_RST_M (SYSTEM_CRYPTO_SHA_RST_V << SYSTEM_CRYPTO_SHA_RST_S) +#define SYSTEM_CRYPTO_SHA_RST_V 0x00000001U +#define SYSTEM_CRYPTO_SHA_RST_S 2 +/** SYSTEM_DMA_RST : R/W; bitpos: [6]; default: 1; + * Set 1 to let DMA reset + */ +#define SYSTEM_DMA_RST (BIT(6)) +#define SYSTEM_DMA_RST_M (SYSTEM_DMA_RST_V << SYSTEM_DMA_RST_S) +#define SYSTEM_DMA_RST_V 0x00000001U +#define SYSTEM_DMA_RST_S 6 +/** SYSTEM_TSENS_RST : R/W; bitpos: [10]; default: 0; + * Set 1 to let TSENS reset + */ +#define SYSTEM_TSENS_RST (BIT(10)) +#define SYSTEM_TSENS_RST_M (SYSTEM_TSENS_RST_V << SYSTEM_TSENS_RST_S) +#define SYSTEM_TSENS_RST_V 0x00000001U +#define SYSTEM_TSENS_RST_S 10 -#define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x20) -/* SYSTEM_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ -/*description: This field is lower power clock frequent division factor.*/ -#define SYSTEM_BT_LPCK_DIV_NUM 0x00000FFF -#define SYSTEM_BT_LPCK_DIV_NUM_M ((SYSTEM_BT_LPCK_DIV_NUM_V)<<(SYSTEM_BT_LPCK_DIV_NUM_S)) -#define SYSTEM_BT_LPCK_DIV_NUM_V 0xFFF +/** SYSTEM_BT_LPCK_DIV_INT_REG register + * clock config register + */ +#define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x20) +/** SYSTEM_BT_LPCK_DIV_NUM : R/W; bitpos: [11:0]; default: 255; + * This field is lower power clock frequent division factor + */ +#define SYSTEM_BT_LPCK_DIV_NUM 0x00000FFFU +#define SYSTEM_BT_LPCK_DIV_NUM_M (SYSTEM_BT_LPCK_DIV_NUM_V << SYSTEM_BT_LPCK_DIV_NUM_S) +#define SYSTEM_BT_LPCK_DIV_NUM_V 0x00000FFFU #define SYSTEM_BT_LPCK_DIV_NUM_S 0 -#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x24) -/* SYSTEM_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Set 1 to enable RTC low power clock.*/ -#define SYSTEM_LPCLK_RTC_EN (BIT(28)) -#define SYSTEM_LPCLK_RTC_EN_M (BIT(28)) -#define SYSTEM_LPCLK_RTC_EN_V 0x1 -#define SYSTEM_LPCLK_RTC_EN_S 28 -/* SYSTEM_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Set 1 to select xtal32k clock as low power clock.*/ -#define SYSTEM_LPCLK_SEL_XTAL32K (BIT(27)) -#define SYSTEM_LPCLK_SEL_XTAL32K_M (BIT(27)) -#define SYSTEM_LPCLK_SEL_XTAL32K_V 0x1 -#define SYSTEM_LPCLK_SEL_XTAL32K_S 27 -/* SYSTEM_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set 1 to select xtal clock as rtc low power clock.*/ -#define SYSTEM_LPCLK_SEL_XTAL (BIT(26)) -#define SYSTEM_LPCLK_SEL_XTAL_M (BIT(26)) -#define SYSTEM_LPCLK_SEL_XTAL_V 0x1 -#define SYSTEM_LPCLK_SEL_XTAL_S 26 -/* SYSTEM_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */ -/*description: Set 1 to select 8m clock as rtc low power clock.*/ -#define SYSTEM_LPCLK_SEL_8M (BIT(25)) -#define SYSTEM_LPCLK_SEL_8M_M (BIT(25)) -#define SYSTEM_LPCLK_SEL_8M_V 0x1 -#define SYSTEM_LPCLK_SEL_8M_S 25 -/* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: Set 1 to select rtc-slow clock as rtc low power clock.*/ -#define SYSTEM_LPCLK_SEL_RTC_SLOW (BIT(24)) -#define SYSTEM_LPCLK_SEL_RTC_SLOW_M (BIT(24)) -#define SYSTEM_LPCLK_SEL_RTC_SLOW_V 0x1 -#define SYSTEM_LPCLK_SEL_RTC_SLOW_S 24 -/* SYSTEM_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */ -/*description: This field is lower power clock frequent division factor a.*/ -#define SYSTEM_BT_LPCK_DIV_A 0x00000FFF -#define SYSTEM_BT_LPCK_DIV_A_M ((SYSTEM_BT_LPCK_DIV_A_V)<<(SYSTEM_BT_LPCK_DIV_A_S)) -#define SYSTEM_BT_LPCK_DIV_A_V 0xFFF -#define SYSTEM_BT_LPCK_DIV_A_S 12 -/* SYSTEM_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */ -/*description: This field is lower power clock frequent division factor b.*/ -#define SYSTEM_BT_LPCK_DIV_B 0x00000FFF -#define SYSTEM_BT_LPCK_DIV_B_M ((SYSTEM_BT_LPCK_DIV_B_V)<<(SYSTEM_BT_LPCK_DIV_B_S)) -#define SYSTEM_BT_LPCK_DIV_B_V 0xFFF +/** SYSTEM_BT_LPCK_DIV_FRAC_REG register + * low power clock configuration register + */ +#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x24) +/** SYSTEM_BT_LPCK_DIV_B : R/W; bitpos: [11:0]; default: 1; + * This field is lower power clock frequent division factor b + */ +#define SYSTEM_BT_LPCK_DIV_B 0x00000FFFU +#define SYSTEM_BT_LPCK_DIV_B_M (SYSTEM_BT_LPCK_DIV_B_V << SYSTEM_BT_LPCK_DIV_B_S) +#define SYSTEM_BT_LPCK_DIV_B_V 0x00000FFFU #define SYSTEM_BT_LPCK_DIV_B_S 0 +/** SYSTEM_BT_LPCK_DIV_A : R/W; bitpos: [23:12]; default: 1; + * This field is lower power clock frequent division factor a + */ +#define SYSTEM_BT_LPCK_DIV_A 0x00000FFFU +#define SYSTEM_BT_LPCK_DIV_A_M (SYSTEM_BT_LPCK_DIV_A_V << SYSTEM_BT_LPCK_DIV_A_S) +#define SYSTEM_BT_LPCK_DIV_A_V 0x00000FFFU +#define SYSTEM_BT_LPCK_DIV_A_S 12 +/** SYSTEM_LPCLK_SEL_RTC_SLOW : R/W; bitpos: [24]; default: 0; + * Set 1 to select rtc-slow clock as rtc low power clock + */ +#define SYSTEM_LPCLK_SEL_RTC_SLOW (BIT(24)) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_M (SYSTEM_LPCLK_SEL_RTC_SLOW_V << SYSTEM_LPCLK_SEL_RTC_SLOW_S) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_V 0x00000001U +#define SYSTEM_LPCLK_SEL_RTC_SLOW_S 24 +/** SYSTEM_LPCLK_SEL_8M : R/W; bitpos: [25]; default: 1; + * Set 1 to select 8m clock as rtc low power clock + */ +#define SYSTEM_LPCLK_SEL_8M (BIT(25)) +#define SYSTEM_LPCLK_SEL_8M_M (SYSTEM_LPCLK_SEL_8M_V << SYSTEM_LPCLK_SEL_8M_S) +#define SYSTEM_LPCLK_SEL_8M_V 0x00000001U +#define SYSTEM_LPCLK_SEL_8M_S 25 +/** SYSTEM_LPCLK_SEL_XTAL : R/W; bitpos: [26]; default: 0; + * Set 1 to select xtal clock as rtc low power clock + */ +#define SYSTEM_LPCLK_SEL_XTAL (BIT(26)) +#define SYSTEM_LPCLK_SEL_XTAL_M (SYSTEM_LPCLK_SEL_XTAL_V << SYSTEM_LPCLK_SEL_XTAL_S) +#define SYSTEM_LPCLK_SEL_XTAL_V 0x00000001U +#define SYSTEM_LPCLK_SEL_XTAL_S 26 +/** SYSTEM_LPCLK_SEL_XTAL32K : R/W; bitpos: [27]; default: 0; + * Set 1 to select xtal32k clock as low power clock + */ +#define SYSTEM_LPCLK_SEL_XTAL32K (BIT(27)) +#define SYSTEM_LPCLK_SEL_XTAL32K_M (SYSTEM_LPCLK_SEL_XTAL32K_V << SYSTEM_LPCLK_SEL_XTAL32K_S) +#define SYSTEM_LPCLK_SEL_XTAL32K_V 0x00000001U +#define SYSTEM_LPCLK_SEL_XTAL32K_S 27 +/** SYSTEM_LPCLK_RTC_EN : R/W; bitpos: [28]; default: 0; + * Set 1 to enable RTC low power clock + */ +#define SYSTEM_LPCLK_RTC_EN (BIT(28)) +#define SYSTEM_LPCLK_RTC_EN_M (SYSTEM_LPCLK_RTC_EN_V << SYSTEM_LPCLK_RTC_EN_S) +#define SYSTEM_LPCLK_RTC_EN_V 0x00000001U +#define SYSTEM_LPCLK_RTC_EN_S 28 -#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x28) -/* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set 1 to generate cpu interrupt 0.*/ +/** SYSTEM_CPU_INTR_FROM_CPU_0_REG register + * interrupt generate register + */ +#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x28) +/** SYSTEM_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0; + * Set 1 to generate cpu interrupt 0 + */ #define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_0_M (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_0_M (SYSTEM_CPU_INTR_FROM_CPU_0_V << SYSTEM_CPU_INTR_FROM_CPU_0_S) +#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x00000001U #define SYSTEM_CPU_INTR_FROM_CPU_0_S 0 -#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x2C) -/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set 1 to generate cpu interrupt 1.*/ +/** SYSTEM_CPU_INTR_FROM_CPU_1_REG register + * interrupt generate register + */ +#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x2c) +/** SYSTEM_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0; + * Set 1 to generate cpu interrupt 1 + */ #define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_1_M (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_1_M (SYSTEM_CPU_INTR_FROM_CPU_1_V << SYSTEM_CPU_INTR_FROM_CPU_1_S) +#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x00000001U #define SYSTEM_CPU_INTR_FROM_CPU_1_S 0 -#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x30) -/* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set 1 to generate cpu interrupt 2.*/ +/** SYSTEM_CPU_INTR_FROM_CPU_2_REG register + * interrupt generate register + */ +#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x30) +/** SYSTEM_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0; + * Set 1 to generate cpu interrupt 2 + */ #define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_2_M (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_2_M (SYSTEM_CPU_INTR_FROM_CPU_2_V << SYSTEM_CPU_INTR_FROM_CPU_2_S) +#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x00000001U #define SYSTEM_CPU_INTR_FROM_CPU_2_S 0 -#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x34) -/* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set 1 to generate cpu interrupt 3.*/ +/** SYSTEM_CPU_INTR_FROM_CPU_3_REG register + * interrupt generate register + */ +#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x34) +/** SYSTEM_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0; + * Set 1 to generate cpu interrupt 3 + */ #define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_3_M (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_3_M (SYSTEM_CPU_INTR_FROM_CPU_3_V << SYSTEM_CPU_INTR_FROM_CPU_3_S) +#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x00000001U #define SYSTEM_CPU_INTR_FROM_CPU_3_S 0 -#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x38) -/* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set 1 to force power down RSA memory. This bit has the highest priority..*/ -#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2)) -#define SYSTEM_RSA_MEM_FORCE_PD_M (BIT(2)) -#define SYSTEM_RSA_MEM_FORCE_PD_V 0x1 -#define SYSTEM_RSA_MEM_FORCE_PD_S 2 -/* SYSTEM_RSA_MEM_FORCE_PU : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set 1 to force power up RSA memory. This bit has the second highest priority..*/ -#define SYSTEM_RSA_MEM_FORCE_PU (BIT(1)) -#define SYSTEM_RSA_MEM_FORCE_PU_M (BIT(1)) -#define SYSTEM_RSA_MEM_FORCE_PU_V 0x1 -#define SYSTEM_RSA_MEM_FORCE_PU_S 1 -/* SYSTEM_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Si -gnature occupies the RSA. This bit is invalid..*/ +/** SYSTEM_RSA_PD_CTRL_REG register + * rsa memory power control register + */ +#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x38) +/** SYSTEM_RSA_MEM_PD : R/W; bitpos: [0]; default: 1; + * Set 1 to power down RSA memory. This bit has the lowest priority.When Digital + * Signature occupies the RSA. This bit is invalid. + */ #define SYSTEM_RSA_MEM_PD (BIT(0)) -#define SYSTEM_RSA_MEM_PD_M (BIT(0)) -#define SYSTEM_RSA_MEM_PD_V 0x1 +#define SYSTEM_RSA_MEM_PD_M (SYSTEM_RSA_MEM_PD_V << SYSTEM_RSA_MEM_PD_S) +#define SYSTEM_RSA_MEM_PD_V 0x00000001U #define SYSTEM_RSA_MEM_PD_S 0 +/** SYSTEM_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 0; + * Set 1 to force power up RSA memory. This bit has the second highest priority. + */ +#define SYSTEM_RSA_MEM_FORCE_PU (BIT(1)) +#define SYSTEM_RSA_MEM_FORCE_PU_M (SYSTEM_RSA_MEM_FORCE_PU_V << SYSTEM_RSA_MEM_FORCE_PU_S) +#define SYSTEM_RSA_MEM_FORCE_PU_V 0x00000001U +#define SYSTEM_RSA_MEM_FORCE_PU_S 1 +/** SYSTEM_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set 1 to force power down RSA memory. This bit has the highest priority. + */ +#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2)) +#define SYSTEM_RSA_MEM_FORCE_PD_M (SYSTEM_RSA_MEM_FORCE_PD_V << SYSTEM_RSA_MEM_FORCE_PD_S) +#define SYSTEM_RSA_MEM_FORCE_PD_V 0x00000001U +#define SYSTEM_RSA_MEM_FORCE_PD_S 2 -#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x3C) -/* SYSTEM_EDMA_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set 1 to let EDMA reset.*/ -#define SYSTEM_EDMA_RESET (BIT(1)) -#define SYSTEM_EDMA_RESET_M (BIT(1)) -#define SYSTEM_EDMA_RESET_V 0x1 -#define SYSTEM_EDMA_RESET_S 1 -/* SYSTEM_EDMA_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Set 1 to enable EDMA clock..*/ +/** SYSTEM_EDMA_CTRL_REG register + * edma clcok and reset register + */ +#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x3c) +/** SYSTEM_EDMA_CLK_ON : R/W; bitpos: [0]; default: 1; + * Set 1 to enable EDMA clock. + */ #define SYSTEM_EDMA_CLK_ON (BIT(0)) -#define SYSTEM_EDMA_CLK_ON_M (BIT(0)) -#define SYSTEM_EDMA_CLK_ON_V 0x1 +#define SYSTEM_EDMA_CLK_ON_M (SYSTEM_EDMA_CLK_ON_V << SYSTEM_EDMA_CLK_ON_S) +#define SYSTEM_EDMA_CLK_ON_V 0x00000001U #define SYSTEM_EDMA_CLK_ON_S 0 +/** SYSTEM_EDMA_RESET : R/W; bitpos: [1]; default: 0; + * Set 1 to let EDMA reset + */ +#define SYSTEM_EDMA_RESET (BIT(1)) +#define SYSTEM_EDMA_RESET_M (SYSTEM_EDMA_RESET_V << SYSTEM_EDMA_RESET_S) +#define SYSTEM_EDMA_RESET_V 0x00000001U +#define SYSTEM_EDMA_RESET_S 1 -#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x40) -/* SYSTEM_DCACHE_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set 1 to let dcache reset.*/ -#define SYSTEM_DCACHE_RESET (BIT(3)) -#define SYSTEM_DCACHE_RESET_M (BIT(3)) -#define SYSTEM_DCACHE_RESET_V 0x1 -#define SYSTEM_DCACHE_RESET_S 3 -/* SYSTEM_DCACHE_CLK_ON : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: Set 1 to enable dcache clock.*/ -#define SYSTEM_DCACHE_CLK_ON (BIT(2)) -#define SYSTEM_DCACHE_CLK_ON_M (BIT(2)) -#define SYSTEM_DCACHE_CLK_ON_V 0x1 -#define SYSTEM_DCACHE_CLK_ON_S 2 -/* SYSTEM_ICACHE_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set 1 to let icache reset.*/ -#define SYSTEM_ICACHE_RESET (BIT(1)) -#define SYSTEM_ICACHE_RESET_M (BIT(1)) -#define SYSTEM_ICACHE_RESET_V 0x1 -#define SYSTEM_ICACHE_RESET_S 1 -/* SYSTEM_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Set 1 to enable icache clock.*/ +/** SYSTEM_CACHE_CONTROL_REG register + * cache control register + */ +#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x40) +/** SYSTEM_ICACHE_CLK_ON : R/W; bitpos: [0]; default: 1; + * Set 1 to enable icache clock + */ #define SYSTEM_ICACHE_CLK_ON (BIT(0)) -#define SYSTEM_ICACHE_CLK_ON_M (BIT(0)) -#define SYSTEM_ICACHE_CLK_ON_V 0x1 +#define SYSTEM_ICACHE_CLK_ON_M (SYSTEM_ICACHE_CLK_ON_V << SYSTEM_ICACHE_CLK_ON_S) +#define SYSTEM_ICACHE_CLK_ON_V 0x00000001U #define SYSTEM_ICACHE_CLK_ON_S 0 +/** SYSTEM_ICACHE_RESET : R/W; bitpos: [1]; default: 0; + * Set 1 to let icache reset + */ +#define SYSTEM_ICACHE_RESET (BIT(1)) +#define SYSTEM_ICACHE_RESET_M (SYSTEM_ICACHE_RESET_V << SYSTEM_ICACHE_RESET_S) +#define SYSTEM_ICACHE_RESET_V 0x00000001U +#define SYSTEM_ICACHE_RESET_S 1 +/** SYSTEM_DCACHE_CLK_ON : R/W; bitpos: [2]; default: 1; + * Set 1 to enable dcache clock + */ +#define SYSTEM_DCACHE_CLK_ON (BIT(2)) +#define SYSTEM_DCACHE_CLK_ON_M (SYSTEM_DCACHE_CLK_ON_V << SYSTEM_DCACHE_CLK_ON_S) +#define SYSTEM_DCACHE_CLK_ON_V 0x00000001U +#define SYSTEM_DCACHE_CLK_ON_S 2 +/** SYSTEM_DCACHE_RESET : R/W; bitpos: [3]; default: 0; + * Set 1 to let dcache reset + */ +#define SYSTEM_DCACHE_RESET (BIT(3)) +#define SYSTEM_DCACHE_RESET_M (SYSTEM_DCACHE_RESET_V << SYSTEM_DCACHE_RESET_S) +#define SYSTEM_DCACHE_RESET_V 0x00000001U +#define SYSTEM_DCACHE_RESET_S 3 -#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x44) -/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set 1 to enable download manual encrypt.*/ -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(3)) -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 -/* SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set 1 to enable download G0CB decrypt.*/ -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (BIT(2)) -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x1 -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 -/* SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set 1 to enable download DB encrypt..*/ -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (BIT(1)) -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x1 -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 -/* SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set 1 to enable the SPI manual encrypt..*/ +/** SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register + * SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG + */ +#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x44) +/** SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0; + * Set 1 to enable the SPI manual encrypt. + */ #define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) -#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (BIT(0)) -#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1 +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S) +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001U #define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 +/** SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0; + * Set 1 to enable download DB encrypt. + */ +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 +/** SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0; + * Set 1 to enable download G0CB decrypt + */ +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001U +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 +/** SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0; + * Set 1 to enable download manual encrypt + */ +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 -#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x48) -/* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: This bit stores the status of RTC memory CRC.1 means finished..*/ -#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31)) -#define SYSTEM_RTC_MEM_CRC_FINISH_M (BIT(31)) -#define SYSTEM_RTC_MEM_CRC_FINISH_V 0x1 -#define SYSTEM_RTC_MEM_CRC_FINISH_S 31 -/* SYSTEM_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */ -/*description: This field is used to set length of RTC memory for CRC based on start address..*/ -#define SYSTEM_RTC_MEM_CRC_LEN 0x000007FF -#define SYSTEM_RTC_MEM_CRC_LEN_M ((SYSTEM_RTC_MEM_CRC_LEN_V)<<(SYSTEM_RTC_MEM_CRC_LEN_S)) -#define SYSTEM_RTC_MEM_CRC_LEN_V 0x7FF -#define SYSTEM_RTC_MEM_CRC_LEN_S 20 -/* SYSTEM_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */ -/*description: This field is used to set address of RTC memory for CRC..*/ -#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007FF -#define SYSTEM_RTC_MEM_CRC_ADDR_M ((SYSTEM_RTC_MEM_CRC_ADDR_V)<<(SYSTEM_RTC_MEM_CRC_ADDR_S)) -#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x7FF -#define SYSTEM_RTC_MEM_CRC_ADDR_S 9 -/* SYSTEM_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set 1 to start the CRC of RTC memory.*/ +/** SYSTEM_RTC_FASTMEM_CONFIG_REG register + * fast memory config register + */ +#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x48) +/** SYSTEM_RTC_MEM_CRC_START : R/W; bitpos: [8]; default: 0; + * Set 1 to start the CRC of RTC memory + */ #define SYSTEM_RTC_MEM_CRC_START (BIT(8)) -#define SYSTEM_RTC_MEM_CRC_START_M (BIT(8)) -#define SYSTEM_RTC_MEM_CRC_START_V 0x1 +#define SYSTEM_RTC_MEM_CRC_START_M (SYSTEM_RTC_MEM_CRC_START_V << SYSTEM_RTC_MEM_CRC_START_S) +#define SYSTEM_RTC_MEM_CRC_START_V 0x00000001U #define SYSTEM_RTC_MEM_CRC_START_S 8 +/** SYSTEM_RTC_MEM_CRC_ADDR : R/W; bitpos: [19:9]; default: 0; + * This field is used to set address of RTC memory for CRC. + */ +#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007FFU +#define SYSTEM_RTC_MEM_CRC_ADDR_M (SYSTEM_RTC_MEM_CRC_ADDR_V << SYSTEM_RTC_MEM_CRC_ADDR_S) +#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x000007FFU +#define SYSTEM_RTC_MEM_CRC_ADDR_S 9 +/** SYSTEM_RTC_MEM_CRC_LEN : R/W; bitpos: [30:20]; default: 2047; + * This field is used to set length of RTC memory for CRC based on start address. + */ +#define SYSTEM_RTC_MEM_CRC_LEN 0x000007FFU +#define SYSTEM_RTC_MEM_CRC_LEN_M (SYSTEM_RTC_MEM_CRC_LEN_V << SYSTEM_RTC_MEM_CRC_LEN_S) +#define SYSTEM_RTC_MEM_CRC_LEN_V 0x000007FFU +#define SYSTEM_RTC_MEM_CRC_LEN_S 20 +/** SYSTEM_RTC_MEM_CRC_FINISH : RO; bitpos: [31]; default: 0; + * This bit stores the status of RTC memory CRC.1 means finished. + */ +#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31)) +#define SYSTEM_RTC_MEM_CRC_FINISH_M (SYSTEM_RTC_MEM_CRC_FINISH_V << SYSTEM_RTC_MEM_CRC_FINISH_S) +#define SYSTEM_RTC_MEM_CRC_FINISH_V 0x00000001U +#define SYSTEM_RTC_MEM_CRC_FINISH_S 31 -#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x4C) -/* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: This field stores the CRC result of RTC memory..*/ -#define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFF -#define SYSTEM_RTC_MEM_CRC_RES_M ((SYSTEM_RTC_MEM_CRC_RES_V)<<(SYSTEM_RTC_MEM_CRC_RES_S)) -#define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFF +/** SYSTEM_RTC_FASTMEM_CRC_REG register + * reserved + */ +#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x4c) +/** SYSTEM_RTC_MEM_CRC_RES : RO; bitpos: [31:0]; default: 0; + * This field stores the CRC result of RTC memory. + */ +#define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFFU +#define SYSTEM_RTC_MEM_CRC_RES_M (SYSTEM_RTC_MEM_CRC_RES_V << SYSTEM_RTC_MEM_CRC_RES_S) +#define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFFU #define SYSTEM_RTC_MEM_CRC_RES_S 0 -#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x50) -/* SYSTEM_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: reg_redundant_eco_result.*/ -#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1)) -#define SYSTEM_REDUNDANT_ECO_RESULT_M (BIT(1)) -#define SYSTEM_REDUNDANT_ECO_RESULT_V 0x1 -#define SYSTEM_REDUNDANT_ECO_RESULT_S 1 -/* SYSTEM_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: reg_redundant_eco_drive.*/ +/** SYSTEM_REDUNDANT_ECO_CTRL_REG register + * eco register + */ +#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x50) +/** SYSTEM_REDUNDANT_ECO_DRIVE : R/W; bitpos: [0]; default: 0; + * reg_redundant_eco_drive + */ #define SYSTEM_REDUNDANT_ECO_DRIVE (BIT(0)) -#define SYSTEM_REDUNDANT_ECO_DRIVE_M (BIT(0)) -#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x1 +#define SYSTEM_REDUNDANT_ECO_DRIVE_M (SYSTEM_REDUNDANT_ECO_DRIVE_V << SYSTEM_REDUNDANT_ECO_DRIVE_S) +#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x00000001U #define SYSTEM_REDUNDANT_ECO_DRIVE_S 0 +/** SYSTEM_REDUNDANT_ECO_RESULT : RO; bitpos: [1]; default: 0; + * reg_redundant_eco_result + */ +#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1)) +#define SYSTEM_REDUNDANT_ECO_RESULT_M (SYSTEM_REDUNDANT_ECO_RESULT_V << SYSTEM_REDUNDANT_ECO_RESULT_S) +#define SYSTEM_REDUNDANT_ECO_RESULT_V 0x00000001U +#define SYSTEM_REDUNDANT_ECO_RESULT_S 1 -#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x54) -/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: reg_clk_en.*/ +/** SYSTEM_CLOCK_GATE_REG register + * clock gating register + */ +#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x54) +/** SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ #define SYSTEM_CLK_EN (BIT(0)) -#define SYSTEM_CLK_EN_M (BIT(0)) -#define SYSTEM_CLK_EN_V 0x1 +#define SYSTEM_CLK_EN_M (SYSTEM_CLK_EN_V << SYSTEM_CLK_EN_S) +#define SYSTEM_CLK_EN_V 0x00000001U #define SYSTEM_CLK_EN_S 0 -#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x58) -/* SYSTEM_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */ -/*description: reg_clk_div_en.*/ -#define SYSTEM_CLK_DIV_EN (BIT(19)) -#define SYSTEM_CLK_DIV_EN_M (BIT(19)) -#define SYSTEM_CLK_DIV_EN_V 0x1 -#define SYSTEM_CLK_DIV_EN_S 19 -/* SYSTEM_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */ -/*description: This field is used to read xtal frequency in MHz..*/ -#define SYSTEM_CLK_XTAL_FREQ 0x0000007F -#define SYSTEM_CLK_XTAL_FREQ_M ((SYSTEM_CLK_XTAL_FREQ_V)<<(SYSTEM_CLK_XTAL_FREQ_S)) -#define SYSTEM_CLK_XTAL_FREQ_V 0x7F -#define SYSTEM_CLK_XTAL_FREQ_S 12 -/* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: This field is used to select soc clock..*/ -#define SYSTEM_SOC_CLK_SEL 0x00000003 -#define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S)) -#define SYSTEM_SOC_CLK_SEL_V 0x3 -#define SYSTEM_SOC_CLK_SEL_S 10 -/* SYSTEM_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ -/*description: This field is used to set the count of prescaler of XTAL_CLK..*/ -#define SYSTEM_PRE_DIV_CNT 0x000003FF -#define SYSTEM_PRE_DIV_CNT_M ((SYSTEM_PRE_DIV_CNT_V)<<(SYSTEM_PRE_DIV_CNT_S)) -#define SYSTEM_PRE_DIV_CNT_V 0x3FF +/** SYSTEM_SYSCLK_CONF_REG register + * system clock config register + */ +#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x58) +/** SYSTEM_PRE_DIV_CNT : R/W; bitpos: [9:0]; default: 1; + * This field is used to set the count of prescaler of XTAL_CLK. + */ +#define SYSTEM_PRE_DIV_CNT 0x000003FFU +#define SYSTEM_PRE_DIV_CNT_M (SYSTEM_PRE_DIV_CNT_V << SYSTEM_PRE_DIV_CNT_S) +#define SYSTEM_PRE_DIV_CNT_V 0x000003FFU #define SYSTEM_PRE_DIV_CNT_S 0 +/** SYSTEM_SOC_CLK_SEL : R/W; bitpos: [11:10]; default: 0; + * This field is used to select soc clock. + */ +#define SYSTEM_SOC_CLK_SEL 0x00000003U +#define SYSTEM_SOC_CLK_SEL_M (SYSTEM_SOC_CLK_SEL_V << SYSTEM_SOC_CLK_SEL_S) +#define SYSTEM_SOC_CLK_SEL_V 0x00000003U +#define SYSTEM_SOC_CLK_SEL_S 10 +/** SYSTEM_CLK_XTAL_FREQ : RO; bitpos: [18:12]; default: 0; + * This field is used to read xtal frequency in MHz. + */ +#define SYSTEM_CLK_XTAL_FREQ 0x0000007FU +#define SYSTEM_CLK_XTAL_FREQ_M (SYSTEM_CLK_XTAL_FREQ_V << SYSTEM_CLK_XTAL_FREQ_S) +#define SYSTEM_CLK_XTAL_FREQ_V 0x0000007FU +#define SYSTEM_CLK_XTAL_FREQ_S 12 +/** SYSTEM_CLK_DIV_EN : RO; bitpos: [19]; default: 0; + * reg_clk_div_en + */ +#define SYSTEM_CLK_DIV_EN (BIT(19)) +#define SYSTEM_CLK_DIV_EN_M (SYSTEM_CLK_DIV_EN_V << SYSTEM_CLK_DIV_EN_S) +#define SYSTEM_CLK_DIV_EN_V 0x00000001U +#define SYSTEM_CLK_DIV_EN_S 19 -#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x5C) -/* SYSTEM_MEM_VT_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: reg_mem_vt_sel.*/ -#define SYSTEM_MEM_VT_SEL 0x00000003 -#define SYSTEM_MEM_VT_SEL_M ((SYSTEM_MEM_VT_SEL_V)<<(SYSTEM_MEM_VT_SEL_S)) -#define SYSTEM_MEM_VT_SEL_V 0x3 -#define SYSTEM_MEM_VT_SEL_S 22 -/* SYSTEM_MEM_TIMING_ERR_CNT : RO ;bitpos:[21:6] ;default: 16'h0 ; */ -/*description: reg_mem_timing_err_cnt.*/ -#define SYSTEM_MEM_TIMING_ERR_CNT 0x0000FFFF -#define SYSTEM_MEM_TIMING_ERR_CNT_M ((SYSTEM_MEM_TIMING_ERR_CNT_V)<<(SYSTEM_MEM_TIMING_ERR_CNT_S)) -#define SYSTEM_MEM_TIMING_ERR_CNT_V 0xFFFF -#define SYSTEM_MEM_TIMING_ERR_CNT_S 6 -/* SYSTEM_MEM_PVT_MONITOR_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: reg_mem_pvt_monitor_en.*/ -#define SYSTEM_MEM_PVT_MONITOR_EN (BIT(5)) -#define SYSTEM_MEM_PVT_MONITOR_EN_M (BIT(5)) -#define SYSTEM_MEM_PVT_MONITOR_EN_V 0x1 -#define SYSTEM_MEM_PVT_MONITOR_EN_S 5 -/* SYSTEM_MEM_ERR_CNT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: reg_mem_err_cnt_clr.*/ -#define SYSTEM_MEM_ERR_CNT_CLR (BIT(4)) -#define SYSTEM_MEM_ERR_CNT_CLR_M (BIT(4)) -#define SYSTEM_MEM_ERR_CNT_CLR_V 0x1 -#define SYSTEM_MEM_ERR_CNT_CLR_S 4 -/* SYSTEM_MEM_PATH_LEN : R/W ;bitpos:[3:0] ;default: 4'h3 ; */ -/*description: reg_mem_path_len.*/ -#define SYSTEM_MEM_PATH_LEN 0x0000000F -#define SYSTEM_MEM_PATH_LEN_M ((SYSTEM_MEM_PATH_LEN_V)<<(SYSTEM_MEM_PATH_LEN_S)) -#define SYSTEM_MEM_PATH_LEN_V 0xF +/** SYSTEM_MEM_PVT_REG register + * mem pvt register + */ +#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x5c) +/** SYSTEM_MEM_PATH_LEN : R/W; bitpos: [3:0]; default: 3; + * reg_mem_path_len + */ +#define SYSTEM_MEM_PATH_LEN 0x0000000FU +#define SYSTEM_MEM_PATH_LEN_M (SYSTEM_MEM_PATH_LEN_V << SYSTEM_MEM_PATH_LEN_S) +#define SYSTEM_MEM_PATH_LEN_V 0x0000000FU #define SYSTEM_MEM_PATH_LEN_S 0 +/** SYSTEM_MEM_ERR_CNT_CLR : WT; bitpos: [4]; default: 0; + * reg_mem_err_cnt_clr + */ +#define SYSTEM_MEM_ERR_CNT_CLR (BIT(4)) +#define SYSTEM_MEM_ERR_CNT_CLR_M (SYSTEM_MEM_ERR_CNT_CLR_V << SYSTEM_MEM_ERR_CNT_CLR_S) +#define SYSTEM_MEM_ERR_CNT_CLR_V 0x00000001U +#define SYSTEM_MEM_ERR_CNT_CLR_S 4 +/** SYSTEM_MEM_PVT_MONITOR_EN : R/W; bitpos: [5]; default: 0; + * reg_mem_pvt_monitor_en + */ +#define SYSTEM_MEM_PVT_MONITOR_EN (BIT(5)) +#define SYSTEM_MEM_PVT_MONITOR_EN_M (SYSTEM_MEM_PVT_MONITOR_EN_V << SYSTEM_MEM_PVT_MONITOR_EN_S) +#define SYSTEM_MEM_PVT_MONITOR_EN_V 0x00000001U +#define SYSTEM_MEM_PVT_MONITOR_EN_S 5 +/** SYSTEM_MEM_TIMING_ERR_CNT : RO; bitpos: [21:6]; default: 0; + * reg_mem_timing_err_cnt + */ +#define SYSTEM_MEM_TIMING_ERR_CNT 0x0000FFFFU +#define SYSTEM_MEM_TIMING_ERR_CNT_M (SYSTEM_MEM_TIMING_ERR_CNT_V << SYSTEM_MEM_TIMING_ERR_CNT_S) +#define SYSTEM_MEM_TIMING_ERR_CNT_V 0x0000FFFFU +#define SYSTEM_MEM_TIMING_ERR_CNT_S 6 +/** SYSTEM_MEM_VT_SEL : R/W; bitpos: [23:22]; default: 0; + * reg_mem_vt_sel + */ +#define SYSTEM_MEM_VT_SEL 0x00000003U +#define SYSTEM_MEM_VT_SEL_M (SYSTEM_MEM_VT_SEL_V << SYSTEM_MEM_VT_SEL_S) +#define SYSTEM_MEM_VT_SEL_V 0x00000003U +#define SYSTEM_MEM_VT_SEL_S 22 -#define SYSTEM_COMB_PVT_LVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x60) -/* SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: reg_comb_pvt_monitor_en_lvt.*/ -#define SYSTEM_COMB_PVT_MONITOR_EN_LVT (BIT(7)) -#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_M (BIT(7)) -#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_V 0x1 -#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_S 7 -/* SYSTEM_COMB_ERR_CNT_CLR_LVT : WT ;bitpos:[6] ;default: 1'b0 ; */ -/*description: reg_comb_err_cnt_clr_lvt.*/ -#define SYSTEM_COMB_ERR_CNT_CLR_LVT (BIT(6)) -#define SYSTEM_COMB_ERR_CNT_CLR_LVT_M (BIT(6)) -#define SYSTEM_COMB_ERR_CNT_CLR_LVT_V 0x1 -#define SYSTEM_COMB_ERR_CNT_CLR_LVT_S 6 -/* SYSTEM_COMB_PATH_LEN_LVT : R/W ;bitpos:[5:0] ;default: 6'h3 ; */ -/*description: reg_comb_path_len_lvt.*/ -#define SYSTEM_COMB_PATH_LEN_LVT 0x0000003F -#define SYSTEM_COMB_PATH_LEN_LVT_M ((SYSTEM_COMB_PATH_LEN_LVT_V)<<(SYSTEM_COMB_PATH_LEN_LVT_S)) -#define SYSTEM_COMB_PATH_LEN_LVT_V 0x3F +/** SYSTEM_COMB_PVT_LVT_CONF_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_LVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x60) +/** SYSTEM_COMB_PATH_LEN_LVT : R/W; bitpos: [5:0]; default: 3; + * reg_comb_path_len_lvt + */ +#define SYSTEM_COMB_PATH_LEN_LVT 0x0000003FU +#define SYSTEM_COMB_PATH_LEN_LVT_M (SYSTEM_COMB_PATH_LEN_LVT_V << SYSTEM_COMB_PATH_LEN_LVT_S) +#define SYSTEM_COMB_PATH_LEN_LVT_V 0x0000003FU #define SYSTEM_COMB_PATH_LEN_LVT_S 0 +/** SYSTEM_COMB_ERR_CNT_CLR_LVT : WT; bitpos: [6]; default: 0; + * reg_comb_err_cnt_clr_lvt + */ +#define SYSTEM_COMB_ERR_CNT_CLR_LVT (BIT(6)) +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_M (SYSTEM_COMB_ERR_CNT_CLR_LVT_V << SYSTEM_COMB_ERR_CNT_CLR_LVT_S) +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_V 0x00000001U +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_S 6 +/** SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W; bitpos: [7]; default: 0; + * reg_comb_pvt_monitor_en_lvt + */ +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT (BIT(7)) +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_M (SYSTEM_COMB_PVT_MONITOR_EN_LVT_V << SYSTEM_COMB_PVT_MONITOR_EN_LVT_S) +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_V 0x00000001U +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_S 7 -#define SYSTEM_COMB_PVT_NVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x64) -/* SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: reg_comb_pvt_monitor_en_nvt.*/ -#define SYSTEM_COMB_PVT_MONITOR_EN_NVT (BIT(7)) -#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_M (BIT(7)) -#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_V 0x1 -#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_S 7 -/* SYSTEM_COMB_ERR_CNT_CLR_NVT : WT ;bitpos:[6] ;default: 1'b0 ; */ -/*description: reg_comb_err_cnt_clr_nvt.*/ -#define SYSTEM_COMB_ERR_CNT_CLR_NVT (BIT(6)) -#define SYSTEM_COMB_ERR_CNT_CLR_NVT_M (BIT(6)) -#define SYSTEM_COMB_ERR_CNT_CLR_NVT_V 0x1 -#define SYSTEM_COMB_ERR_CNT_CLR_NVT_S 6 -/* SYSTEM_COMB_PATH_LEN_NVT : R/W ;bitpos:[5:0] ;default: 6'h3 ; */ -/*description: reg_comb_path_len_nvt.*/ -#define SYSTEM_COMB_PATH_LEN_NVT 0x0000003F -#define SYSTEM_COMB_PATH_LEN_NVT_M ((SYSTEM_COMB_PATH_LEN_NVT_V)<<(SYSTEM_COMB_PATH_LEN_NVT_S)) -#define SYSTEM_COMB_PATH_LEN_NVT_V 0x3F +/** SYSTEM_COMB_PVT_NVT_CONF_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_NVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x64) +/** SYSTEM_COMB_PATH_LEN_NVT : R/W; bitpos: [5:0]; default: 3; + * reg_comb_path_len_nvt + */ +#define SYSTEM_COMB_PATH_LEN_NVT 0x0000003FU +#define SYSTEM_COMB_PATH_LEN_NVT_M (SYSTEM_COMB_PATH_LEN_NVT_V << SYSTEM_COMB_PATH_LEN_NVT_S) +#define SYSTEM_COMB_PATH_LEN_NVT_V 0x0000003FU #define SYSTEM_COMB_PATH_LEN_NVT_S 0 +/** SYSTEM_COMB_ERR_CNT_CLR_NVT : WT; bitpos: [6]; default: 0; + * reg_comb_err_cnt_clr_nvt + */ +#define SYSTEM_COMB_ERR_CNT_CLR_NVT (BIT(6)) +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_M (SYSTEM_COMB_ERR_CNT_CLR_NVT_V << SYSTEM_COMB_ERR_CNT_CLR_NVT_S) +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_V 0x00000001U +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_S 6 +/** SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W; bitpos: [7]; default: 0; + * reg_comb_pvt_monitor_en_nvt + */ +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT (BIT(7)) +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_M (SYSTEM_COMB_PVT_MONITOR_EN_NVT_V << SYSTEM_COMB_PVT_MONITOR_EN_NVT_S) +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_V 0x00000001U +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_S 7 -#define SYSTEM_COMB_PVT_HVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x68) -/* SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: reg_comb_pvt_monitor_en_hvt.*/ -#define SYSTEM_COMB_PVT_MONITOR_EN_HVT (BIT(7)) -#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M (BIT(7)) -#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V 0x1 -#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S 7 -/* SYSTEM_COMB_ERR_CNT_CLR_HVT : WT ;bitpos:[6] ;default: 1'b0 ; */ -/*description: reg_comb_err_cnt_clr_hvt.*/ -#define SYSTEM_COMB_ERR_CNT_CLR_HVT (BIT(6)) -#define SYSTEM_COMB_ERR_CNT_CLR_HVT_M (BIT(6)) -#define SYSTEM_COMB_ERR_CNT_CLR_HVT_V 0x1 -#define SYSTEM_COMB_ERR_CNT_CLR_HVT_S 6 -/* SYSTEM_COMB_PATH_LEN_HVT : R/W ;bitpos:[5:0] ;default: 6'h3 ; */ -/*description: reg_comb_path_len_hvt.*/ -#define SYSTEM_COMB_PATH_LEN_HVT 0x0000003F -#define SYSTEM_COMB_PATH_LEN_HVT_M ((SYSTEM_COMB_PATH_LEN_HVT_V)<<(SYSTEM_COMB_PATH_LEN_HVT_S)) -#define SYSTEM_COMB_PATH_LEN_HVT_V 0x3F +/** SYSTEM_COMB_PVT_HVT_CONF_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_HVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x68) +/** SYSTEM_COMB_PATH_LEN_HVT : R/W; bitpos: [5:0]; default: 3; + * reg_comb_path_len_hvt + */ +#define SYSTEM_COMB_PATH_LEN_HVT 0x0000003FU +#define SYSTEM_COMB_PATH_LEN_HVT_M (SYSTEM_COMB_PATH_LEN_HVT_V << SYSTEM_COMB_PATH_LEN_HVT_S) +#define SYSTEM_COMB_PATH_LEN_HVT_V 0x0000003FU #define SYSTEM_COMB_PATH_LEN_HVT_S 0 +/** SYSTEM_COMB_ERR_CNT_CLR_HVT : WT; bitpos: [6]; default: 0; + * reg_comb_err_cnt_clr_hvt + */ +#define SYSTEM_COMB_ERR_CNT_CLR_HVT (BIT(6)) +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_M (SYSTEM_COMB_ERR_CNT_CLR_HVT_V << SYSTEM_COMB_ERR_CNT_CLR_HVT_S) +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_V 0x00000001U +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_S 6 +/** SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W; bitpos: [7]; default: 0; + * reg_comb_pvt_monitor_en_hvt + */ +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT (BIT(7)) +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M (SYSTEM_COMB_PVT_MONITOR_EN_HVT_V << SYSTEM_COMB_PVT_MONITOR_EN_HVT_S) +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V 0x00000001U +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S 7 -#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x6C) -/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: reg_comb_timing_err_cnt_lvt_site0.*/ -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V 0xFFFF +/** SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x6c) +/** SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_lvt_site0 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_M (SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V << SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V 0x0000FFFFU #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S 0 -#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x70) -/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: reg_comb_timing_err_cnt_nvt_site0.*/ -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V 0xFFFF +/** SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x70) +/** SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_nvt_site0 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M (SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V << SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V 0x0000FFFFU #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S 0 -#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x74) -/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: reg_comb_timing_err_cnt_hvt_site0.*/ -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V 0xFFFF +/** SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x74) +/** SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_hvt_site0 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_M (SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V << SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V 0x0000FFFFU #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S 0 -#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x78) -/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: reg_comb_timing_err_cnt_lvt_site1.*/ -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V 0xFFFF +/** SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x78) +/** SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_lvt_site1 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_M (SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V << SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V 0x0000FFFFU #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S 0 -#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x7C) -/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: reg_comb_timing_err_cnt_nvt_site1.*/ -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V 0xFFFF +/** SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x7c) +/** SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_nvt_site1 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M (SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V << SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V 0x0000FFFFU #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S 0 -#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x80) -/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: reg_comb_timing_err_cnt_hvt_site1.*/ -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V 0xFFFF +/** SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x80) +/** SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_hvt_site1 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_M (SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V << SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V 0x0000FFFFU #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S 0 -#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x84) -/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: reg_comb_timing_err_cnt_lvt_site2.*/ -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V 0xFFFF +/** SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x84) +/** SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_lvt_site2 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_M (SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V << SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V 0x0000FFFFU #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S 0 -#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x88) -/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: reg_comb_timing_err_cnt_nvt_site2.*/ -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V 0xFFFF +/** SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x88) +/** SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_nvt_site2 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M (SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V << SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V 0x0000FFFFU #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S 0 -#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x8C) -/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: reg_comb_timing_err_cnt_hvt_site2.*/ -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V 0xFFFF +/** SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x8c) +/** SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_hvt_site2 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_M (SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V << SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V 0x0000FFFFU #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S 0 -#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x90) -/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: reg_comb_timing_err_cnt_lvt_site3.*/ -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V 0xFFFF +/** SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x90) +/** SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_lvt_site3 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_M (SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V << SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V 0x0000FFFFU #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S 0 -#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x94) -/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: reg_comb_timing_err_cnt_nvt_site3.*/ -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V 0xFFFF +/** SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x94) +/** SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_nvt_site3 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M (SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V << SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V 0x0000FFFFU #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S 0 -#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x98) -/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: reg_comb_timing_err_cnt_hvt_site3.*/ -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V 0xFFFF +/** SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x98) +/** SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_hvt_site3 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_M (SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V << SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V 0x0000FFFFU #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S 0 -#define SYSTEM_REG_DATE_REG (DR_REG_SYSTEM_BASE + 0xFFC) -/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2108190 ; */ -/*description: reg_system_reg_date.*/ -#define SYSTEM_DATE 0x0FFFFFFF -#define SYSTEM_DATE_M ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S)) -#define SYSTEM_DATE_V 0xFFFFFFF -#define SYSTEM_DATE_S 0 - +/** SYSTEM_REG_DATE_REG register + * Version register + */ +#define SYSTEM_REG_DATE_REG (DR_REG_SYSTEM_BASE + 0xffc) +/** SYSTEM_SYSTEM_REG_DATE : R/W; bitpos: [27:0]; default: 34636176; + * reg_system_reg_date + */ +#define SYSTEM_SYSTEM_REG_DATE 0x0FFFFFFFU +#define SYSTEM_SYSTEM_REG_DATE_M (SYSTEM_SYSTEM_REG_DATE_V << SYSTEM_SYSTEM_REG_DATE_S) +#define SYSTEM_SYSTEM_REG_DATE_V 0x0FFFFFFFU +#define SYSTEM_SYSTEM_REG_DATE_S 0 #ifdef __cplusplus } #endif - - - -#endif /*_SOC_SYSTEM_REG_H_ */ diff --git a/components/soc/esp8684/include/soc/system_struct.h b/components/soc/esp8684/include/soc/system_struct.h index 457b9f150d..b53e34d622 100644 --- a/components/soc/esp8684/include/soc/system_struct.h +++ b/components/soc/esp8684/include/soc/system_struct.h @@ -1,1404 +1,915 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_SYSTEM_STRUCT_H_ -#define _SOC_SYSTEM_STRUCT_H_ - +#pragma once +#include #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -typedef volatile struct system_dev_s { - union { - struct { - uint32_t reserved0 : 6; /*reserved*/ - uint32_t clk_en_assist_debug : 1; /*Set 1 to open assist_debug module clock*/ - uint32_t clk_en_dedicated_gpio : 1; /*Set 1 to open dedicated_gpio module clk*/ - uint32_t reserved8 : 24; /*reserved*/ - }; - uint32_t val; - } cpu_peri_clk_en; - union { - struct { - uint32_t reserved0 : 6; /*reserved*/ - uint32_t rst_en_assist_debug : 1; /*Set 1 to let assist_debug module reset*/ - uint32_t rst_en_dedicated_gpio : 1; /*Set 1 to let dedicated_gpio module reset*/ - uint32_t reserved8 : 24; /*reserved*/ - }; - uint32_t val; - } cpu_peri_rst_en; - union { - struct { - uint32_t cpuperiod_sel : 2; /*This field used to sel cpu clock frequent.*/ - uint32_t pll_freq_sel : 1; /*This field used to sel pll frequent.*/ - uint32_t cpu_wait_mode_force_on : 1; /*Set 1 to force cpu_waiti_clk enable.*/ - uint32_t cpu_waiti_delay_num : 4; /*This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close*/ - uint32_t reserved8 : 24; /*reserved*/ - }; - uint32_t val; - } cpu_per_conf; - union { - struct { - uint32_t lslp_mem_pd_mask : 1; /*Set 1 to mask memory power down.*/ - uint32_t reserved1 : 31; /*reserved*/ - }; - uint32_t val; - } mem_pd_mask; - union { - struct { - uint32_t reserved0 : 1; /*reserved*/ - uint32_t spi01_clk_en : 1; /*Set 1 to enable SPI01 clock*/ - uint32_t uart_clk_en : 1; /*Set 1 to enable UART clock*/ - uint32_t reserved3 : 1; /*reserved*/ - uint32_t reserved4 : 1; /*reserved*/ - uint32_t uart1_clk_en : 1; /*Set 1 to enable UART1 clock*/ - uint32_t spi2_clk_en : 1; /*Set 1 to enable SPI2 clock*/ - uint32_t i2c_ext0_clk_en : 1; /*Set 1 to enable I2C_EXT0 clock*/ - uint32_t reserved8 : 1; /*reserved*/ - uint32_t reserved9 : 1; /*reserved*/ - uint32_t reserved10 : 1; /*reserved*/ - uint32_t ledc_clk_en : 1; /*Set 1 to enable LEDC clock*/ - uint32_t reserved12 : 1; /*reserved*/ - uint32_t timergroup_clk_en : 1; /*Set 1 to enable TIMERGROUP clock*/ - uint32_t reserved14 : 1; /*reserved*/ - uint32_t reserved15 : 1; /*reserved*/ - uint32_t reserved16 : 1; /*reserved*/ - uint32_t reserved17 : 1; /*reserved*/ - uint32_t reserved18 : 1; /*reserved*/ - uint32_t reserved19 : 1; /*reserved*/ - uint32_t reserved20 : 1; /*reserved*/ - uint32_t reserved21 : 1; /*reserved*/ - uint32_t reserved22 : 1; /*reserved*/ - uint32_t reserved23 : 1; /*reserved*/ - uint32_t uart_mem_clk_en : 1; /*Set 1 to enable UART_MEM clock*/ - uint32_t reserved25 : 1; /*reserved*/ - uint32_t reserved26 : 1; /*reserved*/ - uint32_t reserved27 : 1; /*reserved*/ - uint32_t apb_saradc_clk_en : 1; /*Set 1 to enable APB_SARADC clock*/ - uint32_t systimer_clk_en : 1; /*Set 1 to enable SYSTEMTIMER clock*/ - uint32_t adc2_arb_clk_en : 1; /*Set 1 to enable ADC2_ARB clock*/ - uint32_t reserved31 : 1; /*reserved*/ - }; - uint32_t val; - } perip_clk_en0; - union { - struct { - uint32_t reserved0 : 1; /*reserved*/ - uint32_t crypto_ecc_clk_en : 1; /*Set 1 to enable ECC clock*/ - uint32_t crypto_sha_clk_en : 1; /*Set 1 to enable SHA clock*/ - uint32_t reserved3 : 1; /*reserved*/ - uint32_t reserved4 : 1; /*reserved*/ - uint32_t reserved5 : 1; /*reserved*/ - uint32_t dma_clk_en : 1; /*Set 1 to enable DMA clock*/ - uint32_t reserved7 : 1; /*reserved*/ - uint32_t reserved8 : 1; /*reserved*/ - uint32_t reserved9 : 1; /*reserved*/ - uint32_t tsens_clk_en : 1; /*Set 1 to enable TSENS clock*/ - uint32_t reserved11 : 21; /*reserved*/ - }; - uint32_t val; - } perip_clk_en1; - union { - struct { - uint32_t reserved0 : 1; /*reserved*/ - uint32_t spi01_rst : 1; /*Set 1 to let SPI01 reset*/ - uint32_t uart_rst : 1; /*Set 1 to let UART reset*/ - uint32_t reserved3 : 1; /*reserved*/ - uint32_t reserved4 : 1; /*reserved*/ - uint32_t uart1_rst : 1; /*Set 1 to let UART1 reset*/ - uint32_t spi2_rst : 1; /*Set 1 to let SPI2 reset*/ - uint32_t i2c_ext0_rst : 1; /*Set 1 to let I2C_EXT0 reset*/ - uint32_t reserved8 : 1; /*reserved*/ - uint32_t reserved9 : 1; /*reserved*/ - uint32_t reserved10 : 1; /*reserved*/ - uint32_t ledc_rst : 1; /*Set 1 to let LEDC reset*/ - uint32_t reserved12 : 1; /*reserved*/ - uint32_t timergroup_rst : 1; /*Set 1 to let TIMERGROUP reset*/ - uint32_t reserved14 : 1; /*reserved*/ - uint32_t reserved15 : 1; /*reserved*/ - uint32_t reserved16 : 1; /*reserved*/ - uint32_t reserved17 : 1; /*reserved*/ - uint32_t reserved18 : 1; /*reserved*/ - uint32_t reserved19 : 1; /*reserved*/ - uint32_t reserved20 : 1; /*reserved*/ - uint32_t reserved21 : 1; /*reserved*/ - uint32_t reserved22 : 1; /*reserved*/ - uint32_t reserved23 : 1; /*reserved*/ - uint32_t uart_mem_rst : 1; /*Set 1 to let UART_MEM reset*/ - uint32_t reserved25 : 1; /*reserved*/ - uint32_t reserved26 : 1; /*reserved*/ - uint32_t reserved27 : 1; /*reserved*/ - uint32_t apb_saradc_rst : 1; /*Set 1 to let APB_SARADC reset*/ - uint32_t systimer_rst : 1; /*Set 1 to let SYSTIMER reset*/ - uint32_t adc2_arb_rst : 1; /*Set 1 to let ADC2_ARB reset*/ - uint32_t reserved31 : 1; /*reserved*/ - }; - uint32_t val; - } perip_rst_en0; - union { - struct { - uint32_t reserved0 : 1; /*reserved*/ - uint32_t crypto_ecc_rst : 1; /*Set 1 to let CRYPTO_ECC reset*/ - uint32_t crypto_sha_rst : 1; /*Set 1 to let CRYPTO_SHA reset*/ - uint32_t reserved3 : 1; /*reserved*/ - uint32_t reserved4 : 1; /*reserved*/ - uint32_t reserved5 : 1; /*reserved*/ - uint32_t dma_rst : 1; /*Set 1 to let DMA reset*/ - uint32_t reserved7 : 1; /*reserved*/ - uint32_t reserved8 : 1; /*reserved*/ - uint32_t reserved9 : 1; /*reserved*/ - uint32_t tsens_rst : 1; /*Set 1 to let TSENS reset*/ - uint32_t reserved11 : 21; /*reserved*/ - }; - uint32_t val; - } perip_rst_en1; - union { - struct { - uint32_t bt_lpck_div_num : 12; /*This field is lower power clock frequent division factor*/ - uint32_t reserved12 : 20; /*reserved*/ - }; - uint32_t val; - } bt_lpck_div_int; - union { - struct { - uint32_t bt_lpck_div_b : 12; /*This field is lower power clock frequent division factor b*/ - uint32_t bt_lpck_div_a : 12; /*This field is lower power clock frequent division factor a*/ - uint32_t lpclk_sel_rtc_slow : 1; /*Set 1 to select rtc-slow clock as rtc low power clock*/ - uint32_t lpclk_sel_8m : 1; /*Set 1 to select 8m clock as rtc low power clock*/ - uint32_t lpclk_sel_xtal : 1; /*Set 1 to select xtal clock as rtc low power clock*/ - uint32_t lpclk_sel_xtal32k : 1; /*Set 1 to select xtal32k clock as low power clock*/ - uint32_t lpclk_rtc_en : 1; /*Set 1 to enable RTC low power clock*/ - uint32_t reserved29 : 3; /*reserved*/ - }; - uint32_t val; - } bt_lpck_div_frac; - union { - struct { - uint32_t cpu_intr_from_cpu_0 : 1; /*Set 1 to generate cpu interrupt 0*/ - uint32_t reserved1 : 31; /*reserved*/ - }; - uint32_t val; - } cpu_intr_from_cpu_0; - union { - struct { - uint32_t cpu_intr_from_cpu_1 : 1; /*Set 1 to generate cpu interrupt 1*/ - uint32_t reserved1 : 31; /*reserved*/ - }; - uint32_t val; - } cpu_intr_from_cpu_1; - union { - struct { - uint32_t cpu_intr_from_cpu_2 : 1; /*Set 1 to generate cpu interrupt 2*/ - uint32_t reserved1 : 31; /*reserved*/ - }; - uint32_t val; - } cpu_intr_from_cpu_2; - union { - struct { - uint32_t cpu_intr_from_cpu_3 : 1; /*Set 1 to generate cpu interrupt 3*/ - uint32_t reserved1 : 31; /*reserved*/ - }; - uint32_t val; - } cpu_intr_from_cpu_3; - union { - struct { - uint32_t rsa_mem_pd : 1; /*Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA. This bit is invalid.*/ - uint32_t rsa_mem_force_pu : 1; /*Set 1 to force power up RSA memory. This bit has the second highest priority.*/ - uint32_t rsa_mem_force_pd : 1; /*Set 1 to force power down RSA memory. This bit has the highest priority.*/ - uint32_t reserved3 : 29; /*reserved*/ - }; - uint32_t val; - } rsa_pd_ctrl; - union { - struct { - uint32_t edma_clk_on : 1; /*Set 1 to enable EDMA clock.*/ - uint32_t edma_reset : 1; /*Set 1 to let EDMA reset*/ - uint32_t reserved2 : 30; /*reserved*/ - }; - uint32_t val; - } edma_ctrl; - union { - struct { - uint32_t icache_clk_on : 1; /*Set 1 to enable icache clock*/ - uint32_t icache_reset : 1; /*Set 1 to let icache reset*/ - uint32_t dcache_clk_on : 1; /*Set 1 to enable dcache clock*/ - uint32_t dcache_reset : 1; /*Set 1 to let dcache reset*/ - uint32_t reserved4 : 28; /*reserved*/ - }; - uint32_t val; - } cache_control; - union { - struct { - uint32_t enable_spi_manual_encrypt : 1; /*Set 1 to enable the SPI manual encrypt.*/ - uint32_t enable_download_db_encrypt : 1; /*Set 1 to enable download DB encrypt.*/ - uint32_t enable_download_g0cb_decrypt : 1; /*Set 1 to enable download G0CB decrypt*/ - uint32_t enable_download_manual_encrypt: 1; /*Set 1 to enable download manual encrypt*/ - uint32_t reserved4 : 28; /*reserved*/ - }; - uint32_t val; - } external_device_encrypt_decrypt_control; - union { - struct { - uint32_t reserved0 : 8; /*fast memory crc register*/ - uint32_t rtc_mem_crc_start : 1; /*Set 1 to start the CRC of RTC memory*/ - uint32_t rtc_mem_crc_addr : 11; /*This field is used to set address of RTC memory for CRC.*/ - uint32_t rtc_mem_crc_len : 11; /*This field is used to set length of RTC memory for CRC based on start address.*/ - uint32_t rtc_mem_crc_finish : 1; /*This bit stores the status of RTC memory CRC.1 means finished.*/ - }; - uint32_t val; - } rtc_fastmem_config; - uint32_t rtc_fastmem_crc; - union { - struct { - uint32_t redundant_eco_drive : 1; /*reg_redundant_eco_drive*/ - uint32_t redundant_eco_result : 1; /*reg_redundant_eco_result*/ - uint32_t reserved2 : 30; /*reserved*/ - }; - uint32_t val; - } redundant_eco_ctrl; - union { - struct { - uint32_t clk_en : 1; /*reg_clk_en*/ - uint32_t reserved1 : 31; /*reserved*/ - }; - uint32_t val; - } clock_gate; - union { - struct { - uint32_t pre_div_cnt : 10; /*This field is used to set the count of prescaler of XTAL_CLK.*/ - uint32_t soc_clk_sel : 2; /*This field is used to select soc clock.*/ - uint32_t clk_xtal_freq : 7; /*This field is used to read xtal frequency in MHz.*/ - uint32_t clk_div_en : 1; /*reg_clk_div_en*/ - uint32_t reserved20 : 12; /*reserved*/ - }; - uint32_t val; - } sysclk_conf; - union { - struct { - uint32_t mem_path_len : 4; /*reg_mem_path_len*/ - uint32_t mem_err_cnt_clr : 1; /*reg_mem_err_cnt_clr*/ - uint32_t mem_pvt_monitor_en : 1; /*reg_mem_pvt_monitor_en*/ - uint32_t mem_timing_err_cnt : 16; /*reg_mem_timing_err_cnt*/ - uint32_t mem_vt_sel : 2; /*reg_mem_vt_sel*/ - uint32_t reserved24 : 8; /*reserved*/ - }; - uint32_t val; - } mem_pvt; - union { - struct { - uint32_t comb_path_len_lvt : 6; /*reg_comb_path_len_lvt*/ - uint32_t comb_err_cnt_clr_lvt : 1; /*reg_comb_err_cnt_clr_lvt*/ - uint32_t comb_pvt_monitor_en_lvt : 1; /*reg_comb_pvt_monitor_en_lvt*/ - uint32_t reserved8 : 18; /*reserved*/ - uint32_t reserved26 : 6; /*reserved*/ - }; - uint32_t val; - } comb_pvt_lvt_conf; - union { - struct { - uint32_t comb_path_len_nvt : 6; /*reg_comb_path_len_nvt*/ - uint32_t comb_err_cnt_clr_nvt : 1; /*reg_comb_err_cnt_clr_nvt*/ - uint32_t comb_pvt_monitor_en_nvt : 1; /*reg_comb_pvt_monitor_en_nvt*/ - uint32_t reserved8 : 18; /*reserved*/ - uint32_t reserved26 : 6; /*reserved*/ - }; - uint32_t val; - } comb_pvt_nvt_conf; - union { - struct { - uint32_t comb_path_len_hvt : 6; /*reg_comb_path_len_hvt*/ - uint32_t comb_err_cnt_clr_hvt : 1; /*reg_comb_err_cnt_clr_hvt*/ - uint32_t comb_pvt_monitor_en_hvt : 1; /*reg_comb_pvt_monitor_en_hvt*/ - uint32_t reserved8 : 18; /*reserved*/ - uint32_t reserved26 : 6; /*reserved*/ - }; - uint32_t val; - } comb_pvt_hvt_conf; - union { - struct { - uint32_t comb_timing_err_cnt_lvt_site0 : 16; /*reg_comb_timing_err_cnt_lvt_site0*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_lvt_site0; - union { - struct { - uint32_t comb_timing_err_cnt_nvt_site0 : 16; /*reg_comb_timing_err_cnt_nvt_site0*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_nvt_site0; - union { - struct { - uint32_t comb_timing_err_cnt_hvt_site0 : 16; /*reg_comb_timing_err_cnt_hvt_site0*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_hvt_site0; - union { - struct { - uint32_t comb_timing_err_cnt_lvt_site1 : 16; /*reg_comb_timing_err_cnt_lvt_site1*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_lvt_site1; - union { - struct { - uint32_t comb_timing_err_cnt_nvt_site1 : 16; /*reg_comb_timing_err_cnt_nvt_site1*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_nvt_site1; - union { - struct { - uint32_t comb_timing_err_cnt_hvt_site1 : 16; /*reg_comb_timing_err_cnt_hvt_site1*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_hvt_site1; - union { - struct { - uint32_t comb_timing_err_cnt_lvt_site2 : 16; /*reg_comb_timing_err_cnt_lvt_site2*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_lvt_site2; - union { - struct { - uint32_t comb_timing_err_cnt_nvt_site2 : 16; /*reg_comb_timing_err_cnt_nvt_site2*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_nvt_site2; - union { - struct { - uint32_t comb_timing_err_cnt_hvt_site2 : 16; /*reg_comb_timing_err_cnt_hvt_site2*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_hvt_site2; - union { - struct { - uint32_t comb_timing_err_cnt_lvt_site3 : 16; /*reg_comb_timing_err_cnt_lvt_site3*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_lvt_site3; - union { - struct { - uint32_t comb_timing_err_cnt_nvt_site3 : 16; /*reg_comb_timing_err_cnt_nvt_site3*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_nvt_site3; - union { - struct { - uint32_t comb_timing_err_cnt_hvt_site3 : 16; /*reg_comb_timing_err_cnt_hvt_site3*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_hvt_site3; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t reserved_fc; - uint32_t reserved_100; - uint32_t reserved_104; - uint32_t reserved_108; - uint32_t reserved_10c; - uint32_t reserved_110; - uint32_t reserved_114; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t reserved_140; - uint32_t reserved_144; - uint32_t reserved_148; - uint32_t reserved_14c; - uint32_t reserved_150; - uint32_t reserved_154; - uint32_t reserved_158; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; - uint32_t reserved_18c; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; - uint32_t reserved_1cc; - uint32_t reserved_1d0; - uint32_t reserved_1d4; - uint32_t reserved_1d8; - uint32_t reserved_1dc; - uint32_t reserved_1e0; - uint32_t reserved_1e4; - uint32_t reserved_1e8; - uint32_t reserved_1ec; - uint32_t reserved_1f0; - uint32_t reserved_1f4; - uint32_t reserved_1f8; - uint32_t reserved_1fc; - uint32_t reserved_200; - uint32_t reserved_204; - uint32_t reserved_208; - uint32_t reserved_20c; - uint32_t reserved_210; - uint32_t reserved_214; - uint32_t reserved_218; - uint32_t reserved_21c; - uint32_t reserved_220; - uint32_t reserved_224; - uint32_t reserved_228; - uint32_t reserved_22c; - uint32_t reserved_230; - uint32_t reserved_234; - uint32_t reserved_238; - uint32_t reserved_23c; - uint32_t reserved_240; - uint32_t reserved_244; - uint32_t reserved_248; - uint32_t reserved_24c; - uint32_t reserved_250; - uint32_t reserved_254; - uint32_t reserved_258; - uint32_t reserved_25c; - uint32_t reserved_260; - uint32_t reserved_264; - uint32_t reserved_268; - uint32_t reserved_26c; - uint32_t reserved_270; - uint32_t reserved_274; - uint32_t reserved_278; - uint32_t reserved_27c; - uint32_t reserved_280; - uint32_t reserved_284; - uint32_t reserved_288; - uint32_t reserved_28c; - uint32_t reserved_290; - uint32_t reserved_294; - uint32_t reserved_298; - uint32_t reserved_29c; - uint32_t reserved_2a0; - uint32_t reserved_2a4; - uint32_t reserved_2a8; - uint32_t reserved_2ac; - uint32_t reserved_2b0; - uint32_t reserved_2b4; - uint32_t reserved_2b8; - uint32_t reserved_2bc; - uint32_t reserved_2c0; - uint32_t reserved_2c4; - uint32_t reserved_2c8; - uint32_t reserved_2cc; - uint32_t reserved_2d0; - uint32_t reserved_2d4; - uint32_t reserved_2d8; - uint32_t reserved_2dc; - uint32_t reserved_2e0; - uint32_t reserved_2e4; - uint32_t reserved_2e8; - uint32_t reserved_2ec; - uint32_t reserved_2f0; - uint32_t reserved_2f4; - uint32_t reserved_2f8; - uint32_t reserved_2fc; - uint32_t reserved_300; - uint32_t reserved_304; - uint32_t reserved_308; - uint32_t reserved_30c; - uint32_t reserved_310; - uint32_t reserved_314; - uint32_t reserved_318; - uint32_t reserved_31c; - uint32_t reserved_320; - uint32_t reserved_324; - uint32_t reserved_328; - uint32_t reserved_32c; - uint32_t reserved_330; - uint32_t reserved_334; - uint32_t reserved_338; - uint32_t reserved_33c; - uint32_t reserved_340; - uint32_t reserved_344; - uint32_t reserved_348; - uint32_t reserved_34c; - uint32_t reserved_350; - uint32_t reserved_354; - uint32_t reserved_358; - uint32_t reserved_35c; - uint32_t reserved_360; - uint32_t reserved_364; - uint32_t reserved_368; - uint32_t reserved_36c; - uint32_t reserved_370; - uint32_t reserved_374; - uint32_t reserved_378; - uint32_t reserved_37c; - uint32_t reserved_380; - uint32_t reserved_384; - uint32_t reserved_388; - uint32_t reserved_38c; - uint32_t reserved_390; - uint32_t reserved_394; - uint32_t reserved_398; - uint32_t reserved_39c; - uint32_t reserved_3a0; - uint32_t reserved_3a4; - uint32_t reserved_3a8; - uint32_t reserved_3ac; - uint32_t reserved_3b0; - uint32_t reserved_3b4; - uint32_t reserved_3b8; - uint32_t reserved_3bc; - uint32_t reserved_3c0; - uint32_t reserved_3c4; - uint32_t reserved_3c8; - uint32_t reserved_3cc; - uint32_t reserved_3d0; - uint32_t reserved_3d4; - uint32_t reserved_3d8; - uint32_t reserved_3dc; - uint32_t reserved_3e0; - uint32_t reserved_3e4; - uint32_t reserved_3e8; - uint32_t reserved_3ec; - uint32_t reserved_3f0; - uint32_t reserved_3f4; - uint32_t reserved_3f8; - uint32_t reserved_3fc; - uint32_t reserved_400; - uint32_t reserved_404; - uint32_t reserved_408; - uint32_t reserved_40c; - uint32_t reserved_410; - uint32_t reserved_414; - uint32_t reserved_418; - uint32_t reserved_41c; - uint32_t reserved_420; - uint32_t reserved_424; - uint32_t reserved_428; - uint32_t reserved_42c; - uint32_t reserved_430; - uint32_t reserved_434; - uint32_t reserved_438; - uint32_t reserved_43c; - uint32_t reserved_440; - uint32_t reserved_444; - uint32_t reserved_448; - uint32_t reserved_44c; - uint32_t reserved_450; - uint32_t reserved_454; - uint32_t reserved_458; - uint32_t reserved_45c; - uint32_t reserved_460; - uint32_t reserved_464; - uint32_t reserved_468; - uint32_t reserved_46c; - uint32_t reserved_470; - uint32_t reserved_474; - uint32_t reserved_478; - uint32_t reserved_47c; - uint32_t reserved_480; - uint32_t reserved_484; - uint32_t reserved_488; - uint32_t reserved_48c; - uint32_t reserved_490; - uint32_t reserved_494; - uint32_t reserved_498; - uint32_t reserved_49c; - uint32_t reserved_4a0; - uint32_t reserved_4a4; - uint32_t reserved_4a8; - uint32_t reserved_4ac; - uint32_t reserved_4b0; - uint32_t reserved_4b4; - uint32_t reserved_4b8; - uint32_t reserved_4bc; - uint32_t reserved_4c0; - uint32_t reserved_4c4; - uint32_t reserved_4c8; - uint32_t reserved_4cc; - uint32_t reserved_4d0; - uint32_t reserved_4d4; - uint32_t reserved_4d8; - uint32_t reserved_4dc; - uint32_t reserved_4e0; - uint32_t reserved_4e4; - uint32_t reserved_4e8; - uint32_t reserved_4ec; - uint32_t reserved_4f0; - uint32_t reserved_4f4; - uint32_t reserved_4f8; - uint32_t reserved_4fc; - uint32_t reserved_500; - uint32_t reserved_504; - uint32_t reserved_508; - uint32_t reserved_50c; - uint32_t reserved_510; - uint32_t reserved_514; - uint32_t reserved_518; - uint32_t reserved_51c; - uint32_t reserved_520; - uint32_t reserved_524; - uint32_t reserved_528; - uint32_t reserved_52c; - uint32_t reserved_530; - uint32_t reserved_534; - uint32_t reserved_538; - uint32_t reserved_53c; - uint32_t reserved_540; - uint32_t reserved_544; - uint32_t reserved_548; - uint32_t reserved_54c; - uint32_t reserved_550; - uint32_t reserved_554; - uint32_t reserved_558; - uint32_t reserved_55c; - uint32_t reserved_560; - uint32_t reserved_564; - uint32_t reserved_568; - uint32_t reserved_56c; - uint32_t reserved_570; - uint32_t reserved_574; - uint32_t reserved_578; - uint32_t reserved_57c; - uint32_t reserved_580; - uint32_t reserved_584; - uint32_t reserved_588; - uint32_t reserved_58c; - uint32_t reserved_590; - uint32_t reserved_594; - uint32_t reserved_598; - uint32_t reserved_59c; - uint32_t reserved_5a0; - uint32_t reserved_5a4; - uint32_t reserved_5a8; - uint32_t reserved_5ac; - uint32_t reserved_5b0; - uint32_t reserved_5b4; - uint32_t reserved_5b8; - uint32_t reserved_5bc; - uint32_t reserved_5c0; - uint32_t reserved_5c4; - uint32_t reserved_5c8; - uint32_t reserved_5cc; - uint32_t reserved_5d0; - uint32_t reserved_5d4; - uint32_t reserved_5d8; - uint32_t reserved_5dc; - uint32_t reserved_5e0; - uint32_t reserved_5e4; - uint32_t reserved_5e8; - uint32_t reserved_5ec; - uint32_t reserved_5f0; - uint32_t reserved_5f4; - uint32_t reserved_5f8; - uint32_t reserved_5fc; - uint32_t reserved_600; - uint32_t reserved_604; - uint32_t reserved_608; - uint32_t reserved_60c; - uint32_t reserved_610; - uint32_t reserved_614; - uint32_t reserved_618; - uint32_t reserved_61c; - uint32_t reserved_620; - uint32_t reserved_624; - uint32_t reserved_628; - uint32_t reserved_62c; - uint32_t reserved_630; - uint32_t reserved_634; - uint32_t reserved_638; - uint32_t reserved_63c; - uint32_t reserved_640; - uint32_t reserved_644; - uint32_t reserved_648; - uint32_t reserved_64c; - uint32_t reserved_650; - uint32_t reserved_654; - uint32_t reserved_658; - uint32_t reserved_65c; - uint32_t reserved_660; - uint32_t reserved_664; - uint32_t reserved_668; - uint32_t reserved_66c; - uint32_t reserved_670; - uint32_t reserved_674; - uint32_t reserved_678; - uint32_t reserved_67c; - uint32_t reserved_680; - uint32_t reserved_684; - uint32_t reserved_688; - uint32_t reserved_68c; - uint32_t reserved_690; - uint32_t reserved_694; - uint32_t reserved_698; - uint32_t reserved_69c; - uint32_t reserved_6a0; - uint32_t reserved_6a4; - uint32_t reserved_6a8; - uint32_t reserved_6ac; - uint32_t reserved_6b0; - uint32_t reserved_6b4; - uint32_t reserved_6b8; - uint32_t reserved_6bc; - uint32_t reserved_6c0; - uint32_t reserved_6c4; - uint32_t reserved_6c8; - uint32_t reserved_6cc; - uint32_t reserved_6d0; - uint32_t reserved_6d4; - uint32_t reserved_6d8; - uint32_t reserved_6dc; - uint32_t reserved_6e0; - uint32_t reserved_6e4; - uint32_t reserved_6e8; - uint32_t reserved_6ec; - uint32_t reserved_6f0; - uint32_t reserved_6f4; - uint32_t reserved_6f8; - uint32_t reserved_6fc; - uint32_t reserved_700; - uint32_t reserved_704; - uint32_t reserved_708; - uint32_t reserved_70c; - uint32_t reserved_710; - uint32_t reserved_714; - uint32_t reserved_718; - uint32_t reserved_71c; - uint32_t reserved_720; - uint32_t reserved_724; - uint32_t reserved_728; - uint32_t reserved_72c; - uint32_t reserved_730; - uint32_t reserved_734; - uint32_t reserved_738; - uint32_t reserved_73c; - uint32_t reserved_740; - uint32_t reserved_744; - uint32_t reserved_748; - uint32_t reserved_74c; - uint32_t reserved_750; - uint32_t reserved_754; - uint32_t reserved_758; - uint32_t reserved_75c; - uint32_t reserved_760; - uint32_t reserved_764; - uint32_t reserved_768; - uint32_t reserved_76c; - uint32_t reserved_770; - uint32_t reserved_774; - uint32_t reserved_778; - uint32_t reserved_77c; - uint32_t reserved_780; - uint32_t reserved_784; - uint32_t reserved_788; - uint32_t reserved_78c; - uint32_t reserved_790; - uint32_t reserved_794; - uint32_t reserved_798; - uint32_t reserved_79c; - uint32_t reserved_7a0; - uint32_t reserved_7a4; - uint32_t reserved_7a8; - uint32_t reserved_7ac; - uint32_t reserved_7b0; - uint32_t reserved_7b4; - uint32_t reserved_7b8; - uint32_t reserved_7bc; - uint32_t reserved_7c0; - uint32_t reserved_7c4; - uint32_t reserved_7c8; - uint32_t reserved_7cc; - uint32_t reserved_7d0; - uint32_t reserved_7d4; - uint32_t reserved_7d8; - uint32_t reserved_7dc; - uint32_t reserved_7e0; - uint32_t reserved_7e4; - uint32_t reserved_7e8; - uint32_t reserved_7ec; - uint32_t reserved_7f0; - uint32_t reserved_7f4; - uint32_t reserved_7f8; - uint32_t reserved_7fc; - uint32_t reserved_800; - uint32_t reserved_804; - uint32_t reserved_808; - uint32_t reserved_80c; - uint32_t reserved_810; - uint32_t reserved_814; - uint32_t reserved_818; - uint32_t reserved_81c; - uint32_t reserved_820; - uint32_t reserved_824; - uint32_t reserved_828; - uint32_t reserved_82c; - uint32_t reserved_830; - uint32_t reserved_834; - uint32_t reserved_838; - uint32_t reserved_83c; - uint32_t reserved_840; - uint32_t reserved_844; - uint32_t reserved_848; - uint32_t reserved_84c; - uint32_t reserved_850; - uint32_t reserved_854; - uint32_t reserved_858; - uint32_t reserved_85c; - uint32_t reserved_860; - uint32_t reserved_864; - uint32_t reserved_868; - uint32_t reserved_86c; - uint32_t reserved_870; - uint32_t reserved_874; - uint32_t reserved_878; - uint32_t reserved_87c; - uint32_t reserved_880; - uint32_t reserved_884; - uint32_t reserved_888; - uint32_t reserved_88c; - uint32_t reserved_890; - uint32_t reserved_894; - uint32_t reserved_898; - uint32_t reserved_89c; - uint32_t reserved_8a0; - uint32_t reserved_8a4; - uint32_t reserved_8a8; - uint32_t reserved_8ac; - uint32_t reserved_8b0; - uint32_t reserved_8b4; - uint32_t reserved_8b8; - uint32_t reserved_8bc; - uint32_t reserved_8c0; - uint32_t reserved_8c4; - uint32_t reserved_8c8; - uint32_t reserved_8cc; - uint32_t reserved_8d0; - uint32_t reserved_8d4; - uint32_t reserved_8d8; - uint32_t reserved_8dc; - uint32_t reserved_8e0; - uint32_t reserved_8e4; - uint32_t reserved_8e8; - uint32_t reserved_8ec; - uint32_t reserved_8f0; - uint32_t reserved_8f4; - uint32_t reserved_8f8; - uint32_t reserved_8fc; - uint32_t reserved_900; - uint32_t reserved_904; - uint32_t reserved_908; - uint32_t reserved_90c; - uint32_t reserved_910; - uint32_t reserved_914; - uint32_t reserved_918; - uint32_t reserved_91c; - uint32_t reserved_920; - uint32_t reserved_924; - uint32_t reserved_928; - uint32_t reserved_92c; - uint32_t reserved_930; - uint32_t reserved_934; - uint32_t reserved_938; - uint32_t reserved_93c; - uint32_t reserved_940; - uint32_t reserved_944; - uint32_t reserved_948; - uint32_t reserved_94c; - uint32_t reserved_950; - uint32_t reserved_954; - uint32_t reserved_958; - uint32_t reserved_95c; - uint32_t reserved_960; - uint32_t reserved_964; - uint32_t reserved_968; - uint32_t reserved_96c; - uint32_t reserved_970; - uint32_t reserved_974; - uint32_t reserved_978; - uint32_t reserved_97c; - uint32_t reserved_980; - uint32_t reserved_984; - uint32_t reserved_988; - uint32_t reserved_98c; - uint32_t reserved_990; - uint32_t reserved_994; - uint32_t reserved_998; - uint32_t reserved_99c; - uint32_t reserved_9a0; - uint32_t reserved_9a4; - uint32_t reserved_9a8; - uint32_t reserved_9ac; - uint32_t reserved_9b0; - uint32_t reserved_9b4; - uint32_t reserved_9b8; - uint32_t reserved_9bc; - uint32_t reserved_9c0; - uint32_t reserved_9c4; - uint32_t reserved_9c8; - uint32_t reserved_9cc; - uint32_t reserved_9d0; - uint32_t reserved_9d4; - uint32_t reserved_9d8; - uint32_t reserved_9dc; - uint32_t reserved_9e0; - uint32_t reserved_9e4; - uint32_t reserved_9e8; - uint32_t reserved_9ec; - uint32_t reserved_9f0; - uint32_t reserved_9f4; - uint32_t reserved_9f8; - uint32_t reserved_9fc; - uint32_t reserved_a00; - uint32_t reserved_a04; - uint32_t reserved_a08; - uint32_t reserved_a0c; - uint32_t reserved_a10; - uint32_t reserved_a14; - uint32_t reserved_a18; - uint32_t reserved_a1c; - uint32_t reserved_a20; - uint32_t reserved_a24; - uint32_t reserved_a28; - uint32_t reserved_a2c; - uint32_t reserved_a30; - uint32_t reserved_a34; - uint32_t reserved_a38; - uint32_t reserved_a3c; - uint32_t reserved_a40; - uint32_t reserved_a44; - uint32_t reserved_a48; - uint32_t reserved_a4c; - uint32_t reserved_a50; - uint32_t reserved_a54; - uint32_t reserved_a58; - uint32_t reserved_a5c; - uint32_t reserved_a60; - uint32_t reserved_a64; - uint32_t reserved_a68; - uint32_t reserved_a6c; - uint32_t reserved_a70; - uint32_t reserved_a74; - uint32_t reserved_a78; - uint32_t reserved_a7c; - uint32_t reserved_a80; - uint32_t reserved_a84; - uint32_t reserved_a88; - uint32_t reserved_a8c; - uint32_t reserved_a90; - uint32_t reserved_a94; - uint32_t reserved_a98; - uint32_t reserved_a9c; - uint32_t reserved_aa0; - uint32_t reserved_aa4; - uint32_t reserved_aa8; - uint32_t reserved_aac; - uint32_t reserved_ab0; - uint32_t reserved_ab4; - uint32_t reserved_ab8; - uint32_t reserved_abc; - uint32_t reserved_ac0; - uint32_t reserved_ac4; - uint32_t reserved_ac8; - uint32_t reserved_acc; - uint32_t reserved_ad0; - uint32_t reserved_ad4; - uint32_t reserved_ad8; - uint32_t reserved_adc; - uint32_t reserved_ae0; - uint32_t reserved_ae4; - uint32_t reserved_ae8; - uint32_t reserved_aec; - uint32_t reserved_af0; - uint32_t reserved_af4; - uint32_t reserved_af8; - uint32_t reserved_afc; - uint32_t reserved_b00; - uint32_t reserved_b04; - uint32_t reserved_b08; - uint32_t reserved_b0c; - uint32_t reserved_b10; - uint32_t reserved_b14; - uint32_t reserved_b18; - uint32_t reserved_b1c; - uint32_t reserved_b20; - uint32_t reserved_b24; - uint32_t reserved_b28; - uint32_t reserved_b2c; - uint32_t reserved_b30; - uint32_t reserved_b34; - uint32_t reserved_b38; - uint32_t reserved_b3c; - uint32_t reserved_b40; - uint32_t reserved_b44; - uint32_t reserved_b48; - uint32_t reserved_b4c; - uint32_t reserved_b50; - uint32_t reserved_b54; - uint32_t reserved_b58; - uint32_t reserved_b5c; - uint32_t reserved_b60; - uint32_t reserved_b64; - uint32_t reserved_b68; - uint32_t reserved_b6c; - uint32_t reserved_b70; - uint32_t reserved_b74; - uint32_t reserved_b78; - uint32_t reserved_b7c; - uint32_t reserved_b80; - uint32_t reserved_b84; - uint32_t reserved_b88; - uint32_t reserved_b8c; - uint32_t reserved_b90; - uint32_t reserved_b94; - uint32_t reserved_b98; - uint32_t reserved_b9c; - uint32_t reserved_ba0; - uint32_t reserved_ba4; - uint32_t reserved_ba8; - uint32_t reserved_bac; - uint32_t reserved_bb0; - uint32_t reserved_bb4; - uint32_t reserved_bb8; - uint32_t reserved_bbc; - uint32_t reserved_bc0; - uint32_t reserved_bc4; - uint32_t reserved_bc8; - uint32_t reserved_bcc; - uint32_t reserved_bd0; - uint32_t reserved_bd4; - uint32_t reserved_bd8; - uint32_t reserved_bdc; - uint32_t reserved_be0; - uint32_t reserved_be4; - uint32_t reserved_be8; - uint32_t reserved_bec; - uint32_t reserved_bf0; - uint32_t reserved_bf4; - uint32_t reserved_bf8; - uint32_t reserved_bfc; - uint32_t reserved_c00; - uint32_t reserved_c04; - uint32_t reserved_c08; - uint32_t reserved_c0c; - uint32_t reserved_c10; - uint32_t reserved_c14; - uint32_t reserved_c18; - uint32_t reserved_c1c; - uint32_t reserved_c20; - uint32_t reserved_c24; - uint32_t reserved_c28; - uint32_t reserved_c2c; - uint32_t reserved_c30; - uint32_t reserved_c34; - uint32_t reserved_c38; - uint32_t reserved_c3c; - uint32_t reserved_c40; - uint32_t reserved_c44; - uint32_t reserved_c48; - uint32_t reserved_c4c; - uint32_t reserved_c50; - uint32_t reserved_c54; - uint32_t reserved_c58; - uint32_t reserved_c5c; - uint32_t reserved_c60; - uint32_t reserved_c64; - uint32_t reserved_c68; - uint32_t reserved_c6c; - uint32_t reserved_c70; - uint32_t reserved_c74; - uint32_t reserved_c78; - uint32_t reserved_c7c; - uint32_t reserved_c80; - uint32_t reserved_c84; - uint32_t reserved_c88; - uint32_t reserved_c8c; - uint32_t reserved_c90; - uint32_t reserved_c94; - uint32_t reserved_c98; - uint32_t reserved_c9c; - uint32_t reserved_ca0; - uint32_t reserved_ca4; - uint32_t reserved_ca8; - uint32_t reserved_cac; - uint32_t reserved_cb0; - uint32_t reserved_cb4; - uint32_t reserved_cb8; - uint32_t reserved_cbc; - uint32_t reserved_cc0; - uint32_t reserved_cc4; - uint32_t reserved_cc8; - uint32_t reserved_ccc; - uint32_t reserved_cd0; - uint32_t reserved_cd4; - uint32_t reserved_cd8; - uint32_t reserved_cdc; - uint32_t reserved_ce0; - uint32_t reserved_ce4; - uint32_t reserved_ce8; - uint32_t reserved_cec; - uint32_t reserved_cf0; - uint32_t reserved_cf4; - uint32_t reserved_cf8; - uint32_t reserved_cfc; - uint32_t reserved_d00; - uint32_t reserved_d04; - uint32_t reserved_d08; - uint32_t reserved_d0c; - uint32_t reserved_d10; - uint32_t reserved_d14; - uint32_t reserved_d18; - uint32_t reserved_d1c; - uint32_t reserved_d20; - uint32_t reserved_d24; - uint32_t reserved_d28; - uint32_t reserved_d2c; - uint32_t reserved_d30; - uint32_t reserved_d34; - uint32_t reserved_d38; - uint32_t reserved_d3c; - uint32_t reserved_d40; - uint32_t reserved_d44; - uint32_t reserved_d48; - uint32_t reserved_d4c; - uint32_t reserved_d50; - uint32_t reserved_d54; - uint32_t reserved_d58; - uint32_t reserved_d5c; - uint32_t reserved_d60; - uint32_t reserved_d64; - uint32_t reserved_d68; - uint32_t reserved_d6c; - uint32_t reserved_d70; - uint32_t reserved_d74; - uint32_t reserved_d78; - uint32_t reserved_d7c; - uint32_t reserved_d80; - uint32_t reserved_d84; - uint32_t reserved_d88; - uint32_t reserved_d8c; - uint32_t reserved_d90; - uint32_t reserved_d94; - uint32_t reserved_d98; - uint32_t reserved_d9c; - uint32_t reserved_da0; - uint32_t reserved_da4; - uint32_t reserved_da8; - uint32_t reserved_dac; - uint32_t reserved_db0; - uint32_t reserved_db4; - uint32_t reserved_db8; - uint32_t reserved_dbc; - uint32_t reserved_dc0; - uint32_t reserved_dc4; - uint32_t reserved_dc8; - uint32_t reserved_dcc; - uint32_t reserved_dd0; - uint32_t reserved_dd4; - uint32_t reserved_dd8; - uint32_t reserved_ddc; - uint32_t reserved_de0; - uint32_t reserved_de4; - uint32_t reserved_de8; - uint32_t reserved_dec; - uint32_t reserved_df0; - uint32_t reserved_df4; - uint32_t reserved_df8; - uint32_t reserved_dfc; - uint32_t reserved_e00; - uint32_t reserved_e04; - uint32_t reserved_e08; - uint32_t reserved_e0c; - uint32_t reserved_e10; - uint32_t reserved_e14; - uint32_t reserved_e18; - uint32_t reserved_e1c; - uint32_t reserved_e20; - uint32_t reserved_e24; - uint32_t reserved_e28; - uint32_t reserved_e2c; - uint32_t reserved_e30; - uint32_t reserved_e34; - uint32_t reserved_e38; - uint32_t reserved_e3c; - uint32_t reserved_e40; - uint32_t reserved_e44; - uint32_t reserved_e48; - uint32_t reserved_e4c; - uint32_t reserved_e50; - uint32_t reserved_e54; - uint32_t reserved_e58; - uint32_t reserved_e5c; - uint32_t reserved_e60; - uint32_t reserved_e64; - uint32_t reserved_e68; - uint32_t reserved_e6c; - uint32_t reserved_e70; - uint32_t reserved_e74; - uint32_t reserved_e78; - uint32_t reserved_e7c; - uint32_t reserved_e80; - uint32_t reserved_e84; - uint32_t reserved_e88; - uint32_t reserved_e8c; - uint32_t reserved_e90; - uint32_t reserved_e94; - uint32_t reserved_e98; - uint32_t reserved_e9c; - uint32_t reserved_ea0; - uint32_t reserved_ea4; - uint32_t reserved_ea8; - uint32_t reserved_eac; - uint32_t reserved_eb0; - uint32_t reserved_eb4; - uint32_t reserved_eb8; - uint32_t reserved_ebc; - uint32_t reserved_ec0; - uint32_t reserved_ec4; - uint32_t reserved_ec8; - uint32_t reserved_ecc; - uint32_t reserved_ed0; - uint32_t reserved_ed4; - uint32_t reserved_ed8; - uint32_t reserved_edc; - uint32_t reserved_ee0; - uint32_t reserved_ee4; - uint32_t reserved_ee8; - uint32_t reserved_eec; - uint32_t reserved_ef0; - uint32_t reserved_ef4; - uint32_t reserved_ef8; - uint32_t reserved_efc; - uint32_t reserved_f00; - uint32_t reserved_f04; - uint32_t reserved_f08; - uint32_t reserved_f0c; - uint32_t reserved_f10; - uint32_t reserved_f14; - uint32_t reserved_f18; - uint32_t reserved_f1c; - uint32_t reserved_f20; - uint32_t reserved_f24; - uint32_t reserved_f28; - uint32_t reserved_f2c; - uint32_t reserved_f30; - uint32_t reserved_f34; - uint32_t reserved_f38; - uint32_t reserved_f3c; - uint32_t reserved_f40; - uint32_t reserved_f44; - uint32_t reserved_f48; - uint32_t reserved_f4c; - uint32_t reserved_f50; - uint32_t reserved_f54; - uint32_t reserved_f58; - uint32_t reserved_f5c; - uint32_t reserved_f60; - uint32_t reserved_f64; - uint32_t reserved_f68; - uint32_t reserved_f6c; - uint32_t reserved_f70; - uint32_t reserved_f74; - uint32_t reserved_f78; - uint32_t reserved_f7c; - uint32_t reserved_f80; - uint32_t reserved_f84; - uint32_t reserved_f88; - uint32_t reserved_f8c; - uint32_t reserved_f90; - uint32_t reserved_f94; - uint32_t reserved_f98; - uint32_t reserved_f9c; - uint32_t reserved_fa0; - uint32_t reserved_fa4; - uint32_t reserved_fa8; - uint32_t reserved_fac; - uint32_t reserved_fb0; - uint32_t reserved_fb4; - uint32_t reserved_fb8; - uint32_t reserved_fbc; - uint32_t reserved_fc0; - uint32_t reserved_fc4; - uint32_t reserved_fc8; - uint32_t reserved_fcc; - uint32_t reserved_fd0; - uint32_t reserved_fd4; - uint32_t reserved_fd8; - uint32_t reserved_fdc; - uint32_t reserved_fe0; - uint32_t reserved_fe4; - uint32_t reserved_fe8; - uint32_t reserved_fec; - uint32_t reserved_ff0; - uint32_t reserved_ff4; - uint32_t reserved_ff8; - union { - struct { - uint32_t system_date : 28; /*reg_system_reg_date*/ - uint32_t reserved28 : 4; /*reserved*/ - }; - uint32_t val; - } date; +/** Group: peripheral clock gating and reset registers */ +/** Type of cpu_peri_clk_en register + * cpu_peripheral clock gating register + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** clk_en_assist_debug : R/W; bitpos: [6]; default: 0; + * Set 1 to open assist_debug module clock + */ + uint32_t clk_en_assist_debug:1; + /** clk_en_dedicated_gpio : R/W; bitpos: [7]; default: 0; + * Set 1 to open dedicated_gpio module clk + */ + uint32_t clk_en_dedicated_gpio:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} system_cpu_peri_clk_en_reg_t; + +/** Type of cpu_peri_rst_en register + * cpu_peripheral reset register + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** rst_en_assist_debug : R/W; bitpos: [6]; default: 1; + * Set 1 to let assist_debug module reset + */ + uint32_t rst_en_assist_debug:1; + /** rst_en_dedicated_gpio : R/W; bitpos: [7]; default: 1; + * Set 1 to let dedicated_gpio module reset + */ + uint32_t rst_en_dedicated_gpio:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} system_cpu_peri_rst_en_reg_t; + +/** Type of perip_clk_en0 register + * peripheral clock gating register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** spi01_clk_en : R/W; bitpos: [1]; default: 1; + * Set 1 to enable SPI01 clock + */ + uint32_t spi01_clk_en:1; + /** uart_clk_en : R/W; bitpos: [2]; default: 1; + * Set 1 to enable UART clock + */ + uint32_t uart_clk_en:1; + uint32_t reserved_3:2; + /** uart1_clk_en : R/W; bitpos: [5]; default: 1; + * Set 1 to enable UART1 clock + */ + uint32_t uart1_clk_en:1; + /** spi2_clk_en : R/W; bitpos: [6]; default: 1; + * Set 1 to enable SPI2 clock + */ + uint32_t spi2_clk_en:1; + /** i2c_ext0_clk_en : R/W; bitpos: [7]; default: 0; + * Set 1 to enable I2C_EXT0 clock + */ + uint32_t i2c_ext0_clk_en:1; + uint32_t reserved_8:3; + /** ledc_clk_en : R/W; bitpos: [11]; default: 0; + * Set 1 to enable LEDC clock + */ + uint32_t ledc_clk_en:1; + uint32_t reserved_12:1; + /** timergroup_clk_en : R/W; bitpos: [13]; default: 1; + * Set 1 to enable TIMERGROUP clock + */ + uint32_t timergroup_clk_en:1; + uint32_t reserved_14:10; + /** uart_mem_clk_en : R/W; bitpos: [24]; default: 1; + * Set 1 to enable UART_MEM clock + */ + uint32_t uart_mem_clk_en:1; + uint32_t reserved_25:3; + /** apb_saradc_clk_en : R/W; bitpos: [28]; default: 1; + * Set 1 to enable APB_SARADC clock + */ + uint32_t apb_saradc_clk_en:1; + /** systimer_clk_en : R/W; bitpos: [29]; default: 1; + * Set 1 to enable SYSTEMTIMER clock + */ + uint32_t systimer_clk_en:1; + /** adc2_arb_clk_en : R/W; bitpos: [30]; default: 1; + * Set 1 to enable ADC2_ARB clock + */ + uint32_t adc2_arb_clk_en:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} system_perip_clk_en0_reg_t; + +/** Type of perip_clk_en1 register + * peripheral clock gating register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** crypto_ecc_clk_en : R/W; bitpos: [1]; default: 0; + * Set 1 to enable ECC clock + */ + uint32_t crypto_ecc_clk_en:1; + /** crypto_sha_clk_en : R/W; bitpos: [2]; default: 0; + * Set 1 to enable SHA clock + */ + uint32_t crypto_sha_clk_en:1; + uint32_t reserved_3:3; + /** dma_clk_en : R/W; bitpos: [6]; default: 0; + * Set 1 to enable DMA clock + */ + uint32_t dma_clk_en:1; + uint32_t reserved_7:3; + /** tsens_clk_en : R/W; bitpos: [10]; default: 0; + * Set 1 to enable TSENS clock + */ + uint32_t tsens_clk_en:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} system_perip_clk_en1_reg_t; + +/** Type of perip_rst_en0 register + * reserved + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** spi01_rst : R/W; bitpos: [1]; default: 0; + * Set 1 to let SPI01 reset + */ + uint32_t spi01_rst:1; + /** uart_rst : R/W; bitpos: [2]; default: 0; + * Set 1 to let UART reset + */ + uint32_t uart_rst:1; + uint32_t reserved_3:2; + /** uart1_rst : R/W; bitpos: [5]; default: 0; + * Set 1 to let UART1 reset + */ + uint32_t uart1_rst:1; + /** spi2_rst : R/W; bitpos: [6]; default: 0; + * Set 1 to let SPI2 reset + */ + uint32_t spi2_rst:1; + /** i2c_ext0_rst : R/W; bitpos: [7]; default: 0; + * Set 1 to let I2C_EXT0 reset + */ + uint32_t i2c_ext0_rst:1; + uint32_t reserved_8:3; + /** ledc_rst : R/W; bitpos: [11]; default: 0; + * Set 1 to let LEDC reset + */ + uint32_t ledc_rst:1; + uint32_t reserved_12:1; + /** timergroup_rst : R/W; bitpos: [13]; default: 0; + * Set 1 to let TIMERGROUP reset + */ + uint32_t timergroup_rst:1; + uint32_t reserved_14:10; + /** uart_mem_rst : R/W; bitpos: [24]; default: 0; + * Set 1 to let UART_MEM reset + */ + uint32_t uart_mem_rst:1; + uint32_t reserved_25:3; + /** apb_saradc_rst : R/W; bitpos: [28]; default: 0; + * Set 1 to let APB_SARADC reset + */ + uint32_t apb_saradc_rst:1; + /** systimer_rst : R/W; bitpos: [29]; default: 0; + * Set 1 to let SYSTIMER reset + */ + uint32_t systimer_rst:1; + /** adc2_arb_rst : R/W; bitpos: [30]; default: 0; + * Set 1 to let ADC2_ARB reset + */ + uint32_t adc2_arb_rst:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} system_perip_rst_en0_reg_t; + +/** Type of perip_rst_en1 register + * peripheral reset register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** crypto_ecc_rst : R/W; bitpos: [1]; default: 1; + * Set 1 to let CRYPTO_ECC reset + */ + uint32_t crypto_ecc_rst:1; + /** crypto_sha_rst : R/W; bitpos: [2]; default: 1; + * Set 1 to let CRYPTO_SHA reset + */ + uint32_t crypto_sha_rst:1; + uint32_t reserved_3:3; + /** dma_rst : R/W; bitpos: [6]; default: 1; + * Set 1 to let DMA reset + */ + uint32_t dma_rst:1; + uint32_t reserved_7:3; + /** tsens_rst : R/W; bitpos: [10]; default: 0; + * Set 1 to let TSENS reset + */ + uint32_t tsens_rst:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} system_perip_rst_en1_reg_t; + +/** Type of edma_ctrl register + * edma clcok and reset register + */ +typedef union { + struct { + /** edma_clk_on : R/W; bitpos: [0]; default: 1; + * Set 1 to enable EDMA clock. + */ + uint32_t edma_clk_on:1; + /** edma_reset : R/W; bitpos: [1]; default: 0; + * Set 1 to let EDMA reset + */ + uint32_t edma_reset:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} system_edma_ctrl_reg_t; + +/** Type of cache_control register + * cache control register + */ +typedef union { + struct { + /** icache_clk_on : R/W; bitpos: [0]; default: 1; + * Set 1 to enable icache clock + */ + uint32_t icache_clk_on:1; + /** icache_reset : R/W; bitpos: [1]; default: 0; + * Set 1 to let icache reset + */ + uint32_t icache_reset:1; + /** dcache_clk_on : R/W; bitpos: [2]; default: 1; + * Set 1 to enable dcache clock + */ + uint32_t dcache_clk_on:1; + /** dcache_reset : R/W; bitpos: [3]; default: 0; + * Set 1 to let dcache reset + */ + uint32_t dcache_reset:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} system_cache_control_reg_t; + + +/** Group: clock config register */ +/** Type of cpu_per_conf register + * cpu clock config register + */ +typedef union { + struct { + /** cpuperiod_sel : R/W; bitpos: [1:0]; default: 0; + * This field used to sel cpu clock frequent. + */ + uint32_t cpuperiod_sel:2; + /** pll_freq_sel : R/W; bitpos: [2]; default: 1; + * This field used to sel pll frequent. + */ + uint32_t pll_freq_sel:1; + /** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1; + * Set 1 to force cpu_waiti_clk enable. + */ + uint32_t cpu_wait_mode_force_on:1; + /** cpu_waiti_delay_num : R/W; bitpos: [7:4]; default: 0; + * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk + * will close + */ + uint32_t cpu_waiti_delay_num:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} system_cpu_per_conf_reg_t; + +/** Type of bt_lpck_div_int register + * clock config register + */ +typedef union { + struct { + /** bt_lpck_div_num : R/W; bitpos: [11:0]; default: 255; + * This field is lower power clock frequent division factor + */ + uint32_t bt_lpck_div_num:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} system_bt_lpck_div_int_reg_t; + +/** Type of bt_lpck_div_frac register + * low power clock configuration register + */ +typedef union { + struct { + /** bt_lpck_div_b : R/W; bitpos: [11:0]; default: 1; + * This field is lower power clock frequent division factor b + */ + uint32_t bt_lpck_div_b:12; + /** bt_lpck_div_a : R/W; bitpos: [23:12]; default: 1; + * This field is lower power clock frequent division factor a + */ + uint32_t bt_lpck_div_a:12; + /** lpclk_sel_rtc_slow : R/W; bitpos: [24]; default: 0; + * Set 1 to select rtc-slow clock as rtc low power clock + */ + uint32_t lpclk_sel_rtc_slow:1; + /** lpclk_sel_8m : R/W; bitpos: [25]; default: 1; + * Set 1 to select 8m clock as rtc low power clock + */ + uint32_t lpclk_sel_8m:1; + /** lpclk_sel_xtal : R/W; bitpos: [26]; default: 0; + * Set 1 to select xtal clock as rtc low power clock + */ + uint32_t lpclk_sel_xtal:1; + /** lpclk_sel_xtal32k : R/W; bitpos: [27]; default: 0; + * Set 1 to select xtal32k clock as low power clock + */ + uint32_t lpclk_sel_xtal32k:1; + /** lpclk_rtc_en : R/W; bitpos: [28]; default: 0; + * Set 1 to enable RTC low power clock + */ + uint32_t lpclk_rtc_en:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} system_bt_lpck_div_frac_reg_t; + +/** Type of sysclk_conf register + * system clock config register + */ +typedef union { + struct { + /** pre_div_cnt : R/W; bitpos: [9:0]; default: 1; + * This field is used to set the count of prescaler of XTAL_CLK. + */ + uint32_t pre_div_cnt:10; + /** soc_clk_sel : R/W; bitpos: [11:10]; default: 0; + * This field is used to select soc clock. + */ + uint32_t soc_clk_sel:2; + /** clk_xtal_freq : RO; bitpos: [18:12]; default: 0; + * This field is used to read xtal frequency in MHz. + */ + uint32_t clk_xtal_freq:7; + /** clk_div_en : RO; bitpos: [19]; default: 0; + * reg_clk_div_en + */ + uint32_t clk_div_en:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} system_sysclk_conf_reg_t; + + +/** Group: Low-power management register */ +/** Type of mem_pd_mask register + * memory power down mask register + */ +typedef union { + struct { + /** lslp_mem_pd_mask : R/W; bitpos: [0]; default: 1; + * Set 1 to mask memory power down. + */ + uint32_t lslp_mem_pd_mask:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} system_mem_pd_mask_reg_t; + +/** Type of rtc_fastmem_config register + * fast memory config register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** rtc_mem_crc_start : R/W; bitpos: [8]; default: 0; + * Set 1 to start the CRC of RTC memory + */ + uint32_t rtc_mem_crc_start:1; + /** rtc_mem_crc_addr : R/W; bitpos: [19:9]; default: 0; + * This field is used to set address of RTC memory for CRC. + */ + uint32_t rtc_mem_crc_addr:11; + /** rtc_mem_crc_len : R/W; bitpos: [30:20]; default: 2047; + * This field is used to set length of RTC memory for CRC based on start address. + */ + uint32_t rtc_mem_crc_len:11; + /** rtc_mem_crc_finish : RO; bitpos: [31]; default: 0; + * This bit stores the status of RTC memory CRC.1 means finished. + */ + uint32_t rtc_mem_crc_finish:1; + }; + uint32_t val; +} system_rtc_fastmem_config_reg_t; + +/** Type of rtc_fastmem_crc register + * reserved + */ +typedef union { + struct { + /** rtc_mem_crc_res : RO; bitpos: [31:0]; default: 0; + * This field stores the CRC result of RTC memory. + */ + uint32_t rtc_mem_crc_res:32; + }; + uint32_t val; +} system_rtc_fastmem_crc_reg_t; + + +/** Group: interrupt register */ +/** Type of cpu_intr_from_cpu_0 register + * interrupt generate register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_0 : R/W; bitpos: [0]; default: 0; + * Set 1 to generate cpu interrupt 0 + */ + uint32_t cpu_intr_from_cpu_0:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} system_cpu_intr_from_cpu_0_reg_t; + +/** Type of cpu_intr_from_cpu_1 register + * interrupt generate register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_1 : R/W; bitpos: [0]; default: 0; + * Set 1 to generate cpu interrupt 1 + */ + uint32_t cpu_intr_from_cpu_1:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} system_cpu_intr_from_cpu_1_reg_t; + +/** Type of cpu_intr_from_cpu_2 register + * interrupt generate register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_2 : R/W; bitpos: [0]; default: 0; + * Set 1 to generate cpu interrupt 2 + */ + uint32_t cpu_intr_from_cpu_2:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} system_cpu_intr_from_cpu_2_reg_t; + +/** Type of cpu_intr_from_cpu_3 register + * interrupt generate register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_3 : R/W; bitpos: [0]; default: 0; + * Set 1 to generate cpu interrupt 3 + */ + uint32_t cpu_intr_from_cpu_3:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} system_cpu_intr_from_cpu_3_reg_t; + + +/** Group: system and memory register */ +/** Type of rsa_pd_ctrl register + * rsa memory power control register + */ +typedef union { + struct { + /** rsa_mem_pd : R/W; bitpos: [0]; default: 1; + * Set 1 to power down RSA memory. This bit has the lowest priority.When Digital + * Signature occupies the RSA. This bit is invalid. + */ + uint32_t rsa_mem_pd:1; + /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 0; + * Set 1 to force power up RSA memory. This bit has the second highest priority. + */ + uint32_t rsa_mem_force_pu:1; + /** rsa_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set 1 to force power down RSA memory. This bit has the highest priority. + */ + uint32_t rsa_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} system_rsa_pd_ctrl_reg_t; + +/** Type of external_device_encrypt_decrypt_control register + * SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG + */ +typedef union { + struct { + /** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0; + * Set 1 to enable the SPI manual encrypt. + */ + uint32_t enable_spi_manual_encrypt:1; + /** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0; + * Set 1 to enable download DB encrypt. + */ + uint32_t enable_download_db_encrypt:1; + /** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0; + * Set 1 to enable download G0CB decrypt + */ + uint32_t enable_download_g0cb_decrypt:1; + /** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0; + * Set 1 to enable download manual encrypt + */ + uint32_t enable_download_manual_encrypt:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} system_external_device_encrypt_decrypt_control_reg_t; + + +/** Group: eco register */ +/** Type of redundant_eco_ctrl register + * eco register + */ +typedef union { + struct { + /** redundant_eco_drive : R/W; bitpos: [0]; default: 0; + * reg_redundant_eco_drive + */ + uint32_t redundant_eco_drive:1; + /** redundant_eco_result : RO; bitpos: [1]; default: 0; + * reg_redundant_eco_result + */ + uint32_t redundant_eco_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} system_redundant_eco_ctrl_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} system_clock_gate_reg_t; + + +/** Group: pvt register */ +/** Type of mem_pvt register + * mem pvt register + */ +typedef union { + struct { + /** mem_path_len : R/W; bitpos: [3:0]; default: 3; + * reg_mem_path_len + */ + uint32_t mem_path_len:4; + /** mem_err_cnt_clr : WT; bitpos: [4]; default: 0; + * reg_mem_err_cnt_clr + */ + uint32_t mem_err_cnt_clr:1; + /** mem_pvt_monitor_en : R/W; bitpos: [5]; default: 0; + * reg_mem_pvt_monitor_en + */ + uint32_t mem_pvt_monitor_en:1; + /** mem_timing_err_cnt : RO; bitpos: [21:6]; default: 0; + * reg_mem_timing_err_cnt + */ + uint32_t mem_timing_err_cnt:16; + /** mem_vt_sel : R/W; bitpos: [23:22]; default: 0; + * reg_mem_vt_sel + */ + uint32_t mem_vt_sel:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} system_mem_pvt_reg_t; + +/** Type of comb_pvt_lvt_conf register + * mem pvt register + */ +typedef union { + struct { + /** comb_path_len_lvt : R/W; bitpos: [5:0]; default: 3; + * reg_comb_path_len_lvt + */ + uint32_t comb_path_len_lvt:6; + /** comb_err_cnt_clr_lvt : WT; bitpos: [6]; default: 0; + * reg_comb_err_cnt_clr_lvt + */ + uint32_t comb_err_cnt_clr_lvt:1; + /** comb_pvt_monitor_en_lvt : R/W; bitpos: [7]; default: 0; + * reg_comb_pvt_monitor_en_lvt + */ + uint32_t comb_pvt_monitor_en_lvt:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} system_comb_pvt_lvt_conf_reg_t; + +/** Type of comb_pvt_nvt_conf register + * mem pvt register + */ +typedef union { + struct { + /** comb_path_len_nvt : R/W; bitpos: [5:0]; default: 3; + * reg_comb_path_len_nvt + */ + uint32_t comb_path_len_nvt:6; + /** comb_err_cnt_clr_nvt : WT; bitpos: [6]; default: 0; + * reg_comb_err_cnt_clr_nvt + */ + uint32_t comb_err_cnt_clr_nvt:1; + /** comb_pvt_monitor_en_nvt : R/W; bitpos: [7]; default: 0; + * reg_comb_pvt_monitor_en_nvt + */ + uint32_t comb_pvt_monitor_en_nvt:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} system_comb_pvt_nvt_conf_reg_t; + +/** Type of comb_pvt_hvt_conf register + * mem pvt register + */ +typedef union { + struct { + /** comb_path_len_hvt : R/W; bitpos: [5:0]; default: 3; + * reg_comb_path_len_hvt + */ + uint32_t comb_path_len_hvt:6; + /** comb_err_cnt_clr_hvt : WT; bitpos: [6]; default: 0; + * reg_comb_err_cnt_clr_hvt + */ + uint32_t comb_err_cnt_clr_hvt:1; + /** comb_pvt_monitor_en_hvt : R/W; bitpos: [7]; default: 0; + * reg_comb_pvt_monitor_en_hvt + */ + uint32_t comb_pvt_monitor_en_hvt:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} system_comb_pvt_hvt_conf_reg_t; + +/** Type of comb_pvt_err_lvt_site0 register + * mem pvt register + */ +typedef union { + struct { + /** comb_timing_err_cnt_lvt_site0 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_lvt_site0 + */ + uint32_t comb_timing_err_cnt_lvt_site0:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} system_comb_pvt_err_lvt_site0_reg_t; + +/** Type of comb_pvt_err_nvt_site0 register + * mem pvt register + */ +typedef union { + struct { + /** comb_timing_err_cnt_nvt_site0 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_nvt_site0 + */ + uint32_t comb_timing_err_cnt_nvt_site0:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} system_comb_pvt_err_nvt_site0_reg_t; + +/** Type of comb_pvt_err_hvt_site0 register + * mem pvt register + */ +typedef union { + struct { + /** comb_timing_err_cnt_hvt_site0 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_hvt_site0 + */ + uint32_t comb_timing_err_cnt_hvt_site0:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} system_comb_pvt_err_hvt_site0_reg_t; + +/** Type of comb_pvt_err_lvt_site1 register + * mem pvt register + */ +typedef union { + struct { + /** comb_timing_err_cnt_lvt_site1 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_lvt_site1 + */ + uint32_t comb_timing_err_cnt_lvt_site1:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} system_comb_pvt_err_lvt_site1_reg_t; + +/** Type of comb_pvt_err_nvt_site1 register + * mem pvt register + */ +typedef union { + struct { + /** comb_timing_err_cnt_nvt_site1 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_nvt_site1 + */ + uint32_t comb_timing_err_cnt_nvt_site1:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} system_comb_pvt_err_nvt_site1_reg_t; + +/** Type of comb_pvt_err_hvt_site1 register + * mem pvt register + */ +typedef union { + struct { + /** comb_timing_err_cnt_hvt_site1 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_hvt_site1 + */ + uint32_t comb_timing_err_cnt_hvt_site1:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} system_comb_pvt_err_hvt_site1_reg_t; + +/** Type of comb_pvt_err_lvt_site2 register + * mem pvt register + */ +typedef union { + struct { + /** comb_timing_err_cnt_lvt_site2 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_lvt_site2 + */ + uint32_t comb_timing_err_cnt_lvt_site2:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} system_comb_pvt_err_lvt_site2_reg_t; + +/** Type of comb_pvt_err_nvt_site2 register + * mem pvt register + */ +typedef union { + struct { + /** comb_timing_err_cnt_nvt_site2 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_nvt_site2 + */ + uint32_t comb_timing_err_cnt_nvt_site2:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} system_comb_pvt_err_nvt_site2_reg_t; + +/** Type of comb_pvt_err_hvt_site2 register + * mem pvt register + */ +typedef union { + struct { + /** comb_timing_err_cnt_hvt_site2 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_hvt_site2 + */ + uint32_t comb_timing_err_cnt_hvt_site2:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} system_comb_pvt_err_hvt_site2_reg_t; + +/** Type of comb_pvt_err_lvt_site3 register + * mem pvt register + */ +typedef union { + struct { + /** comb_timing_err_cnt_lvt_site3 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_lvt_site3 + */ + uint32_t comb_timing_err_cnt_lvt_site3:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} system_comb_pvt_err_lvt_site3_reg_t; + +/** Type of comb_pvt_err_nvt_site3 register + * mem pvt register + */ +typedef union { + struct { + /** comb_timing_err_cnt_nvt_site3 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_nvt_site3 + */ + uint32_t comb_timing_err_cnt_nvt_site3:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} system_comb_pvt_err_nvt_site3_reg_t; + +/** Type of comb_pvt_err_hvt_site3 register + * mem pvt register + */ +typedef union { + struct { + /** comb_timing_err_cnt_hvt_site3 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_hvt_site3 + */ + uint32_t comb_timing_err_cnt_hvt_site3:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} system_comb_pvt_err_hvt_site3_reg_t; + + +/** Group: date register */ +/** Type of reg_date register + * Version register + */ +typedef union { + struct { + /** system_reg_date : R/W; bitpos: [27:0]; default: 34636176; + * reg_system_reg_date + */ + uint32_t system_reg_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} system_reg_date_reg_t; + + +typedef struct { + volatile system_cpu_peri_clk_en_reg_t cpu_peri_clk_en; + volatile system_cpu_peri_rst_en_reg_t cpu_peri_rst_en; + volatile system_cpu_per_conf_reg_t cpu_per_conf; + volatile system_mem_pd_mask_reg_t mem_pd_mask; + volatile system_perip_clk_en0_reg_t perip_clk_en0; + volatile system_perip_clk_en1_reg_t perip_clk_en1; + volatile system_perip_rst_en0_reg_t perip_rst_en0; + volatile system_perip_rst_en1_reg_t perip_rst_en1; + volatile system_bt_lpck_div_int_reg_t bt_lpck_div_int; + volatile system_bt_lpck_div_frac_reg_t bt_lpck_div_frac; + volatile system_cpu_intr_from_cpu_0_reg_t cpu_intr_from_cpu_0; + volatile system_cpu_intr_from_cpu_1_reg_t cpu_intr_from_cpu_1; + volatile system_cpu_intr_from_cpu_2_reg_t cpu_intr_from_cpu_2; + volatile system_cpu_intr_from_cpu_3_reg_t cpu_intr_from_cpu_3; + volatile system_rsa_pd_ctrl_reg_t rsa_pd_ctrl; + volatile system_edma_ctrl_reg_t edma_ctrl; + volatile system_cache_control_reg_t cache_control; + volatile system_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control; + volatile system_rtc_fastmem_config_reg_t rtc_fastmem_config; + volatile system_rtc_fastmem_crc_reg_t rtc_fastmem_crc; + volatile system_redundant_eco_ctrl_reg_t redundant_eco_ctrl; + volatile system_clock_gate_reg_t clock_gate; + volatile system_sysclk_conf_reg_t sysclk_conf; + volatile system_mem_pvt_reg_t mem_pvt; + volatile system_comb_pvt_lvt_conf_reg_t comb_pvt_lvt_conf; + volatile system_comb_pvt_nvt_conf_reg_t comb_pvt_nvt_conf; + volatile system_comb_pvt_hvt_conf_reg_t comb_pvt_hvt_conf; + volatile system_comb_pvt_err_lvt_site0_reg_t comb_pvt_err_lvt_site0; + volatile system_comb_pvt_err_nvt_site0_reg_t comb_pvt_err_nvt_site0; + volatile system_comb_pvt_err_hvt_site0_reg_t comb_pvt_err_hvt_site0; + volatile system_comb_pvt_err_lvt_site1_reg_t comb_pvt_err_lvt_site1; + volatile system_comb_pvt_err_nvt_site1_reg_t comb_pvt_err_nvt_site1; + volatile system_comb_pvt_err_hvt_site1_reg_t comb_pvt_err_hvt_site1; + volatile system_comb_pvt_err_lvt_site2_reg_t comb_pvt_err_lvt_site2; + volatile system_comb_pvt_err_nvt_site2_reg_t comb_pvt_err_nvt_site2; + volatile system_comb_pvt_err_hvt_site2_reg_t comb_pvt_err_hvt_site2; + volatile system_comb_pvt_err_lvt_site3_reg_t comb_pvt_err_lvt_site3; + volatile system_comb_pvt_err_nvt_site3_reg_t comb_pvt_err_nvt_site3; + volatile system_comb_pvt_err_hvt_site3_reg_t comb_pvt_err_hvt_site3; + uint32_t reserved_09c[984]; + volatile system_reg_date_reg_t reg_date; } system_dev_t; -extern system_dev_t SYSTEM; + + +#ifndef __cplusplus +_Static_assert(sizeof(system_dev_t) == 0x1000, "Invalid size of system_dev_t structure"); +#endif + #ifdef __cplusplus } #endif - - - -#endif /*_SOC_SYSTEM_STRUCT_H_ */ diff --git a/components/soc/esp8684/include/soc/systimer_reg.h b/components/soc/esp8684/include/soc/systimer_reg.h index 2def2c456c..34cf8e5377 100644 --- a/components/soc/esp8684/include/soc/systimer_reg.h +++ b/components/soc/esp8684/include/soc/systimer_reg.h @@ -1,10 +1,8 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_SYSTIMER_REG_H_ -#define _SOC_SYSTIMER_REG_H_ #pragma once #include @@ -13,403 +11,548 @@ extern "C" { #endif -#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0) -/* SYSTIMER_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: register file clk gating.*/ -#define SYSTIMER_CLK_EN (BIT(31)) -#define SYSTIMER_CLK_EN_M (BIT(31)) -#define SYSTIMER_CLK_EN_V 0x1 -#define SYSTIMER_CLK_EN_S 31 -/* SYSTIMER_UNIT0_WORK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: timer unit0 work enable.*/ -#define SYSTIMER_UNIT0_WORK_EN (BIT(30)) -#define SYSTIMER_UNIT0_WORK_EN_M (BIT(30)) -#define SYSTIMER_UNIT0_WORK_EN_V 0x1 -#define SYSTIMER_UNIT0_WORK_EN_S 30 -/* SYSTIMER_UNIT1_WORK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: timer unit1 work enable.*/ -#define SYSTIMER_UNIT1_WORK_EN (BIT(29)) -#define SYSTIMER_UNIT1_WORK_EN_M (BIT(29)) -#define SYSTIMER_UNIT1_WORK_EN_V 0x1 -#define SYSTIMER_UNIT1_WORK_EN_S 29 -/* SYSTIMER_UNIT0_CORE0_STALL_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: If timer unit0 is stalled when core0 stalled.*/ -#define SYSTIMER_UNIT0_CORE0_STALL_EN (BIT(28)) -#define SYSTIMER_UNIT0_CORE0_STALL_EN_M (BIT(28)) -#define SYSTIMER_UNIT0_CORE0_STALL_EN_V 0x1 -#define SYSTIMER_UNIT0_CORE0_STALL_EN_S 28 -/* SYSTIMER_UNIT0_CORE1_STALL_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: If timer unit0 is stalled when core1 stalled.*/ -#define SYSTIMER_UNIT0_CORE1_STALL_EN (BIT(27)) -#define SYSTIMER_UNIT0_CORE1_STALL_EN_M (BIT(27)) -#define SYSTIMER_UNIT0_CORE1_STALL_EN_V 0x1 -#define SYSTIMER_UNIT0_CORE1_STALL_EN_S 27 -/* SYSTIMER_UNIT1_CORE0_STALL_EN : R/W ;bitpos:[26] ;default: 1'b1 ; */ -/*description: If timer unit1 is stalled when core0 stalled.*/ -#define SYSTIMER_UNIT1_CORE0_STALL_EN (BIT(26)) -#define SYSTIMER_UNIT1_CORE0_STALL_EN_M (BIT(26)) -#define SYSTIMER_UNIT1_CORE0_STALL_EN_V 0x1 -#define SYSTIMER_UNIT1_CORE0_STALL_EN_S 26 -/* SYSTIMER_UNIT1_CORE1_STALL_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */ -/*description: If timer unit1 is stalled when core1 stalled.*/ -#define SYSTIMER_UNIT1_CORE1_STALL_EN (BIT(25)) -#define SYSTIMER_UNIT1_CORE1_STALL_EN_M (BIT(25)) -#define SYSTIMER_UNIT1_CORE1_STALL_EN_V 0x1 -#define SYSTIMER_UNIT1_CORE1_STALL_EN_S 25 -/* SYSTIMER_TARGET0_WORK_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: target0 work enable.*/ -#define SYSTIMER_TARGET0_WORK_EN (BIT(24)) -#define SYSTIMER_TARGET0_WORK_EN_M (BIT(24)) -#define SYSTIMER_TARGET0_WORK_EN_V 0x1 -#define SYSTIMER_TARGET0_WORK_EN_S 24 -/* SYSTIMER_TARGET1_WORK_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: target1 work enable.*/ -#define SYSTIMER_TARGET1_WORK_EN (BIT(23)) -#define SYSTIMER_TARGET1_WORK_EN_M (BIT(23)) -#define SYSTIMER_TARGET1_WORK_EN_V 0x1 -#define SYSTIMER_TARGET1_WORK_EN_S 23 -/* SYSTIMER_TARGET2_WORK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: target2 work enable.*/ -#define SYSTIMER_TARGET2_WORK_EN (BIT(22)) -#define SYSTIMER_TARGET2_WORK_EN_M (BIT(22)) -#define SYSTIMER_TARGET2_WORK_EN_V 0x1 -#define SYSTIMER_TARGET2_WORK_EN_S 22 -/* SYSTIMER_SYSTIMER_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: systimer clock force on.*/ +/** SYSTIMER_CONF_REG register + * Configure system timer clock + */ +#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0) +/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0; + * systimer clock force on + */ #define SYSTIMER_SYSTIMER_CLK_FO (BIT(0)) -#define SYSTIMER_SYSTIMER_CLK_FO_M (BIT(0)) -#define SYSTIMER_SYSTIMER_CLK_FO_V 0x1 +#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S) +#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001U #define SYSTIMER_SYSTIMER_CLK_FO_S 0 +/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ +#define SYSTIMER_TARGET2_WORK_EN (BIT(22)) +#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S) +#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET2_WORK_EN_S 22 +/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ +#define SYSTIMER_TARGET1_WORK_EN (BIT(23)) +#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S) +#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET1_WORK_EN_S 23 +/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ +#define SYSTIMER_TARGET0_WORK_EN (BIT(24)) +#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S) +#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET0_WORK_EN_S 24 +/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 +/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 +/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 +/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 +/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ +#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29 +/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ +#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30 +/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ +#define SYSTIMER_CLK_EN (BIT(31)) +#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S) +#define SYSTIMER_CLK_EN_V 0x00000001U +#define SYSTIMER_CLK_EN_S 31 -#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4) -/* SYSTIMER_UNIT0_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */ -/*description: update timer_unit0.*/ -#define SYSTIMER_UNIT0_UPDATE (BIT(30)) -#define SYSTIMER_UNIT0_UPDATE_M (BIT(30)) -#define SYSTIMER_UNIT0_UPDATE_V 0x1 -#define SYSTIMER_UNIT0_UPDATE_S 30 -/* SYSTIMER_UNIT0_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ -/*description: timer value is sync and valid.*/ -#define SYSTIMER_UNIT0_VALUE_VALID (BIT(29)) -#define SYSTIMER_UNIT0_VALUE_VALID_M (BIT(29)) -#define SYSTIMER_UNIT0_VALUE_VALID_V 0x1 -#define SYSTIMER_UNIT0_VALUE_VALID_S 29 +/** SYSTIMER_UNIT0_OP_REG register + * system timer unit0 value update register + */ +#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4) +/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ +#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S) +#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30 -#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8) -/* SYSTIMER_UNIT1_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */ -/*description: update timer unit1.*/ -#define SYSTIMER_UNIT1_UPDATE (BIT(30)) -#define SYSTIMER_UNIT1_UPDATE_M (BIT(30)) -#define SYSTIMER_UNIT1_UPDATE_V 0x1 -#define SYSTIMER_UNIT1_UPDATE_S 30 -/* SYSTIMER_UNIT1_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ -/*description: timer value is sync and valid.*/ -#define SYSTIMER_UNIT1_VALUE_VALID (BIT(29)) -#define SYSTIMER_UNIT1_VALUE_VALID_M (BIT(29)) -#define SYSTIMER_UNIT1_VALUE_VALID_V 0x1 -#define SYSTIMER_UNIT1_VALUE_VALID_S 29 +/** SYSTIMER_UNIT1_OP_REG register + * system timer unit1 value update register + */ +#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8) +/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0; + * update timer unit1 + */ +#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S) +#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30 -#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xC) -/* SYSTIMER_UNIT0_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer unit0 load high 20 bits.*/ -#define SYSTIMER_UNIT0_LOAD_HI 0x000FFFFF -#define SYSTIMER_UNIT0_LOAD_HI_M ((SYSTIMER_UNIT0_LOAD_HI_V)<<(SYSTIMER_UNIT0_LOAD_HI_S)) -#define SYSTIMER_UNIT0_LOAD_HI_V 0xFFFFF -#define SYSTIMER_UNIT0_LOAD_HI_S 0 +/** SYSTIMER_UNIT0_LOAD_HI_REG register + * system timer unit0 value high load register + */ +#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc) +/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit0 load high 20 bits + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0 -#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10) -/* SYSTIMER_UNIT0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer unit0 load low 32 bits.*/ -#define SYSTIMER_UNIT0_LOAD_LO 0xFFFFFFFF -#define SYSTIMER_UNIT0_LOAD_LO_M ((SYSTIMER_UNIT0_LOAD_LO_V)<<(SYSTIMER_UNIT0_LOAD_LO_S)) -#define SYSTIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF -#define SYSTIMER_UNIT0_LOAD_LO_S 0 +/** SYSTIMER_UNIT0_LOAD_LO_REG register + * system timer unit0 value low load register + */ +#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10) +/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit0 load low 32 bits + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0 -#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14) -/* SYSTIMER_UNIT1_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer unit1 load high 20 bits.*/ -#define SYSTIMER_UNIT1_LOAD_HI 0x000FFFFF -#define SYSTIMER_UNIT1_LOAD_HI_M ((SYSTIMER_UNIT1_LOAD_HI_V)<<(SYSTIMER_UNIT1_LOAD_HI_S)) -#define SYSTIMER_UNIT1_LOAD_HI_V 0xFFFFF -#define SYSTIMER_UNIT1_LOAD_HI_S 0 +/** SYSTIMER_UNIT1_LOAD_HI_REG register + * system timer unit1 value high load register + */ +#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14) +/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit1 load high 20 bits + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0 -#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18) -/* SYSTIMER_UNIT1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer unit1 load low 32 bits.*/ -#define SYSTIMER_UNIT1_LOAD_LO 0xFFFFFFFF -#define SYSTIMER_UNIT1_LOAD_LO_M ((SYSTIMER_UNIT1_LOAD_LO_V)<<(SYSTIMER_UNIT1_LOAD_LO_S)) -#define SYSTIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF -#define SYSTIMER_UNIT1_LOAD_LO_S 0 +/** SYSTIMER_UNIT1_LOAD_LO_REG register + * system timer unit1 value low load register + */ +#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18) +/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit1 load low 32 bits + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0 -#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1C) -/* SYSTIMER_TARGET0_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer taget0 high 20 bits.*/ -#define SYSTIMER_TARGET0_HI 0x000FFFFF -#define SYSTIMER_TARGET0_HI_M ((SYSTIMER_TARGET0_HI_V)<<(SYSTIMER_TARGET0_HI_S)) -#define SYSTIMER_TARGET0_HI_V 0xFFFFF -#define SYSTIMER_TARGET0_HI_S 0 +/** SYSTIMER_TARGET0_HI_REG register + * system timer comp0 value high register + */ +#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c) +/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget0 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S) +#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET0_HI_S 0 -#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20) -/* SYSTIMER_TARGET0_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer taget0 low 32 bits.*/ -#define SYSTIMER_TARGET0_LO 0xFFFFFFFF -#define SYSTIMER_TARGET0_LO_M ((SYSTIMER_TARGET0_LO_V)<<(SYSTIMER_TARGET0_LO_S)) -#define SYSTIMER_TARGET0_LO_V 0xFFFFFFFF -#define SYSTIMER_TARGET0_LO_S 0 +/** SYSTIMER_TARGET0_LO_REG register + * system timer comp0 value low register + */ +#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20) +/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget0 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S) +#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET0_LO_S 0 -#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24) -/* SYSTIMER_TARGET1_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer taget1 high 20 bits.*/ -#define SYSTIMER_TARGET1_HI 0x000FFFFF -#define SYSTIMER_TARGET1_HI_M ((SYSTIMER_TARGET1_HI_V)<<(SYSTIMER_TARGET1_HI_S)) -#define SYSTIMER_TARGET1_HI_V 0xFFFFF -#define SYSTIMER_TARGET1_HI_S 0 +/** SYSTIMER_TARGET1_HI_REG register + * system timer comp1 value high register + */ +#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24) +/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget1 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S) +#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET1_HI_S 0 -#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28) -/* SYSTIMER_TARGET1_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer taget1 low 32 bits.*/ -#define SYSTIMER_TARGET1_LO 0xFFFFFFFF -#define SYSTIMER_TARGET1_LO_M ((SYSTIMER_TARGET1_LO_V)<<(SYSTIMER_TARGET1_LO_S)) -#define SYSTIMER_TARGET1_LO_V 0xFFFFFFFF -#define SYSTIMER_TARGET1_LO_S 0 +/** SYSTIMER_TARGET1_LO_REG register + * system timer comp1 value low register + */ +#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28) +/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget1 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S) +#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET1_LO_S 0 -#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2C) -/* SYSTIMER_TARGET2_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer taget2 high 20 bits.*/ -#define SYSTIMER_TARGET2_HI 0x000FFFFF -#define SYSTIMER_TARGET2_HI_M ((SYSTIMER_TARGET2_HI_V)<<(SYSTIMER_TARGET2_HI_S)) -#define SYSTIMER_TARGET2_HI_V 0xFFFFF -#define SYSTIMER_TARGET2_HI_S 0 +/** SYSTIMER_TARGET2_HI_REG register + * system timer comp2 value high register + */ +#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c) +/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget2 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S) +#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET2_HI_S 0 -#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30) -/* SYSTIMER_TARGET2_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer taget2 low 32 bits.*/ -#define SYSTIMER_TARGET2_LO 0xFFFFFFFF -#define SYSTIMER_TARGET2_LO_M ((SYSTIMER_TARGET2_LO_V)<<(SYSTIMER_TARGET2_LO_S)) -#define SYSTIMER_TARGET2_LO_V 0xFFFFFFFF -#define SYSTIMER_TARGET2_LO_S 0 +/** SYSTIMER_TARGET2_LO_REG register + * system timer comp2 value low register + */ +#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30) +/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget2 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S) +#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET2_LO_S 0 -#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34) -/* SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: select which unit to compare.*/ -#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) -#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (BIT(31)) -#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x1 -#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31 -/* SYSTIMER_TARGET0_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set target0 to period mode.*/ -#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30)) -#define SYSTIMER_TARGET0_PERIOD_MODE_M (BIT(30)) -#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x1 -#define SYSTIMER_TARGET0_PERIOD_MODE_S 30 -/* SYSTIMER_TARGET0_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: target0 period.*/ -#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFF -#define SYSTIMER_TARGET0_PERIOD_M ((SYSTIMER_TARGET0_PERIOD_V)<<(SYSTIMER_TARGET0_PERIOD_S)) -#define SYSTIMER_TARGET0_PERIOD_V 0x3FFFFFF +/** SYSTIMER_TARGET0_CONF_REG register + * system timer comp0 target mode register + */ +#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34) +/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target0 period + */ +#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S) +#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFFU #define SYSTIMER_TARGET0_PERIOD_S 0 +/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target0 to period mode + */ +#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S) +#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET0_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31 -#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38) -/* SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: select which unit to compare.*/ -#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) -#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (BIT(31)) -#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x1 -#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31 -/* SYSTIMER_TARGET1_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set target1 to period mode.*/ -#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30)) -#define SYSTIMER_TARGET1_PERIOD_MODE_M (BIT(30)) -#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x1 -#define SYSTIMER_TARGET1_PERIOD_MODE_S 30 -/* SYSTIMER_TARGET1_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: target1 period.*/ -#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFF -#define SYSTIMER_TARGET1_PERIOD_M ((SYSTIMER_TARGET1_PERIOD_V)<<(SYSTIMER_TARGET1_PERIOD_S)) -#define SYSTIMER_TARGET1_PERIOD_V 0x3FFFFFF +/** SYSTIMER_TARGET1_CONF_REG register + * system timer comp1 target mode register + */ +#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38) +/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target1 period + */ +#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S) +#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFFU #define SYSTIMER_TARGET1_PERIOD_S 0 +/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target1 to period mode + */ +#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S) +#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET1_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31 -#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3C) -/* SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: select which unit to compare.*/ -#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) -#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (BIT(31)) -#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x1 -#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31 -/* SYSTIMER_TARGET2_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set target2 to period mode.*/ -#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30)) -#define SYSTIMER_TARGET2_PERIOD_MODE_M (BIT(30)) -#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x1 -#define SYSTIMER_TARGET2_PERIOD_MODE_S 30 -/* SYSTIMER_TARGET2_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: target2 period.*/ -#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFF -#define SYSTIMER_TARGET2_PERIOD_M ((SYSTIMER_TARGET2_PERIOD_V)<<(SYSTIMER_TARGET2_PERIOD_S)) -#define SYSTIMER_TARGET2_PERIOD_V 0x3FFFFFF +/** SYSTIMER_TARGET2_CONF_REG register + * system timer comp2 target mode register + */ +#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c) +/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target2 period + */ +#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S) +#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFFU #define SYSTIMER_TARGET2_PERIOD_S 0 +/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target2 to period mode + */ +#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S) +#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET2_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31 -#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40) -/* SYSTIMER_UNIT0_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer read value high 20bits.*/ -#define SYSTIMER_UNIT0_VALUE_HI 0x000FFFFF -#define SYSTIMER_UNIT0_VALUE_HI_M ((SYSTIMER_UNIT0_VALUE_HI_V)<<(SYSTIMER_UNIT0_VALUE_HI_S)) -#define SYSTIMER_UNIT0_VALUE_HI_V 0xFFFFF -#define SYSTIMER_UNIT0_VALUE_HI_S 0 +/** SYSTIMER_UNIT0_VALUE_HI_REG register + * system timer unit0 value high register + */ +#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40) +/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0 -#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44) -/* SYSTIMER_UNIT0_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer read value low 32bits.*/ -#define SYSTIMER_UNIT0_VALUE_LO 0xFFFFFFFF -#define SYSTIMER_UNIT0_VALUE_LO_M ((SYSTIMER_UNIT0_VALUE_LO_V)<<(SYSTIMER_UNIT0_VALUE_LO_S)) -#define SYSTIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF -#define SYSTIMER_UNIT0_VALUE_LO_S 0 +/** SYSTIMER_UNIT0_VALUE_LO_REG register + * system timer unit0 value low register + */ +#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44) +/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0 -#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48) -/* SYSTIMER_UNIT1_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer read value high 20bits.*/ -#define SYSTIMER_UNIT1_VALUE_HI 0x000FFFFF -#define SYSTIMER_UNIT1_VALUE_HI_M ((SYSTIMER_UNIT1_VALUE_HI_V)<<(SYSTIMER_UNIT1_VALUE_HI_S)) -#define SYSTIMER_UNIT1_VALUE_HI_V 0xFFFFF -#define SYSTIMER_UNIT1_VALUE_HI_S 0 +/** SYSTIMER_UNIT1_VALUE_HI_REG register + * system timer unit1 value high register + */ +#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48) +/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0 -#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4C) -/* SYSTIMER_UNIT1_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer read value low 32bits.*/ -#define SYSTIMER_UNIT1_VALUE_LO 0xFFFFFFFF -#define SYSTIMER_UNIT1_VALUE_LO_M ((SYSTIMER_UNIT1_VALUE_LO_V)<<(SYSTIMER_UNIT1_VALUE_LO_S)) -#define SYSTIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF -#define SYSTIMER_UNIT1_VALUE_LO_S 0 +/** SYSTIMER_UNIT1_VALUE_LO_REG register + * system timer unit1 value low register + */ +#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c) +/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0 -#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50) -/* SYSTIMER_COMP0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer comp0 sync enable signal.*/ -#define SYSTIMER_COMP0_LOAD (BIT(0)) -#define SYSTIMER_COMP0_LOAD_M (BIT(0)) -#define SYSTIMER_COMP0_LOAD_V 0x1 -#define SYSTIMER_COMP0_LOAD_S 0 +/** SYSTIMER_COMP0_LOAD_REG register + * system timer comp0 conf sync register + */ +#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50) +/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0; + * timer comp0 sync enable signal + */ +#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S) +#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP0_LOAD_S 0 -#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54) -/* SYSTIMER_COMP1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer comp1 sync enable signal.*/ -#define SYSTIMER_COMP1_LOAD (BIT(0)) -#define SYSTIMER_COMP1_LOAD_M (BIT(0)) -#define SYSTIMER_COMP1_LOAD_V 0x1 -#define SYSTIMER_COMP1_LOAD_S 0 +/** SYSTIMER_COMP1_LOAD_REG register + * system timer comp1 conf sync register + */ +#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54) +/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0; + * timer comp1 sync enable signal + */ +#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S) +#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP1_LOAD_S 0 -#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58) -/* SYSTIMER_COMP2_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer comp2 sync enable signal.*/ -#define SYSTIMER_COMP2_LOAD (BIT(0)) -#define SYSTIMER_COMP2_LOAD_M (BIT(0)) -#define SYSTIMER_COMP2_LOAD_V 0x1 -#define SYSTIMER_COMP2_LOAD_S 0 +/** SYSTIMER_COMP2_LOAD_REG register + * system timer comp2 conf sync register + */ +#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58) +/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0; + * timer comp2 sync enable signal + */ +#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S) +#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP2_LOAD_S 0 -#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5C) -/* SYSTIMER_UNIT0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer unit0 sync enable signal.*/ -#define SYSTIMER_UNIT0_LOAD (BIT(0)) -#define SYSTIMER_UNIT0_LOAD_M (BIT(0)) -#define SYSTIMER_UNIT0_LOAD_V 0x1 -#define SYSTIMER_UNIT0_LOAD_S 0 +/** SYSTIMER_UNIT0_LOAD_REG register + * system timer unit0 conf sync register + */ +#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c) +/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0; + * timer unit0 sync enable signal + */ +#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_LOAD_S 0 -#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60) -/* SYSTIMER_UNIT1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer unit1 sync enable signal.*/ -#define SYSTIMER_UNIT1_LOAD (BIT(0)) -#define SYSTIMER_UNIT1_LOAD_M (BIT(0)) -#define SYSTIMER_UNIT1_LOAD_V 0x1 -#define SYSTIMER_UNIT1_LOAD_S 0 +/** SYSTIMER_UNIT1_LOAD_REG register + * system timer unit1 conf sync register + */ +#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60) +/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0; + * timer unit1 sync enable signal + */ +#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_LOAD_S 0 -#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64) -/* SYSTIMER_TARGET2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: interupt2 enable.*/ -#define SYSTIMER_TARGET2_INT_ENA (BIT(2)) -#define SYSTIMER_TARGET2_INT_ENA_M (BIT(2)) -#define SYSTIMER_TARGET2_INT_ENA_V 0x1 -#define SYSTIMER_TARGET2_INT_ENA_S 2 -/* SYSTIMER_TARGET1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: interupt1 enable.*/ -#define SYSTIMER_TARGET1_INT_ENA (BIT(1)) -#define SYSTIMER_TARGET1_INT_ENA_M (BIT(1)) -#define SYSTIMER_TARGET1_INT_ENA_V 0x1 -#define SYSTIMER_TARGET1_INT_ENA_S 1 -/* SYSTIMER_TARGET0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: interupt0 enable.*/ +/** SYSTIMER_INT_ENA_REG register + * systimer interrupt enable register + */ +#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64) +/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ #define SYSTIMER_TARGET0_INT_ENA (BIT(0)) -#define SYSTIMER_TARGET0_INT_ENA_M (BIT(0)) -#define SYSTIMER_TARGET0_INT_ENA_V 0x1 +#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S) +#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001U #define SYSTIMER_TARGET0_INT_ENA_S 0 +/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ +#define SYSTIMER_TARGET1_INT_ENA (BIT(1)) +#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S) +#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET1_INT_ENA_S 1 +/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ +#define SYSTIMER_TARGET2_INT_ENA (BIT(2)) +#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S) +#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET2_INT_ENA_S 2 -#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68) -/* SYSTIMER_TARGET2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: interupt2 raw.*/ -#define SYSTIMER_TARGET2_INT_RAW (BIT(2)) -#define SYSTIMER_TARGET2_INT_RAW_M (BIT(2)) -#define SYSTIMER_TARGET2_INT_RAW_V 0x1 -#define SYSTIMER_TARGET2_INT_RAW_S 2 -/* SYSTIMER_TARGET1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: interupt1 raw.*/ -#define SYSTIMER_TARGET1_INT_RAW (BIT(1)) -#define SYSTIMER_TARGET1_INT_RAW_M (BIT(1)) -#define SYSTIMER_TARGET1_INT_RAW_V 0x1 -#define SYSTIMER_TARGET1_INT_RAW_S 1 -/* SYSTIMER_TARGET0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: interupt0 raw.*/ +/** SYSTIMER_INT_RAW_REG register + * systimer interrupt raw register + */ +#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68) +/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ #define SYSTIMER_TARGET0_INT_RAW (BIT(0)) -#define SYSTIMER_TARGET0_INT_RAW_M (BIT(0)) -#define SYSTIMER_TARGET0_INT_RAW_V 0x1 +#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S) +#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001U #define SYSTIMER_TARGET0_INT_RAW_S 0 +/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ +#define SYSTIMER_TARGET1_INT_RAW (BIT(1)) +#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S) +#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET1_INT_RAW_S 1 +/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ +#define SYSTIMER_TARGET2_INT_RAW (BIT(2)) +#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S) +#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET2_INT_RAW_S 2 -#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6C) -/* SYSTIMER_TARGET2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: interupt2 clear.*/ -#define SYSTIMER_TARGET2_INT_CLR (BIT(2)) -#define SYSTIMER_TARGET2_INT_CLR_M (BIT(2)) -#define SYSTIMER_TARGET2_INT_CLR_V 0x1 -#define SYSTIMER_TARGET2_INT_CLR_S 2 -/* SYSTIMER_TARGET1_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: interupt1 clear.*/ -#define SYSTIMER_TARGET1_INT_CLR (BIT(1)) -#define SYSTIMER_TARGET1_INT_CLR_M (BIT(1)) -#define SYSTIMER_TARGET1_INT_CLR_V 0x1 -#define SYSTIMER_TARGET1_INT_CLR_S 1 -/* SYSTIMER_TARGET0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: interupt0 clear.*/ +/** SYSTIMER_INT_CLR_REG register + * systimer interrupt clear register + */ +#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c) +/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ #define SYSTIMER_TARGET0_INT_CLR (BIT(0)) -#define SYSTIMER_TARGET0_INT_CLR_M (BIT(0)) -#define SYSTIMER_TARGET0_INT_CLR_V 0x1 +#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S) +#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001U #define SYSTIMER_TARGET0_INT_CLR_S 0 +/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ +#define SYSTIMER_TARGET1_INT_CLR (BIT(1)) +#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S) +#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET1_INT_CLR_S 1 +/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ +#define SYSTIMER_TARGET2_INT_CLR (BIT(2)) +#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S) +#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET2_INT_CLR_S 2 -#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70) -/* SYSTIMER_TARGET2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: interupt2 status.*/ -#define SYSTIMER_TARGET2_INT_ST (BIT(2)) -#define SYSTIMER_TARGET2_INT_ST_M (BIT(2)) -#define SYSTIMER_TARGET2_INT_ST_V 0x1 -#define SYSTIMER_TARGET2_INT_ST_S 2 -/* SYSTIMER_TARGET1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: interupt1 status.*/ -#define SYSTIMER_TARGET1_INT_ST (BIT(1)) -#define SYSTIMER_TARGET1_INT_ST_M (BIT(1)) -#define SYSTIMER_TARGET1_INT_ST_V 0x1 -#define SYSTIMER_TARGET1_INT_ST_S 1 -/* SYSTIMER_TARGET0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: interupt0 status.*/ +/** SYSTIMER_INT_ST_REG register + * systimer interrupt status register + */ +#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70) +/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0; + * interupt0 status + */ #define SYSTIMER_TARGET0_INT_ST (BIT(0)) -#define SYSTIMER_TARGET0_INT_ST_M (BIT(0)) -#define SYSTIMER_TARGET0_INT_ST_V 0x1 +#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S) +#define SYSTIMER_TARGET0_INT_ST_V 0x00000001U #define SYSTIMER_TARGET0_INT_ST_S 0 +/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0; + * interupt1 status + */ +#define SYSTIMER_TARGET1_INT_ST (BIT(1)) +#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S) +#define SYSTIMER_TARGET1_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET1_INT_ST_S 1 +/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0; + * interupt2 status + */ +#define SYSTIMER_TARGET2_INT_ST (BIT(2)) +#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S) +#define SYSTIMER_TARGET2_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET2_INT_ST_S 2 -#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xFC) -/* SYSTIMER_DATE : R/W ;bitpos:[31:0] ;default: 28'h2012251 ; */ -/*description: systimer register version.*/ -#define SYSTIMER_DATE 0xFFFFFFFF -#define SYSTIMER_DATE_M ((SYSTIMER_DATE_V)<<(SYSTIMER_DATE_S)) -#define SYSTIMER_DATE_V 0xFFFFFFFF +/** SYSTIMER_DATE_REG register + * system timer version control register + */ +#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc) +/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33628753; + * systimer register version + */ +#define SYSTIMER_DATE 0xFFFFFFFFU +#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S) +#define SYSTIMER_DATE_V 0xFFFFFFFFU #define SYSTIMER_DATE_S 0 - #ifdef __cplusplus } #endif diff --git a/components/soc/esp8684/ld/esp8684.peripherals.ld b/components/soc/esp8684/ld/esp8684.peripherals.ld index 32d2b070cc..1263ad0a7c 100644 --- a/components/soc/esp8684/ld/esp8684.peripherals.ld +++ b/components/soc/esp8684/ld/esp8684.peripherals.ld @@ -14,8 +14,6 @@ PROVIDE ( RTCIO = 0x60008400 ); PROVIDE ( HINF = 0x6000B000 ); PROVIDE ( I2C0 = 0x60013000 ); PROVIDE ( HOST = 0x60015000 ); -PROVIDE ( RMT = 0x60016000 ); -PROVIDE ( RMTMEM = 0x60016400 ); PROVIDE ( PCNT = 0x60017000 ); PROVIDE ( SLC = 0x60018000 ); PROVIDE ( LEDC = 0x60019000 ); diff --git a/components/soc/esp8684/rmt_periph.c b/components/soc/esp8684/rmt_periph.c deleted file mode 100644 index b2005ea67e..0000000000 --- a/components/soc/esp8684/rmt_periph.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "soc/rmt_periph.h" -#include "soc/gpio_sig_map.h" - -const rmt_signal_conn_t rmt_periph_signals = { - .groups = { - [0] = { - .module = PERIPH_RMT_MODULE, - .irq = ETS_RMT_INTR_SOURCE, - .channels = { - [0] = { - .tx_sig = RMT_SIG_OUT0_IDX, - .rx_sig = -1 - }, - [1] = { - .tx_sig = RMT_SIG_OUT1_IDX, - .rx_sig = -1 - }, - [2] = { - .tx_sig = -1, - .rx_sig = RMT_SIG_IN0_IDX - }, - [3] = { - .tx_sig = -1, - .rx_sig = RMT_SIG_IN1_IDX - }, - } - } - } -}; diff --git a/components/soc/include/soc/soc_memory_types.h b/components/soc/include/soc/soc_memory_types.h index 88bd95a72d..11da1ba3ab 100644 --- a/components/soc/include/soc/soc_memory_types.h +++ b/components/soc/include/soc/soc_memory_types.h @@ -123,22 +123,29 @@ inline static bool IRAM_ATTR esp_ptr_in_diram_iram(const void *p) { return ((intptr_t)p >= SOC_DIRAM_IRAM_LOW && (intptr_t)p < SOC_DIRAM_IRAM_HIGH); } -#if SOC_RTC_FAST_MEM_SUPPORTED inline static bool IRAM_ATTR esp_ptr_in_rtc_iram_fast(const void *p) { +#if SOC_RTC_FAST_MEM_SUPPORTED return ((intptr_t)p >= SOC_RTC_IRAM_LOW && (intptr_t)p < SOC_RTC_IRAM_HIGH); +#else + return false; +#endif } - inline static bool IRAM_ATTR esp_ptr_in_rtc_dram_fast(const void *p) { +#if SOC_RTC_FAST_MEM_SUPPORTED return ((intptr_t)p >= SOC_RTC_DRAM_LOW && (intptr_t)p < SOC_RTC_DRAM_HIGH); -} +#else + return false; #endif +} -#if !CONFIG_IDF_TARGET_ESP8684 -// IDF-3901 inline static bool IRAM_ATTR esp_ptr_in_rtc_slow(const void *p) { +#if SOC_RTC_SLOW_MEM_SUPPORTED return ((intptr_t)p >= SOC_RTC_DATA_LOW && (intptr_t)p < SOC_RTC_DATA_HIGH); -} +#else + return false; #endif +} + /* Convert a D/IRAM DRAM pointer to equivalent word address in IRAM diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index b76b1db1ea..dde3168451 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -1750,7 +1750,6 @@ components/soc/esp32c3/include/soc/rtc_i2c_reg.h components/soc/esp32c3/include/soc/rtc_i2c_struct.h components/soc/esp32c3/include/soc/sensitive_reg.h components/soc/esp32c3/include/soc/sensitive_struct.h -components/soc/esp32c3/include/soc/soc.h components/soc/esp32c3/include/soc/soc_caps.h components/soc/esp32c3/include/soc/soc_pins.h components/soc/esp32c3/include/soc/spi_mem_reg.h