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Merge branch 'feature/add_rom_reset_api' into 'master'

Browse Source 
esp_rom: add rom reset api to IDF

See merge request espressif/esp-idf!19824
This commit is contained in:
morris 2022-08-31 12:29:32 +08:00
commit daea081d54
19 changed files with 120 additions and 34 deletions
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2
components/bootloader_support/src/bootloader_utility.c
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@ -864,7 +864,7 @@ void bootloader_reset(void)
#ifdef BOOTLOADER_BUILD
bootloader_atexit();
esp_rom_delay_us(1000); /* Allow last byte to leave FIFO */
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
esp_rom_software_reset_system();
while (1) { } /* This line will never be reached, used to keep gcc happy */
#else
abort(); /* This function should really not be called from application code */

7
components/esp_hw_support/include/esp_fault.h
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@ -4,7 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "soc/rtc_cntl_reg.h"
#include "esp_rom_sys.h"
#pragma once
@ -70,9 +69,9 @@ extern "C" {
*/
#ifndef ESP_FAULT_ASSERT_DEBUG
#define _ESP_FAULT_RESET() do { \
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); \
_ESP_FAULT_ILLEGAL_INSTRUCTION; \
#define _ESP_FAULT_RESET() do { \
esp_rom_software_reset_system(); \
_ESP_FAULT_ILLEGAL_INSTRUCTION; \
} while(0)
#else // ESP_FAULT_ASSERT_DEBUG

3
components/esp_rom/esp32/ld/esp32.rom.api.ld
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@ -33,6 +33,9 @@ PROVIDE ( esp_rom_md5_init = 0x4005da7c );
PROVIDE ( esp_rom_md5_update = 0x4005da9c );
PROVIDE ( esp_rom_md5_final = 0x4005db1c );
PROVIDE ( esp_rom_software_reset_system = software_reset );
PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );

3
components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld
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@ -34,6 +34,9 @@ PROVIDE ( esp_rom_mbedtls_md5_starts_ret = mbedtls_md5_starts_ret );
PROVIDE ( esp_rom_mbedtls_md5_update_ret = mbedtls_md5_update_ret );
PROVIDE ( esp_rom_mbedtls_md5_finish_ret = mbedtls_md5_finish_ret );
PROVIDE ( esp_rom_software_reset_system = software_reset );
PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );

3
components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld
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@ -32,6 +32,9 @@ PROVIDE ( esp_rom_md5_init = MD5Init );
PROVIDE ( esp_rom_md5_update = MD5Update );
PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_software_reset_system = software_reset );
PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );

3
components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld
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@ -34,6 +34,9 @@ PROVIDE ( esp_rom_md5_init = MD5Init );
PROVIDE ( esp_rom_md5_update = MD5Update );
PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_software_reset_system = software_reset );
PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );

3
components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld
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@ -37,6 +37,9 @@ PROVIDE ( esp_rom_md5_init = MD5Init );
PROVIDE ( esp_rom_md5_update = MD5Update );
PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_software_reset_system = software_reset );
PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );

3
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld
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@ -37,6 +37,9 @@ PROVIDE ( esp_rom_md5_init = MD5Init );
PROVIDE ( esp_rom_md5_update = MD5Update );
PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_software_reset_system = software_reset );
PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );

3
components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld
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@ -34,6 +34,9 @@ PROVIDE ( esp_rom_md5_init = 0x4000526c );
PROVIDE ( esp_rom_md5_update = 0x4000528c );
PROVIDE ( esp_rom_md5_final = 0x4000530c );
PROVIDE ( esp_rom_software_reset_system = software_reset );
PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );

3
components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld
View File

@ -33,6 +33,9 @@ PROVIDE ( esp_rom_md5_init = MD5Init );
PROVIDE ( esp_rom_md5_update = MD5Update );
PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_software_reset_system = software_reset );
PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );

18
components/esp_rom/include/esp_rom_sys.h
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@ -13,6 +13,24 @@
extern "C" {
#endif
/**
* @brief Software Reset digital core include RTC.
*
* It is not recommended to use this function in esp-idf, use
* esp_restart() instead.
*/
void esp_rom_software_reset_system(void);
/**
* @brief Software Reset cpu core.
*
* It is not recommended to use this function in esp-idf, use
* esp_restart() instead.
*
* @param cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
*/
void esp_rom_software_reset_cpu(int cpu_no);
/**
* @brief Print formated string to console device
* @note float and long long data are not supported!

3
components/esp_system/esp_system.c
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@ -14,6 +14,7 @@
#include "soc/rtc_cntl_reg.h"
#include "esp_private/panic_internal.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
#if CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/memprot.h"
@ -42,7 +43,7 @@ void IRAM_ATTR esp_restart_noos_dig(void)
esp_cpu_unstall(PRO_CPU_NUM);
#endif
// reset the digital part
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
esp_rom_software_reset_system();
while (true) {
;
}

11
components/hal/esp32/include/hal/rtc_cntl_ll.h
View File

@ -52,6 +52,17 @@ static inline void rtc_cntl_ll_timer2_set_touch_wait_cycle(uint32_t wait_cycle)
REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, wait_cycle);
}
static inline void rtc_cntl_ll_reset_system(void)
{
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
}
static inline void rtc_cntl_ll_reset_cpu(int cpu_no)
{
uint32_t rtc_cntl_rst = (cpu_no == 0) ? RTC_CNTL_SW_PROCPU_RST : RTC_CNTL_SW_APPCPU_RST;
REG_WRITE(RTC_CNTL_OPTIONS0_REG, rtc_cntl_rst);
}
#ifdef __cplusplus
}
#endif

10
components/hal/esp32c2/include/hal/rtc_cntl_ll.h
View File

@ -54,6 +54,16 @@ static inline void rtc_cntl_ll_disable_cpu_retention(void)
REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN);
}
static inline void rtc_cntl_ll_reset_system(void)
{
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
}
static inline void rtc_cntl_ll_reset_cpu(int cpu_no)
{
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST);
}
#ifdef __cplusplus
}
#endif

28
components/hal/esp32c3/include/hal/rtc_cntl_ll.h
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@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@ -68,6 +60,16 @@ static inline void rtc_cntl_ll_disable_cpu_retention(void)
REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN);
}
static inline void rtc_cntl_ll_reset_system(void)
{
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
}
static inline void rtc_cntl_ll_reset_cpu(int cpu_no)
{
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST);
}
#ifdef __cplusplus
}
#endif

28
components/hal/esp32h2/include/hal/rtc_cntl_ll.h
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@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@ -57,6 +49,16 @@ static inline void rtc_cntl_ll_disable_cpu_retention(void)
// ESP32H2-TODO: IDF-3383
}
static inline void rtc_cntl_ll_reset_system(void)
{
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
}
static inline void rtc_cntl_ll_reset_cpu(int cpu_no)
{
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST);
}
#ifdef __cplusplus
}
#endif

10
components/hal/esp32s2/include/hal/rtc_cntl_ll.h
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@ -52,6 +52,16 @@ static inline void rtc_cntl_ll_timer2_set_touch_wait_cycle(uint32_t wait_cycle)
REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, wait_cycle);
}
static inline void rtc_cntl_ll_reset_system(void)
{
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
}
static inline void rtc_cntl_ll_reset_cpu(int cpu_no)
{
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST);
}
#ifdef __cplusplus
}
#endif

11
components/hal/esp32s3/include/hal/rtc_cntl_ll.h
View File

@ -132,6 +132,17 @@ static inline void rtc_cntl_ll_timer2_set_touch_wait_cycle(uint32_t wait_cycle)
REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, wait_cycle);
}
static inline void rtc_cntl_ll_reset_system(void)
{
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
}
static inline void rtc_cntl_ll_reset_cpu(int cpu_no)
{
uint32_t rtc_cntl_rst = (cpu_no == 0) ? RTC_CNTL_SW_PROCPU_RST : RTC_CNTL_SW_APPCPU_RST;
REG_WRITE(RTC_CNTL_OPTIONS0_REG, rtc_cntl_rst);
}
#ifdef __cplusplus
}
#endif

2
tools/ci/check_copyright_ignore.txt
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@ -708,7 +708,6 @@ components/hal/esp32c3/include/hal/ds_ll.h
components/hal/esp32c3/include/hal/hmac_hal.h
components/hal/esp32c3/include/hal/hmac_ll.h
components/hal/esp32c3/include/hal/mpu_ll.h
components/hal/esp32c3/include/hal/rtc_cntl_ll.h
components/hal/esp32c3/include/hal/sha_ll.h
components/hal/esp32c3/include/hal/spi_flash_encrypted_ll.h
components/hal/esp32c3/include/hal/uhci_ll.h
@ -720,7 +719,6 @@ components/hal/esp32h2/include/hal/ds_ll.h
components/hal/esp32h2/include/hal/hmac_hal.h
components/hal/esp32h2/include/hal/hmac_ll.h
components/hal/esp32h2/include/hal/mpu_ll.h
components/hal/esp32h2/include/hal/rtc_cntl_ll.h
components/hal/esp32h2/include/hal/sha_ll.h
components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h
components/hal/esp32h2/include/hal/uhci_ll.h