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change(esp_hw_support): support wifi modem state for esp32c5

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This commit is contained in:
Li Shuai 2023-12-14 15:19:29 +08:00
parent eeb55c3f04
commit dad039e27f
8 changed files with 224 additions and 40 deletions
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35
components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c
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@ -6,6 +6,7 @@
#include "esp_private/sleep_clock.h" #include "esp_private/sleep_clock.h"
#include "soc/pcr_reg.h" #include "soc/pcr_reg.h"
#include "soc/rtc.h"
#include "modem/modem_syscon_reg.h" #include "modem/modem_syscon_reg.h"
#include "modem/modem_lpcon_reg.h" #include "modem/modem_lpcon_reg.h"
#include "soc/i2c_ana_mst_reg.h" #include "soc/i2c_ana_mst_reg.h"
@ -14,13 +15,43 @@ static const char *TAG = "sleep_clock";
esp_err_t sleep_clock_system_retention_init(void *arg) esp_err_t sleep_clock_system_retention_init(void *arg)
{ {
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
const static sleep_retention_entries_config_t pcr_regs_retention[] = { const static sleep_retention_entries_config_t pcr_regs_retention[] = {
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 74, 0, 0, 0xffffffff, 0xffffffff, 0x7f7, 0x0), .owner = ENTRY(0) | ENTRY(1) }, [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), PCR_AHB_FREQ_CONF_REG, 0, PCR_AHB_DIV_NUM, 1, 0), .owner = ENTRY(0) | ENTRY(1) }, /* Set AHB bus frequency to XTAL frequency */
[1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(0) | ENTRY(1) },
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
[2] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(2), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 74, 0, 0, 0xffffffff, 0xffffffff, 0x7f7, 0x0), .owner = ENTRY(0) | ENTRY(1) },
#endif
}; };
esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM); esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention"); ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
const static sleep_retention_entries_config_t modem_ahb_config[] = {
[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(3), PCR_AHB_FREQ_CONF_REG, 3, PCR_AHB_DIV_NUM, 1, 0), .owner = ENTRY(1) }, /* Set AHB bus frequency to 40 MHz under PMU MODEM state */
[1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(1) },
};
err = sleep_retention_entries_create(modem_ahb_config, ARRAY_SIZE(modem_ahb_config), REGDMA_LINK_PRI_4, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention, 4 level priority");
#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP && CONFIG_XTAL_FREQ_AUTO
uint32_t xtal_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
if (xtal_freq_mhz == SOC_XTAL_FREQ_48M) {
/* For the 48 MHz main XTAL, we need regdma to configured BBPLL by exec
* the PHY_I2C_MST_CMD_TYPE_BBPLL_CFG command from PHY i2c master
* command memory */
sleep_retention_entries_config_t bbpll_config[] = {
[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(1) }, /* I2C MST enable */
[1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(6), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 0), .owner = ENTRY(1) },
[2] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(7), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 0), .owner = ENTRY(1) },
[3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(8), MODEM_LPCON_CLK_CONF_REG, 0, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(1) }, /* I2C MST disable */
};
extern uint32_t phy_ana_i2c_master_burst_bbpll_config(void);
bbpll_config[1].config.write_wait.value = phy_ana_i2c_master_burst_bbpll_config();
err = sleep_retention_entries_create(bbpll_config, ARRAY_SIZE(bbpll_config), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for bbpll configure, 0 level priority");
}
#endif #endif
ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization"); ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
return ESP_OK; return ESP_OK;
} }

108
components/esp_hw_support/sleep_modem.c
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -12,6 +12,7 @@
#include "esp_log.h" #include "esp_log.h"
#include "esp_attr.h" #include "esp_attr.h"
#include "esp_sleep.h" #include "esp_sleep.h"
#include "esp_check.h"
#include "soc/soc_caps.h" #include "soc/soc_caps.h"
#include "esp_private/pm_impl.h" #include "esp_private/pm_impl.h"
#include "esp_private/sleep_modem.h" #include "esp_private/sleep_modem.h"
@ -136,13 +137,21 @@ void IRAM_ATTR mac_bb_power_up_cb_execute(void)
#if SOC_PM_SUPPORT_PMU_MODEM_STATE #if SOC_PM_SUPPORT_PMU_MODEM_STATE
#define PMU_RF_PWR_REG (0x600b0154)
#define SARADC_TSENS_REG (0x6000e058) #define SARADC_TSENS_REG (0x6000e058)
#define SARADC_TSENS_PU (BIT(22)) #define SARADC_TSENS_PU (BIT(22))
#if CONFIG_IDF_TARGET_ESP32C6
#define PMU_RF_PWR_REG (0x600b0154)
#define FECOEX_SET_FREQ_SET_CHAN_REG (0x600a00c0) #define FECOEX_SET_FREQ_SET_CHAN_REG (0x600a00c0)
#define FECOEX_SET_CHAN_EN (BIT(14)) #define FECOEX_SET_CHAN_EN (BIT(14))
#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a00cc) #define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a00cc)
#define FECOEX_SET_CHAN_DONE (BIT(8)) #define FECOEX_SET_CHAN_DONE (BIT(8))
#elif CONFIG_IDF_TARGET_ESP32C5
#define PMU_RF_PWR_REG (0x600b0158)
#define FECOEX_SET_FREQ_SET_CHAN_REG (0x600a001c)
#define FECOEX_SET_CHAN_EN (BIT(17))
#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a0028)
#define FECOEX_SET_CHAN_DONE (BIT(8))
#endif
#define FECOEX_AGC_CONF_REG (0x600a7030) #define FECOEX_AGC_CONF_REG (0x600a7030)
#define FECOEX_AGC_DIS (BIT(29)) #define FECOEX_AGC_DIS (BIT(29))
#define WDEVTXQ_BLOCK (0x600A4ca8) #define WDEVTXQ_BLOCK (0x600A4ca8)
@ -150,15 +159,6 @@ void IRAM_ATTR mac_bb_power_up_cb_execute(void)
#define MODEM_FE_DATA_BASE (0x600a0400) #define MODEM_FE_DATA_BASE (0x600a0400)
#define MODEM_FE_CTRL_BASE (0x600a0800) #define MODEM_FE_CTRL_BASE (0x600a0800)
#define I2C_BURST_VAL(host, start, end) (((host) << 31) | ((end) << 22) | ((start) << 16))
typedef struct {
struct {
uint8_t start, end; /* the start and end index of phy i2c master command memory */
uint8_t host_id; /* phy i2c master host id */
} config[2];
} phy_i2c_master_command_attribute_t;
typedef struct sleep_modem_config { typedef struct sleep_modem_config {
struct { struct {
void *phy_link; void *phy_link;
@ -174,18 +174,63 @@ typedef struct sleep_modem_config {
static sleep_modem_config_t s_sleep_modem = { .wifi.phy_link = NULL, .wifi.flags = 0 }; static sleep_modem_config_t s_sleep_modem = { .wifi.phy_link = NULL, .wifi.flags = 0 };
#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
static esp_err_t sleep_modem_phy_wifi_init(void *arg)
{
#define WIFIMAC_ENTRY() (BIT(SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC))
static sleep_retention_entries_config_t wifi_modem_config[] = {
[0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = WIFIMAC_ENTRY() }, /* I2C MST enable */
/* PMU or software to trigger enable RF PHY */
[1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), I2C_ANA_MST_ANA_CONF0_REG, 0x8, 0xc, 1, 0), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration enable */
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), PMU_RF_PWR_REG, 0xf3800000, 0xf3800000, 1, 0), .owner = WIFIMAC_ENTRY() },
[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), SARADC_TSENS_REG, SARADC_TSENS_PU, 0x400000, 1, 0), .owner = WIFIMAC_ENTRY() },
[4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 0), .owner = WIFIMAC_ENTRY() },
[5] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 0), .owner = WIFIMAC_ENTRY() },
[6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), FECOEX_SET_FREQ_SET_CHAN_REG, FECOEX_SET_CHAN_EN, 0x20000, 1, 0), .owner = WIFIMAC_ENTRY() },
[7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x20000, 1, 0), .owner = WIFIMAC_ENTRY() },
[8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_ST_REG, FECOEX_SET_CHAN_DONE, 0x100, 1, 0), .owner = WIFIMAC_ENTRY() },
[9] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), MODEM_SYSCON_WIFI_BB_CFG_REG, BIT(1), 0x2, 1, 0), .owner = WIFIMAC_ENTRY() },
[10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_AGC_CONF_REG, 0, 0x20000000, 1, 0), .owner = WIFIMAC_ENTRY() },
/* PMU to trigger enable RXBLOCK */
[11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), WDEVTXQ_BLOCK, 0, 0x1000, 1, 0), .owner = WIFIMAC_ENTRY() },
/* PMU or software to trigger disable RF PHY */
[12] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), FECOEX_AGC_CONF_REG, FECOEX_AGC_DIS, 0x20000000, 0, 1), .owner = WIFIMAC_ENTRY() },
[13] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), MODEM_SYSCON_WIFI_BB_CFG_REG, 0, 0x2, 0, 1), .owner = WIFIMAC_ENTRY() },
[14] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x20000, 0, 1), .owner = WIFIMAC_ENTRY() },
[15] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 1), .owner = WIFIMAC_ENTRY() },
[16] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x10), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 1), .owner = WIFIMAC_ENTRY() },
[17] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), SARADC_TSENS_REG, 0, 0x400000, 0, 1), .owner = WIFIMAC_ENTRY() },
[18] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), PMU_RF_PWR_REG, 0, 0xf3800000, 0, 1), .owner = WIFIMAC_ENTRY() },
[19] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), I2C_ANA_MST_ANA_CONF0_REG, 0x4, 0xc, 0, 1), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration disable */
[20] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), MODEM_LPCON_CLK_CONF_REG, 0, MODEM_LPCON_CLK_I2C_MST_EN_M, 0, 1), .owner = WIFIMAC_ENTRY() }, /* I2C MST disable */
/* PMU to trigger disable RXBLOCK */
[21] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x15), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1), .owner = WIFIMAC_ENTRY() },
[22] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x16), WDEVTXQ_BLOCK, WDEV_RXBLOCK, 0x1000, 0, 1), .owner = WIFIMAC_ENTRY() },
[23] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1), .owner = WIFIMAC_ENTRY() },
[24] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), PMU_SLP_WAKEUP_CNTL7_REG, 0x200000, 0xffff0000, 1, 0), .owner = WIFIMAC_ENTRY() },
[25] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), PMU_SLP_WAKEUP_CNTL7_REG, 0x9730000, 0xffff0000, 0, 1), .owner = WIFIMAC_ENTRY() }
};
extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
wifi_modem_config[4].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(true);
wifi_modem_config[15].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
esp_err_t err = sleep_retention_entries_create(wifi_modem_config, ARRAY_SIZE(wifi_modem_config), 7, SLEEP_RETENTION_MODULE_MODEM_PHY);
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate modem phy link for wifi modem state");
return ESP_OK;
}
#endif
esp_err_t sleep_modem_wifi_modem_state_init(void) esp_err_t sleep_modem_wifi_modem_state_init(void)
{ {
esp_err_t err = ESP_OK; esp_err_t err = ESP_OK;
phy_i2c_master_command_attribute_t cmd;
/* get RF on or off configuration info of i2c master command memory */
extern void phy_i2c_master_mem_cfg(phy_i2c_master_command_attribute_t *);
phy_i2c_master_mem_cfg(&cmd);
ESP_LOGD(TAG, "Modem link i2c master configuration: (%d,%d,%d), (%d,%d,%d)", cmd.config[0].host_id, cmd.config[0].start,
cmd.config[0].end, cmd.config[1].host_id, cmd.config[1].start, cmd.config[1].end);
#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
static regdma_link_config_t wifi_modem_config[] = { static regdma_link_config_t wifi_modem_config[] = {
[0] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(0), MODEM_FE_DATA_BASE, MODEM_FE_DATA_BASE, 41, 0, 0), [0] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(0), MODEM_FE_DATA_BASE, MODEM_FE_DATA_BASE, 41, 0, 0),
[1] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(1), MODEM_FE_CTRL_BASE, MODEM_FE_CTRL_BASE, 87, 0, 0), [1] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(1), MODEM_FE_CTRL_BASE, MODEM_FE_CTRL_BASE, 87, 0, 0),
@ -228,8 +273,9 @@ esp_err_t sleep_modem_wifi_modem_state_init(void)
[27] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1a), PMU_SLP_WAKEUP_CNTL7_REG, 0x200000, 0xffff0000, 1, 0), [27] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1a), PMU_SLP_WAKEUP_CNTL7_REG, 0x200000, 0xffff0000, 1, 0),
[28] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1b), PMU_SLP_WAKEUP_CNTL7_REG, 0x9730000, 0xffff0000, 0, 1) [28] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1b), PMU_SLP_WAKEUP_CNTL7_REG, 0x9730000, 0xffff0000, 0, 1)
}; };
wifi_modem_config[7].write_wait.value = I2C_BURST_VAL(cmd.config[1].host_id, cmd.config[1].start, cmd.config[1].end); extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
wifi_modem_config[18].write_wait.value = I2C_BURST_VAL(cmd.config[0].host_id, cmd.config[0].start, cmd.config[0].end); wifi_modem_config[7].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(true);
wifi_modem_config[18].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
void *link = NULL; void *link = NULL;
if (s_sleep_modem.wifi.phy_link == NULL) { if (s_sleep_modem.wifi.phy_link == NULL) {
@ -248,13 +294,33 @@ esp_err_t sleep_modem_wifi_modem_state_init(void)
s_sleep_modem.wifi.flags = 0; s_sleep_modem.wifi.flags = 0;
} }
} }
#elif SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
if (s_sleep_modem.wifi.phy_link == NULL) {
sleep_retention_module_init_param_t init_param = { .cbs = { .create = { .handle = sleep_modem_phy_wifi_init, .arg = NULL } } };
err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_MODEM_PHY, &init_param);
if (err == ESP_OK) {
err = sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_MODEM_PHY);
if (err == ESP_OK) {
s_sleep_modem.wifi.phy_link = sleep_retention_find_link_by_id(REGDMA_PHY_LINK(0x00));
s_sleep_modem.wifi.flags = 0;
}
}
}
#endif
return err; return err;
} }
__attribute__((unused)) void sleep_modem_wifi_modem_state_deinit(void) __attribute__((unused)) void sleep_modem_wifi_modem_state_deinit(void)
{ {
if (s_sleep_modem.wifi.phy_link) { if (s_sleep_modem.wifi.phy_link) {
#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
regdma_link_destroy(s_sleep_modem.wifi.phy_link, 0); regdma_link_destroy(s_sleep_modem.wifi.phy_link, 0);
#elif SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
esp_err_t err = sleep_retention_module_free(SLEEP_RETENTION_MODULE_MODEM_PHY);
if (err == ESP_OK) {
sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_MODEM_PHY);
}
#endif
s_sleep_modem.wifi.phy_link = NULL; s_sleep_modem.wifi.phy_link = NULL;
s_sleep_modem.wifi.flags = 0; s_sleep_modem.wifi.flags = 0;
} }

33
components/esp_phy/include/esp_private/phy.h
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@ -13,17 +13,12 @@ extern "C" {
#define ESP_CAL_DATA_CHECK_FAIL 1 #define ESP_CAL_DATA_CHECK_FAIL 1
typedef enum {
PHY_I2C_MST_CMD_TYPE_OFF = 0,
PHY_I2C_MST_CMD_TYPE_ON,
PHY_I2C_MST_CMD_TYPE_MAX
} phy_i2c_master_command_type_t;
typedef struct { typedef struct {
uint8_t cmd_type; /* the command type of the current phy i2c master command memory config */
struct { struct {
uint8_t start, end; /* the start and end index of phy i2c master command memory */ uint8_t start, end; /* the start and end index of phy i2c master command memory */
uint8_t host_id; /* phy i2c master host id */ uint8_t host_id; /* phy i2c master host id */
} config[PHY_I2C_MST_CMD_TYPE_MAX]; } config;
} phy_i2c_master_command_attribute_t; } phy_i2c_master_command_attribute_t;
/** /**
@ -88,13 +83,14 @@ void phy_xpd_tsens(void);
void phy_init_flag(void); void phy_init_flag(void);
#endif #endif
#if CONFIG_IDF_TARGET_ESP32C6 #if SOC_PM_SUPPORT_PMU_MODEM_STATE
/** /**
* @brief Get the configuration info of PHY i2c master command memory. * @brief Get the configuration info of PHY i2c master command memory.
* *
* @param attr the configuration info of PHY i2c master command memory * @param[out] attr the configuration info of PHY i2c master command memory
* @param[out] size the count of PHY i2c master command memory configuration
*/ */
void phy_i2c_master_mem_cfg(phy_i2c_master_command_attribute_t *attr); void phy_i2c_master_command_mem_cfg(phy_i2c_master_command_attribute_t *attr, int *size);
#endif #endif
/** /**
@ -217,6 +213,23 @@ void phy_ant_clr_update_flag(void);
*/ */
void phy_ant_update(void); void phy_ant_update(void);
#if SOC_PM_SUPPORT_PMU_MODEM_STATE
/**
* @brief Get the REGDMA config value of the BBPLL in analog i2c master burst mode
*
* @return the BBPLL REGDMA configure value of i2c master burst mode
*/
uint32_t phy_ana_i2c_master_burst_bbpll_config(void);
/**
* @brief Get the REGDMA config value of the RF PHY on or off in analog i2c master burst mode
*
* @param[in] on true for enable RF PHY, false for disable RF PHY.
*
* @return the RF on or off configure value of i2c master burst mode
*/
uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
#endif
#ifdef __cplusplus #ifdef __cplusplus
} }

54
components/esp_phy/src/phy_common.c
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@ -294,3 +294,57 @@ esp_err_t esp_phy_get_ant(esp_phy_ant_config_t *config)
memcpy(config, &s_phy_ant_config, sizeof(esp_phy_ant_config_t)); memcpy(config, &s_phy_ant_config, sizeof(esp_phy_ant_config_t));
return ESP_OK; return ESP_OK;
} }
#if SOC_PM_SUPPORT_PMU_MODEM_STATE
typedef enum {
PHY_I2C_MST_CMD_TYPE_RF_OFF = 0,
PHY_I2C_MST_CMD_TYPE_RF_ON,
PHY_I2C_MST_CMD_TYPE_BBPLL_CFG,
PHY_I2C_MST_CMD_TYPE_MAX
} phy_i2c_master_command_type_t;
static uint32_t phy_ana_i2c_master_burst_config(phy_i2c_master_command_attribute_t *attr, int size, phy_i2c_master_command_type_t type)
{
#define I2C1_BURST_VAL(en, start, end) (((en) << 31) | ((end) << 22) | ((start) << 16))
#define I2C0_BURST_VAL(en, start, end) (((en) << 15) | ((end) << 6) | ((start) << 0))
uint32_t brust = 0;
for (int i = 0; i < size; i++) {
if (attr[i].config.start == 0xff || attr[i].config.end == 0xff) /* ignore invalid configure */
continue;
if (attr[i].cmd_type == type) {
if (attr[i].config.host_id) {
brust |= I2C1_BURST_VAL(1, attr[i].config.start, attr[i].config.end);
} else {
brust |= I2C0_BURST_VAL(1, attr[i].config.start, attr[i].config.end);
}
}
}
return brust;
}
uint32_t phy_ana_i2c_master_burst_bbpll_config(void)
{
/* PHY supports 2 I2C masters, and the maximum number of configurations
* supported by the I2C master command memory is the command type
* (PHY_I2C_MST_CMD_TYPE_MAX) multiplied by 2 */
phy_i2c_master_command_attribute_t cmd[2 * PHY_I2C_MST_CMD_TYPE_MAX];
int size = sizeof(cmd) / sizeof(cmd[0]);
phy_i2c_master_command_mem_cfg(cmd, &size);
return phy_ana_i2c_master_burst_config(cmd, size, PHY_I2C_MST_CMD_TYPE_BBPLL_CFG);
}
uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on)
{
/* PHY supports 2 I2C masters, and the maximum number of configurations
* supported by the I2C master command memory is the command type
* (PHY_I2C_MST_CMD_TYPE_MAX) multiplied by 2 */
phy_i2c_master_command_attribute_t cmd[2 * PHY_I2C_MST_CMD_TYPE_MAX];
int size = sizeof(cmd) / sizeof(cmd[0]);
phy_i2c_master_command_mem_cfg(cmd, &size);
return phy_ana_i2c_master_burst_config(cmd, size, on ? PHY_I2C_MST_CMD_TYPE_RF_ON : PHY_I2C_MST_CMD_TYPE_RF_OFF);
}
#endif

13
components/esp_phy/src/phy_init.c
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@ -45,7 +45,7 @@
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
#include "soc/dport_reg.h" #include "soc/dport_reg.h"
#elif CONFIG_IDF_TARGET_ESP32C6 #elif SOC_PM_SUPPORT_PMU_MODEM_STATE
#include "esp_private/sleep_modem.h" #include "esp_private/sleep_modem.h"
#endif #endif
#include "hal/efuse_hal.h" #include "hal/efuse_hal.h"
@ -383,7 +383,7 @@ void esp_phy_modem_init(void)
s_phy_digital_regs_mem = (uint32_t *)heap_caps_malloc(SOC_PHY_DIG_REGS_MEM_SIZE, MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL); s_phy_digital_regs_mem = (uint32_t *)heap_caps_malloc(SOC_PHY_DIG_REGS_MEM_SIZE, MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
} }
#endif // SOC_PM_MODEM_RETENTION_BY_BACKUPDMA #endif // SOC_PM_MODEM_RETENTION_BY_BACKUPDMA
#if CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP #if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
sleep_modem_wifi_modem_state_init(); sleep_modem_wifi_modem_state_init();
#endif // CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP #endif // CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
_lock_release(&s_phy_access_lock); _lock_release(&s_phy_access_lock);
@ -408,7 +408,7 @@ void esp_phy_modem_deinit(void)
phy_init_flag(); phy_init_flag();
#endif // CONFIG_IDF_TARGET_ESP32C3 #endif // CONFIG_IDF_TARGET_ESP32C3
#endif // SOC_PM_MODEM_RETENTION_BY_BACKUPDMA #endif // SOC_PM_MODEM_RETENTION_BY_BACKUPDMA
#if CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP #if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
sleep_modem_wifi_modem_state_deinit(); sleep_modem_wifi_modem_state_deinit();
#endif // CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP #endif // CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
} }
@ -431,7 +431,12 @@ static esp_err_t sleep_retention_wifi_bb_init(void *arg)
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b01, 0x600a7400, 0x600a7400, 14, 0, 0), .owner = BIT(0) | BIT(1) }, /* TX */ [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b01, 0x600a7400, 0x600a7400, 14, 0, 0), .owner = BIT(0) | BIT(1) }, /* TX */
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b02, 0x600a7800, 0x600a7800, 136, 0, 0), .owner = BIT(0) | BIT(1) }, /* NRX */ [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b02, 0x600a7800, 0x600a7800, 136, 0, 0), .owner = BIT(0) | BIT(1) }, /* NRX */
[3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b03, 0x600a7c00, 0x600a7c00, 53, 0, 0), .owner = BIT(0) | BIT(1) }, /* BB */ [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b03, 0x600a7c00, 0x600a7c00, 53, 0, 0), .owner = BIT(0) | BIT(1) }, /* BB */
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b05, 0x600a0000, 0x600a0000, 58, 0, 0), .owner = BIT(0) | BIT(1) } /* FE COEX */ [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b05, 0x600a0000, 0x600a0000, 58, 0, 0), .owner = BIT(0) | BIT(1) }, /* FE COEX */
#ifndef SOC_PM_RETENTION_HAS_CLOCK_BUG
[5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b06, 0x600a8000, 0x000a8000, 39, 0, 0), .owner = BIT(0) | BIT(1) }, /* BRX */
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b07, 0x600a0400, 0x600a0400, 41, 0, 0), .owner = BIT(0) | BIT(1) }, /* FE DATA */
[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b08, 0x600a0800, 0x600a0800, 87, 0, 0), .owner = BIT(0) | BIT(1) } /* FE CTRL */
#endif
}; };
esp_err_t err = sleep_retention_entries_create(bb_regs_retention, ARRAY_SIZE(bb_regs_retention), 3, SLEEP_RETENTION_MODULE_WIFI_BB); esp_err_t err = sleep_retention_entries_create(bb_regs_retention, ARRAY_SIZE(bb_regs_retention), 3, SLEEP_RETENTION_MODULE_WIFI_BB);
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (%s) retention", "WiFi BB"); ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (%s) retention", "WiFi BB");

12
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
View File

@ -1255,6 +1255,10 @@ config SOC_PM_SUPPORT_WIFI_WAKEUP
bool bool
default y default y
config SOC_PM_SUPPORT_BEACON_WAKEUP
bool
default y
config SOC_PM_SUPPORT_CPU_PD config SOC_PM_SUPPORT_CPU_PD
bool bool
default y default y
@ -1295,6 +1299,10 @@ config SOC_PM_SUPPORT_RTC_PERIPH_PD
bool bool
default y default y
config SOC_PM_SUPPORT_PMU_MODEM_STATE
bool
default y
config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
bool bool
default y default y
@ -1327,6 +1335,10 @@ config SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE
bool bool
default y default y
config SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
int
default 4
config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
bool bool
default y default y

2
components/soc/esp32c5/include/soc/retention_periph_defs.h
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@ -43,6 +43,7 @@ typedef enum periph_retention_module {
SLEEP_RETENTION_MODULE_BLE_MAC = 28, SLEEP_RETENTION_MODULE_BLE_MAC = 28,
SLEEP_RETENTION_MODULE_BT_BB = 29, SLEEP_RETENTION_MODULE_BT_BB = 29,
SLEEP_RETENTION_MODULE_802154_MAC = 30, SLEEP_RETENTION_MODULE_802154_MAC = 30,
SLEEP_RETENTION_MODULE_MODEM_PHY = 31,
SLEEP_RETENTION_MODULE_MAX = 31 SLEEP_RETENTION_MODULE_MAX = 31
} periph_retention_module_t; } periph_retention_module_t;
@ -57,6 +58,7 @@ typedef enum periph_retention_module_bitmap {
SLEEP_RETENTION_MODULE_BM_BLE_MAC = BIT(SLEEP_RETENTION_MODULE_BLE_MAC), SLEEP_RETENTION_MODULE_BM_BLE_MAC = BIT(SLEEP_RETENTION_MODULE_BLE_MAC),
SLEEP_RETENTION_MODULE_BM_BT_BB = BIT(SLEEP_RETENTION_MODULE_BT_BB), SLEEP_RETENTION_MODULE_BM_BT_BB = BIT(SLEEP_RETENTION_MODULE_BT_BB),
SLEEP_RETENTION_MODULE_BM_802154_MAC = BIT(SLEEP_RETENTION_MODULE_802154_MAC), SLEEP_RETENTION_MODULE_BM_802154_MAC = BIT(SLEEP_RETENTION_MODULE_802154_MAC),
SLEEP_RETENTION_MODULE_BM_MODEM_PHY = BIT(SLEEP_RETENTION_MODULE_MODEM_PHY),
/* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM, /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
* TEE, APM, IOMUX, SPIMEM, SysTimer, etc.. */ * TEE, APM, IOMUX, SPIMEM, SysTimer, etc.. */

7
components/soc/esp32c5/include/soc/soc_caps.h
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@ -540,7 +540,7 @@
/*-------------------------- Power Management CAPS ----------------------------*/ /*-------------------------- Power Management CAPS ----------------------------*/
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1) #define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
// #define SOC_PM_SUPPORT_BEACON_WAKEUP (1) #define SOC_PM_SUPPORT_BEACON_WAKEUP (1)
#define SOC_PM_SUPPORT_BT_WAKEUP (1) #define SOC_PM_SUPPORT_BT_WAKEUP (1)
#define SOC_PM_SUPPORT_EXT1_WAKEUP (1) #define SOC_PM_SUPPORT_EXT1_WAKEUP (1)
#define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */ #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
@ -555,9 +555,9 @@
#define SOC_PM_SUPPORT_MAC_BB_PD (1) #define SOC_PM_SUPPORT_MAC_BB_PD (1)
#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1) #define SOC_PM_SUPPORT_RTC_PERIPH_PD (1)
// #define SOC_PM_SUPPORT_PMU_MODEM_STATE (1) #define SOC_PM_SUPPORT_PMU_MODEM_STATE (1)
/* macro redefine for pass esp_wifi headers md5sum check */ /* macro redefine for pass esp_wifi headers md5sum check */
// #define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE #define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE
#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */ #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
@ -568,6 +568,7 @@
#define SOC_PM_PAU_LINK_NUM (5) #define SOC_PM_PAU_LINK_NUM (5)
#define SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE (1) #define SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE (1)
#define SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC (4) // The range of values for the link index is [0, SOC_PM_PAU_LINK_NUM)
#define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE (1) #define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE (1)