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Merge branch 'feat/add_efuse_cpu_freq_rating' into 'master'

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efuse/add cpu freq rating

See merge request idf/esp-idf!1994
This commit is contained in:
Angus Gratton 2018-03-29 05:59:52 +08:00
commit da27816314
3 changed files with 49 additions and 22 deletions
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8
components/bootloader/subproject/main/bootloader_start.c
View File

@ -447,6 +447,14 @@ void bootloader_main()
{ {
vddsdio_configure(); vddsdio_configure();
flash_gpio_configure(); flash_gpio_configure();
#if (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ == 240)
//Check if ESP32 is rated for a CPU frequency of 160MHz only
if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED) &&
REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW)) {
ESP_LOGE(TAG, "Chip CPU frequency rated for 160MHz. Modify CPU frequency in menuconfig");
return;
}
#endif
bootloader_clock_configure(); bootloader_clock_configure();
uart_console_configure(); uart_console_configure();
wdt_reset_check(); wdt_reset_check();

16
components/bootloader/subproject/main/flash_qio_mode.c
View File

@ -174,13 +174,15 @@ static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn,
// spiconfig specifies a custom efuse pin configuration. This config defines all pins -except- WP, // spiconfig specifies a custom efuse pin configuration. This config defines all pins -except- WP,
// which is compiled into the bootloader instead. // which is compiled into the bootloader instead.
// //
// Most commonly an overriden pin mapping means ESP32-D2WD. Warn if chip is ESP32-D2WD // Most commonly an overriden pin mapping means ESP32-D2WD or ESP32-PICOD4.
// but someone has changed the WP pin assignment from that chip's WP pin. //Warn if chip is ESP32-D2WD/ESP32-PICOD4 but someone has changed the WP pin
uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_RESERVE); //assignment from that chip's WP pin.
uint32_t pkg_ver = chip_ver & 0x7; uint32_t pkg_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
const int PKG_VER_ESP32_D2WD = 2; // TODO: use chip detection API once available if (CONFIG_BOOTLOADER_SPI_WP_PIN != ESP32_D2WD_WP_GPIO &&
if (pkg_ver == PKG_VER_ESP32_D2WD && CONFIG_BOOTLOADER_SPI_WP_PIN != ESP32_D2WD_WP_GPIO) { (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
ESP_LOGW(TAG, "Chip is ESP32-D2WD but flash WP pin is different value to internal flash"); pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)) {
ESP_LOGW(TAG, "Chip is ESP32-D2WD/ESP32-PICOD4 but flash WP pin is different value to internal flash");
} }
} }

47
components/soc/esp32/include/soc/efuse_reg.h
View File

@ -91,15 +91,21 @@
#define EFUSE_RD_BLK3_PART_RESERVE_M ((EFUSE_RD_BLK3_PART_RESERVE_V)<<(EFUSE_RD_BLK3_PART_RESERVE_S)) #define EFUSE_RD_BLK3_PART_RESERVE_M ((EFUSE_RD_BLK3_PART_RESERVE_V)<<(EFUSE_RD_BLK3_PART_RESERVE_S))
#define EFUSE_RD_BLK3_PART_RESERVE_V 0x1 #define EFUSE_RD_BLK3_PART_RESERVE_V 0x1
#define EFUSE_RD_BLK3_PART_RESERVE_S 14 #define EFUSE_RD_BLK3_PART_RESERVE_S 14
/* EFUSE_RD_CHIP_VER_RESERVE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ /* EFUSE_RD_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: */ /*description: If set, the ESP32's maximum CPU frequency has been rated*/
#define EFUSE_RD_CHIP_VER_RESERVE 0x00000003 #define EFUSE_RD_CHIP_CPU_FREQ_RATED (BIT(13))
#define EFUSE_RD_CHIP_VER_RESERVE_M ((EFUSE_RD_CHIP_VER_RESERVE_V)<<(EFUSE_RD_CHIP_VER_RESERVE_S)) #define EFUSE_RD_CHIP_CPU_FREQ_RATED_M ((EFUSE_RD_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_RD_CHIP_CPU_FREQ_RATED_S))
#define EFUSE_RD_CHIP_VER_RESERVE_V 0x3 #define EFUSE_RD_CHIP_CPU_FREQ_RATED_V 0x1
#define EFUSE_RD_CHIP_VER_RESERVE_S 12 #define EFUSE_RD_CHIP_CPU_FREQ_RATED_S 13
/* EFUSE_RD_CHIP_VER : R/W ;bitpos:[11:9] ;default: 3'b0 ; */ /* EFUSE_RD_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/
#define EFUSE_RD_CHIP_CPU_FREQ_LOW (BIT(12))
#define EFUSE_RD_CHIP_CPU_FREQ_LOW_M ((EFUSE_RD_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_RD_CHIP_CPU_FREQ_LOW_S))
#define EFUSE_RD_CHIP_CPU_FREQ_LOW_V 0x1
#define EFUSE_RD_CHIP_CPU_FREQ_LOW_S 12
/* EFUSE_RD_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
/*description: chip package */ /*description: chip package */
#define EFUSE_RD_CHIP_VER 0x00000007 #define EFUSE_RD_CHIP_VER_PKG 0x00000007
#define EFUSE_RD_CHIP_VER_PKG_M ((EFUSE_RD_CHIP_VER_PKG_V)<<(EFUSE_RD_CHIP_VER_PKG_S)) #define EFUSE_RD_CHIP_VER_PKG_M ((EFUSE_RD_CHIP_VER_PKG_V)<<(EFUSE_RD_CHIP_VER_PKG_S))
#define EFUSE_RD_CHIP_VER_PKG_V 0x7 #define EFUSE_RD_CHIP_VER_PKG_V 0x7
#define EFUSE_RD_CHIP_VER_PKG_S 9 #define EFUSE_RD_CHIP_VER_PKG_S 9
@ -341,18 +347,29 @@
#define EFUSE_BLK3_PART_RESERVE_M ((EFUSE_BLK3_PART_RESERVE_V)<<(EFUSE_BLK3_PART_RESERVE_S)) #define EFUSE_BLK3_PART_RESERVE_M ((EFUSE_BLK3_PART_RESERVE_V)<<(EFUSE_BLK3_PART_RESERVE_S))
#define EFUSE_BLK3_PART_RESERVE_V 0x1 #define EFUSE_BLK3_PART_RESERVE_V 0x1
#define EFUSE_BLK3_PART_RESERVE_S 14 #define EFUSE_BLK3_PART_RESERVE_S 14
/* EFUSE_CHIP_VER_RESERVE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ /* EFUSE_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: */ /*description: If set, the ESP32's maximum CPU frequency has been rated*/
#define EFUSE_CHIP_VER_RESERVE 0x00000003 #define EFUSE_CHIP_CPU_FREQ_RATED (BIT(13))
#define EFUSE_CHIP_VER_RESERVE_M ((EFUSE_CHIP_VER_RESERVE_V)<<(EFUSE_CHIP_VER_RESERVE_S)) #define EFUSE_CHIP_CPU_FREQ_RATED_M ((EFUSE_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_CHIP_CPU_FREQ_RATED_S))
#define EFUSE_CHIP_VER_RESERVE_V 0x3 #define EFUSE_CHIP_CPU_FREQ_RATED_V 0x1
#define EFUSE_CHIP_VER_RESERVE_S 12 #define EFUSE_CHIP_CPU_FREQ_RATED_S 13
/* EFUSE_CHIP_VER : R/W ;bitpos:[11:9] ;default: 3'b0 ; */ /* EFUSE_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: If set alongside EFUSE_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/
#define EFUSE_CHIP_CPU_FREQ_LOW (BIT(12))
#define EFUSE_CHIP_CPU_FREQ_LOW_M ((EFUSE_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_CHIP_CPU_FREQ_LOW_S))
#define EFUSE_CHIP_CPU_FREQ_LOW_V 0x1
#define EFUSE_CHIP_CPU_FREQ_LOW_S 12
/* EFUSE_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
/*description: */ /*description: */
#define EFUSE_CHIP_VER_PKG 0x00000007 #define EFUSE_CHIP_VER_PKG 0x00000007
#define EFUSE_CHIP_VER_PKG_M ((EFUSE_CHIP_VER_PKG_V)<<(EFUSE_CHIP_VER_PKG_S)) #define EFUSE_CHIP_VER_PKG_M ((EFUSE_CHIP_VER_PKG_V)<<(EFUSE_CHIP_VER_PKG_S))
#define EFUSE_CHIP_VER_PKG_V 0x7 #define EFUSE_CHIP_VER_PKG_V 0x7
#define EFUSE_CHIP_VER_PKG_S 9 #define EFUSE_CHIP_VER_PKG_S 9
#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ6 0
#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ5 1
#define EFUSE_CHIP_VER_PKG_ESP32D2WDQ5 2
#define EFUSE_CHIP_VER_PKG_ESP32PICOD2 4
#define EFUSE_CHIP_VER_PKG_ESP32PICOD4 5
/* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */ /* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */
/*description: program for SPI_pad_config_hd*/ /*description: program for SPI_pad_config_hd*/
#define EFUSE_SPI_PAD_CONFIG_HD 0x0000001F #define EFUSE_SPI_PAD_CONFIG_HD 0x0000001F