mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
Merge branch 'bugfix/fix_uart_handler_call_inline_func' into 'master'
driver: fix uart handler in iram calls inline uart_ll_is_tx_idle() placed in flash Closes IDFGH-3775 See merge request espressif/esp-idf!9985
This commit is contained in:
Michael (XIAO Xufeng)
commit
da0b86905f
@ -17,6 +17,7 @@
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#pragma once
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#include "esp_attr.h"
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#include "soc/uart_periph.h"
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#include "hal/uart_types.h"
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@ -67,7 +68,7 @@ typedef enum {
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*
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* @return None.
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*/
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static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
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FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
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{
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hw->conf0.tick_ref_always_on = (source_clk == UART_SCLK_APB) ? 1 : 0;
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}
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@ -80,7 +81,7 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
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*
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* @return None.
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*/
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static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t* source_clk)
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FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t* source_clk)
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{
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*source_clk = hw->conf0.tick_ref_always_on ? UART_SCLK_APB : UART_SCLK_REF_TICK;
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}
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@ -92,7 +93,7 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t* source_clk)
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*
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* @return Current source clock frequency
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*/
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static inline uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw)
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FORCE_INLINE_ATTR uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw)
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{
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return (hw->conf0.tick_ref_always_on) ? APB_CLK_FREQ : REF_CLK_FREQ;
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}
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@ -105,7 +106,7 @@ static inline uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw)
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* @return None
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*/
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static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud)
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FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud)
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{
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uint32_t sclk_freq, clk_div;
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@ -124,7 +125,7 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud)
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*
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* @return The current baudrate
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*/
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static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw)
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FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw)
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{
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uint32_t sclk_freq = uart_ll_get_sclk_freq(hw);
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typeof(hw->clk_div) div_reg = hw->clk_div;
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@ -139,7 +140,7 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw)
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*
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* @return None
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*/
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static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
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FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
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{
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hw->int_ena.val |= mask;
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}
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@ -152,7 +153,7 @@ static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
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*
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* @return None
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*/
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static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
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FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
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{
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hw->int_ena.val &= (~mask);
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}
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@ -164,7 +165,7 @@ static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
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*
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* @return The UART interrupt status.
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*/
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static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
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FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
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{
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return hw->int_st.val;
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}
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@ -177,7 +178,7 @@ static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
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*
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* @return None
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*/
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static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
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FORCE_INLINE_ATTR void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
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{
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hw->int_clr.val = mask;
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}
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@ -189,7 +190,7 @@ static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
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*
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* @return Interrupt enabled value
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*/
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static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
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FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
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{
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return hw->int_ena.val;
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}
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@ -203,7 +204,7 @@ static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
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*
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* @return None.
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*/
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static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
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FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
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{
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//Get the UART APB fifo addr. Read fifo, we use APB address
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uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_REG(0) : (hw == &UART1) ? UART_FIFO_REG(1) : UART_FIFO_REG(2);
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@ -224,7 +225,7 @@ static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd
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*
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* @return None
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*/
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static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
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FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
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{
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//Get the UART AHB fifo addr, Write fifo, we use AHB address
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uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_AHB_REG(0) : (hw == &UART1) ? UART_FIFO_AHB_REG(1) : UART_FIFO_AHB_REG(2);
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@ -240,7 +241,7 @@ static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint
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*
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* @return None
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*/
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static inline void uart_ll_rxfifo_rst(uart_dev_t *hw)
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FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw)
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{
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//Hardware issue: we can not use `rxfifo_rst` to reset the hw rxfifo.
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uint16_t fifo_cnt;
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@ -269,7 +270,7 @@ static inline void uart_ll_rxfifo_rst(uart_dev_t *hw)
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*
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* @return None
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*/
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static inline void uart_ll_txfifo_rst(uart_dev_t *hw)
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FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw)
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{
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if (hw == &UART0) {
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hw->conf0.txfifo_rst = 1;
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@ -284,7 +285,7 @@ static inline void uart_ll_txfifo_rst(uart_dev_t *hw)
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*
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* @return The readable data length in rxfifo.
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*/
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static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
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FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
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{
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uint32_t fifo_cnt = hw->status.rxfifo_cnt;
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typeof(hw->mem_rx_status) rx_status = hw->mem_rx_status;
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@ -310,7 +311,7 @@ static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
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*
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* @return The data length of txfifo can be written.
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*/
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static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
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FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
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{
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return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt;
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}
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@ -323,7 +324,7 @@ static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
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*
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* @return None.
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*/
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static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
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FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
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{
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//workaround for hardware issue, when UART stop bit set as 2-bit mode.
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if(stop_bit == UART_STOP_BITS_2) {
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@ -343,7 +344,7 @@ static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_b
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*
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* @return None.
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*/
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static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
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FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
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{
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//workaround for hardware issue, when UART stop bit set as 2-bit mode.
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if(hw->rs485_conf.dl1_en == 1 && hw->conf0.stop_bit_num == 0x1) {
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@ -361,7 +362,7 @@ static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_
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*
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* @return None.
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*/
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static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
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FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
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{
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if(parity_mode != UART_PARITY_DISABLE) {
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hw->conf0.parity = parity_mode & 0x1;
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@ -377,7 +378,7 @@ static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
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*
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* @return None.
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*/
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static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode)
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FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode)
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{
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if(hw->conf0.parity_en) {
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*parity_mode = 0X2 | hw->conf0.parity;
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@ -395,7 +396,7 @@ static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode
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*
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* @return None.
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*/
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static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
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FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
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{
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hw->conf1.rxfifo_full_thrhd = full_thrhd;
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}
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@ -409,7 +410,7 @@ static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thr
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*
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* @return None.
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*/
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static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
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FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
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{
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hw->conf1.txfifo_empty_thrhd = empty_thrhd;
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}
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@ -423,7 +424,7 @@ static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_t
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*
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* @return None.
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*/
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static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
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FORCE_INLINE_ATTR void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
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{
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hw->idle_conf.rx_idle_thrhd = rx_idle_thr;
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}
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@ -436,7 +437,7 @@ static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
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*
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* @return None.
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*/
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static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
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FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
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{
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hw->idle_conf.tx_idle_num = idle_num;
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}
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@ -449,7 +450,7 @@ static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
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*
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* @return None.
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*/
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static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
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FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
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{
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if(break_num > 0) {
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hw->idle_conf.tx_brk_num = break_num;
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@ -468,7 +469,7 @@ static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
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*
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* @return None.
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*/
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static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs)
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FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs)
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{
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//only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
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if(flow_ctrl & UART_HW_FLOWCTRL_RTS) {
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@ -492,7 +493,7 @@ static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_
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*
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* @return None.
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*/
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static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl)
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FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl)
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{
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*flow_ctrl = UART_HW_FLOWCTRL_DISABLE;
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if(hw->conf1.rx_flow_en) {
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@ -512,7 +513,7 @@ static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_
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*
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* @return None.
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*/
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static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en)
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FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en)
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{
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if(sw_flow_ctrl_en) {
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hw->flow_conf.xonoff_del = 1;
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@ -540,7 +541,7 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *
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*
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* @return None.
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*/
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static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
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FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
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{
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hw->at_cmd_char.data = cmd_char->cmd_char;
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hw->at_cmd_char.char_num = cmd_char->char_num;
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@ -557,7 +558,7 @@ static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_ch
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*
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* @return None.
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*/
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static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit)
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FORCE_INLINE_ATTR void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit)
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{
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hw->conf0.bit_num = data_bit;
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}
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@ -570,7 +571,7 @@ static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t d
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*
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* @return None.
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*/
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static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
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FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
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{
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hw->conf0.sw_rts = level & 0x1;
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}
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@ -583,7 +584,7 @@ static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
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*
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* @return None.
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*/
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static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
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FORCE_INLINE_ATTR void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
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{
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hw->conf0.sw_dtr = level & 0x1;
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}
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@ -597,7 +598,7 @@ static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
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*
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* @return None.
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*/
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static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
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FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
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{
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hw->sleep_conf.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH;
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}
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@ -609,7 +610,7 @@ static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
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*
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* @return None.
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*/
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static inline void uart_ll_set_mode_normal(uart_dev_t *hw)
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FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw)
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{
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hw->rs485_conf.en = 0;
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hw->rs485_conf.tx_rx_en = 0;
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@ -624,7 +625,7 @@ static inline void uart_ll_set_mode_normal(uart_dev_t *hw)
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*
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* @return None.
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*/
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static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
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FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
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{
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// Application software control, remove echo
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hw->rs485_conf.rx_busy_tx_en = 1;
|
||||
@ -641,7 +642,7 @@ static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
|
||||
{
|
||||
// Enable receiver, sw_rts = 1 generates low level on RTS pin
|
||||
hw->conf0.sw_rts = 1;
|
||||
@ -660,7 +661,7 @@ static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
|
||||
{
|
||||
hw->conf0.irda_en = 0;
|
||||
// Transmitters output signal loop back to the receivers input signal
|
||||
@ -678,7 +679,7 @@ static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_irda(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
|
||||
{
|
||||
hw->rs485_conf.en = 0;
|
||||
hw->rs485_conf.tx_rx_en = 0;
|
||||
@ -695,7 +696,7 @@ static inline void uart_ll_set_mode_irda(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
|
||||
{
|
||||
switch (mode) {
|
||||
default:
|
||||
@ -726,7 +727,7 @@ static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
|
||||
{
|
||||
*cmd_char = hw->at_cmd_char.data;
|
||||
*char_num = hw->at_cmd_char.char_num;
|
||||
@ -739,7 +740,7 @@ static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, ui
|
||||
*
|
||||
* @return The UART wakeup threshold value.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
|
||||
{
|
||||
return hw->sleep_conf.active_threshold + UART_LL_MIN_WAKEUP_THRESH;
|
||||
}
|
||||
@ -752,7 +753,7 @@ static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
|
||||
*
|
||||
* @return The bit mode.
|
||||
*/
|
||||
static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
|
||||
{
|
||||
*data_bit = hw->conf0.bit_num;
|
||||
}
|
||||
@ -764,7 +765,7 @@ static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *
|
||||
*
|
||||
* @return True if the state machine is in the IDLE state, otherwise false is returned.
|
||||
*/
|
||||
static inline bool uart_ll_is_tx_idle(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR IRAM_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
|
||||
{
|
||||
typeof(hw->status) status = hw->status;
|
||||
return ((status.txfifo_cnt == 0) && (status.st_utx_out == 0));
|
||||
@ -777,7 +778,7 @@ static inline bool uart_ll_is_tx_idle(uart_dev_t *hw)
|
||||
*
|
||||
* @return True if hw rts flow control is enabled, otherwise false is returned.
|
||||
*/
|
||||
static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
|
||||
{
|
||||
return hw->conf1.rx_flow_en;
|
||||
}
|
||||
@ -789,7 +790,7 @@ static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
|
||||
*
|
||||
* @return True if hw cts flow control is enabled, otherwise false is returned.
|
||||
*/
|
||||
static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
|
||||
{
|
||||
return hw->conf0.tx_flow_en;
|
||||
}
|
||||
@ -802,7 +803,7 @@ static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
|
||||
{
|
||||
hw->conf0.loopback = loop_back_en;
|
||||
}
|
||||
@ -816,7 +817,7 @@ static inline void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
|
||||
FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
|
||||
{
|
||||
typeof(hw->conf0) conf0_reg = hw->conf0;
|
||||
conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0;
|
||||
@ -838,7 +839,7 @@ static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thr)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thr)
|
||||
{
|
||||
if (hw->conf0.tick_ref_always_on == 0) {
|
||||
//Hardware issue workaround: when using ref_tick, the rx timeout threshold needs increase to 10 times.
|
||||
@ -863,7 +864,7 @@ static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thr)
|
||||
*
|
||||
* @return tout_thr The timeout threshold value. If timeout feature is disabled returns 0.
|
||||
*/
|
||||
static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
|
||||
{
|
||||
uint16_t tout_thrd = 0;
|
||||
if (hw->conf1.rx_tout_en > 0) {
|
||||
@ -883,7 +884,7 @@ static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
|
||||
*
|
||||
* @return maximum timeout threshold.
|
||||
*/
|
||||
static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
|
||||
{
|
||||
uint16_t tout_thrd = 0;
|
||||
if (hw->conf0.tick_ref_always_on == 0) {
|
||||
@ -901,7 +902,7 @@ static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_force_xoff(uart_port_t uart_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_force_xoff(uart_port_t uart_num)
|
||||
{
|
||||
/* Note: Set `UART_FORCE_XOFF` can't stop new Tx request. */
|
||||
REG_SET_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XOFF);
|
||||
@ -914,7 +915,7 @@ static inline void uart_ll_force_xoff(uart_port_t uart_num)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_force_xon(uart_port_t uart_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_force_xon(uart_port_t uart_num)
|
||||
{
|
||||
REG_CLR_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XOFF);
|
||||
REG_SET_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XON);
|
||||
@ -928,7 +929,7 @@ static inline void uart_ll_force_xon(uart_port_t uart_num)
|
||||
*
|
||||
* @return UART module FSM status.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_fsm_status(uart_port_t uart_num)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_fsm_status(uart_port_t uart_num)
|
||||
{
|
||||
return REG_GET_FIELD(UART_STATUS_REG(uart_num), UART_ST_UTX_OUT);
|
||||
}
|
||||
|
||||
@ -19,6 +19,7 @@
|
||||
#pragma once
|
||||
#include "hal/uart_types.h"
|
||||
#include "soc/uart_periph.h"
|
||||
#include "esp_attr.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -64,7 +65,7 @@ typedef enum {
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
|
||||
{
|
||||
hw->conf0.tick_ref_always_on = (source_clk == UART_SCLK_APB) ? 1 : 0;
|
||||
}
|
||||
@ -77,7 +78,7 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t* source_clk)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t* source_clk)
|
||||
{
|
||||
*source_clk = hw->conf0.tick_ref_always_on ? UART_SCLK_APB : UART_SCLK_REF_TICK;
|
||||
}
|
||||
@ -89,7 +90,7 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t* source_clk)
|
||||
*
|
||||
* @return Current source clock frequency
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw)
|
||||
{
|
||||
return (hw->conf0.tick_ref_always_on) ? APB_CLK_FREQ : REF_CLK_FREQ;
|
||||
}
|
||||
@ -102,7 +103,7 @@ static inline uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw)
|
||||
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud)
|
||||
{
|
||||
uint32_t sclk_freq, clk_div;
|
||||
|
||||
@ -121,7 +122,7 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud)
|
||||
*
|
||||
* @return The current baudrate
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw)
|
||||
{
|
||||
uint32_t sclk_freq = uart_ll_get_sclk_freq(hw);
|
||||
typeof(hw->clk_div) div_reg = hw->clk_div;
|
||||
@ -136,7 +137,7 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
|
||||
FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
|
||||
{
|
||||
hw->int_ena.val |= mask;
|
||||
}
|
||||
@ -149,7 +150,7 @@ static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
|
||||
FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
|
||||
{
|
||||
hw->int_ena.val &= (~mask);
|
||||
}
|
||||
@ -161,7 +162,7 @@ static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
|
||||
*
|
||||
* @return The UART interrupt status.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
|
||||
{
|
||||
return hw->int_st.val;
|
||||
}
|
||||
@ -174,7 +175,7 @@ static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
|
||||
FORCE_INLINE_ATTR void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
|
||||
{
|
||||
hw->int_clr.val = mask;
|
||||
}
|
||||
@ -186,7 +187,7 @@ static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
|
||||
*
|
||||
* @return interrupt enable value
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
|
||||
{
|
||||
return hw->int_ena.val;
|
||||
}
|
||||
@ -200,7 +201,7 @@ static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
|
||||
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
|
||||
{
|
||||
//Get the UART fifo addr, ESP32-S2 have 2 UART
|
||||
uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_AHB_REG(0) : UART_FIFO_AHB_REG(1);
|
||||
@ -218,7 +219,7 @@ static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
|
||||
FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
|
||||
{
|
||||
//Get the UART fifo addr, ESP32-S2 have 2 UART
|
||||
uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_AHB_REG(0) : UART_FIFO_AHB_REG(1);
|
||||
@ -234,7 +235,7 @@ static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_rxfifo_rst(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw)
|
||||
{
|
||||
hw->conf0.rxfifo_rst = 1;
|
||||
hw->conf0.rxfifo_rst = 0;
|
||||
@ -247,7 +248,7 @@ static inline void uart_ll_rxfifo_rst(uart_dev_t *hw)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_txfifo_rst(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw)
|
||||
{
|
||||
hw->conf0.txfifo_rst = 1;
|
||||
hw->conf0.txfifo_rst = 0;
|
||||
@ -260,7 +261,7 @@ static inline void uart_ll_txfifo_rst(uart_dev_t *hw)
|
||||
*
|
||||
* @return The readable data length in rxfifo.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
|
||||
{
|
||||
return hw->status.rxfifo_cnt;
|
||||
}
|
||||
@ -272,7 +273,7 @@ static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
|
||||
*
|
||||
* @return The data length of txfifo can be written.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
|
||||
{
|
||||
return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt;
|
||||
}
|
||||
@ -285,7 +286,7 @@ static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
|
||||
{
|
||||
hw->conf0.stop_bit_num = stop_bit;
|
||||
}
|
||||
@ -298,7 +299,7 @@ static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_b
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
|
||||
{
|
||||
*stop_bit = hw->conf0.stop_bit_num;
|
||||
}
|
||||
@ -311,7 +312,7 @@ static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
|
||||
{
|
||||
if(parity_mode != UART_PARITY_DISABLE) {
|
||||
hw->conf0.parity = parity_mode & 0x1;
|
||||
@ -327,7 +328,7 @@ static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode)
|
||||
{
|
||||
if(hw->conf0.parity_en) {
|
||||
*parity_mode = 0X2 | hw->conf0.parity;
|
||||
@ -345,7 +346,7 @@ static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
|
||||
{
|
||||
hw->conf1.rxfifo_full_thrhd = full_thrhd;
|
||||
}
|
||||
@ -359,7 +360,7 @@ static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thr
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
|
||||
{
|
||||
hw->conf1.txfifo_empty_thrhd = empty_thrhd;
|
||||
}
|
||||
@ -373,7 +374,7 @@ static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_t
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
|
||||
{
|
||||
hw->idle_conf.rx_idle_thrhd = rx_idle_thr;
|
||||
}
|
||||
@ -386,7 +387,7 @@ static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
|
||||
{
|
||||
hw->idle_conf.tx_idle_num = idle_num;
|
||||
}
|
||||
@ -399,7 +400,7 @@ static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
|
||||
{
|
||||
if(break_num > 0) {
|
||||
hw->idle_conf.tx_brk_num = break_num;
|
||||
@ -418,7 +419,7 @@ static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs)
|
||||
{
|
||||
//only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
|
||||
if(flow_ctrl & UART_HW_FLOWCTRL_RTS) {
|
||||
@ -442,7 +443,7 @@ static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl)
|
||||
{
|
||||
*flow_ctrl = UART_HW_FLOWCTRL_DISABLE;
|
||||
if(hw->conf1.rx_flow_en) {
|
||||
@ -462,7 +463,7 @@ static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en)
|
||||
{
|
||||
if(sw_flow_ctrl_en) {
|
||||
hw->flow_conf.xonoff_del = 1;
|
||||
@ -490,7 +491,7 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
|
||||
{
|
||||
hw->at_cmd_char.data = cmd_char->cmd_char;
|
||||
hw->at_cmd_char.char_num = cmd_char->char_num;
|
||||
@ -507,7 +508,7 @@ static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_ch
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit)
|
||||
{
|
||||
hw->conf0.bit_num = data_bit;
|
||||
}
|
||||
@ -520,7 +521,7 @@ static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t d
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
|
||||
{
|
||||
hw->conf0.sw_rts = level & 0x1;
|
||||
}
|
||||
@ -533,7 +534,7 @@ static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
|
||||
{
|
||||
hw->conf0.sw_dtr = level & 0x1;
|
||||
}
|
||||
@ -547,7 +548,7 @@ static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
|
||||
{
|
||||
hw->sleep_conf.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH;
|
||||
}
|
||||
@ -559,7 +560,7 @@ static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_normal(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw)
|
||||
{
|
||||
hw->rs485_conf.en = 0;
|
||||
hw->rs485_conf.tx_rx_en = 0;
|
||||
@ -574,7 +575,7 @@ static inline void uart_ll_set_mode_normal(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
|
||||
{
|
||||
// Application software control, remove echo
|
||||
hw->rs485_conf.rx_busy_tx_en = 1;
|
||||
@ -591,7 +592,7 @@ static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
|
||||
{
|
||||
// Enable receiver, sw_rts = 1 generates low level on RTS pin
|
||||
hw->conf0.sw_rts = 1;
|
||||
@ -610,7 +611,7 @@ static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
|
||||
{
|
||||
hw->conf0.irda_en = 0;
|
||||
// Transmitters output signal loop back to the receivers input signal
|
||||
@ -628,7 +629,7 @@ static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_irda(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
|
||||
{
|
||||
hw->rs485_conf.en = 0;
|
||||
hw->rs485_conf.tx_rx_en = 0;
|
||||
@ -645,7 +646,7 @@ static inline void uart_ll_set_mode_irda(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
|
||||
{
|
||||
switch (mode) {
|
||||
default:
|
||||
@ -676,7 +677,7 @@ static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
|
||||
{
|
||||
*cmd_char = hw->at_cmd_char.data;
|
||||
*char_num = hw->at_cmd_char.char_num;
|
||||
@ -689,7 +690,7 @@ static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, ui
|
||||
*
|
||||
* @return The UART wakeup threshold value.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
|
||||
{
|
||||
return hw->sleep_conf.active_threshold + UART_LL_MIN_WAKEUP_THRESH;
|
||||
}
|
||||
@ -702,7 +703,7 @@ static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
|
||||
*
|
||||
* @return The bit mode.
|
||||
*/
|
||||
static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
|
||||
{
|
||||
*data_bit = hw->conf0.bit_num;
|
||||
}
|
||||
@ -714,7 +715,7 @@ static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *
|
||||
*
|
||||
* @return True if the state machine is in the IDLE state, otherwise false is returned.
|
||||
*/
|
||||
static inline bool uart_ll_is_tx_idle(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
|
||||
{
|
||||
return ((hw->status.txfifo_cnt == 0) && (hw->fsm_status.st_utx_out == 0));
|
||||
}
|
||||
@ -726,7 +727,7 @@ static inline bool uart_ll_is_tx_idle(uart_dev_t *hw)
|
||||
*
|
||||
* @return True if hw rts flow control is enabled, otherwise false is returned.
|
||||
*/
|
||||
static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
|
||||
{
|
||||
return hw->conf1.rx_flow_en;
|
||||
}
|
||||
@ -738,7 +739,7 @@ static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
|
||||
*
|
||||
* @return True if hw cts flow control is enabled, otherwise false is returned.
|
||||
*/
|
||||
static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
|
||||
{
|
||||
return hw->conf0.tx_flow_en;
|
||||
}
|
||||
@ -751,7 +752,7 @@ static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
|
||||
{
|
||||
hw->conf0.loopback = loop_back_en;
|
||||
}
|
||||
@ -765,7 +766,7 @@ static inline void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
|
||||
FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
|
||||
{
|
||||
typeof(hw->conf0) conf0_reg = hw->conf0;
|
||||
conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0;
|
||||
@ -787,7 +788,7 @@ static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
|
||||
{
|
||||
uint16_t tout_val = tout_thrd;
|
||||
if(tout_thrd > 0) {
|
||||
@ -805,7 +806,7 @@ static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
|
||||
*
|
||||
* @return tout_thr The timeout threshold value. If timeout feature is disabled returns 0.
|
||||
*/
|
||||
static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
|
||||
{
|
||||
uint16_t tout_thrd = 0;
|
||||
if(hw->conf1.rx_tout_en > 0) {
|
||||
@ -821,7 +822,7 @@ static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
|
||||
*
|
||||
* @return maximum timeout threshold.
|
||||
*/
|
||||
static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
|
||||
{
|
||||
return UART_RX_TOUT_THRHD_V;
|
||||
}
|
||||
@ -833,7 +834,7 @@ static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_force_xoff(uart_port_t uart_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_force_xoff(uart_port_t uart_num)
|
||||
{
|
||||
REG_CLR_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XON);
|
||||
REG_SET_BIT(UART_FLOW_CONF_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XOFF);
|
||||
@ -846,7 +847,7 @@ static inline void uart_ll_force_xoff(uart_port_t uart_num)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_force_xon(uart_port_t uart_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_force_xon(uart_port_t uart_num)
|
||||
{
|
||||
REG_CLR_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XOFF);
|
||||
REG_SET_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XON);
|
||||
@ -860,7 +861,7 @@ static inline void uart_ll_force_xon(uart_port_t uart_num)
|
||||
*
|
||||
* @return UART module FSM status.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_fsm_status(uart_port_t uart_num)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_fsm_status(uart_port_t uart_num)
|
||||
{
|
||||
return REG_GET_FIELD(UART_FSM_STATUS_REG(uart_num), UART_ST_UTX_OUT);
|
||||
}
|
||||
|
||||
@ -19,6 +19,7 @@
|
||||
#pragma once
|
||||
#include "hal/uart_types.h"
|
||||
#include "soc/uart_periph.h"
|
||||
#include "esp_attr.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -65,7 +66,7 @@ typedef enum {
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
|
||||
{
|
||||
switch (source_clk) {
|
||||
default:
|
||||
@ -89,7 +90,7 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk)
|
||||
{
|
||||
switch (hw->clk_conf.sclk_sel) {
|
||||
default:
|
||||
@ -112,7 +113,7 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk)
|
||||
*
|
||||
* @return Current source clock frequency
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw)
|
||||
{
|
||||
switch (hw->clk_conf.sclk_sel) {
|
||||
default:
|
||||
@ -133,7 +134,7 @@ static inline uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud)
|
||||
{
|
||||
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
|
||||
uint32_t sclk_freq = uart_ll_get_sclk_freq(hw);
|
||||
@ -156,7 +157,7 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud)
|
||||
*
|
||||
* @return The current baudrate
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw)
|
||||
{
|
||||
uint32_t sclk_freq = uart_ll_get_sclk_freq(hw);
|
||||
typeof(hw->clk_div) div_reg = hw->clk_div;
|
||||
@ -171,7 +172,7 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
|
||||
FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
|
||||
{
|
||||
hw->int_ena.val |= mask;
|
||||
}
|
||||
@ -184,7 +185,7 @@ static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
|
||||
FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
|
||||
{
|
||||
hw->int_ena.val &= (~mask);
|
||||
}
|
||||
@ -196,7 +197,7 @@ static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
|
||||
*
|
||||
* @return The UART interrupt status.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
|
||||
{
|
||||
return hw->int_st.val;
|
||||
}
|
||||
@ -209,7 +210,7 @@ static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
|
||||
FORCE_INLINE_ATTR void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
|
||||
{
|
||||
hw->int_clr.val = mask;
|
||||
}
|
||||
@ -221,7 +222,7 @@ static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
|
||||
*
|
||||
* @return interrupt enable value
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
|
||||
{
|
||||
return hw->int_ena.val;
|
||||
}
|
||||
@ -235,7 +236,7 @@ static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
|
||||
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
|
||||
{
|
||||
for (int i = 0; i < (int)rd_len; i++) {
|
||||
buf[i] = hw->ahb_fifo.rw_byte;
|
||||
@ -251,7 +252,7 @@ static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
|
||||
FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
|
||||
{
|
||||
for (int i = 0; i < (int)wr_len; i++) {
|
||||
hw->ahb_fifo.rw_byte = buf[i];
|
||||
@ -265,7 +266,7 @@ static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_rxfifo_rst(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw)
|
||||
{
|
||||
hw->conf0.rxfifo_rst = 1;
|
||||
hw->conf0.rxfifo_rst = 0;
|
||||
@ -278,7 +279,7 @@ static inline void uart_ll_rxfifo_rst(uart_dev_t *hw)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_txfifo_rst(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw)
|
||||
{
|
||||
hw->conf0.txfifo_rst = 1;
|
||||
hw->conf0.txfifo_rst = 0;
|
||||
@ -291,7 +292,7 @@ static inline void uart_ll_txfifo_rst(uart_dev_t *hw)
|
||||
*
|
||||
* @return The readable data length in rxfifo.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
|
||||
{
|
||||
return hw->status.rxfifo_cnt;
|
||||
}
|
||||
@ -303,7 +304,7 @@ static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
|
||||
*
|
||||
* @return The data length of txfifo can be written.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
|
||||
{
|
||||
return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt;
|
||||
}
|
||||
@ -316,7 +317,7 @@ static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
|
||||
{
|
||||
hw->conf0.stop_bit_num = stop_bit;
|
||||
}
|
||||
@ -329,7 +330,7 @@ static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_b
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
|
||||
{
|
||||
*stop_bit = hw->conf0.stop_bit_num;
|
||||
}
|
||||
@ -342,7 +343,7 @@ static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
|
||||
{
|
||||
if (parity_mode != UART_PARITY_DISABLE) {
|
||||
hw->conf0.parity = parity_mode & 0x1;
|
||||
@ -358,7 +359,7 @@ static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode)
|
||||
{
|
||||
if (hw->conf0.parity_en) {
|
||||
*parity_mode = 0X2 | hw->conf0.parity;
|
||||
@ -376,7 +377,7 @@ static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
|
||||
{
|
||||
hw->conf1.rxfifo_full_thrhd = full_thrhd;
|
||||
}
|
||||
@ -390,7 +391,7 @@ static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thr
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
|
||||
{
|
||||
hw->conf1.txfifo_empty_thrhd = empty_thrhd;
|
||||
}
|
||||
@ -404,7 +405,7 @@ static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_t
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
|
||||
{
|
||||
hw->idle_conf.rx_idle_thrhd = rx_idle_thr;
|
||||
}
|
||||
@ -417,7 +418,7 @@ static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
|
||||
{
|
||||
hw->idle_conf.tx_idle_num = idle_num;
|
||||
}
|
||||
@ -430,7 +431,7 @@ static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
|
||||
{
|
||||
if (break_num > 0) {
|
||||
hw->txbrk_conf.tx_brk_num = break_num;
|
||||
@ -448,7 +449,7 @@ static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs)
|
||||
{
|
||||
//only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
|
||||
if (flow_ctrl & UART_HW_FLOWCTRL_RTS) {
|
||||
@ -472,7 +473,7 @@ static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl)
|
||||
{
|
||||
*flow_ctrl = UART_HW_FLOWCTRL_DISABLE;
|
||||
if (hw->conf1.rx_flow_en) {
|
||||
@ -492,7 +493,7 @@ static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en)
|
||||
{
|
||||
if (sw_flow_ctrl_en) {
|
||||
hw->flow_conf.xonoff_del = 1;
|
||||
@ -520,7 +521,7 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
|
||||
{
|
||||
hw->at_cmd_char.data = cmd_char->cmd_char;
|
||||
hw->at_cmd_char.char_num = cmd_char->char_num;
|
||||
@ -537,12 +538,13 @@ static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_ch
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit)
|
||||
{
|
||||
hw->conf0.bit_num = data_bit;
|
||||
}
|
||||
|
||||
/**
|
||||
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk)
|
||||
* @brief Set the rts active level.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
@ -550,7 +552,7 @@ static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t d
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
|
||||
{
|
||||
hw->conf0.sw_rts = level & 0x1;
|
||||
}
|
||||
@ -563,7 +565,7 @@ static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
|
||||
{
|
||||
hw->conf0.sw_dtr = level & 0x1;
|
||||
}
|
||||
@ -577,7 +579,7 @@ static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
|
||||
{
|
||||
hw->sleep_conf.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH;
|
||||
}
|
||||
@ -589,7 +591,7 @@ static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_normal(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw)
|
||||
{
|
||||
hw->rs485_conf.en = 0;
|
||||
hw->rs485_conf.tx_rx_en = 0;
|
||||
@ -604,7 +606,7 @@ static inline void uart_ll_set_mode_normal(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
|
||||
{
|
||||
// Application software control, remove echo
|
||||
hw->rs485_conf.rx_busy_tx_en = 1;
|
||||
@ -621,7 +623,7 @@ static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
|
||||
{
|
||||
// Enable receiver, sw_rts = 1 generates low level on RTS pin
|
||||
hw->conf0.sw_rts = 1;
|
||||
@ -640,7 +642,7 @@ static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
|
||||
{
|
||||
hw->conf0.irda_en = 0;
|
||||
// Transmitters output signal loop back to the receivers input signal
|
||||
@ -658,7 +660,7 @@ static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_irda(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
|
||||
{
|
||||
hw->rs485_conf.en = 0;
|
||||
hw->rs485_conf.tx_rx_en = 0;
|
||||
@ -675,7 +677,7 @@ static inline void uart_ll_set_mode_irda(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
|
||||
{
|
||||
switch (mode) {
|
||||
default:
|
||||
@ -706,7 +708,7 @@ static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
|
||||
{
|
||||
*cmd_char = hw->at_cmd_char.data;
|
||||
*char_num = hw->at_cmd_char.char_num;
|
||||
@ -719,7 +721,7 @@ static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, ui
|
||||
*
|
||||
* @return The UART wakeup threshold value.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
|
||||
{
|
||||
return hw->sleep_conf.active_threshold + UART_LL_MIN_WAKEUP_THRESH;
|
||||
}
|
||||
@ -732,7 +734,7 @@ static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
|
||||
*
|
||||
* @return The bit mode.
|
||||
*/
|
||||
static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
|
||||
{
|
||||
*data_bit = hw->conf0.bit_num;
|
||||
}
|
||||
@ -744,7 +746,7 @@ static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *
|
||||
*
|
||||
* @return True if the state machine is in the IDLE state, otherwise false is returned.
|
||||
*/
|
||||
static inline bool uart_ll_is_tx_idle(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
|
||||
{
|
||||
return ((hw->status.txfifo_cnt == 0) && (hw->fsm_status.st_utx_out == 0));
|
||||
}
|
||||
@ -756,7 +758,7 @@ static inline bool uart_ll_is_tx_idle(uart_dev_t *hw)
|
||||
*
|
||||
* @return True if hw rts flow control is enabled, otherwise false is returned.
|
||||
*/
|
||||
static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
|
||||
{
|
||||
return hw->conf1.rx_flow_en;
|
||||
}
|
||||
@ -768,7 +770,7 @@ static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
|
||||
*
|
||||
* @return True if hw cts flow control is enabled, otherwise false is returned.
|
||||
*/
|
||||
static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
|
||||
{
|
||||
return hw->conf0.tx_flow_en;
|
||||
}
|
||||
@ -781,7 +783,7 @@ static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
|
||||
{
|
||||
hw->conf0.loopback = loop_back_en;
|
||||
}
|
||||
@ -795,7 +797,7 @@ static inline void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
|
||||
FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
|
||||
{
|
||||
typeof(hw->conf0) conf0_reg = hw->conf0;
|
||||
conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0;
|
||||
@ -817,7 +819,7 @@ static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
|
||||
{
|
||||
uint16_t tout_val = tout_thrd;
|
||||
if(tout_thrd > 0) {
|
||||
@ -835,7 +837,7 @@ static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
|
||||
*
|
||||
* @return tout_thr The timeout threshold value. If timeout feature is disabled returns 0.
|
||||
*/
|
||||
static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
|
||||
{
|
||||
uint16_t tout_thrd = 0;
|
||||
if(hw->conf1.rx_tout_en > 0) {
|
||||
@ -851,7 +853,7 @@ static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
|
||||
*
|
||||
* @return maximum timeout threshold.
|
||||
*/
|
||||
static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
|
||||
{
|
||||
return UART_RX_TOUT_THRHD_V;
|
||||
}
|
||||
@ -876,7 +878,7 @@ static inline void uart_ll_force_xoff(uart_port_t uart_num)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_force_xon(uart_port_t uart_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_force_xon(uart_port_t uart_num)
|
||||
{
|
||||
REG_CLR_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XOFF);
|
||||
REG_SET_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XON);
|
||||
@ -890,7 +892,7 @@ static inline void uart_ll_force_xon(uart_port_t uart_num)
|
||||
*
|
||||
* @return UART module FSM status.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_fsm_status(uart_port_t uart_num)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_fsm_status(uart_port_t uart_num)
|
||||
{
|
||||
return REG_GET_FIELD(UART_FSM_STATUS_REG(uart_num), UART_ST_UTX_OUT);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user