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Merge branch 'staging/improve_riscv_vector_s_file' into 'master'
RISC-V: Fix vectors.S assembly file indentation and macro usage See merge request espressif/esp-idf!15927
This commit is contained in:
Zim Kalinowski
commit
d7d280b9df
@ -1,16 +1,9 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/soc.h"
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#include "soc/interrupt_reg.h"
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#include "riscv/rvruntime-frames.h"
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@ -18,285 +11,274 @@
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#include "sdkconfig.h"
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.equ SAVE_REGS, 32
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.equ CONTEXT_SIZE, (SAVE_REGS * 4)
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.equ panic_from_exception, xt_unhandled_exception
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.equ panic_from_isr, panicHandler
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.equ SAVE_REGS, 32
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.equ CONTEXT_SIZE, (SAVE_REGS * 4)
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.equ panic_from_exception, xt_unhandled_exception
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.equ panic_from_isr, panicHandler
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.macro save_regs
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addi sp, sp, -CONTEXT_SIZE
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sw ra, RV_STK_RA(sp)
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sw tp, RV_STK_TP(sp)
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sw t0, RV_STK_T0(sp)
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sw t1, RV_STK_T1(sp)
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sw t2, RV_STK_T2(sp)
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sw s0, RV_STK_S0(sp)
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sw s1, RV_STK_S1(sp)
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sw a0, RV_STK_A0(sp)
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sw a1, RV_STK_A1(sp)
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sw a2, RV_STK_A2(sp)
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sw a3, RV_STK_A3(sp)
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sw a4, RV_STK_A4(sp)
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sw a5, RV_STK_A5(sp)
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sw a6, RV_STK_A6(sp)
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sw a7, RV_STK_A7(sp)
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sw s2, RV_STK_S2(sp)
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sw s3, RV_STK_S3(sp)
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sw s4, RV_STK_S4(sp)
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sw s5, RV_STK_S5(sp)
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sw s6, RV_STK_S6(sp)
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sw s7, RV_STK_S7(sp)
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sw s8, RV_STK_S8(sp)
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sw s9, RV_STK_S9(sp)
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sw s10, RV_STK_S10(sp)
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sw s11, RV_STK_S11(sp)
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sw t3, RV_STK_T3(sp)
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sw t4, RV_STK_T4(sp)
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sw t5, RV_STK_T5(sp)
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sw t6, RV_STK_T6(sp)
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/* Macro which first allocates space on the stack to save general
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* purpose registers, and then save them. GP register is excluded.
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* The default size allocated on the stack is CONTEXT_SIZE, but it
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* can be overridden. */
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.macro save_general_regs cxt_size=CONTEXT_SIZE
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addi sp, sp, -\cxt_size
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sw ra, RV_STK_RA(sp)
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sw tp, RV_STK_TP(sp)
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sw t0, RV_STK_T0(sp)
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sw t1, RV_STK_T1(sp)
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sw t2, RV_STK_T2(sp)
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sw s0, RV_STK_S0(sp)
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sw s1, RV_STK_S1(sp)
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sw a0, RV_STK_A0(sp)
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sw a1, RV_STK_A1(sp)
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sw a2, RV_STK_A2(sp)
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sw a3, RV_STK_A3(sp)
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sw a4, RV_STK_A4(sp)
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sw a5, RV_STK_A5(sp)
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sw a6, RV_STK_A6(sp)
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sw a7, RV_STK_A7(sp)
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sw s2, RV_STK_S2(sp)
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sw s3, RV_STK_S3(sp)
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sw s4, RV_STK_S4(sp)
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sw s5, RV_STK_S5(sp)
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sw s6, RV_STK_S6(sp)
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sw s7, RV_STK_S7(sp)
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sw s8, RV_STK_S8(sp)
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sw s9, RV_STK_S9(sp)
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sw s10, RV_STK_S10(sp)
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sw s11, RV_STK_S11(sp)
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sw t3, RV_STK_T3(sp)
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sw t4, RV_STK_T4(sp)
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sw t5, RV_STK_T5(sp)
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sw t6, RV_STK_T6(sp)
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.endm
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.macro save_mepc
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csrr t0, mepc
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sw t0, RV_STK_MEPC(sp)
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csrr t0, mepc
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sw t0, RV_STK_MEPC(sp)
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.endm
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.macro restore_regs
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lw ra, RV_STK_RA(sp)
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lw tp, RV_STK_TP(sp)
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lw t0, RV_STK_T0(sp)
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lw t1, RV_STK_T1(sp)
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lw t2, RV_STK_T2(sp)
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lw s0, RV_STK_S0(sp)
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lw s1, RV_STK_S1(sp)
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lw a0, RV_STK_A0(sp)
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lw a1, RV_STK_A1(sp)
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lw a2, RV_STK_A2(sp)
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lw a3, RV_STK_A3(sp)
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lw a4, RV_STK_A4(sp)
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lw a5, RV_STK_A5(sp)
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lw a6, RV_STK_A6(sp)
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lw a7, RV_STK_A7(sp)
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lw s2, RV_STK_S2(sp)
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lw s3, RV_STK_S3(sp)
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lw s4, RV_STK_S4(sp)
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lw s5, RV_STK_S5(sp)
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lw s6, RV_STK_S6(sp)
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lw s7, RV_STK_S7(sp)
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lw s8, RV_STK_S8(sp)
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lw s9, RV_STK_S9(sp)
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lw s10, RV_STK_S10(sp)
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lw s11, RV_STK_S11(sp)
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lw t3, RV_STK_T3(sp)
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lw t4, RV_STK_T4(sp)
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lw t5, RV_STK_T5(sp)
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lw t6, RV_STK_T6(sp)
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addi sp, sp, CONTEXT_SIZE
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/* Restore the general purpose registers (excluding gp) from the context on
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* the stack. The context is then deallocated. The default size is CONTEXT_SIZE
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* but it can be overriden. */
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.macro restore_general_regs cxt_size=CONTEXT_SIZE
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lw ra, RV_STK_RA(sp)
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lw tp, RV_STK_TP(sp)
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lw t0, RV_STK_T0(sp)
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lw t1, RV_STK_T1(sp)
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lw t2, RV_STK_T2(sp)
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lw s0, RV_STK_S0(sp)
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lw s1, RV_STK_S1(sp)
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lw a0, RV_STK_A0(sp)
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lw a1, RV_STK_A1(sp)
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lw a2, RV_STK_A2(sp)
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lw a3, RV_STK_A3(sp)
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lw a4, RV_STK_A4(sp)
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lw a5, RV_STK_A5(sp)
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lw a6, RV_STK_A6(sp)
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lw a7, RV_STK_A7(sp)
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lw s2, RV_STK_S2(sp)
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lw s3, RV_STK_S3(sp)
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lw s4, RV_STK_S4(sp)
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lw s5, RV_STK_S5(sp)
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lw s6, RV_STK_S6(sp)
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lw s7, RV_STK_S7(sp)
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lw s8, RV_STK_S8(sp)
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lw s9, RV_STK_S9(sp)
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lw s10, RV_STK_S10(sp)
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lw s11, RV_STK_S11(sp)
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lw t3, RV_STK_T3(sp)
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lw t4, RV_STK_T4(sp)
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lw t5, RV_STK_T5(sp)
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lw t6, RV_STK_T6(sp)
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addi sp,sp, \cxt_size
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.endm
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.macro restore_mepc
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lw t0, RV_STK_MEPC(sp)
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csrw mepc, t0
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lw t0, RV_STK_MEPC(sp)
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csrw mepc, t0
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.endm
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.global rtos_int_enter
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.global rtos_int_exit
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.global _global_interrupt_handler
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.global rtos_int_enter
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.global rtos_int_exit
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.global _global_interrupt_handler
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.section .exception_vectors.text
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/* This is the vector table. MTVEC points here.
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*
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* Use 4-byte intructions here. 1 instruction = 1 entry of the table.
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* The CPU jumps to MTVEC (i.e. the first entry) in case of an exception,
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* and (MTVEC & 0xfffffffc) + (mcause & 0x7fffffff) * 4, in case of an interrupt.
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*
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* Note: for our CPU, we need to place this on a 256-byte boundary, as CPU
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* only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00).
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*/
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.section .exception_vectors.text
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/* This is the vector table. MTVEC points here.
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*
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* Use 4-byte intructions here. 1 instruction = 1 entry of the table.
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* The CPU jumps to MTVEC (i.e. the first entry) in case of an exception,
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* and (MTVEC & 0xfffffffc) + (mcause & 0x7fffffff) * 4, in case of an interrupt.
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*
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* Note: for our CPU, we need to place this on a 256-byte boundary, as CPU
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* only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00).
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*/
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.balign 0x100
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.global _vector_table
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.type _vector_table, @function
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.balign 0x100
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.global _vector_table
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.type _vector_table, @function
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_vector_table:
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.option push
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.option norvc
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j _panic_handler /* exception handler, entry 0 */
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.rept (ETS_T1_WDT_INUM - 1)
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j _interrupt_handler /* 24 identical entries, all pointing to the interrupt handler */
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.endr
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j _panic_handler /* Call panic handler for ETS_T1_WDT_INUM interrupt (soc-level panic)*/
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.option push
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.option norvc
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j _panic_handler /* exception handler, entry 0 */
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.rept (ETS_T1_WDT_INUM - 1)
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j _interrupt_handler /* 24 identical entries, all pointing to the interrupt handler */
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.endr
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j _panic_handler /* Call panic handler for ETS_T1_WDT_INUM interrupt (soc-level panic)*/
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j _panic_handler /* Call panic handler for ETS_CACHEERR_INUM interrupt (soc-level panic)*/
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#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
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j _panic_handler /* Call panic handler for ETS_MEMPROT_ERR_INUM interrupt (soc-level panic)*/
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.rept (ETS_MAX_INUM - ETS_MEMPROT_ERR_INUM)
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#else
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.rept (ETS_MAX_INUM - ETS_CACHEERR_INUM)
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#endif
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j _interrupt_handler /* 6 identical entries, all pointing to the interrupt handler */
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.endr
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.rept (ETS_MAX_INUM - ETS_MEMPROT_ERR_INUM)
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#else
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.rept (ETS_MAX_INUM - ETS_CACHEERR_INUM)
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#endif //CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
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j _interrupt_handler /* 6 identical entries, all pointing to the interrupt handler */
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.endr
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.option pop
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.size _vector_table, .-_vector_table
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.option pop
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.size _vector_table, .-_vector_table
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/* Exception handler.*/
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.type _panic_handler, @function
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/* Exception handler.*/
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.type _panic_handler, @function
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_panic_handler:
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addi sp, sp, -RV_STK_FRMSZ /* allocate space on stack to store necessary registers */
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/* save general registers */
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sw ra, RV_STK_RA(sp)
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sw gp, RV_STK_GP(sp)
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sw tp, RV_STK_TP(sp)
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sw t0, RV_STK_T0(sp)
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sw t1, RV_STK_T1(sp)
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sw t2, RV_STK_T2(sp)
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sw s0, RV_STK_S0(sp)
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sw s1, RV_STK_S1(sp)
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sw a0, RV_STK_A0(sp)
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sw a1, RV_STK_A1(sp)
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sw a2, RV_STK_A2(sp)
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sw a3, RV_STK_A3(sp)
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sw a4, RV_STK_A4(sp)
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sw a5, RV_STK_A5(sp)
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sw a6, RV_STK_A6(sp)
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sw a7, RV_STK_A7(sp)
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sw s2, RV_STK_S2(sp)
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sw s3, RV_STK_S3(sp)
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sw s4, RV_STK_S4(sp)
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sw s5, RV_STK_S5(sp)
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sw s6, RV_STK_S6(sp)
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sw s7, RV_STK_S7(sp)
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sw s8, RV_STK_S8(sp)
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sw s9, RV_STK_S9(sp)
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sw s10, RV_STK_S10(sp)
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sw s11, RV_STK_S11(sp)
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sw t3, RV_STK_T3(sp)
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sw t4, RV_STK_T4(sp)
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sw t5, RV_STK_T5(sp)
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sw t6, RV_STK_T6(sp)
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addi t0, sp, RV_STK_FRMSZ /* restore sp with the value when trap happened */
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sw t0, RV_STK_SP(sp)
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csrr t0, mepc
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sw t0, RV_STK_MEPC(sp)
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csrr t0, mstatus
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sw t0, RV_STK_MSTATUS(sp)
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csrr t0, mtvec
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sw t0, RV_STK_MTVEC(sp)
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csrr t0, mtval
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sw t0, RV_STK_MTVAL(sp)
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csrr t0, mhartid
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sw t0, RV_STK_MHARTID(sp)
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/* Allocate space on the stack and store general purpose registers */
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save_general_regs RV_STK_FRMSZ
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/* Call panic_from_exception(sp) or panic_from_isr(sp)
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* depending on whether we have a pseudo excause or not.
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* If mcause's highest bit is 1, then an interrupt called this routine,
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* so we have a pseudo excause. Else, it is due to a exception, we don't
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* have an pseudo excause */
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mv a0, sp
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csrr a1, mcause
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/* Branches instructions don't accept immediates values, so use t1 to
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* store our comparator */
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li t0, 0x80000000
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bgeu a1, t0, _call_panic_handler
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sw a1, RV_STK_MCAUSE(sp)
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/* exception_from_panic never returns */
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j panic_from_exception
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/* As gp register is not saved by the macro, save it here */
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sw gp, RV_STK_GP(sp)
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/* Same goes for the SP value before trapping */
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addi t0, sp, RV_STK_FRMSZ /* restore sp with the value when trap happened */
|
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/* Save CSRs */
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sw t0, RV_STK_SP(sp)
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csrr t0, mepc
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sw t0, RV_STK_MEPC(sp)
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csrr t0, mstatus
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sw t0, RV_STK_MSTATUS(sp)
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csrr t0, mtvec
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sw t0, RV_STK_MTVEC(sp)
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csrr t0, mtval
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sw t0, RV_STK_MTVAL(sp)
|
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csrr t0, mhartid
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sw t0, RV_STK_MHARTID(sp)
|
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|
||||
/* Call panic_from_exception(sp) or panic_from_isr(sp)
|
||||
* depending on whether we have a pseudo excause or not.
|
||||
* If mcause's highest bit is 1, then an interrupt called this routine,
|
||||
* so we have a pseudo excause. Else, it is due to a exception, we don't
|
||||
* have an pseudo excause */
|
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mv a0, sp
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csrr a1, mcause
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/* Branches instructions don't accept immediates values, so use t1 to
|
||||
* store our comparator */
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li t0, 0x80000000
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bgeu a1, t0, _call_panic_handler
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sw a1, RV_STK_MCAUSE(sp)
|
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/* exception_from_panic never returns */
|
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j panic_from_exception
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||||
_call_panic_handler:
|
||||
/* Remove highest bit from mcause (a1) register and save it in the
|
||||
* structure */
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||||
not t0, t0
|
||||
and a1, a1, t0
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||||
sw a1, RV_STK_MCAUSE(sp)
|
||||
/* exception_from_isr never returns */
|
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j panic_from_isr
|
||||
.size panic_from_isr, .-panic_from_isr
|
||||
/* Remove highest bit from mcause (a1) register and save it in the
|
||||
* structure */
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not t0, t0
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and a1, a1, t0
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sw a1, RV_STK_MCAUSE(sp)
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/* exception_from_isr never returns */
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j panic_from_isr
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.size panic_from_isr, .-panic_from_isr
|
||||
|
||||
/* This is the interrupt handler.
|
||||
* It saves the registers on the stack,
|
||||
* prepares for interrupt nesting,
|
||||
* re-enables the interrupts,
|
||||
* then jumps to the C dispatcher in interrupt.c.
|
||||
*/
|
||||
.global _interrupt_handler
|
||||
.type _interrupt_handler, @function
|
||||
/* This is the interrupt handler.
|
||||
* It saves the registers on the stack,
|
||||
* prepares for interrupt nesting,
|
||||
* re-enables the interrupts,
|
||||
* then jumps to the C dispatcher in interrupt.c.
|
||||
*/
|
||||
.global _interrupt_handler
|
||||
.type _interrupt_handler, @function
|
||||
_interrupt_handler:
|
||||
/* entry */
|
||||
save_regs
|
||||
save_mepc
|
||||
/* Start by saving the general purpose registers and the PC value before
|
||||
* the interrupt happened. */
|
||||
save_general_regs
|
||||
save_mepc
|
||||
|
||||
/* Before doing anythig preserve the stack pointer */
|
||||
/* It will be saved in current TCB, if needed */
|
||||
mv a0, sp
|
||||
call rtos_int_enter
|
||||
/* Before doing anythig preserve the stack pointer */
|
||||
/* It will be saved in current TCB, if needed */
|
||||
mv a0, sp
|
||||
call rtos_int_enter
|
||||
/* If this is a non-nested interrupt, SP now points to the interrupt stack */
|
||||
|
||||
/* Before dispatch c handler, restore interrupt to enable nested intr */
|
||||
csrr s1, mcause
|
||||
csrr s2, mstatus
|
||||
/* Before dispatch c handler, restore interrupt to enable nested intr */
|
||||
csrr s1, mcause
|
||||
csrr s2, mstatus
|
||||
|
||||
/* Save the interrupt threshold level */
|
||||
la t0, INTERRUPT_CORE0_CPU_INT_THRESH_REG
|
||||
lw s3, 0(t0)
|
||||
/* Save the interrupt threshold level */
|
||||
la t0, INTERRUPT_CORE0_CPU_INT_THRESH_REG
|
||||
lw s3, 0(t0)
|
||||
|
||||
/* Increase interrupt threshold level */
|
||||
li t2, 0x7fffffff
|
||||
and t1, s1, t2 /* t1 = mcause & mask */
|
||||
slli t1, t1, 2 /* t1 = mcause * 4 */
|
||||
la t2, INTC_INT_PRIO_REG(0)
|
||||
add t1, t2, t1 /* t1 = INTC_INT_PRIO_REG + 4 * mcause */
|
||||
lw t2, 0(t1) /* t2 = INTC_INT_PRIO_REG[mcause] */
|
||||
addi t2, t2, 1 /* t2 = t2 +1 */
|
||||
sw t2, 0(t0) /* INTERRUPT_CORE0_CPU_INT_THRESH_REG = t2 */
|
||||
fence
|
||||
/* Increase interrupt threshold level */
|
||||
li t2, 0x7fffffff
|
||||
and t1, s1, t2 /* t1 = mcause & mask */
|
||||
slli t1, t1, 2 /* t1 = mcause * 4 */
|
||||
la t2, INTC_INT_PRIO_REG(0)
|
||||
add t1, t2, t1 /* t1 = INTC_INT_PRIO_REG + 4 * mcause */
|
||||
lw t2, 0(t1) /* t2 = INTC_INT_PRIO_REG[mcause] */
|
||||
addi t2, t2, 1 /* t2 = t2 +1 */
|
||||
sw t2, 0(t0) /* INTERRUPT_CORE0_CPU_INT_THRESH_REG = t2 */
|
||||
fence
|
||||
|
||||
li t0, 0x8
|
||||
csrrs t0, mstatus, t0
|
||||
li t0, 0x8
|
||||
csrrs t0, mstatus, t0
|
||||
/* MIE set. Nested interrupts can now occur */
|
||||
|
||||
#ifdef CONFIG_PM_TRACE
|
||||
li a0, 0 /* = ESP_PM_TRACE_IDLE */
|
||||
#if SOC_CPU_CORES_NUM == 1
|
||||
li a1, 0 /* No need to check core ID on single core hardware */
|
||||
#else
|
||||
csrr a1, mhartid
|
||||
#endif
|
||||
la t0, esp_pm_trace_exit
|
||||
jalr t0 /* absolute jump, avoid the 1 MiB range constraint */
|
||||
#endif
|
||||
#ifdef CONFIG_PM_TRACE
|
||||
li a0, 0 /* = ESP_PM_TRACE_IDLE */
|
||||
#if SOC_CPU_CORES_NUM == 1
|
||||
li a1, 0 /* No need to check core ID on single core hardware */
|
||||
#else
|
||||
csrr a1, mhartid
|
||||
#endif
|
||||
la t0, esp_pm_trace_exit
|
||||
jalr t0 /* absolute jump, avoid the 1 MiB range constraint */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PM_ENABLE
|
||||
la t0, esp_pm_impl_isr_hook
|
||||
jalr t0 /* absolute jump, avoid the 1 MiB range constraint */
|
||||
#endif
|
||||
#ifdef CONFIG_PM_ENABLE
|
||||
la t0, esp_pm_impl_isr_hook
|
||||
jalr t0 /* absolute jump, avoid the 1 MiB range constraint */
|
||||
#endif
|
||||
|
||||
/* call the C dispatcher */
|
||||
mv a0, sp /* argument 1, stack pointer */
|
||||
mv a1, s1 /* argument 2, interrupt number (mcause) */
|
||||
/* mask off the interrupt flag of mcause */
|
||||
li t0, 0x7fffffff
|
||||
and a1, a1, t0
|
||||
jal _global_interrupt_handler
|
||||
/* call the C dispatcher */
|
||||
mv a0, sp /* argument 1, stack pointer */
|
||||
mv a1, s1 /* argument 2, interrupt number (mcause) */
|
||||
/* mask off the interrupt flag of mcause */
|
||||
li t0, 0x7fffffff
|
||||
and a1, a1, t0
|
||||
jal _global_interrupt_handler
|
||||
|
||||
/* After dispatch c handler, disable interrupt to make freertos make context switch */
|
||||
/* After dispatch c handler, disable interrupt to make freertos make context switch */
|
||||
|
||||
li t0, 0x8
|
||||
csrrc t0, mstatus, t0
|
||||
li t0, 0x8
|
||||
csrrc t0, mstatus, t0
|
||||
/* MIE cleared. Nested interrupts are disabled */
|
||||
|
||||
/* restore the interrupt threshold level */
|
||||
la t0, INTERRUPT_CORE0_CPU_INT_THRESH_REG
|
||||
sw s3, 0(t0)
|
||||
fence
|
||||
/* restore the interrupt threshold level */
|
||||
la t0, INTERRUPT_CORE0_CPU_INT_THRESH_REG
|
||||
sw s3, 0(t0)
|
||||
fence
|
||||
|
||||
/* Yield to the next task is needed: */
|
||||
mv a0, sp
|
||||
call rtos_int_exit
|
||||
/* Yield to the next task is needed: */
|
||||
mv a0, sp
|
||||
call rtos_int_exit
|
||||
/* If this is a non-nested interrupt, context switch called, SP now points to back to task stack. */
|
||||
|
||||
/* The next (or current) stack pointer is returned in a0 */
|
||||
mv sp, a0
|
||||
/* The next (or current) stack pointer is returned in a0 */
|
||||
mv sp, a0
|
||||
|
||||
/* restore the rest of the registers */
|
||||
csrw mcause, s1
|
||||
csrw mstatus, s2
|
||||
restore_mepc
|
||||
restore_regs
|
||||
/* restore the rest of the registers */
|
||||
csrw mcause, s1
|
||||
csrw mstatus, s2
|
||||
restore_mepc
|
||||
restore_general_regs
|
||||
|
||||
/* exit, this will also re-enable the interrupts */
|
||||
mret
|
||||
.size _interrupt_handler, .-_interrupt_handler
|
||||
/* exit, this will also re-enable the interrupts */
|
||||
mret
|
||||
.size _interrupt_handler, .-_interrupt_handler
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user