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https://github.com/espressif/esp-idf.git
synced 2024-09-19 14:26:01 -04:00
feat(mbedtls/sha): Support in AXI-DMA SHA driver layer
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853bff88c5
commit
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@ -27,7 +27,7 @@ extern "C" {
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* GDMA_TRIG_PERIPH_SHA
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* @return esp_err_t ESP_FAIL if no GDMA channel available
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*/
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esp_err_t esp_crypto_shared_gdma_start(const lldesc_t *input, const lldesc_t *output, gdma_trigger_peripheral_t peripheral);
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esp_err_t esp_crypto_shared_gdma_start(const lldesc_t *input, const lldesc_t *output, gdma_trigger_peripheral_t peripheral) __attribute__((deprecated("use esp_crypto_shared_gdma_start_axi_ahb instead")));
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/**
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* @brief Start a GDMA transfer on the shared crypto DMA channel
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@ -12,7 +12,7 @@
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#include "hal/crypto_dma_ll.h"
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esp_err_t esp_sha_dma_start(const lldesc_t *input)
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esp_err_t esp_sha_dma_start(const crypto_dma_desc_t *input)
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{
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crypto_dma_ll_set_mode(CRYPTO_DMA_SHA);
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crypto_dma_ll_reset();
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@ -7,7 +7,7 @@
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#include "esp_sha_dma_priv.h"
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#include "esp_crypto_shared_gdma.h"
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esp_err_t esp_sha_dma_start(const lldesc_t *input)
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esp_err_t esp_sha_dma_start(const crypto_dma_desc_t *input)
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{
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return esp_crypto_shared_gdma_start(input, NULL, GDMA_TRIG_PERIPH_SHA);
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return esp_crypto_shared_gdma_start_axi_ahb(input, NULL, GDMA_TRIG_PERIPH_SHA);
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}
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@ -1,21 +1,13 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/lldesc.h"
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#include "soc/soc_caps.h"
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#include "esp_crypto_dma.h"
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#include "esp_err.h"
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#ifdef __cplusplus
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@ -30,7 +22,7 @@ extern "C" {
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* - ESP_OK: Successfully started the DMA
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* - ESP_ERR_INVALID_STATE: No DMA channel available
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*/
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esp_err_t esp_sha_dma_start(const lldesc_t *input);
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esp_err_t esp_sha_dma_start(const crypto_dma_desc_t *input);
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#ifdef __cplusplus
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@ -33,7 +33,7 @@
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#include "esp_memory_utils.h"
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#include "esp_crypto_lock.h"
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#include "esp_attr.h"
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#include "soc/lldesc.h"
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#include "esp_crypto_dma.h"
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#include "esp_cache.h"
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#include "soc/ext_mem_defs.h"
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#include "soc/periph_defs.h"
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@ -58,14 +58,6 @@
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#endif
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const static char *TAG = "esp-sha";
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static bool s_check_dma_capable(const void *p);
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/* These are static due to:
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* * Must be in DMA capable memory, so stack is not a safe place to put them
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* * To avoid having to malloc/free them for every DMA operation
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*/
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static DRAM_ATTR lldesc_t s_dma_descr_input;
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static DRAM_ATTR lldesc_t s_dma_descr_buf;
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void esp_sha_write_digest_state(esp_sha_type sha_type, void *digest_state)
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{
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@ -129,6 +121,16 @@ void esp_sha_release_hardware()
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SHA_RELEASE();
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}
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static bool s_check_dma_capable(const void *p)
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{
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bool is_capable = false;
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#if CONFIG_SPIRAM
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is_capable |= esp_ptr_dma_ext_capable(p);
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#endif
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is_capable |= esp_ptr_dma_capable(p);
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return is_capable;
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}
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/* Hash the input block by block, using non-DMA mode */
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static void esp_sha_block_mode(esp_sha_type sha_type, const uint8_t *input, uint32_t ilen,
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@ -153,10 +155,60 @@ static void esp_sha_block_mode(esp_sha_type sha_type, const uint8_t *input, uint
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}
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}
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/* These are static due to:
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* * Must be in DMA capable memory, so stack is not a safe place to put them
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* * To avoid having to malloc/free them for every DMA operation
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*/
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static DRAM_ATTR crypto_dma_desc_t s_dma_descr_input;
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static DRAM_ATTR crypto_dma_desc_t s_dma_descr_buf;
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/* Performs SHA on multiple blocks at a time */
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static esp_err_t esp_sha_dma_process(esp_sha_type sha_type, const void *input, uint32_t ilen,
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const void *buf, uint32_t buf_len, bool is_first_block)
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{
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int ret = 0;
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crypto_dma_desc_t *dma_descr_head = NULL;
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size_t num_blks = (ilen + buf_len) / block_length(sha_type);
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static int esp_sha_dma_process(esp_sha_type sha_type, const void *input, uint32_t ilen,
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const void *buf, uint32_t buf_len, bool is_first_block);
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memset(&s_dma_descr_input, 0, sizeof(crypto_dma_desc_t));
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memset(&s_dma_descr_buf, 0, sizeof(crypto_dma_desc_t));
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/* DMA descriptor for Memory to DMA-SHA transfer */
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if (ilen) {
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s_dma_descr_input.dw0.length = ilen;
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s_dma_descr_input.dw0.size = ilen;
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s_dma_descr_input.dw0.owner = 1;
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s_dma_descr_input.dw0.suc_eof = 1;
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s_dma_descr_input.buffer = (void *) input;
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dma_descr_head = &s_dma_descr_input;
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}
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/* Check after input to overide head if there is any buf*/
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if (buf_len) {
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s_dma_descr_buf.dw0.length = buf_len;
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s_dma_descr_buf.dw0.size = buf_len;
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s_dma_descr_buf.dw0.owner = 1;
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s_dma_descr_buf.dw0.suc_eof = 1;
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s_dma_descr_buf.buffer = (void *) buf;
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dma_descr_head = &s_dma_descr_buf;
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}
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/* Link DMA lists */
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if (buf_len && ilen) {
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s_dma_descr_buf.dw0.suc_eof = 0;
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s_dma_descr_buf.next = (&s_dma_descr_input);
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}
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if (esp_sha_dma_start(dma_descr_head) != ESP_OK) {
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ESP_LOGE(TAG, "esp_sha_dma_start failed, no DMA channel available");
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return -1;
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}
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sha_hal_hash_dma(sha_type, num_blks, is_first_block);
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sha_hal_wait_idle();
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return ret;
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}
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/* Performs SHA on multiple blocks at a time using DMA
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splits up into smaller operations for inputs that exceed a single DMA list
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@ -235,63 +287,3 @@ cleanup:
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free(dma_cap_buf);
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return ret;
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}
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/* Performs SHA on multiple blocks at a time */
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static esp_err_t esp_sha_dma_process(esp_sha_type sha_type, const void *input, uint32_t ilen,
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const void *buf, uint32_t buf_len, bool is_first_block)
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{
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int ret = 0;
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lldesc_t *dma_descr_head = NULL;
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size_t num_blks = (ilen + buf_len) / block_length(sha_type);
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memset(&s_dma_descr_input, 0, sizeof(lldesc_t));
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memset(&s_dma_descr_buf, 0, sizeof(lldesc_t));
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/* DMA descriptor for Memory to DMA-SHA transfer */
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if (ilen) {
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s_dma_descr_input.length = ilen;
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s_dma_descr_input.size = ilen;
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s_dma_descr_input.owner = 1;
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s_dma_descr_input.eof = 1;
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s_dma_descr_input.buf = (uint8_t *)input;
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dma_descr_head = &s_dma_descr_input;
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}
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/* Check after input to overide head if there is any buf*/
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if (buf_len) {
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s_dma_descr_buf.length = buf_len;
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s_dma_descr_buf.size = buf_len;
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s_dma_descr_buf.owner = 1;
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s_dma_descr_buf.eof = 1;
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s_dma_descr_buf.buf = (uint8_t *)buf;
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dma_descr_head = &s_dma_descr_buf;
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}
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/* Link DMA lists */
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if (buf_len && ilen) {
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s_dma_descr_buf.eof = 0;
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s_dma_descr_buf.empty = (uint32_t)(&s_dma_descr_input);
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}
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if (esp_sha_dma_start(dma_descr_head) != ESP_OK) {
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ESP_LOGE(TAG, "esp_sha_dma_start failed, no DMA channel available");
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return -1;
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}
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sha_hal_hash_dma(sha_type, num_blks, is_first_block);
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sha_hal_wait_idle();
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return ret;
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}
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static bool s_check_dma_capable(const void *p)
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{
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bool is_capable = false;
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#if CONFIG_SPIRAM
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is_capable |= esp_ptr_dma_ext_capable(p);
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#endif
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is_capable |= esp_ptr_dma_capable(p);
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return is_capable;
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}
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@ -519,7 +519,6 @@ components/mbedtls/port/include/sha/sha_parallel_engine.h
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components/mbedtls/port/include/sha1_alt.h
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components/mbedtls/port/include/sha256_alt.h
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components/mbedtls/port/include/sha512_alt.h
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components/mbedtls/port/sha/dma/include/esp_sha_dma_priv.h
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components/mbedtls/port/sha/dma/sha.c
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components/mbedtls/port/sha/parallel_engine/sha.c
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components/nvs_flash/include/nvs_handle.hpp
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