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Merge branch 'bugfix/bbpll_wakeup_reset_v3.2' into 'release/v3.2'
BBPLL reset fixes (backport v3.2) See merge request idf/esp-idf!4011
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commit
d59d9eef4f
@ -39,10 +39,16 @@
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#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_8M / 256)
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#define RTC_SLOW_CLK_FREQ_32K 32768
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/* BBPLL configuration values */
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#define BBPLL_ENDIV5_VAL_320M 0x43
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#define BBPLL_BBADC_DSMP_VAL_320M 0x84
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#define BBPLL_ENDIV5_VAL_480M 0xc3
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#define BBPLL_BBADC_DSMP_VAL_480M 0x74
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#define BBPLL_IR_CAL_DELAY_VAL 0x18
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#define BBPLL_IR_CAL_EXT_CAP_VAL 0x20
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#define BBPLL_OC_ENB_FCAL_VAL 0x9a
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#define BBPLL_OC_ENB_VCON_VAL 0x00
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#define BBPLL_BBADC_CAL_7_0_VAL 0x00
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#define APLL_SDM_STOP_VAL_1 0x09
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#define APLL_SDM_STOP_VAL_2_REV0 0x69
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@ -429,6 +435,13 @@ static void rtc_clk_bbpll_enable()
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
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RTC_CNTL_BIAS_I2C_FORCE_PD | RTC_CNTL_BB_I2C_FORCE_PD |
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RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
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/* reset BBPLL configuration */
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, BBPLL_IR_CAL_DELAY_VAL);
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL);
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL);
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL);
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, BBPLL_BBADC_CAL_7_0_VAL);
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}
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/**
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