From 87b958c814c8824145b47f1dc12ccc284ed2d944 Mon Sep 17 00:00:00 2001 From: Yuriy Shestakov Date: Wed, 18 Aug 2021 23:12:01 +0300 Subject: [PATCH 1/2] Fixed GLITCH_RTC_RST for esp32-c3 revision 3 * Issue: https://github.com/espressif/esp-idf/issues/7082 Signed-off-by: Yuriy Shestakov Closes https://github.com/espressif/esp-idf/issues/7082 Closes https://github.com/espressif/esp-idf/pull/7441 --- components/bootloader_support/src/esp32c3/bootloader_esp32c3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c index 7f022f6560..e561f83fb4 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c +++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c @@ -273,7 +273,8 @@ static inline void bootloader_glitch_reset_disable(void) uint8_t chip_version = bootloader_common_get_chip_revision(); if (chip_version < 2) { REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST); - } else if (chip_version == 2) { + } else { + // checked on ESP32-C3 revisions 2 and 3 REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST | RTC_CNTL_FIB_BOR_RST); } } From bf1dde723331f3a8d0af68d2222cdc98d9b50f04 Mon Sep 17 00:00:00 2001 From: Sachin Parekh Date: Fri, 27 Aug 2021 09:37:52 +0530 Subject: [PATCH 2/2] bootloader: Enable clock glitch detection Reset the device when clock glitch detected. Clock glitch detection is only active in bootloader --- .../subproject/main/ld/esp32/bootloader.ld | 1 + .../subproject/main/ld/esp32c3/bootloader.ld | 1 + .../subproject/main/ld/esp32h2/bootloader.ld | 1 + .../subproject/main/ld/esp32s2/bootloader.ld | 1 + .../subproject/main/ld/esp32s3/bootloader.ld | 1 + components/bootloader_support/CMakeLists.txt | 1 + .../include_bootloader/bootloader_soc.h | 27 ++++++++++++ .../src/bootloader_utility.c | 7 ++++ .../src/esp32/bootloader_soc.c | 21 ++++++++++ .../src/esp32c3/bootloader_esp32c3.c | 31 ++++++++++---- .../src/esp32c3/bootloader_soc.c | 41 +++++++++++++++++++ .../src/esp32h2/bootloader_esp32h2.c | 20 ++++----- .../src/esp32h2/bootloader_soc.c | 41 +++++++++++++++++++ .../src/esp32s2/bootloader_soc.c | 21 ++++++++++ .../src/esp32s3/bootloader_esp32s3.c | 10 +++++ .../src/esp32s3/bootloader_soc.c | 41 +++++++++++++++++++ .../soc/esp32s3/include/soc/rtc_cntl_reg.h | 4 ++ 17 files changed, 250 insertions(+), 20 deletions(-) create mode 100644 components/bootloader_support/include_bootloader/bootloader_soc.h create mode 100644 components/bootloader_support/src/esp32/bootloader_soc.c create mode 100644 components/bootloader_support/src/esp32c3/bootloader_soc.c create mode 100644 components/bootloader_support/src/esp32h2/bootloader_soc.c create mode 100644 components/bootloader_support/src/esp32s2/bootloader_soc.c create mode 100644 components/bootloader_support/src/esp32s3/bootloader_soc.c diff --git a/components/bootloader/subproject/main/ld/esp32/bootloader.ld b/components/bootloader/subproject/main/ld/esp32/bootloader.ld index 0c065d2c0c..30e5a79c45 100644 --- a/components/bootloader/subproject/main/ld/esp32/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32/bootloader.ld @@ -49,6 +49,7 @@ SECTIONS *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*) *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*) *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*) *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) diff --git a/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld b/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld index 4da19b44de..c9b2da7612 100644 --- a/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld @@ -36,6 +36,7 @@ SECTIONS *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*) *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*) *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*) *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) diff --git a/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld b/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld index dc49e09123..c5648b815e 100644 --- a/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld @@ -36,6 +36,7 @@ SECTIONS *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*) *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*) *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*) *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*) diff --git a/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld b/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld index 6ba052d6aa..92e0126cf0 100644 --- a/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld @@ -36,6 +36,7 @@ SECTIONS *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*) *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*) *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*) *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) diff --git a/components/bootloader/subproject/main/ld/esp32s3/bootloader.ld b/components/bootloader/subproject/main/ld/esp32s3/bootloader.ld index 85daecd512..244482f823 100644 --- a/components/bootloader/subproject/main/ld/esp32s3/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32s3/bootloader.ld @@ -37,6 +37,7 @@ SECTIONS *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*) *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*) *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*) *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) diff --git a/components/bootloader_support/CMakeLists.txt b/components/bootloader_support/CMakeLists.txt index f2da1dbb2e..664a59817d 100644 --- a/components/bootloader_support/CMakeLists.txt +++ b/components/bootloader_support/CMakeLists.txt @@ -26,6 +26,7 @@ if(BOOTLOADER_BUILD) "src/bootloader_console_loader.c" "src/bootloader_panic.c" "src/${IDF_TARGET}/bootloader_sha.c" + "src/${IDF_TARGET}/bootloader_soc.c" "src/${IDF_TARGET}/bootloader_${IDF_TARGET}.c" ) list(APPEND priv_requires hal) diff --git a/components/bootloader_support/include_bootloader/bootloader_soc.h b/components/bootloader_support/include_bootloader/bootloader_soc.h new file mode 100644 index 0000000000..a7414fd3f3 --- /dev/null +++ b/components/bootloader_support/include_bootloader/bootloader_soc.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +/** + * @brief Configure analog super WDT reset + * + * @param enable Boolean to enable or disable super WDT reset + */ +void bootloader_ana_super_wdt_reset_config(bool enable); + +/** + * @brief Configure analog brownout reset + * + * @param enable Boolean to enable or disable brownout reset + */ +void bootloader_ana_bod_reset_config(bool enable); + +/** + * @brief Configure analog clock glitch reset + * + * @param enable Boolean to enable or disable clock glitch reset + */ +void bootloader_ana_clock_glitch_reset_config(bool enable); diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c index dddf93f3a8..8533f2b3ce 100644 --- a/components/bootloader_support/src/bootloader_utility.c +++ b/components/bootloader_support/src/bootloader_utility.c @@ -76,6 +76,7 @@ #include "bootloader_utility.h" #include "bootloader_sha.h" #include "bootloader_console.h" +#include "bootloader_soc.h" #include "esp_efuse.h" static const char *TAG = "boot"; @@ -636,6 +637,12 @@ static void load_image(const esp_image_metadata_t *image_data) ESP_LOGI(TAG, "Disabling RNG early entropy source..."); bootloader_random_disable(); + /* Disable glitch reset after all the security checks are completed. + * Glitch detection can be falsely triggered by EMI interference (high RF TX power, etc) + * and to avoid such false alarms, disable it. + */ + bootloader_ana_clock_glitch_reset_config(false); + // copy loaded segments to RAM, set up caches for mapped segments, and start application unpack_load_app(image_data); } diff --git a/components/bootloader_support/src/esp32/bootloader_soc.c b/components/bootloader_support/src/esp32/bootloader_soc.c new file mode 100644 index 0000000000..242a575508 --- /dev/null +++ b/components/bootloader_support/src/esp32/bootloader_soc.c @@ -0,0 +1,21 @@ +/* + * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +void bootloader_ana_super_wdt_reset_config(bool enable) +{ + (void)enable; +} + +void bootloader_ana_bod_reset_config(bool enable) +{ + (void)enable; +} + +void bootloader_ana_clock_glitch_reset_config(bool enable) +{ + (void)enable; +} diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c index e561f83fb4..608654e091 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c +++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c @@ -36,6 +36,7 @@ #include "regi2c_ctrl.h" #include "bootloader_console.h" #include "bootloader_flash_priv.h" +#include "bootloader_soc.h" #include "esp_efuse.h" static const char *TAG = "boot.esp32c3"; @@ -263,7 +264,7 @@ static inline void bootloader_hardware_init(void) } } -static inline void bootloader_glitch_reset_disable(void) +static inline void bootloader_ana_reset_config(void) { /* For origin chip & ECO1: only support swt reset; @@ -271,11 +272,27 @@ static inline void bootloader_glitch_reset_disable(void) For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset. */ uint8_t chip_version = bootloader_common_get_chip_revision(); - if (chip_version < 2) { - REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST); - } else { - // checked on ESP32-C3 revisions 2 and 3 - REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST | RTC_CNTL_FIB_BOR_RST); + switch (chip_version) { + case 0: + case 1: + //Enable WDT reset. Disable BOR and GLITCH reset + bootloader_ana_super_wdt_reset_config(true); + bootloader_ana_bod_reset_config(false); + bootloader_ana_clock_glitch_reset_config(false); + break; + case 2: + //Enable WDT and BOR reset. Disable GLITCH reset + bootloader_ana_super_wdt_reset_config(true); + bootloader_ana_bod_reset_config(true); + bootloader_ana_clock_glitch_reset_config(false); + break; + case 3: + default: + //Enable WDT, BOR, and GLITCH reset + bootloader_ana_super_wdt_reset_config(true); + bootloader_ana_bod_reset_config(true); + bootloader_ana_clock_glitch_reset_config(true); + break; } } @@ -284,7 +301,7 @@ esp_err_t bootloader_init(void) esp_err_t ret = ESP_OK; bootloader_hardware_init(); - bootloader_glitch_reset_disable(); + bootloader_ana_reset_config(); bootloader_super_wdt_auto_feed(); // protect memory region bootloader_init_mem(); diff --git a/components/bootloader_support/src/esp32c3/bootloader_soc.c b/components/bootloader_support/src/esp32c3/bootloader_soc.c new file mode 100644 index 0000000000..7104528a58 --- /dev/null +++ b/components/bootloader_support/src/esp32c3/bootloader_soc.c @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include "soc/soc.h" +#include "soc/rtc_cntl_reg.h" + +void bootloader_ana_super_wdt_reset_config(bool enable) +{ + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); + + if (enable) { + REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); + } else { + REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); + } +} + +void bootloader_ana_bod_reset_config(bool enable) +{ + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST); + + if (enable) { + REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); + } else { + REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); + } +} + +void bootloader_ana_clock_glitch_reset_config(bool enable) +{ + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); + + if (enable) { + REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); + } else { + REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); + } +} diff --git a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c index a483b34ceb..7ff27dd693 100644 --- a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c +++ b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c @@ -36,6 +36,7 @@ #include "regi2c_ctrl.h" #include "bootloader_console.h" #include "bootloader_flash_priv.h" +#include "bootloader_soc.h" static const char *TAG = "boot.esp32h2"; @@ -257,19 +258,12 @@ static inline void bootloader_hardware_init(void) } -static inline void bootloader_glitch_reset_disable(void) +static inline void bootloader_ana_reset_config(void) { - /* - For origin chip & ECO1: only support swt reset; - For ECO2: fix brownout reset bug, support swt & brownout reset; - For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset. - */ - uint8_t chip_version = bootloader_common_get_chip_revision(); - if (chip_version < 2) { - REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST); - } else if (chip_version == 2) { - REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST | RTC_CNTL_FIB_BOR_RST); - } + //Enable WDT, BOR, and GLITCH reset + bootloader_ana_super_wdt_reset_config(true); + bootloader_ana_bod_reset_config(true); + bootloader_ana_clock_glitch_reset_config(true); } esp_err_t bootloader_init(void) @@ -277,7 +271,7 @@ esp_err_t bootloader_init(void) esp_err_t ret = ESP_OK; bootloader_hardware_init(); - bootloader_glitch_reset_disable(); + bootloader_ana_reset_config(); bootloader_super_wdt_auto_feed(); // protect memory region bootloader_init_mem(); diff --git a/components/bootloader_support/src/esp32h2/bootloader_soc.c b/components/bootloader_support/src/esp32h2/bootloader_soc.c new file mode 100644 index 0000000000..7104528a58 --- /dev/null +++ b/components/bootloader_support/src/esp32h2/bootloader_soc.c @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include "soc/soc.h" +#include "soc/rtc_cntl_reg.h" + +void bootloader_ana_super_wdt_reset_config(bool enable) +{ + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); + + if (enable) { + REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); + } else { + REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); + } +} + +void bootloader_ana_bod_reset_config(bool enable) +{ + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST); + + if (enable) { + REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); + } else { + REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); + } +} + +void bootloader_ana_clock_glitch_reset_config(bool enable) +{ + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); + + if (enable) { + REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); + } else { + REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); + } +} diff --git a/components/bootloader_support/src/esp32s2/bootloader_soc.c b/components/bootloader_support/src/esp32s2/bootloader_soc.c new file mode 100644 index 0000000000..242a575508 --- /dev/null +++ b/components/bootloader_support/src/esp32s2/bootloader_soc.c @@ -0,0 +1,21 @@ +/* + * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +void bootloader_ana_super_wdt_reset_config(bool enable) +{ + (void)enable; +} + +void bootloader_ana_bod_reset_config(bool enable) +{ + (void)enable; +} + +void bootloader_ana_clock_glitch_reset_config(bool enable) +{ + (void)enable; +} diff --git a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c index f4aae147b2..8346b00d02 100644 --- a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c +++ b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c @@ -34,6 +34,7 @@ #include "bootloader_mem.h" #include "bootloader_console.h" #include "bootloader_flash_priv.h" +#include "bootloader_soc.h" #include "esp_efuse.h" @@ -296,9 +297,18 @@ static void bootloader_super_wdt_auto_feed(void) REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0); } +static inline void bootloader_ana_reset_config(void) +{ + //Enable WDT, BOR, and GLITCH reset + bootloader_ana_super_wdt_reset_config(true); + bootloader_ana_bod_reset_config(true); + bootloader_ana_clock_glitch_reset_config(true); +} + esp_err_t bootloader_init(void) { esp_err_t ret = ESP_OK; + bootloader_ana_reset_config(); bootloader_super_wdt_auto_feed(); // protect memory region bootloader_init_mem(); diff --git a/components/bootloader_support/src/esp32s3/bootloader_soc.c b/components/bootloader_support/src/esp32s3/bootloader_soc.c new file mode 100644 index 0000000000..7104528a58 --- /dev/null +++ b/components/bootloader_support/src/esp32s3/bootloader_soc.c @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include "soc/soc.h" +#include "soc/rtc_cntl_reg.h" + +void bootloader_ana_super_wdt_reset_config(bool enable) +{ + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); + + if (enable) { + REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); + } else { + REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); + } +} + +void bootloader_ana_bod_reset_config(bool enable) +{ + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST); + + if (enable) { + REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); + } else { + REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); + } +} + +void bootloader_ana_clock_glitch_reset_config(bool enable) +{ + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); + + if (enable) { + REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); + } else { + REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); + } +} diff --git a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h index 353c0a53e2..4f15782f5b 100644 --- a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h @@ -3584,6 +3584,10 @@ ork.*/ #define RTC_CNTL_FIB_SEL_V 0x7 #define RTC_CNTL_FIB_SEL_S 0 +#define RTC_CNTL_FIB_GLITCH_RST BIT(0) +#define RTC_CNTL_FIB_BOR_RST BIT(1) +#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) + #define RTC_CNTL_TOUCH_DAC_REG (DR_REG_RTCCNTL_BASE + 0x14C) /* RTC_CNTL_TOUCH_PAD0_DAC : R/W ;bitpos:[31:29] ;default: 3'd0 ; */ /*description: .*/