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soc: remove param checking in cpu related abstractions

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This commit is contained in:
Renz Christian Bagaporo 2020-02-21 08:27:14 +05:00
parent f75cb2ef00
commit d46989efa3
7 changed files with 16 additions and 75 deletions
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20
components/soc/include/hal/cpu_hal.h
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@ -76,21 +76,15 @@ extern "C" {
*
* @param id breakpoint to set [0..SOC_CPU_BREAKPOINTS_NUM - 1]
* @param addr address to set a breakpoint on
*
* @return ESP_OK success
* @return others fail
*/
esp_err_t cpu_hal_set_breakpoint(int id, const void* addr);
void cpu_hal_set_breakpoint(int id, const void* addr);
/**
* Clear and disable breakpoint.
*
* @param id breakpoint to clear [0..SOC_CPU_BREAKPOINTS_NUM - 1]
*
* @return ESP_OK success
* @return others fail
*/
esp_err_t cpu_hal_clear_breakpoint(int id);
void cpu_hal_clear_breakpoint(int id);
#endif // SOC_CPU_BREAKPOINTS_NUM > 0
@ -103,21 +97,15 @@ esp_err_t cpu_hal_clear_breakpoint(int id);
* @param addr starting address
* @param size number of bytes from starting address to watch
* @param trigger operation on specified memory range that triggers the watchpoint (read, write, read/write)
*
* @return ESP_OK success
* @return others fail
*/
esp_err_t cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoint_trigger_t trigger);
void cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoint_trigger_t trigger);
/**
* Clear and disable watchpoint.
*
* @param id watchpoint to clear [0..SOC_CPU_WATCHPOINTS_NUM - 1]
*
* @return ESP_OK success
* @return others fail
*/
esp_err_t cpu_hal_clear_watchpoint(int id);
void cpu_hal_clear_watchpoint(int id);
#endif // SOC_CPU_WATCHPOINTS_NUM > 0

5
components/soc/include/hal/mpu_hal.h
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@ -28,11 +28,8 @@ extern "C" {
* @param id index to the region table; on targets not SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED,
* the region divisions is predefined in hardware which is likely reflected in LL implementation.
* @param access type of access allowed
*
* @return ESP_OK success
* @return others fail
*/
esp_err_t mpu_hal_set_region_access(int id, mpu_access_t access);
void mpu_hal_set_region_access(int id, mpu_access_t access);
#ifdef __cplusplus
}

6
components/soc/include/hal/soc_hal.h
View File

@ -17,8 +17,9 @@
#include <stdint.h>
#include <stdbool.h>
#include "hal/cpu_hal.h"
#include "soc/soc_caps.h"
#include "hal/cpu_hal.h"
#include "hal/soc_ll.h"
#include "esp_err.h"
@ -27,7 +28,6 @@ extern "C" {
#endif
#if SOC_CPU_CORES_NUM > 1
// Utility functions for multicore targets
#define __SOC_HAL_PERFORM_ON_OTHER_CORES(action) { \
for (int i = 0, cur = cpu_hal_get_core_id(); i < SOC_CPU_CORES_NUM; i++) { \
@ -68,7 +68,7 @@ void soc_hal_unstall_core(int core);
*
* @param core core to reset [0..SOC_CPU_CORES_NUM - 1]
*/
void soc_hal_reset_core(int core);
#define soc_hal_reset_core(core) soc_ll_reset_core((core))
#ifdef __cplusplus
}

3
components/soc/src/cpu_util.c
View File

@ -65,7 +65,8 @@ esp_err_t IRAM_ATTR esp_set_watchpoint(int no, void *adr, int size, int flags)
return ESP_ERR_INVALID_ARG;
}
return cpu_hal_set_watchpoint(no, adr, size, trigger);
cpu_hal_set_watchpoint(no, adr, size, trigger);
return ESP_OK;
}
void IRAM_ATTR esp_clear_watchpoint(int no)

24
components/soc/src/hal/cpu_hal.c
View File

@ -22,33 +22,21 @@
#include "soc/cpu_caps.h"
#define CHECK(cond) { if (!(cond)) abort(); }
#if SOC_CPU_BREAKPOINTS_NUM > 0
esp_err_t cpu_hal_set_breakpoint(int id, const void* addr)
void cpu_hal_set_breakpoint(int id, const void* addr)
{
CHECK(id < SOC_CPU_BREAKPOINTS_NUM && id >= 0);
cpu_ll_set_breakpoint(id, cpu_ll_ptr_to_pc(addr));
return ESP_OK;
}
esp_err_t cpu_hal_clear_breakpoint(int id)
void cpu_hal_clear_breakpoint(int id)
{
CHECK(id < SOC_CPU_BREAKPOINTS_NUM && id >= 0);
cpu_ll_clear_breakpoint(id);
return ESP_OK;
}
#endif // SOC_CPU_BREAKPOINTS_NUM > 0
#if SOC_CPU_WATCHPOINTS_NUM > 0
esp_err_t cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoint_trigger_t trigger)
void cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoint_trigger_t trigger)
{
CHECK(id < SOC_CPU_WATCHPOINTS_NUM && id >= 0);
CHECK(size <= SOC_CPU_WATCHPOINT_SIZE);
CHECK(trigger == WATCHPOINT_TRIGGER_ON_RO ||
trigger == WATCHPOINT_TRIGGER_ON_WO ||
trigger == WATCHPOINT_TRIGGER_ON_RW);
bool on_read = false, on_write = false;
if (trigger == WATCHPOINT_TRIGGER_ON_RO) {
@ -60,14 +48,10 @@ esp_err_t cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoi
}
cpu_ll_set_watchpoint(id, addr, size, on_read, on_write);
return ESP_OK;
}
esp_err_t cpu_hal_clear_watchpoint(int id)
void cpu_hal_clear_watchpoint(int id)
{
CHECK(id < SOC_CPU_WATCHPOINTS_NUM && id >= 0);
cpu_ll_clear_watchpoint(id);
return ESP_OK;
}
#endif // SOC_CPU_WATCHPOINTS_NUM > 0

19
components/soc/src/hal/mpu_hal.c
View File

@ -23,23 +23,8 @@
#include "soc/mpu_caps.h"
#define CHECK(cond) { if (!(cond)) abort(); }
esp_err_t mpu_hal_set_region_access(int id, mpu_access_t access)
void mpu_hal_set_region_access(int id, mpu_access_t access)
{
CHECK(id < SOC_MPU_REGIONS_MAX_NUM && id >= 0);
CHECK(
#if SOC_MPU_REGION_RO_SUPPORTED
access == MPU_REGION_RO ||
#endif
#if SOC_MPU_REGION_WO_SUPPORTED
access == MPU_REGION_WO ||
#endif
access == MPU_REGION_RW ||
access == MPU_REGION_X ||
access == MPU_REGION_RWX ||
access == MPU_REGION_ILLEGAL);
uint32_t addr = cpu_ll_id_to_addr(id);
switch (access)
@ -66,6 +51,4 @@ esp_err_t mpu_hal_set_region_access(int id, mpu_access_t access)
default:
break;
}
return ESP_OK;
}

14
components/soc/src/hal/soc_hal.c
View File

@ -21,26 +21,14 @@
#include "hal/soc_ll.h"
#include "soc/soc_caps.h"
#define CHECK(cond) { if (!(cond)) abort(); }
#if SOC_CPU_CORES_NUM > 1
void soc_hal_stall_core(int core)
{
CHECK(core < SOC_CPU_CORES_NUM && core >= 0);
soc_ll_stall_core(core);
}
void soc_hal_unstall_core(int core)
{
CHECK(core < SOC_CPU_CORES_NUM && core >= 0);
soc_ll_unstall_core(core);
}
#endif // SOC_CPU_CORES_NUM > 1
void soc_hal_reset_core(int core)
{
CHECK(core < SOC_CPU_CORES_NUM && core >= 0);
soc_ll_reset_core(core);
}
#endif // SOC_CPU_CORES_NUM > 1