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rtc: support access internal i2c register
This commit is contained in:
fuzhibo
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parent
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commit
d337559a17
@ -39,6 +39,7 @@ SECTIONS
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*libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
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*libspi_flash.a:*.*(.literal .text .literal.* .text.*)
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*libsoc.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
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*libsoc.a:i2c_rtc_clk.*(.literal .text .literal.* .text.*)
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*libefuse.a:*.*(.literal .text .literal.* .text.*)
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*(.fini.literal)
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*(.fini)
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77
components/soc/soc/esp32s2/i2c_saradc.h
Normal file
77
components/soc/soc/esp32s2/i2c_saradc.h
Normal file
@ -0,0 +1,77 @@
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// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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/**
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* @file i2c_sar.h
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* @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC.
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*
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* This file lists register fields of SAR, located on an internal configuration
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* bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
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* function in adc_ll.h.
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*/
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#define I2C_SAR_ADC 0X69
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#define I2C_SAR_ADC_HOSTID 0
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#define ADC_ANA_CONFIG2_REG 0x6000E048
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#define ADC_SAR1_ENCAL_GND_ADDR 0x7
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#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
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#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
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#define ADC_SAR2_ENCAL_GND_ADDR 0x7
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#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
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#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
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#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
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#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
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#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
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#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0
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#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
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#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
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#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
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#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
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#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
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#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
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#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
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#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
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#define ADC_SAR1_DREF_ADDR 0x2
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#define ADC_SAR1_DREF_ADDR_MSB 0x6
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#define ADC_SAR1_DREF_ADDR_LSB 0x4
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#define ADC_SAR2_DREF_ADDR 0x5
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#define ADC_SAR2_DREF_ADDR_MSB 0x6
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#define ADC_SAR2_DREF_ADDR_LSB 0x4
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#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
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#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
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#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
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#define ADC_SARADC_DTEST_RTC_ADDR 0x7
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#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1
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#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0
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#define ADC_SARADC_ENT_TSENS_ADDR 0x7
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#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2
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#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2
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#define ADC_SARADC_ENT_RTC_ADDR 0x7
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#define ADC_SARADC_ENT_RTC_ADDR_MSB 3
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#define ADC_SARADC_ENT_RTC_ADDR_LSB 3
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@ -2,6 +2,7 @@ set(srcs "adc_hal.c"
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"dac_hal.c"
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"brownout_hal.c"
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"rtc_clk.c"
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"i2c_rtc_clk.c"
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"rtc_clk_init.c"
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"rtc_init.c"
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"rtc_pm.c"
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169
components/soc/src/esp32s2/i2c_rtc_clk.c
Normal file
169
components/soc/src/esp32s2/i2c_rtc_clk.c
Normal file
@ -0,0 +1,169 @@
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// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp_err.h"
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#include "soc/soc.h"
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#include "soc/apb_ctrl_reg.h"
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#include "i2c_rtc_clk.h"
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#include "i2c_brownout.h"
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#include "esp_log.h"
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#define I2C_RTC_WIFI_CLK_EN (APB_CTRL_WIFI_CLK_EN_REG)
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#define I2C_RTC_CLK_GATE_EN (BIT(18))
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#define I2C_RTC_CLK_GATE_EN_M (BIT(18))
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#define I2C_RTC_CLK_GATE_EN_V 0x1
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#define I2C_RTC_CLK_GATE_EN_S 18
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#define I2C_RTC_CONFIG0 0x6000e048
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#define I2C_RTC_MAGIC_CTRL 0x00001FFF
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#define I2C_RTC_MAGIC_CTRL_M ((I2C_RTC_MAGIC_CTRL_V)<<(I2C_RTC_MAGIC_CTRL_S))
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#define I2C_RTC_MAGIC_CTRL_V 0x1FFF
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#define I2C_RTC_MAGIC_CTRL_S 4
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#define I2C_RTC_CONFIG1 0x6000e044
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#define I2C_RTC_BOD_MASK (BIT(22))
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#define I2C_RTC_BOD_MASK_M (BIT(22))
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#define I2C_RTC_BOD_MASK_V 0x1
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#define I2C_RTC_BOD_MASK_S 22
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#define I2C_RTC_SAR_MASK (BIT(18))
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#define I2C_RTC_SAR_MASK_M (BIT(18))
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#define I2C_RTC_SAR_MASK_V 0x1
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#define I2C_RTC_SAR_MASK_S 18
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#define I2C_RTC_BBPLL_MASK (BIT(17))
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#define I2C_RTC_BBPLL_MASK_M (BIT(17))
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#define I2C_RTC_BBPLL_MASK_V 0x1
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#define I2C_RTC_BBPLL_MASK_S 17
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#define I2C_RTC_APLL_MASK (BIT(14))
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#define I2C_RTC_APLL_MASK_M (BIT(14))
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#define I2C_RTC_APLL_MASK_V 0x1
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#define I2C_RTC_APLL_MASK_S 14
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#define I2C_RTC_ALL_MASK 0x00007FFF
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#define I2C_RTC_ALL_MASK_M ((I2C_RTC_ALL_MASK_V)<<(I2C_RTC_ALL_MASK_S))
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#define I2C_RTC_ALL_MASK_V 0x7FFF
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#define I2C_RTC_ALL_MASK_S 8
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#define I2C_RTC_CONFIG2 0x6000e000
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#define I2C_RTC_BUSY (BIT(25))
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#define I2C_RTC_BUSY_M (BIT(25))
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#define I2C_RTC_BUSY_V 0x1
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#define I2C_RTC_BUSY_S 25
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#define I2C_RTC_WR_CNTL (BIT(24))
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#define I2C_RTC_WR_CNTL_M (BIT(24))
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#define I2C_RTC_WR_CNTL_V 0x1
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#define I2C_RTC_WR_CNTL_S 24
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#define I2C_RTC_DATA 0x000000FF
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#define I2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S))
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#define I2C_RTC_DATA_V 0xFF
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#define I2C_RTC_DATA_S 16
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#define I2C_RTC_ADDR 0x000000FF
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#define I2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S))
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#define I2C_RTC_ADDR_V 0xFF
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#define I2C_RTC_ADDR_S 8
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#define I2C_RTC_SLAVE_ID 0x000000FF
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#define I2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S))
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#define I2C_RTC_SLAVE_ID_V 0xFF
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#define I2C_RTC_SLAVE_ID_S 0
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#define I2C_RTC_MAGIC_DEFAULT (0x1c40)
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static void i2c_rtc_enable_block(uint8_t block)
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{
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REG_SET_FIELD(I2C_RTC_CONFIG0, I2C_RTC_MAGIC_CTRL, I2C_RTC_MAGIC_DEFAULT);
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REG_SET_FIELD(I2C_RTC_CONFIG1, I2C_RTC_ALL_MASK, I2C_RTC_ALL_MASK_V);
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REG_SET_BIT(I2C_RTC_WIFI_CLK_EN, I2C_RTC_CLK_GATE_EN);
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switch (block) {
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case I2C_APLL:
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REG_CLR_BIT(I2C_RTC_CONFIG1, I2C_RTC_APLL_MASK);
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break;
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case I2C_BBPLL:
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REG_CLR_BIT(I2C_RTC_CONFIG1, I2C_RTC_BBPLL_MASK);
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break;
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case I2C_SAR_ADC:
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REG_CLR_BIT(I2C_RTC_CONFIG1, I2C_RTC_SAR_MASK);
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break;
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case I2C_BOD:
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REG_CLR_BIT(I2C_RTC_CONFIG1, I2C_RTC_BOD_MASK);
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break;
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}
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}
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uint8_t i2c_rtc_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add)
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{
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i2c_rtc_enable_block(block);
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uint32_t temp = ((block & I2C_RTC_SLAVE_ID_V) << I2C_RTC_SLAVE_ID_S)
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| (reg_add & I2C_RTC_ADDR_V) << I2C_RTC_ADDR_S;
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REG_WRITE(I2C_RTC_CONFIG2, temp);
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while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
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return REG_GET_FIELD(I2C_RTC_CONFIG2, I2C_RTC_DATA);
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}
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uint8_t i2c_rtc_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
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{
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assert(msb - lsb < 8);
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i2c_rtc_enable_block(block);
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uint32_t temp = ((block & I2C_RTC_SLAVE_ID_V) << I2C_RTC_SLAVE_ID_S)
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| (reg_add & I2C_RTC_ADDR_V) << I2C_RTC_ADDR_S;
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REG_WRITE(I2C_RTC_CONFIG2, temp);
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while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
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uint32_t data = REG_GET_FIELD(I2C_RTC_CONFIG2, I2C_RTC_DATA);
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return (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1))));
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}
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void i2c_rtc_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
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{
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i2c_rtc_enable_block(block);
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uint32_t temp = ((block & I2C_RTC_SLAVE_ID_V) << I2C_RTC_SLAVE_ID_S)
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| ((reg_add & I2C_RTC_ADDR_V) << I2C_RTC_ADDR_S)
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| ((0x1 & I2C_RTC_WR_CNTL_V) << I2C_RTC_WR_CNTL_S)
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| (((uint32_t)data & I2C_RTC_DATA_V) << I2C_RTC_DATA_S);
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REG_WRITE(I2C_RTC_CONFIG2, temp);
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while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
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}
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void i2c_rtc_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
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{
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assert(msb - lsb < 8);
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i2c_rtc_enable_block(block);
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/*Read the i2c bus register*/
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uint32_t temp = ((block & I2C_RTC_SLAVE_ID_V) << I2C_RTC_SLAVE_ID_S)
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| (reg_add & I2C_RTC_ADDR_V) << I2C_RTC_ADDR_S;
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REG_WRITE(I2C_RTC_CONFIG2, temp);
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while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
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temp = REG_GET_FIELD(I2C_RTC_CONFIG2, I2C_RTC_DATA);
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/*Write the i2c bus register*/
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temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1)));
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temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp;
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temp = ((block & I2C_RTC_SLAVE_ID_V) << I2C_RTC_SLAVE_ID_S)
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| ((reg_add & I2C_RTC_ADDR_V) << I2C_RTC_ADDR_S)
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| ((0x1 & I2C_RTC_WR_CNTL_V) << I2C_RTC_WR_CNTL_S)
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| ((temp & I2C_RTC_DATA_V) << I2C_RTC_DATA_S);
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REG_WRITE(I2C_RTC_CONFIG2, temp);
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while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
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}
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@ -17,6 +17,7 @@
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#include "i2c_apll.h"
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#include "i2c_bbpll.h"
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#include "i2c_ulp.h"
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#include "i2c_saradc.h"
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#ifdef __cplusplus
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extern "C" {
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@ -31,26 +32,27 @@ extern "C" {
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/* Clear to enable BBPLL */
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#define I2C_BBPLL_M (BIT(17))
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/* ROM functions which read/write internal control bus */
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uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
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uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
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void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
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void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
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/* Read/Write internal control bus */
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uint8_t i2c_rtc_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add);
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uint8_t i2c_rtc_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
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void i2c_rtc_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
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void i2c_rtc_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
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void i2c_rtc_init(void);
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/* Convenience macros for the above functions, these use register definitions
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* from i2c_apll.h/i2c_bbpll.h header files.
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*/
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#define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \
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rom_i2c_writeReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
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i2c_rtc_write_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
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#define I2C_READREG_MASK_RTC(block, reg_add) \
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rom_i2c_readReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
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i2c_rtc_read_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
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#define I2C_WRITEREG_RTC(block, reg_add, indata) \
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rom_i2c_writeReg(block, block##_HOSTID, reg_add, indata)
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i2c_rtc_write_reg(block, block##_HOSTID, reg_add, indata)
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#define I2C_READREG_RTC(block, reg_add) \
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rom_i2c_readReg(block, block##_HOSTID, reg_add)
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i2c_rtc_read_reg(block, block##_HOSTID, reg_add)
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#ifdef __cplusplus
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}
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@ -69,62 +69,6 @@ typedef enum {
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ADC2_CTRL_FORCE_DIG = 6, /*!<For ADC2. Arbiter in shield mode. Force select digital controller work. */
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} adc_controller_t;
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/* ADC calibration defines. */
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#define ADC_LL_I2C_ADC 0X69
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#define ADC_LL_I2C_ADC_HOSTID 0
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#define ADC_LL_ANA_CONFIG2_REG 0x6000E048
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#define ADC_LL_SAR1_ENCAL_GND_ADDR 0x7
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#define ADC_LL_SAR1_ENCAL_GND_ADDR_MSB 5
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#define ADC_LL_SAR1_ENCAL_GND_ADDR_LSB 5
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#define ADC_LL_SAR2_ENCAL_GND_ADDR 0x7
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#define ADC_LL_SAR2_ENCAL_GND_ADDR_MSB 7
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#define ADC_LL_SAR2_ENCAL_GND_ADDR_LSB 7
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#define ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
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#define ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
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#define ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
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#define ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR 0x0
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#define ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
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#define ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
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#define ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
|
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#define ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
|
||||
#define ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR 0x3
|
||||
#define ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
|
||||
#define ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_LL_SAR1_DREF_ADDR 0x2
|
||||
#define ADC_LL_SAR1_DREF_ADDR_MSB 0x6
|
||||
#define ADC_LL_SAR1_DREF_ADDR_LSB 0x4
|
||||
|
||||
#define ADC_LL_SAR2_DREF_ADDR 0x5
|
||||
#define ADC_LL_SAR2_DREF_ADDR_MSB 0x6
|
||||
#define ADC_LL_SAR2_DREF_ADDR_LSB 0x4
|
||||
|
||||
#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR 0x2
|
||||
#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
|
||||
#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_LL_SARADC_DTEST_RTC_ADDR 0x7
|
||||
#define ADC_LL_SARADC_DTEST_RTC_ADDR_MSB 1
|
||||
#define ADC_LL_SARADC_DTEST_RTC_ADDR_LSB 0
|
||||
|
||||
#define ADC_LL_SARADC_ENT_TSENS_ADDR 0x7
|
||||
#define ADC_LL_SARADC_ENT_TSENS_ADDR_MSB 2
|
||||
#define ADC_LL_SARADC_ENT_TSENS_ADDR_LSB 2
|
||||
|
||||
#define ADC_LL_SARADC_ENT_RTC_ADDR 0x7
|
||||
#define ADC_LL_SARADC_ENT_RTC_ADDR_MSB 3
|
||||
#define ADC_LL_SARADC_ENT_RTC_ADDR_LSB 3
|
||||
|
||||
/* ADC calibration defines end. */
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Digital controller setting
|
||||
---------------------------------------------------------------*/
|
||||
@ -155,13 +99,11 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa
|
||||
static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
|
||||
{
|
||||
/* Should be called before writing I2C registers. */
|
||||
void phy_get_romfunc_addr(void);
|
||||
phy_get_romfunc_addr();
|
||||
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
|
||||
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
|
||||
SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16));
|
||||
SET_PERI_REG_MASK(ADC_ANA_CONFIG2_REG, BIT(16));
|
||||
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -1194,27 +1136,25 @@ static inline void adc_ll_disable_sleep_controller(void)
|
||||
static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t channel, bool internal_gnd)
|
||||
{
|
||||
/* Should be called before writing I2C registers. */
|
||||
void phy_get_romfunc_addr(void);
|
||||
phy_get_romfunc_addr();
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M);
|
||||
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
|
||||
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
|
||||
SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16));
|
||||
SET_PERI_REG_MASK(ADC_ANA_CONFIG2_REG, BIT(16));
|
||||
|
||||
/* Enable/disable internal connect GND (for calibration). */
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_DREF_ADDR, 4);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 4);
|
||||
if (internal_gnd) {
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_ENCAL_GND_ADDR, 1);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1);
|
||||
} else {
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_ENCAL_GND_ADDR, 0);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
|
||||
}
|
||||
} else {
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_DREF_ADDR, 4);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 4);
|
||||
if (internal_gnd) {
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_ENCAL_GND_ADDR, 1);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 1);
|
||||
} else {
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_ENCAL_GND_ADDR, 0);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1227,9 +1167,9 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t
|
||||
static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n)
|
||||
{
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_ENCAL_GND_ADDR, 0);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
|
||||
} else {
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_ENCAL_GND_ADDR, 0);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1245,18 +1185,16 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
|
||||
uint8_t msb = param >> 8;
|
||||
uint8_t lsb = param & 0xFF;
|
||||
/* Should be called before writing I2C registers. */
|
||||
void phy_get_romfunc_addr(void);
|
||||
phy_get_romfunc_addr();
|
||||
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
|
||||
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
|
||||
SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16));
|
||||
SET_PERI_REG_MASK(ADC_ANA_CONFIG2_REG, BIT(16));
|
||||
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
|
||||
} else {
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR, msb);
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR, lsb);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, msb);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, lsb);
|
||||
}
|
||||
}
|
||||
/* Temp code end. */
|
||||
@ -1275,23 +1213,21 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
|
||||
static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en)
|
||||
{
|
||||
/* Should be called before writing I2C registers. */
|
||||
void phy_get_romfunc_addr(void);
|
||||
phy_get_romfunc_addr();
|
||||
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
|
||||
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
|
||||
SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16));
|
||||
SET_PERI_REG_MASK(ADC_ANA_CONFIG2_REG, BIT(16));
|
||||
|
||||
if (en) {
|
||||
if (adc == ADC_NUM_1) {
|
||||
/* Config test mux to route v_ref to ADC1 Channels */
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_DTEST_RTC_ADDR, 1);
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 0);
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 1);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 1);
|
||||
} else {
|
||||
/* Config test mux to route v_ref to ADC2 Channels */
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_DTEST_RTC_ADDR, 0);
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 1);
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 0);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 1);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
|
||||
}
|
||||
//in sleep force to use rtc to control ADC
|
||||
SENS.sar_meas2_mux.sar2_rtc_force = 1;
|
||||
@ -1302,8 +1238,8 @@ static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, b
|
||||
//set en_pad for ADC2 channels (bits 0x380)
|
||||
SENS.sar_meas2_ctrl2.sar2_en_pad = 1 << channel;
|
||||
} else {
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 0);
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 0);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
|
||||
SENS.sar_meas2_mux.sar2_rtc_force = 0;
|
||||
//set sar2_en_test
|
||||
SENS.sar_meas2_ctrl1.sar2_en_test = 0;
|
||||
|
||||
@ -290,7 +290,8 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
|
||||
abort();
|
||||
}
|
||||
}
|
||||
s_cur_pll_freq = pll_freq;
|
||||
|
||||
s_cur_pll_freq = pll_freq;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
Loading…
Reference in New Issue
Block a user