diff --git a/components/bootloader/subproject/main/ld/esp32/bootloader.rom.ld b/components/bootloader/subproject/main/ld/esp32/bootloader.rom.ld
index c9639540a4..e69de29bb2 100644
--- a/components/bootloader/subproject/main/ld/esp32/bootloader.rom.ld
+++ b/components/bootloader/subproject/main/ld/esp32/bootloader.rom.ld
@@ -1,9 +0,0 @@
-PROVIDE ( ets_update_cpu_frequency = 0x40008550 ); /* Updates g_ticks_per_us on the current CPU only; not on the other core */
-PROVIDE ( MD5Final = 0x4005db1c );
-PROVIDE ( MD5Init = 0x4005da7c );
-PROVIDE ( MD5Update = 0x4005da9c );
-
-/* bootloader will use following functions from xtensa hal library */
-xthal_get_ccount = 0x4000c050;
-xthal_get_ccompare = 0x4000c078;
-xthal_set_ccompare = 0x4000c058;
diff --git a/components/bootloader/subproject/main/ld/esp32s2/bootloader.rom.ld b/components/bootloader/subproject/main/ld/esp32s2/bootloader.rom.ld
index 0a600f8dc0..e69de29bb2 100644
--- a/components/bootloader/subproject/main/ld/esp32s2/bootloader.rom.ld
+++ b/components/bootloader/subproject/main/ld/esp32s2/bootloader.rom.ld
@@ -1,13 +0,0 @@
-/*
- * ESP32S2 ROM address table
- * Generated for ROM with MD5sum: 0a2c7ec5109c17884606d23b47045796
-*/
-PROVIDE (ets_update_cpu_frequency = 0x4000d8a4);
-
-PROVIDE (MD5Final = 0x4000530c);
-PROVIDE (MD5Init = 0x4000526c);
-PROVIDE (MD5Update = 0x4000528c);
-/* bootloader will use following functions from xtensa hal library */
-xthal_get_ccount = 0x4001aa90;
-xthal_get_ccompare = 0x4001aabc;
-xthal_set_ccompare = 0x4001aa98;
diff --git a/components/bootloader/subproject/main/ld/esp32s3/bootloader.rom.ld b/components/bootloader/subproject/main/ld/esp32s3/bootloader.rom.ld
index 7a21fa7465..e69de29bb2 100644
--- a/components/bootloader/subproject/main/ld/esp32s3/bootloader.rom.ld
+++ b/components/bootloader/subproject/main/ld/esp32s3/bootloader.rom.ld
@@ -1,6 +0,0 @@
-/**
- * ESP32S3 ROM address table
- * Generated for ROM with MD5sum: d20fb231463ce337432b1fa9cba0b3c9
- */
-
-PROVIDE ( ets_update_cpu_frequency = 0x40043164 );
diff --git a/components/esp_hw_support/esp_clk.c b/components/esp_hw_support/esp_clk.c
index 511b73eb4a..a8763920d1 100644
--- a/components/esp_hw_support/esp_clk.c
+++ b/components/esp_hw_support/esp_clk.c
@@ -47,11 +47,6 @@
 
 // g_ticks_us defined in ROMs for PRO and APP CPU
 extern uint32_t g_ticks_per_us_pro;
-#if SOC_CPU_CORES_NUM > 1
-#ifndef CONFIG_FREERTOS_UNICORE
-extern uint32_t g_ticks_per_us_app;
-#endif
-#endif
 
 static portMUX_TYPE s_esp_rtc_time_lock = portMUX_INITIALIZER_UNLOCKED;
 
@@ -88,19 +83,6 @@ int IRAM_ATTR esp_clk_xtal_freq(void)
     return rtc_clk_xtal_freq_get() * MHZ;
 }
 
-#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
-void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us)
-{
-    /* Update scale factors used by esp_rom_delay_us */
-    g_ticks_per_us_pro = ticks_per_us;
-#if SOC_CPU_CORES_NUM > 1
-#ifndef CONFIG_FREERTOS_UNICORE
-    g_ticks_per_us_app = ticks_per_us;
-#endif
-#endif
-}
-#endif
-
 uint64_t esp_rtc_get_time_us(void)
 {
     portENTER_CRITICAL_SAFE(&s_esp_rtc_time_lock);
diff --git a/components/esp_hw_support/port/esp32/rtc_clk.c b/components/esp_hw_support/port/esp32/rtc_clk.c
index 3f3a086667..bab0bdb3ce 100644
--- a/components/esp_hw_support/port/esp32/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32/rtc_clk.c
@@ -22,7 +22,6 @@
 #include "sdkconfig.h"
 #include "esp_rom_sys.h"
 #include "esp_rom_gpio.h"
-#include "esp32/rom/ets_sys.h" // for ets_update_cpu_frequency
 #include "esp32/rom/rtc.h"
 #include "hal/clk_tree_ll.h"
 #include "soc/rtc_cntl_reg.h"
@@ -354,7 +353,7 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
  */
 void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
 {
-    ets_update_cpu_frequency(cpu_freq);
+    esp_rom_set_cpu_ticks_per_us(cpu_freq);
     /* set divider from XTAL to APB clock */
     clk_ll_cpu_set_divider(div);
     /* adjust ref_tick */
@@ -369,7 +368,7 @@ void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
 
 static void rtc_clk_cpu_freq_to_8m(void)
 {
-    ets_update_cpu_frequency(8);
+    esp_rom_set_cpu_ticks_per_us(8);
     REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
     clk_ll_cpu_set_divider(1);
     /* adjust ref_tick */
@@ -394,7 +393,7 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
     /* switch clock source */
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
     rtc_clk_apb_freq_update(80 * MHZ);
-    ets_update_cpu_frequency(cpu_freq_mhz);
+    esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
     rtc_clk_wait_for_slow_cycle();
 }
 
diff --git a/components/esp_hw_support/port/esp32c2/rtc_clk.c b/components/esp_hw_support/port/esp32c2/rtc_clk.c
index 425552b25f..c065b4476a 100644
--- a/components/esp_hw_support/port/esp32c2/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32c2/rtc_clk.c
@@ -10,7 +10,6 @@
 #include <assert.h>
 #include <stdlib.h>
 #include "sdkconfig.h"
-#include "esp32c2/rom/ets_sys.h"
 #include "esp32c2/rom/rtc.h"
 #include "esp32c2/rom/uart.h"
 #include "esp32c2/rom/gpio.h"
@@ -147,7 +146,7 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
 
     rtc_clk_apb_freq_update(40 * MHZ);
-    ets_update_cpu_frequency(cpu_freq_mhz);
+    esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
 }
 
 bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config)
@@ -289,7 +288,7 @@ void rtc_clk_cpu_set_to_default_config(void)
  */
 void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
 {
-    ets_update_cpu_frequency(cpu_freq);
+    esp_rom_set_cpu_ticks_per_us(cpu_freq);
     /* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */
     clk_ll_cpu_set_divider(1);
     clk_ll_cpu_set_divider(div);
@@ -300,7 +299,7 @@ void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
 
 static void rtc_clk_cpu_freq_to_8m(void)
 {
-    ets_update_cpu_frequency(20);
+    esp_rom_set_cpu_ticks_per_us(20);
     clk_ll_cpu_set_divider(1);
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
     rtc_clk_apb_freq_update(SOC_CLK_RC_FAST_FREQ_APPROX);
diff --git a/components/esp_hw_support/port/esp32c3/rtc_clk.c b/components/esp_hw_support/port/esp32c3/rtc_clk.c
index 89bf37e28a..ea8881f088 100644
--- a/components/esp_hw_support/port/esp32c3/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32c3/rtc_clk.c
@@ -10,7 +10,6 @@
 #include <assert.h>
 #include <stdlib.h>
 #include "sdkconfig.h"
-#include "esp32c3/rom/ets_sys.h"
 #include "esp32c3/rom/rtc.h"
 #include "soc/rtc.h"
 #include "esp_private/rtc_clk.h"
@@ -170,7 +169,7 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
     clk_ll_cpu_set_divider(1);
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
     rtc_clk_apb_freq_update(80 * MHZ);
-    ets_update_cpu_frequency(cpu_freq_mhz);
+    esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
 }
 
 bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config)
@@ -314,7 +313,7 @@ void rtc_clk_cpu_set_to_default_config(void)
  */
 static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
 {
-    ets_update_cpu_frequency(cpu_freq);
+    esp_rom_set_cpu_ticks_per_us(cpu_freq);
     /* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */
     clk_ll_cpu_set_divider(1);
     clk_ll_cpu_set_divider(div);
@@ -325,7 +324,7 @@ static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
 
 static void rtc_clk_cpu_freq_to_8m(void)
 {
-    ets_update_cpu_frequency(20);
+    esp_rom_set_cpu_ticks_per_us(20);
     clk_ll_cpu_set_divider(1);
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
     rtc_clk_apb_freq_update(SOC_CLK_RC_FAST_FREQ_APPROX);
diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk.c b/components/esp_hw_support/port/esp32c6/rtc_clk.c
index b21523b5cb..b05a3b0915 100644
--- a/components/esp_hw_support/port/esp32c6/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32c6/rtc_clk.c
@@ -10,7 +10,6 @@
 #include <assert.h>
 #include <stdlib.h>
 #include "sdkconfig.h"
-#include "esp32c6/rom/ets_sys.h"
 #include "esp32c6/rom/rtc.h"
 #include "soc/rtc.h"
 #include "esp_private/rtc_clk.h"
@@ -164,7 +163,7 @@ static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
     clk_ll_ahb_set_ls_divider(div);
     clk_ll_cpu_set_ls_divider(div);
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
-    ets_update_cpu_frequency(cpu_freq);
+    esp_rom_set_cpu_ticks_per_us(cpu_freq);
 }
 
 static void rtc_clk_cpu_freq_to_8m(void)
@@ -172,7 +171,7 @@ static void rtc_clk_cpu_freq_to_8m(void)
     clk_ll_ahb_set_ls_divider(1);
     clk_ll_cpu_set_ls_divider(1);
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
-    ets_update_cpu_frequency(20);
+    esp_rom_set_cpu_ticks_per_us(20);
 }
 
 /**
@@ -184,7 +183,7 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
 {
     clk_ll_cpu_set_hs_divider(CLK_LL_PLL_480M_FREQ_MHZ / cpu_freq_mhz);
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
-    ets_update_cpu_frequency(cpu_freq_mhz);
+    esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
 }
 
 bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config)
diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk.c b/components/esp_hw_support/port/esp32h2/rtc_clk.c
index 93c66b0f70..d834c09cb4 100644
--- a/components/esp_hw_support/port/esp32h2/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32h2/rtc_clk.c
@@ -10,7 +10,6 @@
 #include <assert.h>
 #include <stdlib.h>
 #include "sdkconfig.h"
-#include "esp32h2/rom/ets_sys.h"
 #include "esp32h2/rom/rtc.h"
 #include "soc/rtc.h"
 #include "esp_private/rtc_clk.h"
@@ -183,7 +182,7 @@ static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
     clk_ll_ahb_set_divider(div);
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
     clk_ll_bus_update();
-    ets_update_cpu_frequency(cpu_freq);
+    esp_rom_set_cpu_ticks_per_us(cpu_freq);
 }
 
 static void rtc_clk_cpu_freq_to_8m(void)
@@ -193,7 +192,7 @@ static void rtc_clk_cpu_freq_to_8m(void)
     clk_ll_ahb_set_divider(1);
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
     clk_ll_bus_update();
-    ets_update_cpu_frequency(8);
+    esp_rom_set_cpu_ticks_per_us(8);
 }
 
 /**
@@ -212,7 +211,7 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
     clk_ll_ahb_set_divider(ahb_divider);
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
     clk_ll_bus_update();
-    ets_update_cpu_frequency(cpu_freq_mhz);
+    esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
 }
 
 /**
@@ -229,7 +228,7 @@ static void rtc_clk_cpu_freq_to_flash_pll(uint32_t cpu_freq_mhz, uint32_t cpu_di
     clk_ll_ahb_set_divider(ahb_divider);
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_FLASH_PLL);
     clk_ll_bus_update();
-    ets_update_cpu_frequency(cpu_freq_mhz);
+    esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
 }
 
 bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config)
diff --git a/components/esp_hw_support/port/esp32h4/rtc_clk.c b/components/esp_hw_support/port/esp32h4/rtc_clk.c
index 417d5be1a8..d709d55c78 100644
--- a/components/esp_hw_support/port/esp32h4/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32h4/rtc_clk.c
@@ -10,7 +10,6 @@
 #include <assert.h>
 #include <stdlib.h>
 #include "sdkconfig.h"
-#include "esp32h4/rom/ets_sys.h"
 #include "esp32h4/rom/rtc.h"
 #include "esp32h4/rom/uart.h"
 #include "esp32h4/rom/gpio.h"
@@ -216,7 +215,7 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
         clk_ll_ahb_set_divider(1);
     }
 
-    ets_update_cpu_frequency(cpu_freq_mhz);
+    esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
     rtc_clk_apb_freq_update(rtc_clk_apb_freq_get());
 }
 
@@ -255,7 +254,7 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
     uint32_t src_freq_mhz = rtc_clk_select_root_clk(config->source);
     uint32_t div = src_freq_mhz / (config->freq_mhz);
     rtc_clk_cpu_freq_set(config->source, div);
-    ets_update_cpu_frequency(config->freq_mhz);
+    esp_rom_set_cpu_ticks_per_us(config->freq_mhz);
 }
 
 void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
@@ -335,7 +334,7 @@ void rtc_clk_cpu_set_to_default_config(void)
  */
 static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
 {
-    ets_update_cpu_frequency(cpu_freq);
+    esp_rom_set_cpu_ticks_per_us(cpu_freq);
     /* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */
     rtc_clk_cpu_freq_set(SOC_CPU_CLK_SRC_XTAL, div);
     /* no need to adjust the REF_TICK */
@@ -345,7 +344,7 @@ static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
 
 void rtc_clk_cpu_freq_to_8m(void)
 {
-    ets_update_cpu_frequency(RTC_OSC_FREQ_RC8M);
+    esp_rom_set_cpu_ticks_per_us(RTC_OSC_FREQ_RC8M);
     rtc_clk_select_root_clk(SOC_CPU_CLK_SRC_RC_FAST);
     rtc_clk_apb_freq_update(rtc_clk_apb_freq_get());
 }
diff --git a/components/esp_hw_support/port/esp32s2/rtc_clk.c b/components/esp_hw_support/port/esp32s2/rtc_clk.c
index 703ddd006f..bf53944bb4 100644
--- a/components/esp_hw_support/port/esp32s2/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32s2/rtc_clk.c
@@ -10,7 +10,6 @@
 #include <assert.h>
 #include <stdlib.h>
 #include "sdkconfig.h"
-#include "esp32s2/rom/ets_sys.h" // for ets_update_cpu_frequency
 #include "esp32s2/rom/rtc.h"
 #include "soc/rtc.h"
 #include "esp_private/rtc_clk.h"
@@ -263,7 +262,7 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
     REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias);
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
     rtc_clk_apb_freq_update(80 * MHZ);
-    ets_update_cpu_frequency(cpu_freq_mhz);
+    esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
 }
 
 bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t* out_config)
@@ -412,7 +411,7 @@ void rtc_clk_cpu_set_to_default_config(void)
  */
 static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
 {
-    ets_update_cpu_frequency(cpu_freq);
+    esp_rom_set_cpu_ticks_per_us(cpu_freq);
     /* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */
     clk_ll_cpu_set_divider(1);
     clk_ll_cpu_set_divider(div);
@@ -427,7 +426,7 @@ static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
 
 static void rtc_clk_cpu_freq_to_8m(void)
 {
-    ets_update_cpu_frequency(8);
+    esp_rom_set_cpu_ticks_per_us(8);
     REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
     clk_ll_cpu_set_divider(1);
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk.c b/components/esp_hw_support/port/esp32s3/rtc_clk.c
index 481436e4be..29b96aac18 100644
--- a/components/esp_hw_support/port/esp32s3/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32s3/rtc_clk.c
@@ -10,7 +10,6 @@
 #include <assert.h>
 #include <stdlib.h>
 #include "sdkconfig.h"
-#include "esp32s3/rom/ets_sys.h"
 #include "esp32s3/rom/rtc.h"
 #include "soc/rtc.h"
 #include "esp_private/rtc_clk.h"
@@ -215,14 +214,14 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
         /* switch clock source */
         clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
         rtc_clk_apb_freq_update(80 * MHZ);
-        ets_update_cpu_frequency(cpu_freq_mhz);
+        esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
     } else {
         clk_ll_cpu_set_freq_mhz_from_pll(cpu_freq_mhz);
         clk_ll_cpu_set_divider(1);
         /* switch clock source */
         clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
         rtc_clk_apb_freq_update(80 * MHZ);
-        ets_update_cpu_frequency(cpu_freq_mhz);
+        esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
         REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD,  DEFAULT_LDO_SLAVE >> pd_slave);
     }
 }
@@ -380,7 +379,7 @@ void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m);
     esp_rom_delay_us(40);
-    ets_update_cpu_frequency(cpu_freq);
+    esp_rom_set_cpu_ticks_per_us(cpu_freq);
     /* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */
     clk_ll_cpu_set_divider(1);
     clk_ll_cpu_set_divider(div);
@@ -392,7 +391,7 @@ void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
 
 static void rtc_clk_cpu_freq_to_8m(void)
 {
-    ets_update_cpu_frequency(20);
+    esp_rom_set_cpu_ticks_per_us(20);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m);
     esp_rom_delay_us(40);
diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld
index 058a31ace9..04d9bcb388 100644
--- a/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld
+++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld
@@ -43,6 +43,7 @@ PROVIDE ( esp_rom_delay_us = ets_delay_us );
 PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
 PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
 PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
+PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency );
 
 PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach );
 PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld
index 50461e94ad..4c4a4628d1 100644
--- a/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld
+++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld
@@ -38,6 +38,7 @@ PROVIDE ( esp_rom_delay_us = ets_delay_us );
 PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
 PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
 PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
+PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency );
 
 PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
 PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable );
diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld
index b0468f877e..cf8c34778e 100644
--- a/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld
+++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld
@@ -44,6 +44,7 @@ PROVIDE ( esp_rom_delay_us = ets_delay_us );
 PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
 PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
 PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
+PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency );
 
 PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach );
 PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
diff --git a/components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld b/components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld
index e6b948b6a3..773b57b5f2 100644
--- a/components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld
+++ b/components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld
@@ -44,6 +44,7 @@ PROVIDE ( esp_rom_delay_us = ets_delay_us );
 PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
 PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
 PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
+PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency );
 
 PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach );
 PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
diff --git a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld b/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld
index 8a1eb5afe0..b22f07d47d 100644
--- a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld
+++ b/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld
@@ -45,6 +45,7 @@ PROVIDE ( esp_rom_delay_us = ets_delay_us );
 PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
 PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
 PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
+PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency );
 
 PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach );
 PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
diff --git a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.api.ld b/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.api.ld
index 7c821b46b1..7f03179c06 100644
--- a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.api.ld
+++ b/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.api.ld
@@ -45,6 +45,7 @@ PROVIDE ( esp_rom_delay_us = ets_delay_us );
 PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
 PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
 PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
+PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency );
 
 PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
 PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);
diff --git a/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld b/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld
index 6f0b083a67..98bda8396f 100644
--- a/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld
+++ b/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld
@@ -44,6 +44,7 @@ PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
 PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
 PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
 PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
+PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency );
 
 PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
 PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);
diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld
index 6355190a6c..2c63ea2647 100644
--- a/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld
+++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld
@@ -42,6 +42,7 @@ PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
 PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
 PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
 PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
+PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency );
 
 PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach );
 PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
diff --git a/components/esp_rom/include/esp_rom_sys.h b/components/esp_rom/include/esp_rom_sys.h
index 6d119edda6..1e90583b5a 100644
--- a/components/esp_rom/include/esp_rom_sys.h
+++ b/components/esp_rom/include/esp_rom_sys.h
@@ -92,6 +92,15 @@ void esp_rom_route_intr_matrix(int cpu_core, uint32_t periph_intr_id, uint32_t c
  */
 uint32_t esp_rom_get_cpu_ticks_per_us(void);
 
+/**
+ * @brief Set the real CPU tick rate
+ *
+ * @note Call this function when CPU frequency is changed, otherwise the `esp_rom_delay_us` can be inaccurate.
+ *
+ * @param ticks_per_us CPU ticks per us
+ */
+void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_rom/patches/esp_rom_sys.c b/components/esp_rom/patches/esp_rom_sys.c
index dde99a1210..2d354aebb7 100644
--- a/components/esp_rom/patches/esp_rom_sys.c
+++ b/components/esp_rom/patches/esp_rom_sys.c
@@ -1,13 +1,14 @@
 /*
- * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include <stdint.h>
 #include <stdbool.h>
+#include "sdkconfig.h"
 #include "esp_attr.h"
-
+#include "soc/soc_caps.h"
 #include "esp_rom_caps.h"
 
 IRAM_ATTR void esp_rom_install_channel_putc(int channel, void (*putc)(char c))
@@ -39,3 +40,22 @@ IRAM_ATTR void esp_rom_install_uart_printf(void)
     ets_install_uart_printf();
 }
 #endif
+
+#if CONFIG_IDF_TARGET_ESP32
+extern uint32_t g_ticks_per_us_pro;
+#if SOC_CPU_CORES_NUM > 1
+#ifndef CONFIG_FREERTOS_UNICORE
+extern uint32_t g_ticks_per_us_app;
+#endif
+#endif
+IRAM_ATTR void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us)
+{
+    /* Update scale factors used by esp_rom_delay_us */
+    g_ticks_per_us_pro = ticks_per_us;
+#if SOC_CPU_CORES_NUM > 1
+#ifndef CONFIG_FREERTOS_UNICORE
+    g_ticks_per_us_app = ticks_per_us;
+#endif
+#endif
+}
+#endif // CONFIG_IDF_TARGET_ESP32
diff --git a/components/esp_system/fpga_overrides.c b/components/esp_system/fpga_overrides.c
index 7439c7cfa3..0f7c92057d 100644
--- a/components/esp_system/fpga_overrides.c
+++ b/components/esp_system/fpga_overrides.c
@@ -34,8 +34,6 @@
 
 static const char *TAG = "fpga";
 
-extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
-
 static void s_warn(void)
 {
     ESP_EARLY_LOGW(TAG, "Project configuration is for internal FPGA use, not all functions will work");
@@ -54,7 +52,7 @@ void bootloader_clock_configure(void)
 #else
     uint32_t apb_freq_hz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000;
 #endif // CONFIG_IDF_TARGET_ESP32S2
-    ets_update_cpu_frequency(apb_freq_hz / 1000000);
+    esp_rom_set_cpu_ticks_per_us(apb_freq_hz / 1000000);
 #ifdef RTC_APB_FREQ_REG
     REG_WRITE(RTC_APB_FREQ_REG, (apb_freq_hz >> 12) | ((apb_freq_hz >> 12) << 16));
 #endif