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https://github.com/espressif/esp-idf.git
synced 2024-09-20 20:56:01 -04:00
bootloader_support: Fix unused-variable compiler warning
Builds for every chip other than ESP32 resulted in a compiler warning due to "drom_load_addr_aligned" and "irom_load_addr_aligned" not being used, besides being possible to actually reuse them. Furthermore, extended the logic for the other similar variables. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
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02237e4b77
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@ -720,8 +720,8 @@ static void set_cache_and_start_app(
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#endif
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#endif
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/* Clear the MMU entries that are already set up,
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/* Clear the MMU entries that are already set up,
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so the new app only has the mappings it creates.
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* so the new app only has the mappings it creates.
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*/
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*/
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#if CONFIG_IDF_TARGET_ESP32
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#if CONFIG_IDF_TARGET_ESP32
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for (int i = 0; i < DPORT_FLASH_MMU_TABLE_SIZE; i++) {
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for (int i = 0; i < DPORT_FLASH_MMU_TABLE_SIZE; i++) {
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DPORT_PRO_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL;
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DPORT_PRO_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL;
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@ -732,31 +732,33 @@ static void set_cache_and_start_app(
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}
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}
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#endif
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#endif
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uint32_t drom_load_addr_aligned = drom_load_addr & MMU_FLASH_MASK;
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uint32_t drom_load_addr_aligned = drom_load_addr & MMU_FLASH_MASK;
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uint32_t drom_addr_aligned = drom_addr & MMU_FLASH_MASK;
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uint32_t drom_page_count = bootloader_cache_pages_to_map(drom_size, drom_load_addr);
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uint32_t drom_page_count = bootloader_cache_pages_to_map(drom_size, drom_load_addr);
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ESP_LOGV(TAG, "d mmu set paddr=%08x vaddr=%08x size=%d n=%d",
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ESP_LOGV(TAG, "d mmu set paddr=%08x vaddr=%08x size=%d n=%d",
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drom_addr & MMU_FLASH_MASK, drom_load_addr_aligned, drom_size, drom_page_count);
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drom_addr_aligned, drom_load_addr_aligned, drom_size, drom_page_count);
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#if CONFIG_IDF_TARGET_ESP32
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#if CONFIG_IDF_TARGET_ESP32
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rc = cache_flash_mmu_set(0, 0, drom_load_addr_aligned, drom_addr & MMU_FLASH_MASK, 64, drom_page_count);
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rc = cache_flash_mmu_set(0, 0, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count);
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#elif CONFIG_IDF_TARGET_ESP32S2
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#elif CONFIG_IDF_TARGET_ESP32S2
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rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0);
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rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count, 0);
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#elif CONFIG_IDF_TARGET_ESP32S3
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#elif CONFIG_IDF_TARGET_ESP32S3
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rc = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0);
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rc = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count, 0);
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#elif CONFIG_IDF_TARGET_ESP32C3
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#elif CONFIG_IDF_TARGET_ESP32C3
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rc = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0);
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rc = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count, 0);
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#elif CONFIG_IDF_TARGET_ESP32H2
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#elif CONFIG_IDF_TARGET_ESP32H2
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rc = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0);
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rc = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count, 0);
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#endif
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#endif
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ESP_LOGV(TAG, "rc=%d", rc);
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ESP_LOGV(TAG, "rc=%d", rc);
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#if CONFIG_IDF_TARGET_ESP32
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#if CONFIG_IDF_TARGET_ESP32
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rc = cache_flash_mmu_set(1, 0, drom_load_addr_aligned, drom_addr & MMU_FLASH_MASK, 64, drom_page_count);
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rc = cache_flash_mmu_set(1, 0, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count);
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ESP_LOGV(TAG, "rc=%d", rc);
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ESP_LOGV(TAG, "rc=%d", rc);
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#endif
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#endif
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uint32_t irom_load_addr_aligned = irom_load_addr & MMU_FLASH_MASK;
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uint32_t irom_load_addr_aligned = irom_load_addr & MMU_FLASH_MASK;
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uint32_t irom_addr_aligned = irom_addr & MMU_FLASH_MASK;
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uint32_t irom_page_count = bootloader_cache_pages_to_map(irom_size, irom_load_addr);
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uint32_t irom_page_count = bootloader_cache_pages_to_map(irom_size, irom_load_addr);
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ESP_LOGV(TAG, "i mmu set paddr=%08x vaddr=%08x size=%d n=%d",
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ESP_LOGV(TAG, "i mmu set paddr=%08x vaddr=%08x size=%d n=%d",
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irom_addr & MMU_FLASH_MASK, irom_load_addr_aligned, irom_size, irom_page_count);
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irom_addr_aligned, irom_load_addr_aligned, irom_size, irom_page_count);
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#if CONFIG_IDF_TARGET_ESP32
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#if CONFIG_IDF_TARGET_ESP32
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rc = cache_flash_mmu_set(0, 0, irom_load_addr_aligned, irom_addr & MMU_FLASH_MASK, 64, irom_page_count);
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rc = cache_flash_mmu_set(0, 0, irom_load_addr_aligned, irom_addr_aligned, 64, irom_page_count);
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#elif CONFIG_IDF_TARGET_ESP32S2
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#elif CONFIG_IDF_TARGET_ESP32S2
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uint32_t iram1_used = 0;
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uint32_t iram1_used = 0;
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if (irom_load_addr + irom_size > IRAM1_ADDRESS_LOW) {
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if (irom_load_addr + irom_size > IRAM1_ADDRESS_LOW) {
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@ -767,17 +769,17 @@ static void set_cache_and_start_app(
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rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM1_ADDRESS_LOW, 0, 64, 64, 1);
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rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM1_ADDRESS_LOW, 0, 64, 64, 1);
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REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_IRAM1);
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REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_IRAM1);
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}
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}
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rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0);
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rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr_aligned, irom_addr_aligned, 64, irom_page_count, 0);
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#elif CONFIG_IDF_TARGET_ESP32S3
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#elif CONFIG_IDF_TARGET_ESP32S3
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rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0);
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rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr_aligned, irom_addr_aligned, 64, irom_page_count, 0);
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#elif CONFIG_IDF_TARGET_ESP32C3
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#elif CONFIG_IDF_TARGET_ESP32C3
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rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0);
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rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr_aligned, irom_addr_aligned, 64, irom_page_count, 0);
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#elif CONFIG_IDF_TARGET_ESP32H2
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#elif CONFIG_IDF_TARGET_ESP32H2
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rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0);
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rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr_aligned, irom_addr_aligned, 64, irom_page_count, 0);
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#endif
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#endif
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ESP_LOGV(TAG, "rc=%d", rc);
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ESP_LOGV(TAG, "rc=%d", rc);
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#if CONFIG_IDF_TARGET_ESP32
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#if CONFIG_IDF_TARGET_ESP32
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rc = cache_flash_mmu_set(1, 0, irom_load_addr_aligned, irom_addr & MMU_FLASH_MASK, 64, irom_page_count);
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rc = cache_flash_mmu_set(1, 0, irom_load_addr_aligned, irom_addr_aligned, 64, irom_page_count);
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ESP_LOGV(TAG, "rc=%d", rc);
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ESP_LOGV(TAG, "rc=%d", rc);
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DPORT_REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG,
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DPORT_REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG,
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(DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) |
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(DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) |
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