Merge branch 'refactor/split_esp32s2_soc_include_folder' into 'master'

refactor(soc): sort esp32s2 soc headers

See merge request espressif/esp-idf!33310

components/soc/esp32s2/include/soc/dport_reg.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,15 +10,15 @@
 extern "C" {
 #endif
 
-#include "interrupt_reg.h"
-#include "system_reg.h"
-#include "sensitive_reg.h"
-#include "soc.h"
+#include "soc/interrupt_reg.h"
+#include "soc/system_reg.h"
+#include "soc/sensitive_reg.h"
+#include "soc/soc.h"
 
 #define DPORT_DATE_REG SYSTEM_DATE_REG
 
 #ifndef __ASSEMBLER__
-#include "dport_access.h"
+#include "soc/dport_access.h"
 #endif
 
 #ifdef __cplusplus

components/soc/esp32s2/include/soc/soc.h

@@ -12,7 +12,7 @@
 #endif
 
 #include "esp_bit_defs.h"
-#include "reg_base.h"
+#include "soc/reg_base.h"
 
 #define PRO_CPU_NUM (0)
 

components/soc/esp32s2/include/soc/usb_dwc_struct.h

@@ -33,7 +33,7 @@ typedef union {
         uint32_t hnpreq: 1;
         uint32_t hstsethnpen: 1;
         uint32_t devhnpen: 1;
-        uint32_t ehen: 1;
+        uint32_t ehen: 1;       // codespell:ignore ehen
         uint32_t reserved_13: 2;
         uint32_t dbncefltrbypass: 1;
         uint32_t conidsts: 1;

components/soc/esp32s2/register/soc/apb_ctrl_reg.h

@@ -11,7 +11,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 #define APB_CTRL_SYSCLK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x000)
 /* APB_CTRL_SOC_CLK_SEL : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
 /*description: */

components/soc/esp32s2/register/soc/apb_saradc_reg.h

@@ -1,16 +1,8 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_APB_SARADC_REG_H_
 #define _SOC_APB_SARADC_REG_H_
 
@@ -18,7 +10,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 #define APB_SARADC_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x000)
 /* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */
 /*description: wait arbit signal stable after sar_done*/

components/soc/esp32s2/register/soc/assist_debug_reg.h

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #define ASSIST_DEBUG_BASE DR_REG_ASSIST_DEBUG_BASE
 
 #define ASSIST_DEBUG_INTERRUPT_ENA              ((ASSIST_DEBUG_BASE) +0x00)
@@ -80,8 +85,8 @@
 
 #define ASSIST_DEBUG_PRO_RCD_PDEBUGSTATUS	((ASSIST_DEBUG_BASE) +0x64)
 /* register layout:
- * BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ == 0
- * INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ > 0
+ * BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for possible values. When DPORT_RECORD_PDEBUGINST_SZ == 0
+ * INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for possible values. When DPORT_RECORD_PDEBUGINST_SZ > 0
 */
 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_M             ((DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)<<(DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S))
 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V             0x3F

components/soc/esp32s2/register/soc/cp_dma_reg.h

@@ -573,7 +573,7 @@ extern "C" {
 #define CP_DMA_CRC_CAL_EN_V  0x00000001
 #define CP_DMA_CRC_CAL_EN_S  9
 /** CP_DMA_CRC_BIG_ENDIAN_EN : R/W; bitpos: [10]; default: 0;
- *  Set this bit to reorder the bit of data which will be send to excute crc.
+ *  Set this bit to reorder the bit of data which will be send to execute crc.
  */
 #define CP_DMA_CRC_BIG_ENDIAN_EN    (BIT(10))
 #define CP_DMA_CRC_BIG_ENDIAN_EN_M  (CP_DMA_CRC_BIG_ENDIAN_EN_V << CP_DMA_CRC_BIG_ENDIAN_EN_S)
@@ -629,7 +629,7 @@ extern "C" {
 #define CP_DMA_FIFO_EMPTY_S  23
 
 /** CP_DMA_OUT_ST_REG register
- *  Status register of trasmitting data
+ *  Status register of transmitting data
  */
 #define CP_DMA_OUT_ST_REG (DR_REG_CP_BASE + 0x44)
 /** CP_DMA_OUTLINK_DSCR_ADDR : RO; bitpos: [17:0]; default: 0;

components/soc/esp32s2/register/soc/cp_dma_struct.h

@@ -327,7 +327,7 @@ typedef union {
          */
         uint32_t dma_crc_cal_en: 1;
         /** dma_crc_big_endian_en : R/W; bitpos: [10]; default: 0;
-         *  Set this bit to reorder the bit of data which will be send to excute crc.
+         *  Set this bit to reorder the bit of data which will be send to execute crc.
          */
         uint32_t dma_crc_big_endian_en: 1;
         /** dma_crc_out_reverse_en : R/W; bitpos: [11]; default: 0;

components/soc/esp32s2/register/soc/crypto_dma_reg.h

@@ -1,16 +1,8 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_CRYPTO_DMA_REG_H_
 #define _SOC_CRYPTO_DMA_REG_H_
 
@@ -18,7 +10,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 
 /* CRYPTO_DMA_CONF0 : RO ;bitpos:[31:14] ;default: 18'h0 ; */
 /* CONF0_REG_GEN_CLK_EN : RW ;bitpos:[13] ;default: 1'b0 ; */

components/soc/esp32s2/register/soc/dedic_gpio_reg.h

@@ -1,16 +1,7 @@
-/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 #pragma once

components/soc/esp32s2/register/soc/dedic_gpio_struct.h

@@ -1,16 +1,7 @@
-/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 #pragma once
 

components/soc/esp32s2/register/soc/efuse_reg.h

@@ -7,7 +7,7 @@
 
 #include <stdint.h>
 #include "soc/soc.h"
-#include "efuse_defs.h"
+#include "soc/efuse_defs.h"
 #ifdef __cplusplus
 extern "C" {
 #endif

components/soc/esp32s2/register/soc/extmem_reg.h

@@ -1,16 +1,8 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_EXTMEM_REG_H_
 #define _SOC_EXTMEM_REG_H_
 
@@ -18,7 +10,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 #define EXTMEM_PRO_DCACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x000)
 /* EXTMEM_PRO_DCACHE_LOCK_DONE : RO ;bitpos:[25] ;default: 1'b0 ; */
 /*description: The bit is used to indicate lock operation is finished.*/

components/soc/esp32s2/register/soc/gpio_reg.h

@@ -1,16 +1,8 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_GPIO_REG_H_
 #define _SOC_GPIO_REG_H_
 
@@ -18,7 +10,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 #define GPIO_PIN_CONFIG_MSB                    12
 #define GPIO_PIN_CONFIG_LSB                     11
 #define GPIO_PIN_CONFIG_MASK                   0x00001800

components/soc/esp32s2/register/soc/gpio_sd_reg.h

@@ -6,7 +6,7 @@
 
 #pragma once
 
-#include "soc.h"
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {

components/soc/esp32s2/register/soc/i2c_reg.h

@@ -1,16 +1,8 @@
-// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_I2C_REG_H_
 #define _SOC_I2C_REG_H_
 
@@ -18,7 +10,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 #define I2C_SCL_LOW_PERIOD_REG(i)          (REG_I2C_BASE(i) + 0x0000)
 /* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
 /*description: */

components/soc/esp32s2/register/soc/i2s_reg.h

@@ -10,7 +10,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 #define I2S_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0008)
 /* I2S_RX_RESET_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
 /*description: */

components/soc/esp32s2/register/soc/interrupt_reg.h

@@ -1,16 +1,8 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_INTERRUPT_REG_H_
 #define _SOC_INTERRUPT_REG_H_
 
@@ -18,7 +10,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 #define DPORT_PRO_MAC_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x000)
 /* DPORT_PRO_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
 /*description: */

components/soc/esp32s2/register/soc/io_mux_reg.h

@@ -6,7 +6,7 @@
 #ifndef _SOC_IO_MUX_REG_H_
 #define _SOC_IO_MUX_REG_H_
 
-#include "soc.h"
+#include "soc/soc.h"
 
 /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
 /* Output enable in sleep mode */

components/soc/esp32s2/register/soc/ledc_reg.h

@@ -1,16 +1,8 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_LEDC_REG_H_
 #define _SOC_LEDC_REG_H_
 
@@ -18,7 +10,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 #define LEDC_LSCH0_CONF0_REG          (DR_REG_LEDC_BASE + 0x0000)
 /* LEDC_OVF_CNT_RESET_ST_LSCH0 : RO ;bitpos:[17] ;default: 1'b0 ; */
 /*description: */

components/soc/esp32s2/register/soc/rmt_reg.h

@@ -5,7 +5,7 @@
  */
 #pragma once
 
-#include "soc.h"
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {

components/soc/esp32s2/register/soc/rtc_cntl_reg.h

@@ -9,7 +9,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 #define RTC_CNTL_TIME0_REG		RTC_CNTL_TIME_LOW0_REG
 #define RTC_CNTL_TIME1_REG		RTC_CNTL_TIME_HIGH0_REG
 
@@ -506,7 +506,7 @@ extern "C" {
 
 #define RTC_CNTL_INT_ENA_REG          (DR_REG_RTCCNTL_BASE + 0x0040)
 /* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: enbale gitch det interrupt*/
+/*description: enable gitch det interrupt*/
 #define RTC_CNTL_GLITCH_DET_INT_ENA  (BIT(19))
 #define RTC_CNTL_GLITCH_DET_INT_ENA_M  (BIT(19))
 #define RTC_CNTL_GLITCH_DET_INT_ENA_V  0x1
@@ -2206,7 +2206,7 @@ extern "C" {
 #define RTC_CNTL_SWD_AUTO_FEED_EN_V  0x1
 #define RTC_CNTL_SWD_AUTO_FEED_EN_S  31
 /* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: disabel SWD*/
+/*description: disable SWD*/
 #define RTC_CNTL_SWD_DISABLE  (BIT(30))
 #define RTC_CNTL_SWD_DISABLE_M  (BIT(30))
 #define RTC_CNTL_SWD_DISABLE_V  0x1
@@ -2745,7 +2745,7 @@ extern "C" {
 #define RTC_CNTL_XTAL32K_RESTART_WAIT_V  0xFFFF
 #define RTC_CNTL_XTAL32K_RESTART_WAIT_S  4
 /* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: cycles to wait to return noral xtal 32k*/
+/*description: cycles to wait to return normal xtal 32k*/
 #define RTC_CNTL_XTAL32K_RETURN_WAIT  0x0000000F
 #define RTC_CNTL_XTAL32K_RETURN_WAIT_M  ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S))
 #define RTC_CNTL_XTAL32K_RETURN_WAIT_V  0xF

components/soc/esp32s2/register/soc/rtc_cntl_struct.h

@@ -1,16 +1,8 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_RTC_CNTL_STRUCT_H_
 #define _SOC_RTC_CNTL_STRUCT_H_
 #ifdef __cplusplus
@@ -201,7 +193,7 @@ typedef volatile struct rtc_cntl_dev_s {
             uint32_t rtc_xtal32k_dead:            1;     /*enable xtal32k_dead  interrupt*/
             uint32_t rtc_cocpu_trap:              1;     /*enable cocpu trap interrupt*/
             uint32_t rtc_touch_timeout:           1;     /*enable touch timeout interrupt*/
-            uint32_t rtc_glitch_det:              1;     /*enbale gitch det interrupt*/
+            uint32_t rtc_glitch_det:              1;     /*enable gitch det interrupt*/
             uint32_t reserved20:                 12;
         };
         uint32_t val;
@@ -565,7 +557,7 @@ typedef volatile struct rtc_cntl_dev_s {
             uint32_t swd_signal_width:10;                /*adjust signal width send to swd*/
             uint32_t swd_rst_flag_clr: 1;                /*reset swd reset flag*/
             uint32_t swd_feed:         1;                /*Sw feed swd*/
-            uint32_t swd_disable:      1;                /*disabel SWD*/
+            uint32_t swd_disable:      1;                /*disable SWD*/
             uint32_t swd_auto_feed_en: 1;                /*automatically feed swd when int comes*/
         };
         uint32_t val;
@@ -690,7 +682,7 @@ typedef volatile struct rtc_cntl_dev_s {
     uint32_t xtal32k_clk_factor;                     /*xtal 32k watch dog backup clock factor*/
     union {
         struct {
-            uint32_t xtal32k_return_wait:  4;            /*cycles to wait to return noral xtal 32k*/
+            uint32_t xtal32k_return_wait:  4;            /*cycles to wait to return normal xtal 32k*/
             uint32_t xtal32k_restart_wait:16;            /*cycles to wait to repower on xtal 32k*/
             uint32_t xtal32k_wdt_timeout:  8;            /*If no clock detected for this amount of time  32k is regarded as dead*/
             uint32_t xtal32k_stable_thres: 4;            /*if restarted xtal32k period is smaller than this  it is regarded as stable*/

components/soc/esp32s2/register/soc/rtc_i2c_reg.h

@@ -1,16 +1,8 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_RTC_I2C_REG_H_
 #define _SOC_RTC_I2C_REG_H_
 
@@ -18,7 +10,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 
 /**
  * This file lists peripheral registers of an I2C controller which is part of the RTC.

components/soc/esp32s2/register/soc/rtc_io_reg.h

@@ -1,16 +1,8 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_RTC_IO_REG_H_
 #define _SOC_RTC_IO_REG_H_
 
@@ -18,7 +10,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 #define RTC_GPIO_OUT_REG          (DR_REG_RTCIO_BASE + 0x0)
 /* RTC_GPIO_OUT_DATA : R/W ;bitpos:[31:10] ;default: 0 ; */
 /*description: RTC GPIO 0 ~ 21 output data*/

components/soc/esp32s2/register/soc/sens_reg.h

@@ -1,16 +1,8 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_SENS_REG_H_
 #define _SOC_SENS_REG_H_
 
@@ -18,7 +10,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 #define SENS_SAR_READER1_CTRL_REG          (DR_REG_SENS_BASE + 0x0000)
 /* SENS_SAR1_INT_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
 /*description: enable saradc1 to send out interrupt*/

components/soc/esp32s2/register/soc/sensitive_reg.h

@@ -1,16 +1,8 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_SENSITIVE_REG_H_
 #define _SOC_SENSITIVE_REG_H_
 
@@ -18,7 +10,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 #define DPORT_PMS_SDIO_0_REG          (DR_REG_SENSITIVE_BASE + 0x000)
 /* DPORT_PMS_SDIO_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
 /*description: */

components/soc/esp32s2/register/soc/spi_mem_reg.h

@@ -6,7 +6,7 @@
 #ifndef _SOC_SPI_MEM_REG_H_
 #define _SOC_SPI_MEM_REG_H_
 
-#include "soc.h"
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -286,7 +286,7 @@ extern "C" {
 #define SPI_MEM_CS_HOLD_DLY_RES_S  2
 /* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
 /*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1:
- SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
+ SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
 #define SPI_MEM_CLK_MODE  0x00000003
 #define SPI_MEM_CLK_MODE_M  ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
 #define SPI_MEM_CLK_MODE_V  0x3
@@ -543,7 +543,7 @@ extern "C" {
 #define SPI_MEM_CS_POL_V  0x3
 #define SPI_MEM_CS_POL_S  5
 /* SPI_MEM_TRANS_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable the intterrupt of SPI transmitting done.*/
+/*description: The bit is used to enable the interrupt of SPI transmitting done.*/
 #define SPI_MEM_TRANS_END_INT_ENA  (BIT(4))
 #define SPI_MEM_TRANS_END_INT_ENA_M  (BIT(4))
 #define SPI_MEM_TRANS_END_INT_ENA_V  0x1
@@ -807,7 +807,7 @@ extern "C" {
 #define SPI_MEM_SWB_MODE_S  2
 /* SPI_MEM_SCLK_MODE : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
 /*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1:
- SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
+ SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
 #define SPI_MEM_SCLK_MODE  0x00000003
 #define SPI_MEM_SCLK_MODE_M  ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S))
 #define SPI_MEM_SCLK_MODE_V  0x3
@@ -847,7 +847,7 @@ extern "C" {
 
 #define SPI_MEM_SRAM_CLK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x050)
 /* SPI_MEM_SCLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: For SPI0 sram interface  1: spi_mem_clk is eqaul to system 0:
+/*description: For SPI0 sram interface  1: spi_mem_clk is equal to system 0:
  spi_mem_clk is divided from system clock.*/
 #define SPI_MEM_SCLK_EQU_SYSCLK  (BIT(31))
 #define SPI_MEM_SCLK_EQU_SYSCLK_M  (BIT(31))

components/soc/esp32s2/register/soc/spi_mem_struct.h

@@ -64,7 +64,7 @@ typedef volatile struct spi_mem_dev_s {
     } ctrl;
     union {
         struct {
-            uint32_t clk_mode:        2;                        /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
+            uint32_t clk_mode:        2;                        /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
             uint32_t cs_hold_dly_res:12;                        /*Delay cycles of resume Flash when resume Flash from standby mode is enable by spi clock.*/
             uint32_t cs_hold_dly:    12;                        /*SPI fsm is delayed to idle by spi clock cycles.*/
             uint32_t cs_dly_num:      2;                        /*spi_mem_cs signal is delayed by system clock cycles*/
@@ -162,7 +162,7 @@ typedef volatile struct spi_mem_dev_s {
             uint32_t cs1_dis:           1;                      /*SPI CS1 pin enable  1: disable CS1  0: spi_mem_cs1 signal is from/to CS1 pin*/
             uint32_t reserved2:         1;                      /*reserved*/
             uint32_t trans_end:         1;                      /*The bit is used to indicate the transimitting is done.*/
-            uint32_t trans_end_en:      1;                      /*The bit is used to enable the intterrupt of SPI transmitting done.*/
+            uint32_t trans_end_en:      1;                      /*The bit is used to enable the interrupt of SPI transmitting done.*/
             uint32_t cs_pol:            2;                      /*In the master mode the bits are the polarity of spi cs line  the value is equivalent to spi_mem_cs ^ spi_mem_master_cs_pol.*/
             uint32_t fsub_pin:          1;                      /*For SPI0   flash is connected to SUBPINs.*/
             uint32_t ssub_pin:          1;                      /*For SPI0   sram is connected to SUBPINs.*/
@@ -208,7 +208,7 @@ typedef volatile struct spi_mem_dev_s {
     } cache_sctrl;
     union {
         struct {
-            uint32_t sclk_mode:  2;                             /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
+            uint32_t sclk_mode:  2;                             /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
             uint32_t swb_mode:   8;                             /*Mode bits in the psram fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
             uint32_t sdin_dual:  1;                             /*For SPI0 sram  din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
             uint32_t sdout_dual: 1;                             /*For SPI0 sram  dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
@@ -249,7 +249,7 @@ typedef volatile struct spi_mem_dev_s {
             uint32_t cnt_h:           8;                        /*For SPI0 sram interface  it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
             uint32_t cnt_n:           8;                        /*For SPI0 sram interface  it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
             uint32_t reserved24:      7;                        /*reserved*/
-            uint32_t equ_sysclk:      1;                        /*For SPI0 sram interface  1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/
+            uint32_t equ_sysclk:      1;                        /*For SPI0 sram interface  1: spi_mem_clk is equal to system 0: spi_mem_clk is divided from system clock.*/
         };
         uint32_t val;
     } sram_clk;

components/soc/esp32s2/register/soc/spi_reg.h

@@ -6,7 +6,7 @@
 #ifndef _SOC_SPI_REG_H_
 #define _SOC_SPI_REG_H_
 
-#include "soc.h"
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -179,7 +179,7 @@ extern "C" {
 #define SPI_CLK_MODE_13_S  2
 /* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
 /*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1:
- SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/
+ SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. Can be configured in CONF state.*/
 #define SPI_CLK_MODE  0x00000003
 #define SPI_CLK_MODE_M  ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S))
 #define SPI_CLK_MODE_V  0x3
@@ -217,7 +217,7 @@ extern "C" {
 
 #define SPI_CLOCK_REG(i)          (REG_SPI_BASE(i) + 0x014)
 /* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is
+/*description: In the master mode 1: spi_clk is equal to system 0: spi_clk is
  divided from system clock. Can be configured in CONF state.*/
 #define SPI_CLK_EQU_SYSCLK  (BIT(31))
 #define SPI_CLK_EQU_SYSCLK_M  (BIT(31))

components/soc/esp32s2/register/soc/spi_struct.h

@@ -52,7 +52,7 @@ typedef volatile struct spi_dev_s {
     } ctrl;
     union {
         struct {
-            uint32_t clk_mode:      2;                    /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/
+            uint32_t clk_mode:      2;                    /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. Can be configured in CONF state.*/
             uint32_t clk_mode_13:   1;                    /*{CPOL  CPHA} 1: support spi clk mode 1 and 3  first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2  first edge output data B[1]/B[6].*/
             uint32_t rsck_data_out: 1;                    /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge*/
             uint32_t w16_17_wr_ena: 1;                    /*1:reg_buf[16] [17] can be written   0:reg_buf[16] [17] can not  be written. Can be configured in CONF state.*/
@@ -78,7 +78,7 @@ typedef volatile struct spi_dev_s {
             uint32_t clkcnt_h:       6;                   /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/
             uint32_t clkcnt_n:       6;                   /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/
             uint32_t clkdiv_pre:    13;                   /*In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.*/
-            uint32_t clk_equ_sysclk: 1;                   /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
+            uint32_t clk_equ_sysclk: 1;                   /*In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
         };
         uint32_t val;
     } clock;

components/soc/esp32s2/register/soc/syscon_reg.h

@@ -10,7 +10,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 #define SYSCON_SYSCLK_CONF_REG          (DR_REG_SYSCON_BASE + 0x000)
 /* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
 /*description: */

components/soc/esp32s2/register/soc/system_reg.h

@@ -10,7 +10,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 #define DPORT_ROM_CTRL_0_REG          (DR_REG_SYSTEM_BASE + 0x000)
 /* DPORT_ROM_FO : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
 /*description: */

components/soc/esp32s2/register/soc/systimer_reg.h

@@ -1,16 +1,7 @@
-/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 #pragma once
 

components/soc/esp32s2/register/soc/systimer_struct.h

@@ -1,16 +1,7 @@
-/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 #pragma once
 

components/soc/esp32s2/register/soc/uart_reg.h

@@ -1,16 +1,8 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_UART_REG_H_
 #define _SOC_UART_REG_H_
 
@@ -18,7 +10,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 #define UART_FIFO_REG(i)          (REG_UART_BASE(i) + 0x0)
 /* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */
 /*description: */

components/soc/esp32s2/register/soc/uhci_reg.h

@@ -1,16 +1,8 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_UHCI_REG_H_
 #define _SOC_UHCI_REG_H_
 
@@ -18,7 +10,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 #define UHCI_CONF0_REG(i)          (REG_UHCI_BASE(i) + 0x0)
 /* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
 /*description: */

components/soc/esp32s2/register/soc/usb_reg.h

@@ -607,7 +607,7 @@ extern "C" {
 #define USB_H_LSPDDEV0_V  0x00000001
 #define USB_H_LSPDDEV0_S  17
 /** USB_H_EPTYPE0 : R/W; bitpos: [20:18]; default: 0;
- *  0x0 (CTRL): Contro
+ *  0x0 (CTRL): Control
  *  0x1 (ISOC): Isochronous
  *  0x2 (BULK): Bulk
  *  0x3 (INTERR): Interrupt
@@ -646,7 +646,7 @@ extern "C" {
 #define USB_H_ODDFRM0_S  29
 /** USB_H_CHDIS0 : R/W; bitpos: [30]; default: 0;
  *  Channel Disable
- *  0x0 : Transmit/Recieve norma
+ *  0x0 : Transmit/Receive norma
  *  0x1 : Stop transmitting/receiving data on channel
  */
 #define USB_H_CHDIS0    (BIT(30))
@@ -719,7 +719,7 @@ extern "C" {
 #define USB_H_LSPDDEV1_V  0x00000001
 #define USB_H_LSPDDEV1_S  17
 /** USB_H_EPTYPE1 : R/W; bitpos: [20:18]; default: 0;
- *  0x0 (CTRL): Contro
+ *  0x0 (CTRL): Control
  *  0x1 (ISOC): Isochronous
  *  0x2 (BULK): Bulk
  *  0x3 (INTERR): Interrupt
@@ -758,7 +758,7 @@ extern "C" {
 #define USB_H_ODDFRM1_S  29
 /** USB_H_CHDIS1 : R/W; bitpos: [30]; default: 0;
  *  Channel Disable
- *  0x0 : Transmit/Recieve norma
+ *  0x0 : Transmit/Receive norma
  *  0x1 : Stop transmitting/receiving data on channel
  */
 #define USB_H_CHDIS1    (BIT(30))
@@ -831,7 +831,7 @@ extern "C" {
 #define USB_H_LSPDDEV2_V  0x00000001
 #define USB_H_LSPDDEV2_S  17
 /** USB_H_EPTYPE2 : R/W; bitpos: [20:18]; default: 0;
- *  0x0 (CTRL): Contro
+ *  0x0 (CTRL): Control
  *  0x1 (ISOC): Isochronous
  *  0x2 (BULK): Bulk
  *  0x3 (INTERR): Interrupt
@@ -870,7 +870,7 @@ extern "C" {
 #define USB_H_ODDFRM2_S  29
 /** USB_H_CHDIS2 : R/W; bitpos: [30]; default: 0;
  *  Channel Disable
- *  0x0 : Transmit/Recieve norma
+ *  0x0 : Transmit/Receive norma
  *  0x1 : Stop transmitting/receiving data on channel
  */
 #define USB_H_CHDIS2    (BIT(30))
@@ -943,7 +943,7 @@ extern "C" {
 #define USB_H_LSPDDEV3_V  0x00000001
 #define USB_H_LSPDDEV3_S  17
 /** USB_H_EPTYPE3 : R/W; bitpos: [20:18]; default: 0;
- *  0x0 (CTRL): Contro
+ *  0x0 (CTRL): Control
  *  0x1 (ISOC): Isochronous
  *  0x2 (BULK): Bulk
  *  0x3 (INTERR): Interrupt
@@ -982,7 +982,7 @@ extern "C" {
 #define USB_H_ODDFRM3_S  29
 /** USB_H_CHDIS3 : R/W; bitpos: [30]; default: 0;
  *  Channel Disable
- *  0x0 : Transmit/Recieve norma
+ *  0x0 : Transmit/Receive norma
  *  0x1 : Stop transmitting/receiving data on channel
  */
 #define USB_H_CHDIS3    (BIT(30))
@@ -1055,7 +1055,7 @@ extern "C" {
 #define USB_H_LSPDDEV4_V  0x00000001
 #define USB_H_LSPDDEV4_S  17
 /** USB_H_EPTYPE4 : R/W; bitpos: [20:18]; default: 0;
- *  0x0 (CTRL): Contro
+ *  0x0 (CTRL): Control
  *  0x1 (ISOC): Isochronous
  *  0x2 (BULK): Bulk
  *  0x3 (INTERR): Interrupt
@@ -1094,7 +1094,7 @@ extern "C" {
 #define USB_H_ODDFRM4_S  29
 /** USB_H_CHDIS4 : R/W; bitpos: [30]; default: 0;
  *  Channel Disable
- *  0x0 : Transmit/Recieve norma
+ *  0x0 : Transmit/Receive norma
  *  0x1 : Stop transmitting/receiving data on channel
  */
 #define USB_H_CHDIS4    (BIT(30))
@@ -1167,7 +1167,7 @@ extern "C" {
 #define USB_H_LSPDDEV5_V  0x00000001
 #define USB_H_LSPDDEV5_S  17
 /** USB_H_EPTYPE5 : R/W; bitpos: [20:18]; default: 0;
- *  0x0 (CTRL): Contro
+ *  0x0 (CTRL): Control
  *  0x1 (ISOC): Isochronous
  *  0x2 (BULK): Bulk
  *  0x3 (INTERR): Interrupt
@@ -1206,7 +1206,7 @@ extern "C" {
 #define USB_H_ODDFRM5_S  29
 /** USB_H_CHDIS5 : R/W; bitpos: [30]; default: 0;
  *  Channel Disable
- *  0x0 : Transmit/Recieve norma
+ *  0x0 : Transmit/Receive norma
  *  0x1 : Stop transmitting/receiving data on channel
  */
 #define USB_H_CHDIS5    (BIT(30))
@@ -1279,7 +1279,7 @@ extern "C" {
 #define USB_H_LSPDDEV6_V  0x00000001
 #define USB_H_LSPDDEV6_S  17
 /** USB_H_EPTYPE6 : R/W; bitpos: [20:18]; default: 0;
- *  0x0 (CTRL): Contro
+ *  0x0 (CTRL): Control
  *  0x1 (ISOC): Isochronous
  *  0x2 (BULK): Bulk
  *  0x3 (INTERR): Interrupt
@@ -1318,7 +1318,7 @@ extern "C" {
 #define USB_H_ODDFRM6_S  29
 /** USB_H_CHDIS6 : R/W; bitpos: [30]; default: 0;
  *  Channel Disable
- *  0x0 : Transmit/Recieve norma
+ *  0x0 : Transmit/Receive norma
  *  0x1 : Stop transmitting/receiving data on channel
  */
 #define USB_H_CHDIS6    (BIT(30))
@@ -1391,7 +1391,7 @@ extern "C" {
 #define USB_H_LSPDDEV7_V  0x00000001
 #define USB_H_LSPDDEV7_S  17
 /** USB_H_EPTYPE7 : R/W; bitpos: [20:18]; default: 0;
- *  0x0 (CTRL): Contro
+ *  0x0 (CTRL): Control
  *  0x1 (ISOC): Isochronous
  *  0x2 (BULK): Bulk
  *  0x3 (INTERR): Interrupt
@@ -1430,7 +1430,7 @@ extern "C" {
 #define USB_H_ODDFRM7_S  29
 /** USB_H_CHDIS7 : R/W; bitpos: [30]; default: 0;
  *  Channel Disable
- *  0x0 : Transmit/Recieve norma
+ *  0x0 : Transmit/Receive norma
  *  0x1 : Stop transmitting/receiving data on channel
  */
 #define USB_H_CHDIS7    (BIT(30))
@@ -1475,7 +1475,7 @@ extern "C" {
 /** USB_NZSTSOUTHSHK : R/W; bitpos: [2]; default: 0;
  *  1'b0: Send the received OUT packet to the application (zero-length or non-zero
  *  length) and send a handshake based on NAK and STALL bits for the endpoint in the
- *  Devce Endpoint Control Register
+ *  Device Endpoint Control Register
  *  1'b1: Send a STALL handshake on a nonzero-length status OUT transaction and do not
  *  send the received OUT packet to the application
  */
@@ -1487,7 +1487,7 @@ extern "C" {
  *  This bit can be set only if FS PHY interface is selected.
  *  Otherwise, this bit needs to be set to zero.
  *  1'b0: USB 1.1 Full-Speed Serial transiver not selected
- *  1'b1: If FS PHY interface is choosen and this bit is set, the PHY clock during Suspend
+ *  1'b1: If FS PHY interface is chosen and this bit is set, the PHY clock during Suspend
  *  must be switched from 48 MHz to 32 KHz
  */
 #define USB_ENA32KHZSUSP    (BIT(3))
@@ -1579,7 +1579,7 @@ extern "C" {
 #define USB_DCTL_REG (SOC_DPORT_USB_BASE + 0x804)
 /** USB_RMTWKUPSIG : R/W; bitpos: [0]; default: 0;
  *  0x0 : Core does not send Remote Wakeup Signaling
- *  0x1 : Core sends Remote Wakeup Signalin
+ *  0x1 : Core sends Remote Wakeup Signaling
  */
 #define USB_RMTWKUPSIG    (BIT(0))
 #define USB_RMTWKUPSIG_M  (USB_RMTWKUPSIG_V << USB_RMTWKUPSIG_S)
@@ -4728,7 +4728,7 @@ extern "C" {
 #define USB_H_NACK0_S  4
 /** USB_H_ACK0 : R/W1C; bitpos: [5]; default: 0;
  *  1'b0: No ACK Response Received or Transmitted Interrupt
- *  1'b1: ACK Response Received or Transmitted Interrup
+ *  1'b1: ACK Response Received or Transmitted Interrupt
  */
 #define USB_H_ACK0    (BIT(5))
 #define USB_H_ACK0_M  (USB_H_ACK0_V << USB_H_ACK0_S)
@@ -4964,7 +4964,7 @@ extern "C" {
 #define USB_H_NACK1_S  4
 /** USB_H_ACK1 : R/W1C; bitpos: [5]; default: 0;
  *  1'b0: No ACK Response Received or Transmitted Interrupt
- *  1'b1: ACK Response Received or Transmitted Interrup
+ *  1'b1: ACK Response Received or Transmitted Interrupt
  */
 #define USB_H_ACK1    (BIT(5))
 #define USB_H_ACK1_M  (USB_H_ACK1_V << USB_H_ACK1_S)
@@ -5200,7 +5200,7 @@ extern "C" {
 #define USB_H_NACK2_S  4
 /** USB_H_ACK2 : R/W1C; bitpos: [5]; default: 0;
  *  1'b0: No ACK Response Received or Transmitted Interrupt
- *  1'b1: ACK Response Received or Transmitted Interrup
+ *  1'b1: ACK Response Received or Transmitted Interrupt
  */
 #define USB_H_ACK2    (BIT(5))
 #define USB_H_ACK2_M  (USB_H_ACK2_V << USB_H_ACK2_S)
@@ -5436,7 +5436,7 @@ extern "C" {
 #define USB_H_NACK3_S  4
 /** USB_H_ACK3 : R/W1C; bitpos: [5]; default: 0;
  *  1'b0: No ACK Response Received or Transmitted Interrupt
- *  1'b1: ACK Response Received or Transmitted Interrup
+ *  1'b1: ACK Response Received or Transmitted Interrupt
  */
 #define USB_H_ACK3    (BIT(5))
 #define USB_H_ACK3_M  (USB_H_ACK3_V << USB_H_ACK3_S)
@@ -5672,7 +5672,7 @@ extern "C" {
 #define USB_H_NACK4_S  4
 /** USB_H_ACK4 : R/W1C; bitpos: [5]; default: 0;
  *  1'b0: No ACK Response Received or Transmitted Interrupt
- *  1'b1: ACK Response Received or Transmitted Interrup
+ *  1'b1: ACK Response Received or Transmitted Interrupt
  */
 #define USB_H_ACK4    (BIT(5))
 #define USB_H_ACK4_M  (USB_H_ACK4_V << USB_H_ACK4_S)
@@ -5908,7 +5908,7 @@ extern "C" {
 #define USB_H_NACK5_S  4
 /** USB_H_ACK5 : R/W1C; bitpos: [5]; default: 0;
  *  1'b0: No ACK Response Received or Transmitted Interrupt
- *  1'b1: ACK Response Received or Transmitted Interrup
+ *  1'b1: ACK Response Received or Transmitted Interrupt
  */
 #define USB_H_ACK5    (BIT(5))
 #define USB_H_ACK5_M  (USB_H_ACK5_V << USB_H_ACK5_S)
@@ -6144,7 +6144,7 @@ extern "C" {
 #define USB_H_NACK6_S  4
 /** USB_H_ACK6 : R/W1C; bitpos: [5]; default: 0;
  *  1'b0: No ACK Response Received or Transmitted Interrupt
- *  1'b1: ACK Response Received or Transmitted Interrup
+ *  1'b1: ACK Response Received or Transmitted Interrupt
  */
 #define USB_H_ACK6    (BIT(5))
 #define USB_H_ACK6_M  (USB_H_ACK6_V << USB_H_ACK6_S)
@@ -6380,7 +6380,7 @@ extern "C" {
 #define USB_H_NACK7_S  4
 /** USB_H_ACK7 : R/W1C; bitpos: [5]; default: 0;
  *  1'b0: No ACK Response Received or Transmitted Interrupt
- *  1'b1: ACK Response Received or Transmitted Interrup
+ *  1'b1: ACK Response Received or Transmitted Interrupt
  */
 #define USB_H_ACK7    (BIT(5))
 #define USB_H_ACK7_M  (USB_H_ACK7_V << USB_H_ACK7_S)
@@ -8914,9 +8914,9 @@ extern "C" {
 #define USB_AHBSINGLE_V  0x00000001
 #define USB_AHBSINGLE_S  23
 /** USB_INVDESCENDIANESS : R/W; bitpos: [24]; default: 0;
- *  Invert Descriptor Endianess
+ *  Invert Descriptor Endianness
  *  1'b0: Descriptor Endianness is same as AHB Master Endianness
- *  1'b1:Invert Descriptor Endianess according to AHB Master endianness
+ *  1'b1:Invert Descriptor Endianness according to AHB Master endianness
  */
 #define USB_INVDESCENDIANESS    (BIT(24))
 #define USB_INVDESCENDIANESS_M  (USB_INVDESCENDIANESS_V << USB_INVDESCENDIANESS_S)
@@ -9677,7 +9677,7 @@ extern "C" {
 
 
 /** USB_GSNPSID_REG register
- *  Synopsys ID Register
+ *  ID Register
  */
 #define USB_GSNPSID_REG (SOC_DPORT_USB_BASE + 0x40)
 /** USB_SYNOPSYSID : RO; bitpos: [32:0]; default: 1330921482;

components/soc/esp32s2/register/soc/usb_struct.h

@@ -50,7 +50,7 @@ typedef struct usb_reg {
     volatile uint32_t gnptxfsiz;            // 0x0028 Non-periodic Transmit FIFO Size Register
     volatile uint32_t gnptxsts;             // 0x002c Non-periodic Transmit FIFO/Queue Status Register
     uint32_t reserved_0x0030_0x0040[4];     // 0x0030 to 0x0040
-    volatile uint32_t gsnpsid;              // 0x0040 Synopsys ID Register
+    volatile uint32_t gsnpsid;              // 0x0040 ID Register
     volatile uint32_t ghwcfg1;              // 0x0044 User Hardware Configuration 1 Register
     volatile uint32_t ghwcfg2;              // 0x0048 User Hardware Configuration 2 Register
     volatile uint32_t ghwcfg3;              // 0x004c User Hardware Configuration 3 Register

components/soc/esp32s2/register/soc/usb_wrap_reg.h

@@ -1,16 +1,7 @@
-/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 #pragma once
 

components/soc/esp32s2/register/soc/usb_wrap_struct.h

@@ -1,16 +1,7 @@
-/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 #pragma once
 

tools/ci/check_copyright_ignore.txt

@@ -556,37 +556,16 @@ components/soc/esp32c3/include/soc/wdev_reg.h
 components/soc/esp32c3/interrupts.c
 components/soc/esp32c3/ledc_periph.c
 components/soc/esp32s2/adc_periph.c
-components/soc/esp32s2/include/soc/apb_saradc_reg.h
-components/soc/esp32s2/include/soc/assist_debug_reg.h
 components/soc/esp32s2/include/soc/bb_reg.h
 components/soc/esp32s2/include/soc/boot_mode.h
-components/soc/esp32s2/include/soc/crypto_dma_reg.h
-components/soc/esp32s2/include/soc/dedic_gpio_reg.h
-components/soc/esp32s2/include/soc/dedic_gpio_struct.h
-components/soc/esp32s2/include/soc/extmem_reg.h
 components/soc/esp32s2/include/soc/fe_reg.h
-components/soc/esp32s2/include/soc/gpio_reg.h
 components/soc/esp32s2/include/soc/gpio_sig_map.h
-components/soc/esp32s2/include/soc/i2c_reg.h
-components/soc/esp32s2/include/soc/interrupt_reg.h
-components/soc/esp32s2/include/soc/ledc_reg.h
 components/soc/esp32s2/include/soc/memprot_defs.h
 components/soc/esp32s2/include/soc/nrx_reg.h
-components/soc/esp32s2/include/soc/rtc_cntl_struct.h
-components/soc/esp32s2/include/soc/rtc_i2c_reg.h
-components/soc/esp32s2/include/soc/rtc_io_reg.h
-components/soc/esp32s2/include/soc/sens_reg.h
-components/soc/esp32s2/include/soc/sensitive_reg.h
 components/soc/esp32s2/include/soc/soc_ulp.h
-components/soc/esp32s2/include/soc/systimer_reg.h
-components/soc/esp32s2/include/soc/systimer_struct.h
 components/soc/esp32s2/include/soc/touch_sensor_channel.h
 components/soc/esp32s2/include/soc/touch_sensor_pins.h
 components/soc/esp32s2/include/soc/uart_pins.h
-components/soc/esp32s2/include/soc/uart_reg.h
-components/soc/esp32s2/include/soc/uhci_reg.h
-components/soc/esp32s2/include/soc/usb_wrap_reg.h
-components/soc/esp32s2/include/soc/usb_wrap_struct.h
 components/soc/esp32s2/include/soc/wdev_reg.h
 components/soc/esp32s2/ledc_periph.c
 components/soc/esp32s3/include/soc/apb_saradc_reg.h