From d202fc5993b2b242f4678444da57ec14746251d5 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Tue, 13 Jun 2023 19:47:03 +0800 Subject: [PATCH] ci: sync master flash_psram test and add access psram with DFS unity test --- .../flash_psram/main/test_flash_psram.c | 167 ++++++++++++++++-- .../system/flash_psram/sdkconfig.defaults | 13 ++ 2 files changed, 163 insertions(+), 17 deletions(-) create mode 100644 tools/test_apps/system/flash_psram/sdkconfig.defaults diff --git a/tools/test_apps/system/flash_psram/main/test_flash_psram.c b/tools/test_apps/system/flash_psram/main/test_flash_psram.c index cf24dcabac..71f1fa2be3 100644 --- a/tools/test_apps/system/flash_psram/main/test_flash_psram.c +++ b/tools/test_apps/system/flash_psram/main/test_flash_psram.c @@ -9,11 +9,14 @@ #include "sdkconfig.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" +#include "freertos/semphr.h" #include "esp_system.h" #include "esp_check.h" #include "esp_attr.h" #include "esp_flash.h" #include "esp_partition.h" +#include "esp_pm.h" +#include "esp_private/esp_clk.h" #if CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/spi_flash.h" #include "esp32s3/rom/opi_flash.h" @@ -31,7 +34,23 @@ #define LENGTH_PER_TIME 1024 #endif -static esp_err_t spi0_psram_test(void) +#define MHZ (1000000) +#ifndef MIN +#define MIN(x, y) (((x) < (y)) ? (x) : (y)) +#endif + +#if CONFIG_IDF_TARGET_ESP32 +typedef esp_pm_config_esp32_t esp_pm_config_t; +#elif CONFIG_IDF_TARGET_ESP32S2 +typedef esp_pm_config_esp32s2_t esp_pm_config_t; +#elif CONFIG_IDF_TARGET_ESP32S3 +typedef esp_pm_config_esp32s3_t esp_pm_config_t; +#endif + +static SemaphoreHandle_t DoneSemphr; +static SemaphoreHandle_t StopSemphr; + +static void psram_read_write_task(void* arg) { printf("----------SPI0 PSRAM Test----------\n"); @@ -41,30 +60,145 @@ static esp_err_t spi0_psram_test(void) abort(); } - uint32_t *psram_rd_buf = (uint32_t *)heap_caps_malloc(SPI0_PSRAM_TEST_LEN, MALLOC_CAP_32BIT | MALLOC_CAP_SPIRAM); + uint8_t *psram_rd_buf = (uint8_t *)heap_caps_malloc(SPI0_PSRAM_TEST_LEN, MALLOC_CAP_32BIT | MALLOC_CAP_SPIRAM); if (!psram_rd_buf) { printf("no memory\n"); abort(); } srand(399); - for (int i = 0; i < SPI0_PSRAM_TEST_LEN / LENGTH_PER_TIME; i++) { - for (int j = 0; j < sizeof(psram_wr_buf); j++) { - psram_wr_buf[j] = rand(); - } - memcpy(psram_rd_buf + i * LENGTH_PER_TIME, psram_wr_buf, LENGTH_PER_TIME); + for (uint32_t loop = 0; loop < (uint32_t)(arg); loop++) { + for (int i = 0; i < SPI0_PSRAM_TEST_LEN / LENGTH_PER_TIME; i++) { + for (int j = 0; j < sizeof(psram_wr_buf); j++) { + psram_wr_buf[j] = rand(); + } + memcpy(psram_rd_buf + i * LENGTH_PER_TIME, psram_wr_buf, LENGTH_PER_TIME); - if (memcmp(psram_rd_buf + i * LENGTH_PER_TIME, psram_wr_buf, LENGTH_PER_TIME) != 0) { - printf("Fail\n"); - free(psram_rd_buf); - free(psram_wr_buf); + if (memcmp(psram_rd_buf + i * LENGTH_PER_TIME, psram_wr_buf, LENGTH_PER_TIME) != 0) { + free(psram_rd_buf); + free(psram_wr_buf); + abort(); + } + } + xSemaphoreGive(DoneSemphr); + vTaskDelay(10); + } + free(psram_rd_buf); + free(psram_wr_buf); + vTaskDelete(NULL); +} + +static void pm_light_sleep_enable(void) +{ + int cur_freq_mhz = esp_clk_cpu_freq() / MHZ; + int xtal_freq = esp_clk_xtal_freq() / MHZ; + + esp_pm_config_t pm_config = { + .max_freq_mhz = cur_freq_mhz, + .min_freq_mhz = xtal_freq, + .light_sleep_enable = true + }; + ESP_ERROR_CHECK( esp_pm_configure(&pm_config) ); +} + +static void pm_light_sleep_disable(void) +{ + int cur_freq_mhz = esp_clk_cpu_freq() / MHZ; + + esp_pm_config_t pm_config = { + .max_freq_mhz = cur_freq_mhz, + .min_freq_mhz = cur_freq_mhz, + }; + ESP_ERROR_CHECK( esp_pm_configure(&pm_config) ); +} + +static void pm_switch_freq(int max_cpu_freq_mhz) +{ + int xtal_freq_mhz = esp_clk_xtal_freq() / MHZ; + + esp_pm_config_t pm_config = { + .max_freq_mhz = max_cpu_freq_mhz, + .min_freq_mhz = MIN(max_cpu_freq_mhz, xtal_freq_mhz), + }; + ESP_ERROR_CHECK( esp_pm_configure(&pm_config) ); + printf("Waiting for frequency to be set to %d MHz...\n", max_cpu_freq_mhz); + while (esp_clk_cpu_freq() / MHZ != max_cpu_freq_mhz) + { + vTaskDelay(pdMS_TO_TICKS(200)); + printf("Frequency is %d MHz\n", esp_clk_cpu_freq() / MHZ); + } +} + +static void goto_idle_and_check_stop(uint32_t period) +{ + if (xSemaphoreTake(StopSemphr, pdMS_TO_TICKS(period)) == pdTRUE) { + pm_switch_freq(CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ); + vSemaphoreDelete(StopSemphr); + vTaskDelete(NULL); + } +} + +static void pm_switch_task(void *arg) +{ + pm_light_sleep_disable(); + uint32_t period = 100; + StopSemphr = xSemaphoreCreateBinary(); + while (1) { + pm_light_sleep_enable(); + goto_idle_and_check_stop(period); + pm_light_sleep_disable(); + goto_idle_and_check_stop(period); + pm_switch_freq(10); + goto_idle_and_check_stop(period); + pm_switch_freq(80); + goto_idle_and_check_stop(period); + pm_switch_freq(40); + goto_idle_and_check_stop(period); + } +} + +static esp_err_t spi0_psram_test(void) +{ + DoneSemphr = xSemaphoreCreateCounting(1, 0); + xTaskCreate(psram_read_write_task, "", 2048, (void *)(1), 3, NULL); + if (xSemaphoreTake(DoneSemphr, pdMS_TO_TICKS(1000)) == pdTRUE) { + printf(DRAM_STR("----------SPI0 PSRAM Test Success----------\n\n")); + } else { + printf(DRAM_STR("----------SPI0 PSRAM Test Timeout----------\n\n")); + return ESP_FAIL; + } + + vSemaphoreDelete(DoneSemphr); + /* Wait for test_task to finish up */ + vTaskDelay(100); + return ESP_OK; +} + +static esp_err_t spi0_psram_with_dfs_test(void) +{ + printf("----------Access SPI0 PSRAM with DFS Test----------\n"); + + uint32_t test_loop = 50; + DoneSemphr = xSemaphoreCreateCounting(test_loop, 0); + + xTaskCreatePinnedToCore(pm_switch_task, "", 4096, NULL, 3, NULL, 0); + xTaskCreatePinnedToCore(psram_read_write_task, "", 2048, (void *)(test_loop), 3, NULL, 1); + + int cnt = 0; + while (cnt < test_loop) { + if (xSemaphoreTake(DoneSemphr, pdMS_TO_TICKS(1000)) == pdTRUE) { + cnt++; + } else { + vSemaphoreDelete(DoneSemphr); + printf(DRAM_STR("----------SPI0 PSRAM Test Timeout----------\n\n")); return ESP_FAIL; } } - - free(psram_rd_buf); - free(psram_wr_buf); - printf(DRAM_STR("----------SPI0 PSRAM Test Success----------\n\n")); + xSemaphoreGive(StopSemphr); + vSemaphoreDelete(DoneSemphr); + /* Wait for test_task to finish up */ + vTaskDelay(pdMS_TO_TICKS(500)); + printf(DRAM_STR("----------Access SPI0 PSRAM with DFS Test Success----------\n\n")); return ESP_OK; } #endif @@ -76,8 +210,6 @@ static esp_err_t spi0_psram_test(void) #define SPI1_FLASH_TEST_NUM (SECTOR_LEN / SPI1_FLASH_TEST_LEN) #define SPI1_FLASH_TEST_ADDR 0x2a0000 -extern void spi_flash_disable_interrupts_caches_and_other_cpu(void); -extern void spi_flash_enable_interrupts_caches_and_other_cpu(void); static uint8_t rd_buf[SPI1_FLASH_TEST_LEN]; static uint8_t wr_buf[SPI1_FLASH_TEST_LEN]; @@ -158,6 +290,7 @@ void app_main(void) #if CONFIG_SPIRAM ESP_ERROR_CHECK(spi0_psram_test()); + ESP_ERROR_CHECK(spi0_psram_with_dfs_test()); #endif ESP_ERROR_CHECK(spi1_flash_test()); diff --git a/tools/test_apps/system/flash_psram/sdkconfig.defaults b/tools/test_apps/system/flash_psram/sdkconfig.defaults new file mode 100644 index 0000000000..37e3ef3de0 --- /dev/null +++ b/tools/test_apps/system/flash_psram/sdkconfig.defaults @@ -0,0 +1,13 @@ +CONFIG_FREERTOS_HZ=1000 +CONFIG_ESP_TASK_WDT_EN=n + +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions.csv" + +# For test access psram with DFS enabled +CONFIG_SPIRAM_FETCH_INSTRUCTIONS=y +CONFIG_SPIRAM_RODATA=y +CONFIG_PM_ENABLE=y +CONFIG_FREERTOS_USE_TICKLESS_IDLE=y +CONFIG_FREERTOS_IDLE_TIME_BEFORE_SLEEP=5