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test: fix the IRAM type conflict issue using heap_caps_malloc

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This commit is contained in:
Michael (XIAO Xufeng) 2018-10-19 12:00:16 +08:00
parent 7c29a39d6f
commit d0361a32d7
3 changed files with 40 additions and 17 deletions
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21
components/driver/test/test_spi_master.c
View File

@ -507,7 +507,6 @@ TEST_CASE("SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)"
TEST_ASSERT(spi_bus_free(host) == ESP_OK);
}
IRAM_ATTR static uint32_t data_iram[80];
DRAM_ATTR static uint32_t data_dram[80]={0};
//force to place in code area.
static const uint8_t data_drom[320+3] = {
@ -544,13 +543,24 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]")
#ifdef CONFIG_SPIRAM_SUPPORT
//test psram if enabled
ESP_LOGI(TAG, "testing PSRAM...");
uint32_t* data_malloc = (uint32_t*)heap_caps_calloc(1, 324, MALLOC_CAP_SPIRAM);
uint32_t* data_malloc = (uint32_t*)heap_caps_malloc(324, MALLOC_CAP_SPIRAM);
TEST_ASSERT(esp_ptr_external_ram(data_malloc));
#else
uint32_t* data_malloc = (uint32_t*)heap_caps_calloc(1, 324, MALLOC_CAP_DMA);
uint32_t* data_malloc = (uint32_t*)heap_caps_malloc(324, MALLOC_CAP_DMA);
TEST_ASSERT(esp_ptr_in_dram(data_malloc));
#endif
TEST_ASSERT(data_malloc != NULL);
//refer to soc_memory_layout.c
uint32_t* data_iram = (uint32_t*)heap_caps_malloc(324, MALLOC_CAP_EXEC);
TEST_ASSERT(data_iram != NULL);
ESP_LOGI(TAG, "iram: %p, dram: %p", data_iram, data_dram);
ESP_LOGI(TAG, "drom: %p, malloc: %p", data_drom, data_malloc);
TEST_ASSERT(esp_ptr_in_dram(data_dram));
TEST_ASSERT(esp_ptr_in_iram(data_iram));
TEST_ASSERT(esp_ptr_in_drom(data_drom));
srand(52);
for (int i = 0; i < 320/4; i++) {
data_iram[i] = rand();
@ -577,8 +587,6 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]")
static spi_transaction_t trans[TEST_REGION_SIZE];
int x;
ESP_LOGI(TAG, "iram: %p, dram: %p", data_iram, data_dram);
ESP_LOGI(TAG, "drom: %p, malloc: %p", data_drom, data_malloc);
memset(trans, 0, sizeof(trans));
@ -619,6 +627,7 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]")
TEST_ASSERT(spi_bus_remove_device(spi) == ESP_OK);
TEST_ASSERT(spi_bus_free(HSPI_HOST) == ESP_OK);
free(data_malloc);
free(data_iram);
}
//this part tests 3 DMA issues in master mode, full-duplex in IDF2.1

24
components/soc/esp32/include/soc/soc.h
View File

@ -59,16 +59,18 @@
#define APP_CPU_NUM (1)
/* Overall memory map */
#define SOC_IROM_LOW 0x400D0000
#define SOC_IROM_HIGH 0x40400000
#define SOC_DROM_LOW 0x3F400000
#define SOC_DROM_HIGH 0x3F800000
#define SOC_RTC_IRAM_LOW 0x400C0000
#define SOC_RTC_IRAM_HIGH 0x400C2000
#define SOC_RTC_DATA_LOW 0x50000000
#define SOC_RTC_DATA_HIGH 0x50002000
#define SOC_EXTRAM_DATA_LOW 0x3F800000
#define SOC_EXTRAM_DATA_HIGH 0x3FC00000
#define SOC_IROM_LOW 0x400D0000
#define SOC_IROM_HIGH 0x40400000
#define SOC_DROM_LOW 0x3F400000
#define SOC_DROM_HIGH 0x3F800000
#define SOC_DRAM_LOW 0x3FAE0000
#define SOC_DRAM_HIGH 0x40000000
#define SOC_RTC_IRAM_LOW 0x400C0000
#define SOC_RTC_IRAM_HIGH 0x400C2000
#define SOC_RTC_DATA_LOW 0x50000000
#define SOC_RTC_DATA_HIGH 0x50002000
#define SOC_EXTRAM_DATA_LOW 0x3F800000
#define SOC_EXTRAM_DATA_HIGH 0x3FC00000
#define DR_REG_DPORT_BASE 0x3ff00000
@ -130,7 +132,7 @@
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
#ifndef __ASSEMBLER__
#define BIT(nr) (1UL << (nr))

12
components/soc/include/soc/soc_memory_layout.h
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@ -173,3 +173,15 @@ inline static bool IRAM_ATTR esp_ptr_internal(const void *p) {
inline static bool IRAM_ATTR esp_ptr_external_ram(const void *p) {
return ((intptr_t)p >= SOC_EXTRAM_DATA_LOW && (intptr_t)p < SOC_EXTRAM_DATA_HIGH);
}
inline static bool IRAM_ATTR esp_ptr_in_iram(const void *p) {
return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH);
}
inline static bool IRAM_ATTR esp_ptr_in_drom(const void *p) {
return ((intptr_t)p >= SOC_DROM_LOW && (intptr_t)p < SOC_DROM_HIGH);
}
inline static bool IRAM_ATTR esp_ptr_in_dram(const void *p) {
return ((intptr_t)p >= SOC_DRAM_LOW && (intptr_t)p < SOC_DRAM_HIGH);
}