diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.ld index 58573775ad..11ccda2fb8 100644 --- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.ld +++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.ld @@ -1,13 +1,12 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ - /* ROM function interface esp32h2.rom.ld for esp32h2 * * - * Generated from ./interface-esp32h2.yml md5sum a4343bd6a9a68319e4e3cc26aea38574 + * Generated from ./target/esp32h2/interface-esp32h2.yml md5sum da4c474a48c097d4ac9acad67f70fda6 * * Compatible with ROM where ECO version equal or greater to 0. * @@ -34,35 +33,39 @@ ets_install_lock = 0x40000044; ets_backup_dma_copy = 0x40000048; ets_apb_backup_init_lock_func = 0x4000004c; UartRxString = 0x40000050; -uart_tx_one_char = 0x40000054; -uart_tx_one_char2 = 0x40000058; -uart_rx_one_char = 0x4000005c; -uart_rx_one_char_block = 0x40000060; -uart_rx_readbuff = 0x40000064; -uartAttach = 0x40000068; -uart_tx_flush = 0x4000006c; -uart_tx_wait_idle = 0x40000070; -uart_div_modify = 0x40000074; -ets_write_char_uart = 0x40000078; -uart_tx_switch = 0x4000007c; -multofup = 0x40000080; -software_reset = 0x40000084; -software_reset_cpu = 0x40000088; -assist_debug_clock_enable = 0x4000008c; -assist_debug_record_enable = 0x40000090; -clear_super_wdt_reset_flag = 0x40000094; -disable_default_watchdog = 0x40000098; -esp_rom_set_rtc_wake_addr = 0x4000009c; -esp_rom_get_rtc_wake_addr = 0x400000a0; -send_packet = 0x400000a4; -recv_packet = 0x400000a8; -GetUartDevice = 0x400000ac; -UartDwnLdProc = 0x400000b0; -Uart_Init = 0x400000b4; -ets_set_user_start = 0x400000b8; +UartGetCmdLn = 0x40000054; +uart_tx_one_char = 0x40000058; +uart_tx_one_char2 = 0x4000005c; +uart_rx_one_char = 0x40000060; +uart_rx_one_char_block = 0x40000064; +uart_rx_readbuff = 0x40000068; +uartAttach = 0x4000006c; +uart_tx_flush = 0x40000070; +uart_tx_wait_idle = 0x40000074; +uart_div_modify = 0x40000078; +ets_write_char_uart = 0x4000007c; +uart_tx_switch = 0x40000080; +multofup = 0x40000084; +software_reset = 0x40000088; +software_reset_cpu = 0x4000008c; +assist_debug_clock_enable = 0x40000090; +assist_debug_record_enable = 0x40000094; +clear_super_wdt_reset_flag = 0x40000098; +disable_default_watchdog = 0x4000009c; +esp_rom_set_rtc_wake_addr = 0x400000a0; +esp_rom_get_rtc_wake_addr = 0x400000a4; +send_packet = 0x400000a8; +recv_packet = 0x400000ac; +GetUartDevice = 0x400000b0; +UartDwnLdProc = 0x400000b4; +GetSecurityInfoProc = 0x400000b8; +Uart_Init = 0x400000bc; +ets_set_user_start = 0x400000c0; /* Data (.data, .bss, .rodata) */ ets_rom_layout_p = 0x3ff1fffc; -ets_ops_table_ptr = 0x3fcdfffc; +ets_ops_table_ptr = 0x3fcdfff8; +g_uart_print = 0x3fcdfffd; +g_usb_print = 0x3fcdfffc; /*************************************** @@ -70,22 +73,31 @@ ets_ops_table_ptr = 0x3fcdfffc; ***************************************/ /* Functions */ -mz_adler32 = 0x400000bc; -mz_free = 0x400000c0; -tdefl_compress = 0x400000c4; -tdefl_compress_buffer = 0x400000c8; -tdefl_compress_mem_to_heap = 0x400000cc; -tdefl_compress_mem_to_mem = 0x400000d0; -tdefl_compress_mem_to_output = 0x400000d4; -tdefl_get_adler32 = 0x400000d8; -tdefl_get_prev_return_status = 0x400000dc; -tdefl_init = 0x400000e0; -tdefl_write_image_to_png_file_in_memory = 0x400000e4; -tdefl_write_image_to_png_file_in_memory_ex = 0x400000e8; -tinfl_decompress = 0x400000ec; -tinfl_decompress_mem_to_callback = 0x400000f0; -tinfl_decompress_mem_to_heap = 0x400000f4; -tinfl_decompress_mem_to_mem = 0x400000f8; +mz_adler32 = 0x400000c4; +mz_free = 0x400000c8; +tdefl_compress = 0x400000cc; +tdefl_compress_buffer = 0x400000d0; +tdefl_compress_mem_to_heap = 0x400000d4; +tdefl_compress_mem_to_mem = 0x400000d8; +tdefl_compress_mem_to_output = 0x400000dc; +tdefl_get_adler32 = 0x400000e0; +tdefl_get_prev_return_status = 0x400000e4; +tdefl_init = 0x400000e8; +tdefl_write_image_to_png_file_in_memory = 0x400000ec; +tdefl_write_image_to_png_file_in_memory_ex = 0x400000f0; +tinfl_decompress = 0x400000f4; +tinfl_decompress_mem_to_callback = 0x400000f8; +tinfl_decompress_mem_to_heap = 0x400000fc; +tinfl_decompress_mem_to_mem = 0x40000100; + + +/*************************************** + Group tjpgd + ***************************************/ + +/* Functions */ +jd_prepare = 0x40000104; +jd_decomp = 0x40000108; /*************************************** @@ -93,81 +105,81 @@ tinfl_decompress_mem_to_mem = 0x400000f8; ***************************************/ /* Functions */ -PROVIDE( esp_rom_spiflash_wait_idle = 0x400000fc ); -PROVIDE( esp_rom_spiflash_write_encrypted = 0x40000100 ); -PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000104 ); -PROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000108 ); -PROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x4000010c ); -PROVIDE( esp_rom_spiflash_erase_chip = 0x40000110 ); -PROVIDE( _esp_rom_spiflash_erase_sector = 0x40000114 ); -PROVIDE( _esp_rom_spiflash_erase_block = 0x40000118 ); -PROVIDE( _esp_rom_spiflash_write = 0x4000011c ); -PROVIDE( _esp_rom_spiflash_read = 0x40000120 ); -PROVIDE( _esp_rom_spiflash_unlock = 0x40000124 ); -PROVIDE( _SPIEraseArea = 0x40000128 ); -PROVIDE( _SPI_write_enable = 0x4000012c ); -PROVIDE( esp_rom_spiflash_erase_sector = 0x40000130 ); -PROVIDE( esp_rom_spiflash_erase_block = 0x40000134 ); -PROVIDE( esp_rom_spiflash_write = 0x40000138 ); -PROVIDE( esp_rom_spiflash_read = 0x4000013c ); -PROVIDE( esp_rom_spiflash_unlock = 0x40000140 ); -PROVIDE( SPIEraseArea = 0x40000144 ); -PROVIDE( SPI_write_enable = 0x40000148 ); -PROVIDE( esp_rom_spiflash_config_param = 0x4000014c ); -PROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000150 ); -PROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000154 ); -PROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000158 ); -PROVIDE( esp_rom_spi_flash_send_resume = 0x4000015c ); -PROVIDE( esp_rom_spi_flash_update_id = 0x40000160 ); -PROVIDE( esp_rom_spiflash_config_clk = 0x40000164 ); -PROVIDE( esp_rom_spiflash_config_readmode = 0x40000168 ); -PROVIDE( esp_rom_spiflash_read_status = 0x4000016c ); -PROVIDE( esp_rom_spiflash_read_statushigh = 0x40000170 ); -PROVIDE( esp_rom_spiflash_write_status = 0x40000174 ); -PROVIDE( spi_flash_attach = 0x40000178 ); -PROVIDE( spi_flash_get_chip_size = 0x4000017c ); -PROVIDE( spi_flash_guard_set = 0x40000180 ); -PROVIDE( spi_flash_guard_get = 0x40000184 ); -PROVIDE( spi_flash_read_encrypted = 0x40000188 ); -PROVIDE( spi_flash_mmap_os_func_set = 0x4000018c ); -PROVIDE( spi_flash_mmap_page_num_init = 0x40000190 ); -PROVIDE( spi_flash_mmap = 0x40000194 ); -PROVIDE( spi_flash_mmap_pages = 0x40000198 ); -PROVIDE( spi_flash_munmap = 0x4000019c ); -PROVIDE( spi_flash_mmap_dump = 0x400001a0 ); -PROVIDE( spi_flash_check_and_flush_cache = 0x400001a4 ); -PROVIDE( spi_flash_mmap_get_free_pages = 0x400001a8 ); -PROVIDE( spi_flash_cache2phys = 0x400001ac ); -PROVIDE( spi_flash_phys2cache = 0x400001b0 ); -PROVIDE( spi_flash_disable_cache = 0x400001b4 ); -PROVIDE( spi_flash_restore_cache = 0x400001b8 ); -PROVIDE( spi_flash_cache_enabled = 0x400001bc ); -PROVIDE( spi_flash_enable_cache = 0x400001c0 ); -PROVIDE( spi_cache_mode_switch = 0x400001c4 ); -PROVIDE( spi_common_set_dummy_output = 0x400001c8 ); -PROVIDE( spi_common_set_flash_cs_timing = 0x400001cc ); -PROVIDE( esp_rom_spi_set_address_bit_len = 0x400001d0 ); -PROVIDE( esp_enable_cache_flash_wrap = 0x400001d4 ); -PROVIDE( SPILock = 0x400001d8 ); -PROVIDE( SPIMasterReadModeCnfig = 0x400001dc ); -PROVIDE( SPI_Common_Command = 0x400001e0 ); -PROVIDE( SPI_WakeUp = 0x400001e4 ); -PROVIDE( SPI_block_erase = 0x400001e8 ); -PROVIDE( SPI_chip_erase = 0x400001ec ); -PROVIDE( SPI_init = 0x400001f0 ); -PROVIDE( SPI_page_program = 0x400001f4 ); -PROVIDE( SPI_read_data = 0x400001f8 ); -PROVIDE( SPI_sector_erase = 0x400001fc ); -PROVIDE( SelectSpiFunction = 0x40000200 ); -PROVIDE( SetSpiDrvs = 0x40000204 ); -PROVIDE( Wait_SPI_Idle = 0x40000208 ); -PROVIDE( spi_dummy_len_fix = 0x4000020c ); -PROVIDE( Disable_QMode = 0x40000210 ); -PROVIDE( Enable_QMode = 0x40000214 ); +PROVIDE( esp_rom_spiflash_wait_idle = 0x4000010c ); +PROVIDE( esp_rom_spiflash_write_encrypted = 0x40000110 ); +PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000114 ); +PROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000118 ); +PROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x4000011c ); +PROVIDE( esp_rom_spiflash_erase_chip = 0x40000120 ); +PROVIDE( _esp_rom_spiflash_erase_sector = 0x40000124 ); +PROVIDE( _esp_rom_spiflash_erase_block = 0x40000128 ); +PROVIDE( _esp_rom_spiflash_write = 0x4000012c ); +PROVIDE( _esp_rom_spiflash_read = 0x40000130 ); +PROVIDE( _esp_rom_spiflash_unlock = 0x40000134 ); +PROVIDE( _SPIEraseArea = 0x40000138 ); +PROVIDE( _SPI_write_enable = 0x4000013c ); +PROVIDE( esp_rom_spiflash_erase_sector = 0x40000140 ); +PROVIDE( esp_rom_spiflash_erase_block = 0x40000144 ); +PROVIDE( esp_rom_spiflash_write = 0x40000148 ); +PROVIDE( esp_rom_spiflash_read = 0x4000014c ); +PROVIDE( esp_rom_spiflash_unlock = 0x40000150 ); +PROVIDE( SPIEraseArea = 0x40000154 ); +PROVIDE( SPI_write_enable = 0x40000158 ); +PROVIDE( esp_rom_spiflash_config_param = 0x4000015c ); +PROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000160 ); +PROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000164 ); +PROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000168 ); +PROVIDE( esp_rom_spi_flash_send_resume = 0x4000016c ); +PROVIDE( esp_rom_spi_flash_update_id = 0x40000170 ); +PROVIDE( esp_rom_spiflash_config_clk = 0x40000174 ); +PROVIDE( esp_rom_spiflash_config_readmode = 0x40000178 ); +PROVIDE( esp_rom_spiflash_read_status = 0x4000017c ); +PROVIDE( esp_rom_spiflash_read_statushigh = 0x40000180 ); +PROVIDE( esp_rom_spiflash_write_status = 0x40000184 ); +PROVIDE( spi_flash_attach = 0x40000188 ); +PROVIDE( spi_flash_get_chip_size = 0x4000018c ); +PROVIDE( spi_flash_guard_set = 0x40000190 ); +PROVIDE( spi_flash_guard_get = 0x40000194 ); +PROVIDE( spi_flash_read_encrypted = 0x40000198 ); +PROVIDE( spi_flash_mmap_os_func_set = 0x4000019c ); +PROVIDE( spi_flash_mmap_page_num_init = 0x400001a0 ); +PROVIDE( spi_flash_mmap = 0x400001a4 ); +PROVIDE( spi_flash_mmap_pages = 0x400001a8 ); +PROVIDE( spi_flash_munmap = 0x400001ac ); +PROVIDE( spi_flash_mmap_dump = 0x400001b0 ); +PROVIDE( spi_flash_check_and_flush_cache = 0x400001b4 ); +PROVIDE( spi_flash_mmap_get_free_pages = 0x400001b8 ); +PROVIDE( spi_flash_cache2phys = 0x400001bc ); +PROVIDE( spi_flash_phys2cache = 0x400001c0 ); +PROVIDE( spi_flash_disable_cache = 0x400001c4 ); +PROVIDE( spi_flash_restore_cache = 0x400001c8 ); +PROVIDE( spi_flash_cache_enabled = 0x400001cc ); +PROVIDE( spi_flash_enable_cache = 0x400001d0 ); +PROVIDE( spi_cache_mode_switch = 0x400001d4 ); +PROVIDE( spi_common_set_dummy_output = 0x400001d8 ); +PROVIDE( spi_common_set_flash_cs_timing = 0x400001dc ); +PROVIDE( esp_rom_spi_set_address_bit_len = 0x400001e0 ); +PROVIDE( esp_enable_cache_flash_wrap = 0x400001e4 ); +PROVIDE( SPILock = 0x400001e8 ); +PROVIDE( SPIMasterReadModeCnfig = 0x400001ec ); +PROVIDE( SPI_Common_Command = 0x400001f0 ); +PROVIDE( SPI_WakeUp = 0x400001f4 ); +PROVIDE( SPI_block_erase = 0x400001f8 ); +PROVIDE( SPI_chip_erase = 0x400001fc ); +PROVIDE( SPI_init = 0x40000200 ); +PROVIDE( SPI_page_program = 0x40000204 ); +PROVIDE( SPI_read_data = 0x40000208 ); +PROVIDE( SPI_sector_erase = 0x4000020c ); +PROVIDE( SelectSpiFunction = 0x40000210 ); +PROVIDE( SetSpiDrvs = 0x40000214 ); +PROVIDE( Wait_SPI_Idle = 0x40000218 ); +PROVIDE( spi_dummy_len_fix = 0x4000021c ); +PROVIDE( Disable_QMode = 0x40000220 ); +PROVIDE( Enable_QMode = 0x40000224 ); /* Data (.data, .bss, .rodata) */ -PROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff4 ); -PROVIDE( rom_spiflash_legacy_data = 0x3fcdfff0 ); -PROVIDE( g_flash_guard_ops = 0x3fcdfff8 ); +PROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff0 ); +PROVIDE( rom_spiflash_legacy_data = 0x3fcdffec ); +PROVIDE( g_flash_guard_ops = 0x3fcdfff4 ); /*************************************** @@ -175,55 +187,55 @@ PROVIDE( g_flash_guard_ops = 0x3fcdfff8 ); ***************************************/ /* Functions */ -PROVIDE( spi_flash_hal_poll_cmd_done = 0x40000218 ); -PROVIDE( spi_flash_hal_device_config = 0x4000021c ); -PROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000220 ); -PROVIDE( spi_flash_hal_common_command = 0x40000224 ); -PROVIDE( spi_flash_hal_read = 0x40000228 ); -PROVIDE( spi_flash_hal_erase_chip = 0x4000022c ); -PROVIDE( spi_flash_hal_erase_sector = 0x40000230 ); -PROVIDE( spi_flash_hal_erase_block = 0x40000234 ); -PROVIDE( spi_flash_hal_program_page = 0x40000238 ); -PROVIDE( spi_flash_hal_set_write_protect = 0x4000023c ); -PROVIDE( spi_flash_hal_host_idle = 0x40000240 ); -PROVIDE( spi_flash_hal_check_status = 0x40000244 ); -PROVIDE( spi_flash_hal_setup_read_suspend = 0x40000248 ); -PROVIDE( spi_flash_hal_setup_auto_suspend_mode = 0x4000024c ); -PROVIDE( spi_flash_hal_setup_auto_resume_mode = 0x40000250 ); -PROVIDE( spi_flash_hal_disable_auto_suspend_mode = 0x40000254 ); -PROVIDE( spi_flash_hal_disable_auto_resume_mode = 0x40000258 ); -PROVIDE( spi_flash_hal_resume = 0x4000025c ); -PROVIDE( spi_flash_hal_suspend = 0x40000260 ); -PROVIDE( spi_flash_encryption_hal_enable = 0x40000264 ); -PROVIDE( spi_flash_encryption_hal_disable = 0x40000268 ); -PROVIDE( spi_flash_encryption_hal_prepare = 0x4000026c ); -PROVIDE( spi_flash_encryption_hal_done = 0x40000270 ); -PROVIDE( spi_flash_encryption_hal_destroy = 0x40000274 ); -PROVIDE( spi_flash_encryption_hal_check = 0x40000278 ); -PROVIDE( wdt_hal_init = 0x4000027c ); -PROVIDE( wdt_hal_deinit = 0x40000280 ); -PROVIDE( wdt_hal_config_stage = 0x40000284 ); -PROVIDE( wdt_hal_write_protect_disable = 0x40000288 ); -PROVIDE( wdt_hal_write_protect_enable = 0x4000028c ); -PROVIDE( wdt_hal_enable = 0x40000290 ); -PROVIDE( wdt_hal_disable = 0x40000294 ); -PROVIDE( wdt_hal_handle_intr = 0x40000298 ); -PROVIDE( wdt_hal_feed = 0x4000029c ); -PROVIDE( wdt_hal_set_flashboot_en = 0x400002a0 ); -PROVIDE( wdt_hal_is_enabled = 0x400002a4 ); -PROVIDE( systimer_hal_init = 0x400002a8 ); -PROVIDE( systimer_hal_get_counter_value = 0x400002ac ); -PROVIDE( systimer_hal_get_time = 0x400002b0 ); -PROVIDE( systimer_hal_set_alarm_target = 0x400002b4 ); -PROVIDE( systimer_hal_set_alarm_period = 0x400002b8 ); -PROVIDE( systimer_hal_get_alarm_value = 0x400002bc ); -PROVIDE( systimer_hal_enable_alarm_int = 0x400002c0 ); -PROVIDE( systimer_hal_on_apb_freq_update = 0x400002c4 ); -PROVIDE( systimer_hal_counter_value_advance = 0x400002c8 ); -PROVIDE( systimer_hal_enable_counter = 0x400002cc ); -PROVIDE( systimer_hal_select_alarm_mode = 0x400002d0 ); -PROVIDE( systimer_hal_connect_alarm_counter = 0x400002d4 ); -PROVIDE( systimer_hal_counter_can_stall_by_cpu = 0x400002d8 ); +PROVIDE( spi_flash_hal_poll_cmd_done = 0x40000228 ); +PROVIDE( spi_flash_hal_device_config = 0x4000022c ); +PROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000230 ); +PROVIDE( spi_flash_hal_common_command = 0x40000234 ); +PROVIDE( spi_flash_hal_read = 0x40000238 ); +PROVIDE( spi_flash_hal_erase_chip = 0x4000023c ); +PROVIDE( spi_flash_hal_erase_sector = 0x40000240 ); +PROVIDE( spi_flash_hal_erase_block = 0x40000244 ); +PROVIDE( spi_flash_hal_program_page = 0x40000248 ); +PROVIDE( spi_flash_hal_set_write_protect = 0x4000024c ); +PROVIDE( spi_flash_hal_host_idle = 0x40000250 ); +PROVIDE( spi_flash_hal_check_status = 0x40000254 ); +PROVIDE( spi_flash_hal_setup_read_suspend = 0x40000258 ); +PROVIDE( spi_flash_hal_setup_auto_suspend_mode = 0x4000025c ); +PROVIDE( spi_flash_hal_setup_auto_resume_mode = 0x40000260 ); +PROVIDE( spi_flash_hal_disable_auto_suspend_mode = 0x40000264 ); +PROVIDE( spi_flash_hal_disable_auto_resume_mode = 0x40000268 ); +PROVIDE( spi_flash_hal_resume = 0x4000026c ); +PROVIDE( spi_flash_hal_suspend = 0x40000270 ); +PROVIDE( spi_flash_encryption_hal_enable = 0x40000274 ); +PROVIDE( spi_flash_encryption_hal_disable = 0x40000278 ); +PROVIDE( spi_flash_encryption_hal_prepare = 0x4000027c ); +PROVIDE( spi_flash_encryption_hal_done = 0x40000280 ); +PROVIDE( spi_flash_encryption_hal_destroy = 0x40000284 ); +PROVIDE( spi_flash_encryption_hal_check = 0x40000288 ); +PROVIDE( wdt_hal_init = 0x4000028c ); +PROVIDE( wdt_hal_deinit = 0x40000290 ); +PROVIDE( wdt_hal_config_stage = 0x40000294 ); +PROVIDE( wdt_hal_write_protect_disable = 0x40000298 ); +PROVIDE( wdt_hal_write_protect_enable = 0x4000029c ); +PROVIDE( wdt_hal_enable = 0x400002a0 ); +PROVIDE( wdt_hal_disable = 0x400002a4 ); +PROVIDE( wdt_hal_handle_intr = 0x400002a8 ); +PROVIDE( wdt_hal_feed = 0x400002ac ); +PROVIDE( wdt_hal_set_flashboot_en = 0x400002b0 ); +PROVIDE( wdt_hal_is_enabled = 0x400002b4 ); +PROVIDE( systimer_hal_init = 0x400002b8 ); +PROVIDE( systimer_hal_get_counter_value = 0x400002bc ); +PROVIDE( systimer_hal_get_time = 0x400002c0 ); +PROVIDE( systimer_hal_set_alarm_target = 0x400002c4 ); +PROVIDE( systimer_hal_set_alarm_period = 0x400002c8 ); +PROVIDE( systimer_hal_get_alarm_value = 0x400002cc ); +PROVIDE( systimer_hal_enable_alarm_int = 0x400002d0 ); +PROVIDE( systimer_hal_on_apb_freq_update = 0x400002d4 ); +PROVIDE( systimer_hal_counter_value_advance = 0x400002d8 ); +PROVIDE( systimer_hal_enable_counter = 0x400002dc ); +PROVIDE( systimer_hal_select_alarm_mode = 0x400002e0 ); +PROVIDE( systimer_hal_connect_alarm_counter = 0x400002e4 ); +PROVIDE( systimer_hal_counter_can_stall_by_cpu = 0x400002e8 ); /*************************************** @@ -231,49 +243,49 @@ PROVIDE( systimer_hal_counter_can_stall_by_cpu = 0x400002d8 ); ***************************************/ /* Functions */ -PROVIDE( tlsf_create = 0x400002dc ); -PROVIDE( tlsf_create_with_pool = 0x400002e0 ); -PROVIDE( tlsf_get_pool = 0x400002e4 ); -PROVIDE( tlsf_add_pool = 0x400002e8 ); -PROVIDE( tlsf_remove_pool = 0x400002ec ); -PROVIDE( tlsf_malloc = 0x400002f0 ); -PROVIDE( tlsf_memalign = 0x400002f4 ); -PROVIDE( tlsf_memalign_offs = 0x400002f8 ); -PROVIDE( tlsf_realloc = 0x400002fc ); -PROVIDE( tlsf_free = 0x40000300 ); -PROVIDE( tlsf_block_size = 0x40000304 ); -PROVIDE( tlsf_size = 0x40000308 ); -PROVIDE( tlsf_align_size = 0x4000030c ); -PROVIDE( tlsf_block_size_min = 0x40000310 ); -PROVIDE( tlsf_block_size_max = 0x40000314 ); -PROVIDE( tlsf_pool_overhead = 0x40000318 ); -PROVIDE( tlsf_alloc_overhead = 0x4000031c ); -PROVIDE( tlsf_walk_pool = 0x40000320 ); -PROVIDE( tlsf_check = 0x40000324 ); -PROVIDE( tlsf_check_pool = 0x40000328 ); -PROVIDE( tlsf_poison_fill_pfunc_set = 0x4000032c ); -PROVIDE( multi_heap_get_block_address_impl = 0x40000330 ); -PROVIDE( multi_heap_get_allocated_size_impl = 0x40000334 ); -PROVIDE( multi_heap_register_impl = 0x40000338 ); -PROVIDE( multi_heap_set_lock = 0x4000033c ); -PROVIDE( multi_heap_mutex_init = 0x40000340 ); -PROVIDE( multi_heap_internal_lock = 0x40000344 ); -PROVIDE( multi_heap_internal_unlock = 0x40000348 ); -PROVIDE( multi_heap_get_first_block = 0x4000034c ); -PROVIDE( multi_heap_get_next_block = 0x40000350 ); -PROVIDE( multi_heap_is_free = 0x40000354 ); -PROVIDE( multi_heap_malloc_impl = 0x40000358 ); -PROVIDE( multi_heap_free_impl = 0x4000035c ); -PROVIDE( multi_heap_realloc_impl = 0x40000360 ); -PROVIDE( multi_heap_aligned_alloc_impl_offs = 0x40000364 ); -PROVIDE( multi_heap_aligned_alloc_impl = 0x40000368 ); -PROVIDE( multi_heap_check = 0x4000036c ); -PROVIDE( multi_heap_dump = 0x40000370 ); -PROVIDE( multi_heap_free_size_impl = 0x40000374 ); -PROVIDE( multi_heap_minimum_free_size_impl = 0x40000378 ); -PROVIDE( multi_heap_get_info_impl = 0x4000037c ); +PROVIDE( tlsf_create = 0x400002ec ); +PROVIDE( tlsf_create_with_pool = 0x400002f0 ); +PROVIDE( tlsf_get_pool = 0x400002f4 ); +PROVIDE( tlsf_add_pool = 0x400002f8 ); +PROVIDE( tlsf_remove_pool = 0x400002fc ); +PROVIDE( tlsf_malloc = 0x40000300 ); +PROVIDE( tlsf_memalign = 0x40000304 ); +PROVIDE( tlsf_memalign_offs = 0x40000308 ); +PROVIDE( tlsf_realloc = 0x4000030c ); +PROVIDE( tlsf_free = 0x40000310 ); +PROVIDE( tlsf_block_size = 0x40000314 ); +PROVIDE( tlsf_size = 0x40000318 ); +PROVIDE( tlsf_align_size = 0x4000031c ); +PROVIDE( tlsf_block_size_min = 0x40000320 ); +PROVIDE( tlsf_block_size_max = 0x40000324 ); +PROVIDE( tlsf_pool_overhead = 0x40000328 ); +PROVIDE( tlsf_alloc_overhead = 0x4000032c ); +PROVIDE( tlsf_walk_pool = 0x40000330 ); +PROVIDE( tlsf_check = 0x40000334 ); +PROVIDE( tlsf_check_pool = 0x40000338 ); +PROVIDE( tlsf_poison_fill_pfunc_set = 0x4000033c ); +PROVIDE( multi_heap_get_block_address_impl = 0x40000340 ); +PROVIDE( multi_heap_get_allocated_size_impl = 0x40000344 ); +PROVIDE( multi_heap_register_impl = 0x40000348 ); +PROVIDE( multi_heap_set_lock = 0x4000034c ); +PROVIDE( multi_heap_mutex_init = 0x40000350 ); +PROVIDE( multi_heap_internal_lock = 0x40000354 ); +PROVIDE( multi_heap_internal_unlock = 0x40000358 ); +PROVIDE( multi_heap_get_first_block = 0x4000035c ); +PROVIDE( multi_heap_get_next_block = 0x40000360 ); +PROVIDE( multi_heap_is_free = 0x40000364 ); +PROVIDE( multi_heap_malloc_impl = 0x40000368 ); +PROVIDE( multi_heap_free_impl = 0x4000036c ); +PROVIDE( multi_heap_realloc_impl = 0x40000370 ); +PROVIDE( multi_heap_aligned_alloc_impl_offs = 0x40000374 ); +PROVIDE( multi_heap_aligned_alloc_impl = 0x40000378 ); +PROVIDE( multi_heap_check = 0x4000037c ); +PROVIDE( multi_heap_dump = 0x40000380 ); +PROVIDE( multi_heap_free_size_impl = 0x40000384 ); +PROVIDE( multi_heap_minimum_free_size_impl = 0x40000388 ); +PROVIDE( multi_heap_get_info_impl = 0x4000038c ); /* Data (.data, .bss, .rodata) */ -PROVIDE( heap_tlsf_table_ptr = 0x3fcdffec ); +PROVIDE( heap_tlsf_table_ptr = 0x3fcdffe8 ); /*************************************** @@ -281,41 +293,41 @@ PROVIDE( heap_tlsf_table_ptr = 0x3fcdffec ); ***************************************/ /* Functions */ -PROVIDE( spi_flash_chip_generic_probe = 0x40000380 ); -PROVIDE( spi_flash_chip_generic_detect_size = 0x40000384 ); -PROVIDE( spi_flash_chip_generic_write = 0x40000388 ); -PROVIDE( spi_flash_chip_generic_write_encrypted = 0x4000038c ); -PROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000390 ); -PROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000394 ); -PROVIDE( spi_flash_chip_generic_reset = 0x40000398 ); -PROVIDE( spi_flash_chip_generic_erase_chip = 0x4000039c ); -PROVIDE( spi_flash_chip_generic_erase_sector = 0x400003a0 ); -PROVIDE( spi_flash_chip_generic_erase_block = 0x400003a4 ); -PROVIDE( spi_flash_chip_generic_page_program = 0x400003a8 ); -PROVIDE( spi_flash_chip_generic_get_write_protect = 0x400003ac ); -PROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400003b0 ); -PROVIDE( spi_flash_chip_generic_read_reg = 0x400003b4 ); -PROVIDE( spi_flash_chip_generic_yield = 0x400003b8 ); -PROVIDE( spi_flash_generic_wait_host_idle = 0x400003bc ); -PROVIDE( spi_flash_chip_generic_wait_idle = 0x400003c0 ); -PROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x400003c4 ); -PROVIDE( spi_flash_chip_generic_read = 0x400003c8 ); -PROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400003cc ); -PROVIDE( spi_flash_chip_generic_get_io_mode = 0x400003d0 ); -PROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400003d4 ); -PROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400003d8 ); -PROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400003dc ); -PROVIDE( spi_flash_common_set_io_mode = 0x400003e0 ); -PROVIDE( spi_flash_chip_generic_set_io_mode = 0x400003e4 ); -PROVIDE( spi_flash_chip_generic_read_unique_id = 0x400003e8 ); -PROVIDE( spi_flash_chip_generic_get_caps = 0x400003ec ); -PROVIDE( spi_flash_chip_generic_suspend_cmd_conf = 0x400003f0 ); -PROVIDE( spi_flash_chip_gd_get_io_mode = 0x400003f4 ); -PROVIDE( spi_flash_chip_gd_probe = 0x400003f8 ); -PROVIDE( spi_flash_chip_gd_set_io_mode = 0x400003fc ); +PROVIDE( spi_flash_chip_generic_probe = 0x40000390 ); +PROVIDE( spi_flash_chip_generic_detect_size = 0x40000394 ); +PROVIDE( spi_flash_chip_generic_write = 0x40000398 ); +PROVIDE( spi_flash_chip_generic_write_encrypted = 0x4000039c ); +PROVIDE( spi_flash_chip_generic_set_write_protect = 0x400003a0 ); +PROVIDE( spi_flash_common_write_status_16b_wrsr = 0x400003a4 ); +PROVIDE( spi_flash_chip_generic_reset = 0x400003a8 ); +PROVIDE( spi_flash_chip_generic_erase_chip = 0x400003ac ); +PROVIDE( spi_flash_chip_generic_erase_sector = 0x400003b0 ); +PROVIDE( spi_flash_chip_generic_erase_block = 0x400003b4 ); +PROVIDE( spi_flash_chip_generic_page_program = 0x400003b8 ); +PROVIDE( spi_flash_chip_generic_get_write_protect = 0x400003bc ); +PROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400003c0 ); +PROVIDE( spi_flash_chip_generic_read_reg = 0x400003c4 ); +PROVIDE( spi_flash_chip_generic_yield = 0x400003c8 ); +PROVIDE( spi_flash_generic_wait_host_idle = 0x400003cc ); +PROVIDE( spi_flash_chip_generic_wait_idle = 0x400003d0 ); +PROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x400003d4 ); +PROVIDE( spi_flash_chip_generic_read = 0x400003d8 ); +PROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400003dc ); +PROVIDE( spi_flash_chip_generic_get_io_mode = 0x400003e0 ); +PROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400003e4 ); +PROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400003e8 ); +PROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400003ec ); +PROVIDE( spi_flash_common_set_io_mode = 0x400003f0 ); +PROVIDE( spi_flash_chip_generic_set_io_mode = 0x400003f4 ); +PROVIDE( spi_flash_chip_generic_read_unique_id = 0x400003f8 ); +PROVIDE( spi_flash_chip_generic_get_caps = 0x400003fc ); +PROVIDE( spi_flash_chip_generic_suspend_cmd_conf = 0x40000400 ); +PROVIDE( spi_flash_chip_gd_get_io_mode = 0x40000404 ); +PROVIDE( spi_flash_chip_gd_probe = 0x40000408 ); +PROVIDE( spi_flash_chip_gd_set_io_mode = 0x4000040c ); /* Data (.data, .bss, .rodata) */ -PROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 ); -PROVIDE( spi_flash_encryption = 0x3fcdffe4 ); +PROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe4 ); +PROVIDE( spi_flash_encryption = 0x3fcdffe0 ); /*************************************** @@ -323,18 +335,18 @@ PROVIDE( spi_flash_encryption = 0x3fcdffe4 ); ***************************************/ /* Functions */ -PROVIDE( memspi_host_read_id_hs = 0x40000400 ); -PROVIDE( memspi_host_read_status_hs = 0x40000404 ); -PROVIDE( memspi_host_flush_cache = 0x40000408 ); -PROVIDE( memspi_host_erase_chip = 0x4000040c ); -PROVIDE( memspi_host_erase_sector = 0x40000410 ); -PROVIDE( memspi_host_erase_block = 0x40000414 ); -PROVIDE( memspi_host_program_page = 0x40000418 ); -PROVIDE( memspi_host_read = 0x4000041c ); -PROVIDE( memspi_host_set_write_protect = 0x40000420 ); -PROVIDE( memspi_host_set_max_read_len = 0x40000424 ); -PROVIDE( memspi_host_read_data_slicer = 0x40000428 ); -PROVIDE( memspi_host_write_data_slicer = 0x4000042c ); +PROVIDE( memspi_host_read_id_hs = 0x40000410 ); +PROVIDE( memspi_host_read_status_hs = 0x40000414 ); +PROVIDE( memspi_host_flush_cache = 0x40000418 ); +PROVIDE( memspi_host_erase_chip = 0x4000041c ); +PROVIDE( memspi_host_erase_sector = 0x40000420 ); +PROVIDE( memspi_host_erase_block = 0x40000424 ); +PROVIDE( memspi_host_program_page = 0x40000428 ); +PROVIDE( memspi_host_read = 0x4000042c ); +PROVIDE( memspi_host_set_write_protect = 0x40000430 ); +PROVIDE( memspi_host_set_max_read_len = 0x40000434 ); +PROVIDE( memspi_host_read_data_slicer = 0x40000438 ); +PROVIDE( memspi_host_write_data_slicer = 0x4000043c ); /*************************************** @@ -342,30 +354,30 @@ PROVIDE( memspi_host_write_data_slicer = 0x4000042c ); ***************************************/ /* Functions */ -PROVIDE( esp_flash_chip_driver_initialized = 0x40000430 ); -PROVIDE( esp_flash_read_id = 0x40000434 ); -PROVIDE( esp_flash_get_size = 0x40000438 ); -PROVIDE( esp_flash_erase_chip = 0x4000043c ); -PROVIDE( esp_flash_erase_region = 0x40000440 ); -PROVIDE( esp_flash_get_chip_write_protect = 0x40000444 ); -PROVIDE( esp_flash_set_chip_write_protect = 0x40000448 ); -PROVIDE( esp_flash_get_protectable_regions = 0x4000044c ); -PROVIDE( esp_flash_get_protected_region = 0x40000450 ); -PROVIDE( esp_flash_set_protected_region = 0x40000454 ); -PROVIDE( esp_flash_read = 0x40000458 ); -PROVIDE( esp_flash_write = 0x4000045c ); -PROVIDE( esp_flash_write_encrypted = 0x40000460 ); -PROVIDE( esp_flash_read_encrypted = 0x40000464 ); -PROVIDE( esp_flash_get_io_mode = 0x40000468 ); -PROVIDE( esp_flash_set_io_mode = 0x4000046c ); -PROVIDE( spi_flash_boot_attach = 0x40000470 ); -PROVIDE( esp_flash_read_chip_id = 0x40000474 ); -PROVIDE( detect_spi_flash_chip = 0x40000478 ); -PROVIDE( esp_rom_spiflash_write_disable = 0x4000047c ); -PROVIDE( esp_flash_suspend_cmd_init = 0x40000480 ); +PROVIDE( esp_flash_chip_driver_initialized = 0x40000440 ); +PROVIDE( esp_flash_read_id = 0x40000444 ); +PROVIDE( esp_flash_get_size = 0x40000448 ); +PROVIDE( esp_flash_erase_chip = 0x4000044c ); +PROVIDE( esp_flash_erase_region = 0x40000450 ); +PROVIDE( esp_flash_get_chip_write_protect = 0x40000454 ); +PROVIDE( esp_flash_set_chip_write_protect = 0x40000458 ); +PROVIDE( esp_flash_get_protectable_regions = 0x4000045c ); +PROVIDE( esp_flash_get_protected_region = 0x40000460 ); +PROVIDE( esp_flash_set_protected_region = 0x40000464 ); +PROVIDE( esp_flash_read = 0x40000468 ); +PROVIDE( esp_flash_write = 0x4000046c ); +PROVIDE( esp_flash_write_encrypted = 0x40000470 ); +PROVIDE( esp_flash_read_encrypted = 0x40000474 ); +PROVIDE( esp_flash_get_io_mode = 0x40000478 ); +PROVIDE( esp_flash_set_io_mode = 0x4000047c ); +PROVIDE( spi_flash_boot_attach = 0x40000480 ); +PROVIDE( esp_flash_read_chip_id = 0x40000484 ); +PROVIDE( detect_spi_flash_chip = 0x40000488 ); +PROVIDE( esp_rom_spiflash_write_disable = 0x4000048c ); +PROVIDE( esp_flash_suspend_cmd_init = 0x40000490 ); /* Data (.data, .bss, .rodata) */ -PROVIDE( esp_flash_default_chip = 0x3fcdffe0 ); -PROVIDE( esp_flash_api_funcs = 0x3fcdffdc ); +PROVIDE( esp_flash_default_chip = 0x3fcdffdc ); +PROVIDE( esp_flash_api_funcs = 0x3fcdffd8 ); /*************************************** @@ -373,61 +385,61 @@ PROVIDE( esp_flash_api_funcs = 0x3fcdffdc ); ***************************************/ /* Functions */ -PROVIDE( Cache_Get_ICache_Line_Size = 0x400006e0 ); -PROVIDE( Cache_Get_Mode = 0x400006e4 ); -PROVIDE( Cache_Address_Through_IBus = 0x400006e8 ); -PROVIDE( Cache_Address_Through_DBus = 0x400006ec ); -PROVIDE( Cache_Set_Default_Mode = 0x400006f0 ); -PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400006f4 ); -PROVIDE( ROM_Boot_Cache_Init = 0x400006f8 ); -PROVIDE( Cache_Invalidate_ICache_Items = 0x400006fc ); -PROVIDE( Cache_Op_Addr = 0x40000700 ); -PROVIDE( Cache_Invalidate_Addr = 0x40000704 ); -PROVIDE( Cache_Invalidate_ICache_All = 0x40000708 ); -PROVIDE( Cache_Mask_All = 0x4000070c ); -PROVIDE( Cache_UnMask_Dram0 = 0x40000710 ); -PROVIDE( Cache_Suspend_ICache_Autoload = 0x40000714 ); -PROVIDE( Cache_Resume_ICache_Autoload = 0x40000718 ); -PROVIDE( Cache_Start_ICache_Preload = 0x4000071c ); -PROVIDE( Cache_ICache_Preload_Done = 0x40000720 ); -PROVIDE( Cache_End_ICache_Preload = 0x40000724 ); -PROVIDE( Cache_Config_ICache_Autoload = 0x40000728 ); -PROVIDE( Cache_Enable_ICache_Autoload = 0x4000072c ); -PROVIDE( Cache_Disable_ICache_Autoload = 0x40000730 ); -PROVIDE( Cache_Enable_ICache_PreLock = 0x40000734 ); -PROVIDE( Cache_Disable_ICache_PreLock = 0x40000738 ); -PROVIDE( Cache_Lock_ICache_Items = 0x4000073c ); -PROVIDE( Cache_Unlock_ICache_Items = 0x40000740 ); -PROVIDE( Cache_Lock_Addr = 0x40000744 ); -PROVIDE( Cache_Unlock_Addr = 0x40000748 ); -PROVIDE( Cache_Disable_ICache = 0x4000074c ); -PROVIDE( Cache_Enable_ICache = 0x40000750 ); -PROVIDE( Cache_Suspend_ICache = 0x40000754 ); -PROVIDE( Cache_Resume_ICache = 0x40000758 ); -PROVIDE( Cache_Freeze_ICache_Enable = 0x4000075c ); -PROVIDE( Cache_Freeze_ICache_Disable = 0x40000760 ); -PROVIDE( Cache_Pms_Lock = 0x40000764 ); -PROVIDE( Cache_Ibus_Pms_Set_Addr = 0x40000768 ); -PROVIDE( Cache_Ibus_Pms_Set_Attr = 0x4000076c ); -PROVIDE( Cache_Dbus_Pms_Set_Addr = 0x40000770 ); -PROVIDE( Cache_Dbus_Pms_Set_Attr = 0x40000774 ); -PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000778 ); -PROVIDE( Cache_Get_IROM_MMU_End = 0x4000077c ); -PROVIDE( Cache_Get_DROM_MMU_End = 0x40000780 ); -PROVIDE( Cache_Owner_Init = 0x40000784 ); -PROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000788 ); -PROVIDE( Cache_MMU_Init = 0x4000078c ); -PROVIDE( Cache_Ibus_MMU_Set = 0x40000790 ); -PROVIDE( Cache_Dbus_MMU_Set = 0x40000794 ); -PROVIDE( Cache_Count_Flash_Pages = 0x40000798 ); -PROVIDE( Cache_Travel_Tag_Memory = 0x4000079c ); -PROVIDE( Cache_Get_Virtual_Addr = 0x400007a0 ); -PROVIDE( Cache_Get_Memory_BaseAddr = 0x400007a4 ); -PROVIDE( Cache_Get_Memory_Addr = 0x400007a8 ); -PROVIDE( Cache_Get_Memory_value = 0x400007ac ); +PROVIDE( Cache_Get_ICache_Line_Size = 0x400006f0 ); +PROVIDE( Cache_Get_Mode = 0x400006f4 ); +PROVIDE( Cache_Address_Through_IBus = 0x400006f8 ); +PROVIDE( Cache_Address_Through_DBus = 0x400006fc ); +PROVIDE( Cache_Set_Default_Mode = 0x40000700 ); +PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x40000704 ); +PROVIDE( ROM_Boot_Cache_Init = 0x40000708 ); +PROVIDE( Cache_Invalidate_ICache_Items = 0x4000070c ); +PROVIDE( Cache_Op_Addr = 0x40000710 ); +PROVIDE( Cache_Invalidate_Addr = 0x40000714 ); +PROVIDE( Cache_Invalidate_ICache_All = 0x40000718 ); +PROVIDE( Cache_Mask_All = 0x4000071c ); +PROVIDE( Cache_UnMask_Dram0 = 0x40000720 ); +PROVIDE( Cache_Suspend_ICache_Autoload = 0x40000724 ); +PROVIDE( Cache_Resume_ICache_Autoload = 0x40000728 ); +PROVIDE( Cache_Start_ICache_Preload = 0x4000072c ); +PROVIDE( Cache_ICache_Preload_Done = 0x40000730 ); +PROVIDE( Cache_End_ICache_Preload = 0x40000734 ); +PROVIDE( Cache_Config_ICache_Autoload = 0x40000738 ); +PROVIDE( Cache_Enable_ICache_Autoload = 0x4000073c ); +PROVIDE( Cache_Disable_ICache_Autoload = 0x40000740 ); +PROVIDE( Cache_Enable_ICache_PreLock = 0x40000744 ); +PROVIDE( Cache_Disable_ICache_PreLock = 0x40000748 ); +PROVIDE( Cache_Lock_ICache_Items = 0x4000074c ); +PROVIDE( Cache_Unlock_ICache_Items = 0x40000750 ); +PROVIDE( Cache_Lock_Addr = 0x40000754 ); +PROVIDE( Cache_Unlock_Addr = 0x40000758 ); +PROVIDE( Cache_Disable_ICache = 0x4000075c ); +PROVIDE( Cache_Enable_ICache = 0x40000760 ); +PROVIDE( Cache_Suspend_ICache = 0x40000764 ); +PROVIDE( Cache_Resume_ICache = 0x40000768 ); +PROVIDE( Cache_Freeze_ICache_Enable = 0x4000076c ); +PROVIDE( Cache_Freeze_ICache_Disable = 0x40000770 ); +PROVIDE( Cache_Pms_Lock = 0x40000774 ); +PROVIDE( Cache_Ibus_Pms_Set_Addr = 0x40000778 ); +PROVIDE( Cache_Ibus_Pms_Set_Attr = 0x4000077c ); +PROVIDE( Cache_Dbus_Pms_Set_Addr = 0x40000780 ); +PROVIDE( Cache_Dbus_Pms_Set_Attr = 0x40000784 ); +PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000788 ); +PROVIDE( Cache_Get_IROM_MMU_End = 0x4000078c ); +PROVIDE( Cache_Get_DROM_MMU_End = 0x40000790 ); +PROVIDE( Cache_Owner_Init = 0x40000794 ); +PROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000798 ); +PROVIDE( Cache_MMU_Init = 0x4000079c ); +PROVIDE( Cache_Ibus_MMU_Set = 0x400007a0 ); +PROVIDE( Cache_Dbus_MMU_Set = 0x400007a4 ); +PROVIDE( Cache_Count_Flash_Pages = 0x400007a8 ); +PROVIDE( Cache_Travel_Tag_Memory = 0x400007ac ); +PROVIDE( Cache_Get_Virtual_Addr = 0x400007b0 ); +PROVIDE( Cache_Get_Memory_BaseAddr = 0x400007b4 ); +PROVIDE( Cache_Get_Memory_Addr = 0x400007b8 ); +PROVIDE( Cache_Get_Memory_value = 0x400007bc ); /* Data (.data, .bss, .rodata) */ -PROVIDE( rom_cache_op_cb = 0x3fcdffd0 ); -PROVIDE( rom_cache_internal_table_ptr = 0x3fcdffcc ); +PROVIDE( rom_cache_op_cb = 0x3fcdffcc ); +PROVIDE( rom_cache_internal_table_ptr = 0x3fcdffc8 ); /*************************************** @@ -435,13 +447,13 @@ PROVIDE( rom_cache_internal_table_ptr = 0x3fcdffcc ); ***************************************/ /* Functions */ -ets_get_apb_freq = 0x400007b0; -ets_get_cpu_frequency = 0x400007b4; -ets_update_cpu_frequency = 0x400007b8; -ets_get_printf_channel = 0x400007bc; -ets_get_xtal_div = 0x400007c0; -ets_set_xtal_div = 0x400007c4; -ets_get_xtal_freq = 0x400007c8; +ets_get_apb_freq = 0x400007c0; +ets_get_cpu_frequency = 0x400007c4; +ets_update_cpu_frequency = 0x400007c8; +ets_get_printf_channel = 0x400007cc; +ets_get_xtal_div = 0x400007d0; +ets_set_xtal_div = 0x400007d4; +ets_get_xtal_freq = 0x400007d8; /*************************************** @@ -449,23 +461,23 @@ ets_get_xtal_freq = 0x400007c8; ***************************************/ /* Functions */ -gpio_input_get = 0x400007cc; -gpio_matrix_in = 0x400007d0; -gpio_matrix_out = 0x400007d4; -gpio_output_disable = 0x400007d8; -gpio_output_enable = 0x400007dc; -gpio_output_set = 0x400007e0; -gpio_pad_hold = 0x400007e4; -gpio_pad_input_disable = 0x400007e8; -gpio_pad_input_enable = 0x400007ec; -gpio_pad_pulldown = 0x400007f0; -gpio_pad_pullup = 0x400007f4; -gpio_pad_select_gpio = 0x400007f8; -gpio_pad_set_drv = 0x400007fc; -gpio_pad_unhold = 0x40000800; -gpio_pin_wakeup_disable = 0x40000804; -gpio_pin_wakeup_enable = 0x40000808; -gpio_bypass_matrix_in = 0x4000080c; +gpio_input_get = 0x400007dc; +gpio_matrix_in = 0x400007e0; +gpio_matrix_out = 0x400007e4; +gpio_output_disable = 0x400007e8; +gpio_output_enable = 0x400007ec; +gpio_output_set = 0x400007f0; +gpio_pad_hold = 0x400007f4; +gpio_pad_input_disable = 0x400007f8; +gpio_pad_input_enable = 0x400007fc; +gpio_pad_pulldown = 0x40000800; +gpio_pad_pullup = 0x40000804; +gpio_pad_select_gpio = 0x40000808; +gpio_pad_set_drv = 0x4000080c; +gpio_pad_unhold = 0x40000810; +gpio_pin_wakeup_disable = 0x40000814; +gpio_pin_wakeup_enable = 0x40000818; +gpio_bypass_matrix_in = 0x4000081c; /*************************************** @@ -473,18 +485,18 @@ gpio_bypass_matrix_in = 0x4000080c; ***************************************/ /* Functions */ -esprv_intc_int_set_priority = 0x40000810; -esprv_intc_int_set_threshold = 0x40000814; -esprv_intc_int_enable = 0x40000818; -esprv_intc_int_disable = 0x4000081c; -esprv_intc_int_set_type = 0x40000820; -PROVIDE( intr_handler_set = 0x40000824 ); -intr_matrix_set = 0x40000828; -ets_intr_lock = 0x4000082c; -ets_intr_unlock = 0x40000830; -ets_isr_attach = 0x40000834; -ets_isr_mask = 0x40000838; -ets_isr_unmask = 0x4000083c; +esprv_intc_int_set_priority = 0x40000820; +esprv_intc_int_set_threshold = 0x40000824; +esprv_intc_int_enable = 0x40000828; +esprv_intc_int_disable = 0x4000082c; +esprv_intc_int_set_type = 0x40000830; +PROVIDE( intr_handler_set = 0x40000834 ); +intr_matrix_set = 0x40000838; +ets_intr_lock = 0x4000083c; +ets_intr_unlock = 0x40000840; +ets_isr_attach = 0x40000844; +ets_isr_mask = 0x40000848; +ets_isr_unmask = 0x4000084c; /*************************************** @@ -492,52 +504,52 @@ ets_isr_unmask = 0x4000083c; ***************************************/ /* Functions */ -md5_vector = 0x40000840; -MD5Init = 0x40000844; -MD5Update = 0x40000848; -MD5Final = 0x4000084c; -crc32_le = 0x40000850; -crc16_le = 0x40000854; -crc8_le = 0x40000858; -crc32_be = 0x4000085c; -crc16_be = 0x40000860; -crc8_be = 0x40000864; -esp_crc8 = 0x40000868; -ets_sha_enable = 0x4000086c; -ets_sha_disable = 0x40000870; -ets_sha_get_state = 0x40000874; -ets_sha_init = 0x40000878; -ets_sha_process = 0x4000087c; -ets_sha_starts = 0x40000880; -ets_sha_update = 0x40000884; -ets_sha_finish = 0x40000888; -ets_sha_clone = 0x4000088c; -ets_hmac_enable = 0x40000890; -ets_hmac_disable = 0x40000894; -ets_hmac_calculate_message = 0x40000898; -ets_hmac_calculate_downstream = 0x4000089c; -ets_hmac_invalidate_downstream = 0x400008a0; -ets_jtag_enable_temporarily = 0x400008a4; -ets_aes_enable = 0x400008a8; -ets_aes_disable = 0x400008ac; -ets_aes_setkey = 0x400008b0; -ets_aes_block = 0x400008b4; -ets_aes_setkey_dec = 0x400008b8; -ets_aes_setkey_enc = 0x400008bc; -ets_bigint_enable = 0x400008c0; -ets_bigint_disable = 0x400008c4; -ets_bigint_multiply = 0x400008c8; -ets_bigint_modmult = 0x400008cc; -ets_bigint_modexp = 0x400008d0; -ets_bigint_wait_finish = 0x400008d4; -ets_bigint_getz = 0x400008d8; -ets_ds_enable = 0x400008dc; -ets_ds_disable = 0x400008e0; -ets_ds_start_sign = 0x400008e4; -ets_ds_is_busy = 0x400008e8; -ets_ds_finish_sign = 0x400008ec; -ets_ds_encrypt_params = 0x400008f0; -ets_mgf1_sha256 = 0x400008f4; +md5_vector = 0x40000850; +MD5Init = 0x40000854; +MD5Update = 0x40000858; +MD5Final = 0x4000085c; +crc32_le = 0x40000860; +crc16_le = 0x40000864; +crc8_le = 0x40000868; +crc32_be = 0x4000086c; +crc16_be = 0x40000870; +crc8_be = 0x40000874; +esp_crc8 = 0x40000878; +ets_sha_enable = 0x4000087c; +ets_sha_disable = 0x40000880; +ets_sha_get_state = 0x40000884; +ets_sha_init = 0x40000888; +ets_sha_process = 0x4000088c; +ets_sha_starts = 0x40000890; +ets_sha_update = 0x40000894; +ets_sha_finish = 0x40000898; +ets_sha_clone = 0x4000089c; +ets_hmac_enable = 0x400008a0; +ets_hmac_disable = 0x400008a4; +ets_hmac_calculate_message = 0x400008a8; +ets_hmac_calculate_downstream = 0x400008ac; +ets_hmac_invalidate_downstream = 0x400008b0; +ets_jtag_enable_temporarily = 0x400008b4; +ets_aes_enable = 0x400008b8; +ets_aes_disable = 0x400008bc; +ets_aes_setkey = 0x400008c0; +ets_aes_block = 0x400008c4; +ets_aes_setkey_dec = 0x400008c8; +ets_aes_setkey_enc = 0x400008cc; +ets_bigint_enable = 0x400008d0; +ets_bigint_disable = 0x400008d4; +ets_bigint_multiply = 0x400008d8; +ets_bigint_modmult = 0x400008dc; +ets_bigint_modexp = 0x400008e0; +ets_bigint_wait_finish = 0x400008e4; +ets_bigint_getz = 0x400008e8; +ets_ds_enable = 0x400008ec; +ets_ds_disable = 0x400008f0; +ets_ds_start_sign = 0x400008f4; +ets_ds_is_busy = 0x400008f8; +ets_ds_finish_sign = 0x400008fc; +ets_ds_encrypt_params = 0x40000900; +ets_mgf1_sha256 = 0x40000904; /* Data (.data, .bss, .rodata) */ crc32_le_table_ptr = 0x3ff1fff8; crc16_le_table_ptr = 0x3ff1fff4; @@ -552,36 +564,36 @@ crc8_be_table_ptr = 0x3ff1ffe4; ***************************************/ /* Functions */ -ets_efuse_read = 0x400008f8; -ets_efuse_program = 0x400008fc; -ets_efuse_clear_program_registers = 0x40000900; -ets_efuse_write_key = 0x40000904; -ets_efuse_get_read_register_address = 0x40000908; -ets_efuse_get_key_purpose = 0x4000090c; -ets_efuse_key_block_unused = 0x40000910; -ets_efuse_find_unused_key_block = 0x40000914; -ets_efuse_rs_calculate = 0x40000918; -ets_efuse_count_unused_key_blocks = 0x4000091c; -ets_efuse_secure_boot_enabled = 0x40000920; -ets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000924; -ets_efuse_cache_encryption_enabled = 0x40000928; -ets_efuse_download_modes_disabled = 0x4000092c; -ets_efuse_find_purpose = 0x40000930; -ets_efuse_force_send_resume = 0x40000934; -ets_efuse_get_flash_delay_us = 0x40000938; -ets_efuse_get_mac = 0x4000093c; -ets_efuse_get_uart_print_control = 0x40000940; -ets_efuse_direct_boot_mode_disabled = 0x40000944; -ets_efuse_security_download_modes_enabled = 0x40000948; -ets_efuse_set_timing = 0x4000094c; -ets_efuse_jtag_disabled = 0x40000950; -ets_efuse_get_spiconfig = 0x40000954; -ets_efuse_get_wp_pad = 0x40000958; -ets_efuse_usb_print_is_disabled = 0x4000095c; -ets_efuse_usb_download_mode_disabled = 0x40000960; -ets_efuse_usb_module_disabled = 0x40000964; -ets_efuse_usb_device_disabled = 0x40000968; -ets_efuse_secure_boot_fast_wake_enabled = 0x4000096c; +ets_efuse_read = 0x40000908; +ets_efuse_program = 0x4000090c; +ets_efuse_clear_program_registers = 0x40000910; +ets_efuse_write_key = 0x40000914; +ets_efuse_get_read_register_address = 0x40000918; +ets_efuse_get_key_purpose = 0x4000091c; +ets_efuse_key_block_unused = 0x40000920; +ets_efuse_find_unused_key_block = 0x40000924; +ets_efuse_rs_calculate = 0x40000928; +ets_efuse_count_unused_key_blocks = 0x4000092c; +ets_efuse_secure_boot_enabled = 0x40000930; +ets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000934; +ets_efuse_cache_encryption_enabled = 0x40000938; +ets_efuse_download_modes_disabled = 0x4000093c; +ets_efuse_find_purpose = 0x40000940; +ets_efuse_force_send_resume = 0x40000944; +ets_efuse_get_flash_delay_us = 0x40000948; +ets_efuse_get_mac = 0x4000094c; +ets_efuse_get_uart_print_control = 0x40000950; +ets_efuse_direct_boot_mode_disabled = 0x40000954; +ets_efuse_security_download_modes_enabled = 0x40000958; +ets_efuse_set_timing = 0x4000095c; +ets_efuse_jtag_disabled = 0x40000960; +ets_efuse_get_spiconfig = 0x40000964; +ets_efuse_get_wp_pad = 0x40000968; +ets_efuse_usb_print_is_disabled = 0x4000096c; +ets_efuse_usb_download_mode_disabled = 0x40000970; +ets_efuse_usb_module_disabled = 0x40000974; +ets_efuse_usb_device_disabled = 0x40000978; +ets_efuse_secure_boot_fast_wake_enabled = 0x4000097c; /*************************************** @@ -589,228 +601,214 @@ ets_efuse_secure_boot_fast_wake_enabled = 0x4000096c; ***************************************/ /* Functions */ -ets_emsa_pss_verify = 0x40000970; -ets_rsa_pss_verify = 0x40000974; -ets_ecdsa_verify = 0x40000978; -ets_secure_boot_verify_bootloader_with_keys = 0x4000097c; -ets_secure_boot_verify_signature = 0x40000980; -ets_secure_boot_read_key_digests = 0x40000984; -ets_secure_boot_revoke_public_key_digest = 0x40000988; +ets_emsa_pss_verify = 0x40000980; +ets_rsa_pss_verify = 0x40000984; +ets_secure_boot_verify_bootloader_with_keys = 0x40000988; +ets_secure_boot_verify_signature = 0x4000098c; +ets_secure_boot_read_key_digests = 0x40000990; +ets_secure_boot_revoke_public_key_digest = 0x40000994; /*************************************** - Group usb_uart + Group btdm ***************************************/ /* Functions */ -PROVIDE( usb_uart_device_rx_one_char = 0x40000afc ); -PROVIDE( usb_uart_device_rx_one_char_block = 0x40000b00 ); -PROVIDE( usb_uart_device_tx_flush = 0x40000b04 ); -PROVIDE( usb_uart_device_tx_one_char = 0x40000b08 ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( g_uart_print = 0x3fcdffc9 ); -PROVIDE( g_usb_print = 0x3fcdffc8 ); - - -/*************************************** - Group bluetooth - ***************************************/ - -/* Functions */ -ble_controller_rom_data_init = 0x40000b0c; -ble_osi_coex_funcs_register = 0x40000b10; -bt_rf_coex_cfg_get_default = 0x40000b14; -bt_rf_coex_dft_pti_get_default = 0x40000b18; -bt_rf_coex_hooks_p_set = 0x40000b1c; -r__os_mbuf_copypkthdr = 0x40000b20; -r__os_msys_find_pool = 0x40000b24; -r_ble_controller_get_rom_compile_version = 0x40000b28; -r_ble_hci_ram_hs_acl_tx = 0x40000b2c; -r_ble_hci_ram_hs_cmd_tx = 0x40000b30; -r_ble_hci_ram_ll_acl_tx = 0x40000b34; -r_ble_hci_ram_ll_evt_tx = 0x40000b38; -r_ble_hci_ram_reset = 0x40000b3c; -r_ble_hci_ram_set_acl_free_cb = 0x40000b40; -r_ble_hci_trans_acl_buf_alloc = 0x40000b44; -r_ble_hci_trans_buf_alloc = 0x40000b48; -r_ble_hci_trans_buf_free = 0x40000b4c; -r_ble_hci_trans_cfg_hs = 0x40000b50; -r_ble_hci_trans_cfg_ll = 0x40000b54; -r_ble_hci_trans_deinit = 0x40000b58; -r_ble_hci_trans_env_init = 0x40000b5c; -r_ble_hci_trans_init = 0x40000b60; -r_ble_hci_uart_acl_tx = 0x40000b64; -r_ble_hci_uart_cmdevt_tx = 0x40000b68; -r_ble_hci_uart_config = 0x40000b6c; -r_ble_hci_uart_free_pkt = 0x40000b70; -r_ble_hci_uart_hs_acl_tx = 0x40000b74; -r_ble_hci_uart_hs_cmd_tx = 0x40000b78; -r_ble_hci_uart_ll_acl_tx = 0x40000b7c; -r_ble_hci_uart_ll_evt_tx = 0x40000b80; -r_ble_hci_uart_rx_acl = 0x40000b84; -r_ble_hci_uart_rx_char = 0x40000b88; -r_ble_hci_uart_rx_cmd = 0x40000b8c; -r_ble_hci_uart_rx_evt = 0x40000b90; -r_ble_hci_uart_rx_evt_cb = 0x40000b94; -r_ble_hci_uart_rx_le_evt = 0x40000b98; -r_ble_hci_uart_rx_pkt_type = 0x40000b9c; -r_ble_hci_uart_rx_skip_acl = 0x40000ba0; -r_ble_hci_uart_rx_skip_cmd = 0x40000ba4; -r_ble_hci_uart_rx_skip_evt = 0x40000ba8; -r_ble_hci_uart_rx_sync_loss = 0x40000bac; -r_ble_hci_uart_set_acl_free_cb = 0x40000bb0; -r_ble_hci_uart_sync_lost = 0x40000bb4; -r_ble_hci_uart_trans_reset = 0x40000bb8; -r_ble_hci_uart_tx_char = 0x40000bbc; -r_ble_hci_uart_tx_pkt_type = 0x40000bc0; -r_ble_hw_driver_deinit = 0x40000bc4; -r_ble_hw_driver_env_init = 0x40000bc8; -r_ble_hw_encrypt_block = 0x40000bcc; -r_ble_hw_get_public_addr = 0x40000bd0; -r_ble_hw_get_static_addr = 0x40000bd4; -r_ble_hw_periodiclist_add = 0x40000bd8; -r_ble_hw_periodiclist_clear = 0x40000bdc; -r_ble_hw_periodiclist_rmv = 0x40000be0; -r_ble_hw_resolv_list_cur_entry = 0x40000be4; -r_ble_hw_resolv_list_match = 0x40000be8; -r_ble_hw_resolv_list_set = 0x40000bec; -r_ble_hw_rng_init = 0x40000bf0; -r_ble_hw_rng_start = 0x40000bf4; -r_ble_hw_rng_stop = 0x40000bf8; -r_ble_hw_rx_local_is_rpa = 0x40000bfc; -r_ble_hw_whitelist_add = 0x40000c00; -r_ble_hw_whitelist_clear = 0x40000c04; -r_ble_hw_whitelist_dev_num = 0x40000c08; -r_ble_hw_whitelist_get_base = 0x40000c0c; -r_ble_hw_whitelist_rmv = 0x40000c10; -r_ble_hw_whitelist_search = 0x40000c14; -r_ble_hw_whitelist_sort = 0x40000c18; -r_ble_ll_acl_data_in = 0x40000c1c; -r_ble_ll_addr_is_id = 0x40000c20; -r_ble_ll_addr_subtype = 0x40000c24; -r_ble_ll_adv_active_chanset_clear = 0x40000c28; -r_ble_ll_adv_active_chanset_is_pri = 0x40000c2c; -r_ble_ll_adv_active_chanset_is_sec = 0x40000c30; -r_ble_ll_adv_active_chanset_set_pri = 0x40000c34; -r_ble_ll_adv_active_chanset_set_sec = 0x40000c38; -r_ble_ll_adv_aux_calculate = 0x40000c3c; -r_ble_ll_adv_aux_conn_rsp_pdu_make = 0x40000c40; -r_ble_ll_adv_aux_pdu_make = 0x40000c44; -r_ble_ll_adv_aux_scannable_pdu_make = 0x40000c48; -r_ble_ll_adv_aux_scannable_pdu_payload_len = 0x40000c4c; -r_ble_ll_adv_aux_schedule = 0x40000c50; -r_ble_ll_adv_aux_schedule_first = 0x40000c54; -r_ble_ll_adv_aux_schedule_next = 0x40000c58; -r_ble_ll_adv_aux_scheduled = 0x40000c5c; -r_ble_ll_adv_aux_set_start_time = 0x40000c60; -r_ble_ll_adv_aux_txed = 0x40000c64; -r_ble_ll_adv_can_chg_whitelist = 0x40000c68; -r_ble_ll_adv_chk_rpa_timeout = 0x40000c6c; -r_ble_ll_adv_clear_all = 0x40000c70; -r_ble_ll_adv_coex_dpc_calc_pti_update_itvl = 0x40000c74; -r_ble_ll_adv_coex_dpc_process_pri = 0x40000c78; -r_ble_ll_adv_coex_dpc_process_sec = 0x40000c7c; -r_ble_ll_adv_coex_dpc_pti_get = 0x40000c80; -r_ble_ll_adv_coex_dpc_update = 0x40000c84; -r_ble_ll_adv_coex_dpc_update_on_adv_start = 0x40000c88; -r_ble_ll_adv_coex_dpc_update_on_aux_scheduled = 0x40000c8c; -r_ble_ll_adv_coex_dpc_update_on_data_updated = 0x40000c90; -r_ble_ll_adv_coex_dpc_update_on_event_end = 0x40000c94; -r_ble_ll_adv_coex_dpc_update_on_event_scheduled = 0x40000c98; -r_ble_ll_adv_conn_req_rxd = 0x40000c9c; -r_ble_ll_adv_deinit = 0x40000ca0; -r_ble_ll_adv_done = 0x40000ca4; -r_ble_ll_adv_drop_event = 0x40000ca8; -r_ble_ll_adv_enabled = 0x40000cac; -r_ble_ll_adv_env_init = 0x40000cb0; -r_ble_ll_adv_event_done = 0x40000cb4; -r_ble_ll_adv_event_rmvd_from_sched = 0x40000cb8; -r_ble_ll_adv_ext_estimate_data_itvl = 0x40000cbc; -r_ble_ll_adv_ext_set_adv_data = 0x40000cc0; -r_ble_ll_adv_ext_set_enable = 0x40000cc4; -r_ble_ll_adv_ext_set_param = 0x40000cc8; -r_ble_ll_adv_ext_set_scan_rsp = 0x40000ccc; -r_ble_ll_adv_final_chan = 0x40000cd0; -r_ble_ll_adv_first_chan = 0x40000cd4; -r_ble_ll_adv_flags_clear = 0x40000cd8; -r_ble_ll_adv_flags_set = 0x40000cdc; -r_ble_ll_adv_get_local_rpa = 0x40000ce0; -r_ble_ll_adv_get_peer_rpa = 0x40000ce4; -r_ble_ll_adv_get_sec_pdu_len = 0x40000ce8; -r_ble_ll_adv_halt = 0x40000cec; -r_ble_ll_adv_hci_set_random_addr = 0x40000cf0; -r_ble_ll_adv_init = 0x40000cf4; -r_ble_ll_adv_legacy_pdu_make = 0x40000cf8; -r_ble_ll_adv_make_done = 0x40000cfc; -r_ble_ll_adv_pdu_make = 0x40000d00; -r_ble_ll_adv_periodic_check_data_itvl = 0x40000d04; -r_ble_ll_adv_periodic_done = 0x40000d08; -r_ble_ll_adv_periodic_enable = 0x40000d0c; -r_ble_ll_adv_periodic_estimate_data_itvl = 0x40000d10; -r_ble_ll_adv_periodic_event_done = 0x40000d14; -r_ble_ll_adv_periodic_rmvd_from_sched = 0x40000d18; -r_ble_ll_adv_periodic_schedule_first = 0x40000d1c; -r_ble_ll_adv_periodic_schedule_next = 0x40000d20; -r_ble_ll_adv_periodic_send_sync_ind = 0x40000d24; -r_ble_ll_adv_periodic_set_data = 0x40000d28; -r_ble_ll_adv_periodic_set_info_transfer = 0x40000d2c; -r_ble_ll_adv_periodic_set_param = 0x40000d30; -r_ble_ll_adv_put_aux_ptr = 0x40000d34; -r_ble_ll_adv_put_syncinfo = 0x40000d38; -r_ble_ll_adv_rd_max_adv_data_len = 0x40000d3c; -r_ble_ll_adv_rd_sup_adv_sets = 0x40000d40; -r_ble_ll_adv_read_txpwr = 0x40000d44; -r_ble_ll_adv_remove = 0x40000d48; -r_ble_ll_adv_reschedule_event = 0x40000d4c; -r_ble_ll_adv_reschedule_periodic_event = 0x40000d50; -r_ble_ll_adv_reset = 0x40000d54; -r_ble_ll_adv_rpa_timeout = 0x40000d58; -r_ble_ll_adv_rpa_update = 0x40000d5c; -r_ble_ll_adv_rx_isr_end = 0x40000d60; -r_ble_ll_adv_rx_isr_start = 0x40000d64; -r_ble_ll_adv_rx_pkt_in = 0x40000d68; -r_ble_ll_adv_rx_req = 0x40000d6c; -r_ble_ll_adv_scan_rsp_legacy_pdu_make = 0x40000d70; -r_ble_ll_adv_scan_rsp_pdu_make = 0x40000d74; -r_ble_ll_adv_scheduled = 0x40000d78; -r_ble_ll_adv_sec_done = 0x40000d7c; -r_ble_ll_adv_sec_event_done = 0x40000d80; -r_ble_ll_adv_secondary_tx_start_cb = 0x40000d84; -r_ble_ll_adv_send_conn_comp_ev = 0x40000d88; -r_ble_ll_adv_set_adv_data = 0x40000d8c; -r_ble_ll_adv_set_adv_params = 0x40000d90; -r_ble_ll_adv_set_enable = 0x40000d94; -r_ble_ll_adv_set_random_addr = 0x40000d98; -r_ble_ll_adv_set_scan_rsp_data = 0x40000d9c; -r_ble_ll_adv_set_sched = 0x40000da0; -r_ble_ll_adv_sm_deinit = 0x40000da4; -r_ble_ll_adv_sm_event_init = 0x40000da8; -r_ble_ll_adv_sm_event_restore = 0x40000dac; -r_ble_ll_adv_sm_event_store = 0x40000db0; -r_ble_ll_adv_sm_find_configured = 0x40000db4; -r_ble_ll_adv_sm_get = 0x40000db8; -r_ble_ll_adv_sm_init = 0x40000dbc; -r_ble_ll_adv_sm_reset = 0x40000dc0; -r_ble_ll_adv_sm_start = 0x40000dc4; -r_ble_ll_adv_sm_start_periodic = 0x40000dc8; -r_ble_ll_adv_sm_stop = 0x40000dcc; -r_ble_ll_adv_sm_stop_limit_reached = 0x40000dd0; -r_ble_ll_adv_sm_stop_periodic = 0x40000dd4; -r_ble_ll_adv_sm_stop_timeout = 0x40000dd8; -r_ble_ll_adv_sync_calculate = 0x40000ddc; -r_ble_ll_adv_sync_get_pdu_len = 0x40000de0; -r_ble_ll_adv_sync_next_scheduled = 0x40000de4; -r_ble_ll_adv_sync_pdu_make = 0x40000de8; -r_ble_ll_adv_sync_schedule = 0x40000dec; -r_ble_ll_adv_sync_tx_done = 0x40000df0; -r_ble_ll_adv_sync_tx_end = 0x40000df4; -r_ble_ll_adv_sync_tx_start_cb = 0x40000df8; -r_ble_ll_adv_tx_done = 0x40000dfc; -r_ble_ll_adv_tx_start_cb = 0x40000e00; -r_ble_ll_adv_update_adv_scan_rsp_data = 0x40000e04; -r_ble_ll_adv_update_data_mbuf = 0x40000e08; -r_ble_ll_adv_update_did = 0x40000e0c; -r_ble_ll_adv_update_periodic_data = 0x40000e10; +ble_controller_rom_data_init = 0x40000b08; +ble_osi_coex_funcs_register = 0x40000b0c; +bt_rf_coex_cfg_get_default = 0x40000b10; +bt_rf_coex_dft_pti_get_default = 0x40000b14; +bt_rf_coex_hooks_p_set = 0x40000b18; +r__os_mbuf_copypkthdr = 0x40000b1c; +r__os_msys_find_pool = 0x40000b20; +r_ble_controller_get_rom_compile_version = 0x40000b24; +r_ble_hci_ram_hs_acl_tx = 0x40000b28; +r_ble_hci_ram_hs_cmd_tx = 0x40000b2c; +r_ble_hci_ram_ll_acl_tx = 0x40000b30; +r_ble_hci_ram_ll_evt_tx = 0x40000b34; +r_ble_hci_ram_reset = 0x40000b38; +r_ble_hci_ram_set_acl_free_cb = 0x40000b3c; +r_ble_hci_trans_acl_buf_alloc = 0x40000b40; +r_ble_hci_trans_buf_alloc = 0x40000b44; +r_ble_hci_trans_buf_free = 0x40000b48; +r_ble_hci_trans_cfg_hs = 0x40000b4c; +r_ble_hci_trans_cfg_ll = 0x40000b50; +r_ble_hci_trans_deinit = 0x40000b54; +r_ble_hci_trans_env_init = 0x40000b58; +r_ble_hci_trans_init = 0x40000b5c; +r_ble_hci_uart_acl_tx = 0x40000b60; +r_ble_hci_uart_cmdevt_tx = 0x40000b64; +r_ble_hci_uart_config = 0x40000b68; +r_ble_hci_uart_free_pkt = 0x40000b6c; +r_ble_hci_uart_hs_acl_tx = 0x40000b70; +r_ble_hci_uart_hs_cmd_tx = 0x40000b74; +r_ble_hci_uart_ll_acl_tx = 0x40000b78; +r_ble_hci_uart_ll_evt_tx = 0x40000b7c; +r_ble_hci_uart_rx_acl = 0x40000b80; +r_ble_hci_uart_rx_char = 0x40000b84; +r_ble_hci_uart_rx_cmd = 0x40000b88; +r_ble_hci_uart_rx_evt = 0x40000b8c; +r_ble_hci_uart_rx_evt_cb = 0x40000b90; +r_ble_hci_uart_rx_le_evt = 0x40000b94; +r_ble_hci_uart_rx_pkt_type = 0x40000b98; +r_ble_hci_uart_rx_skip_acl = 0x40000b9c; +r_ble_hci_uart_rx_skip_cmd = 0x40000ba0; +r_ble_hci_uart_rx_skip_evt = 0x40000ba4; +r_ble_hci_uart_rx_sync_loss = 0x40000ba8; +r_ble_hci_uart_set_acl_free_cb = 0x40000bac; +r_ble_hci_uart_sync_lost = 0x40000bb0; +r_ble_hci_uart_trans_reset = 0x40000bb4; +r_ble_hci_uart_tx_char = 0x40000bb8; +r_ble_hci_uart_tx_pkt_type = 0x40000bbc; +r_ble_hw_driver_deinit = 0x40000bc0; +r_ble_hw_driver_env_init = 0x40000bc4; +r_ble_hw_encrypt_block = 0x40000bc8; +r_ble_hw_get_public_addr = 0x40000bcc; +r_ble_hw_get_static_addr = 0x40000bd0; +r_ble_hw_periodiclist_add = 0x40000bd4; +r_ble_hw_periodiclist_clear = 0x40000bd8; +r_ble_hw_periodiclist_rmv = 0x40000bdc; +r_ble_hw_resolv_list_cur_entry = 0x40000be0; +r_ble_hw_resolv_list_match = 0x40000be4; +r_ble_hw_resolv_list_set = 0x40000be8; +r_ble_hw_rng_init = 0x40000bec; +r_ble_hw_rng_start = 0x40000bf0; +r_ble_hw_rng_stop = 0x40000bf4; +r_ble_hw_rx_local_is_rpa = 0x40000bf8; +r_ble_hw_whitelist_add = 0x40000bfc; +r_ble_hw_whitelist_clear = 0x40000c00; +r_ble_hw_whitelist_dev_num = 0x40000c04; +r_ble_hw_whitelist_get_base = 0x40000c08; +r_ble_hw_whitelist_rmv = 0x40000c0c; +r_ble_hw_whitelist_search = 0x40000c10; +r_ble_hw_whitelist_sort = 0x40000c14; +r_ble_ll_acl_data_in = 0x40000c18; +r_ble_ll_addr_is_id = 0x40000c1c; +r_ble_ll_addr_subtype = 0x40000c20; +r_ble_ll_adv_active_chanset_clear = 0x40000c24; +r_ble_ll_adv_active_chanset_is_pri = 0x40000c28; +r_ble_ll_adv_active_chanset_is_sec = 0x40000c2c; +r_ble_ll_adv_active_chanset_set_pri = 0x40000c30; +r_ble_ll_adv_active_chanset_set_sec = 0x40000c34; +r_ble_ll_adv_aux_calculate = 0x40000c38; +r_ble_ll_adv_aux_conn_rsp_pdu_make = 0x40000c3c; +r_ble_ll_adv_aux_pdu_make = 0x40000c40; +r_ble_ll_adv_aux_scannable_pdu_make = 0x40000c44; +r_ble_ll_adv_aux_scannable_pdu_payload_len = 0x40000c48; +r_ble_ll_adv_aux_schedule = 0x40000c4c; +r_ble_ll_adv_aux_schedule_first = 0x40000c50; +r_ble_ll_adv_aux_schedule_next = 0x40000c54; +r_ble_ll_adv_aux_scheduled = 0x40000c58; +r_ble_ll_adv_aux_set_start_time = 0x40000c5c; +r_ble_ll_adv_aux_txed = 0x40000c60; +r_ble_ll_adv_can_chg_whitelist = 0x40000c64; +r_ble_ll_adv_chk_rpa_timeout = 0x40000c68; +r_ble_ll_adv_clear_all = 0x40000c6c; +r_ble_ll_adv_coex_dpc_calc_pti_update_itvl = 0x40000c70; +r_ble_ll_adv_coex_dpc_process_pri = 0x40000c74; +r_ble_ll_adv_coex_dpc_process_sec = 0x40000c78; +r_ble_ll_adv_coex_dpc_pti_get = 0x40000c7c; +r_ble_ll_adv_coex_dpc_update = 0x40000c80; +r_ble_ll_adv_coex_dpc_update_on_adv_start = 0x40000c84; +r_ble_ll_adv_coex_dpc_update_on_aux_scheduled = 0x40000c88; +r_ble_ll_adv_coex_dpc_update_on_data_updated = 0x40000c8c; +r_ble_ll_adv_coex_dpc_update_on_event_end = 0x40000c90; +r_ble_ll_adv_coex_dpc_update_on_event_scheduled = 0x40000c94; +r_ble_ll_adv_conn_req_rxd = 0x40000c98; +r_ble_ll_adv_deinit = 0x40000c9c; +r_ble_ll_adv_done = 0x40000ca0; +r_ble_ll_adv_drop_event = 0x40000ca4; +r_ble_ll_adv_enabled = 0x40000ca8; +r_ble_ll_adv_env_init = 0x40000cac; +r_ble_ll_adv_event_done = 0x40000cb0; +r_ble_ll_adv_event_rmvd_from_sched = 0x40000cb4; +r_ble_ll_adv_ext_estimate_data_itvl = 0x40000cb8; +r_ble_ll_adv_ext_set_adv_data = 0x40000cbc; +r_ble_ll_adv_ext_set_enable = 0x40000cc0; +r_ble_ll_adv_ext_set_param = 0x40000cc4; +r_ble_ll_adv_ext_set_scan_rsp = 0x40000cc8; +r_ble_ll_adv_final_chan = 0x40000ccc; +r_ble_ll_adv_first_chan = 0x40000cd0; +r_ble_ll_adv_flags_clear = 0x40000cd4; +r_ble_ll_adv_flags_set = 0x40000cd8; +r_ble_ll_adv_get_local_rpa = 0x40000cdc; +r_ble_ll_adv_get_peer_rpa = 0x40000ce0; +r_ble_ll_adv_get_sec_pdu_len = 0x40000ce4; +r_ble_ll_adv_halt = 0x40000ce8; +r_ble_ll_adv_hci_set_random_addr = 0x40000cec; +r_ble_ll_adv_init = 0x40000cf0; +r_ble_ll_adv_legacy_pdu_make = 0x40000cf4; +r_ble_ll_adv_make_done = 0x40000cf8; +r_ble_ll_adv_pdu_make = 0x40000cfc; +r_ble_ll_adv_periodic_check_data_itvl = 0x40000d00; +r_ble_ll_adv_periodic_done = 0x40000d04; +r_ble_ll_adv_periodic_enable = 0x40000d08; +r_ble_ll_adv_periodic_estimate_data_itvl = 0x40000d0c; +r_ble_ll_adv_periodic_event_done = 0x40000d10; +r_ble_ll_adv_periodic_rmvd_from_sched = 0x40000d14; +r_ble_ll_adv_periodic_schedule_first = 0x40000d18; +r_ble_ll_adv_periodic_schedule_next = 0x40000d1c; +r_ble_ll_adv_periodic_send_sync_ind = 0x40000d20; +r_ble_ll_adv_periodic_set_data = 0x40000d24; +r_ble_ll_adv_periodic_set_info_transfer = 0x40000d28; +r_ble_ll_adv_periodic_set_param = 0x40000d2c; +r_ble_ll_adv_put_aux_ptr = 0x40000d30; +r_ble_ll_adv_put_syncinfo = 0x40000d34; +r_ble_ll_adv_rd_max_adv_data_len = 0x40000d38; +r_ble_ll_adv_rd_sup_adv_sets = 0x40000d3c; +r_ble_ll_adv_read_txpwr = 0x40000d40; +r_ble_ll_adv_remove = 0x40000d44; +r_ble_ll_adv_reschedule_event = 0x40000d48; +r_ble_ll_adv_reschedule_periodic_event = 0x40000d4c; +r_ble_ll_adv_reset = 0x40000d50; +r_ble_ll_adv_rpa_timeout = 0x40000d54; +r_ble_ll_adv_rpa_update = 0x40000d58; +r_ble_ll_adv_rx_isr_end = 0x40000d5c; +r_ble_ll_adv_rx_isr_start = 0x40000d60; +r_ble_ll_adv_rx_pkt_in = 0x40000d64; +r_ble_ll_adv_rx_req = 0x40000d68; +r_ble_ll_adv_scan_rsp_legacy_pdu_make = 0x40000d6c; +r_ble_ll_adv_scan_rsp_pdu_make = 0x40000d70; +r_ble_ll_adv_scheduled = 0x40000d74; +r_ble_ll_adv_sec_done = 0x40000d78; +r_ble_ll_adv_sec_event_done = 0x40000d7c; +r_ble_ll_adv_secondary_tx_start_cb = 0x40000d80; +r_ble_ll_adv_send_conn_comp_ev = 0x40000d84; +r_ble_ll_adv_set_adv_data = 0x40000d88; +r_ble_ll_adv_set_adv_params = 0x40000d8c; +r_ble_ll_adv_set_enable = 0x40000d90; +r_ble_ll_adv_set_random_addr = 0x40000d94; +r_ble_ll_adv_set_scan_rsp_data = 0x40000d98; +r_ble_ll_adv_set_sched = 0x40000d9c; +r_ble_ll_adv_sm_deinit = 0x40000da0; +r_ble_ll_adv_sm_event_init = 0x40000da4; +r_ble_ll_adv_sm_event_restore = 0x40000da8; +r_ble_ll_adv_sm_event_store = 0x40000dac; +r_ble_ll_adv_sm_find_configured = 0x40000db0; +r_ble_ll_adv_sm_get = 0x40000db4; +r_ble_ll_adv_sm_init = 0x40000db8; +r_ble_ll_adv_sm_reset = 0x40000dbc; +r_ble_ll_adv_sm_start = 0x40000dc0; +r_ble_ll_adv_sm_start_periodic = 0x40000dc4; +r_ble_ll_adv_sm_stop = 0x40000dc8; +r_ble_ll_adv_sm_stop_limit_reached = 0x40000dcc; +r_ble_ll_adv_sm_stop_periodic = 0x40000dd0; +r_ble_ll_adv_sm_stop_timeout = 0x40000dd4; +r_ble_ll_adv_sync_calculate = 0x40000dd8; +r_ble_ll_adv_sync_get_pdu_len = 0x40000ddc; +r_ble_ll_adv_sync_next_scheduled = 0x40000de0; +r_ble_ll_adv_sync_pdu_make = 0x40000de4; +r_ble_ll_adv_sync_schedule = 0x40000de8; +r_ble_ll_adv_sync_tx_done = 0x40000dec; +r_ble_ll_adv_sync_tx_end = 0x40000df0; +r_ble_ll_adv_sync_tx_start_cb = 0x40000df4; +r_ble_ll_adv_tx_done = 0x40000df8; +r_ble_ll_adv_tx_start_cb = 0x40000dfc; +r_ble_ll_adv_update_adv_scan_rsp_data = 0x40000e00; +r_ble_ll_adv_update_data_mbuf = 0x40000e04; +r_ble_ll_adv_update_did = 0x40000e08; +r_ble_ll_adv_update_periodic_data = 0x40000e0c; +r_ble_ll_adv_update_rsp_offset = 0x40000e10; r_ble_ll_adv_wfr_timer_exp = 0x40000e14; r_ble_ll_arr_pool_init = 0x40000e18; r_ble_ll_auth_pyld_tmo_event_send = 0x40000e1c; diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.libgcc.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.libgcc.ld index 8e383324b6..f96bf11486 100644 --- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.libgcc.ld +++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.libgcc.ld @@ -1,13 +1,12 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ - /* ROM function interface esp32h2.rom.libgcc.ld for esp32h2 * * - * Generated from ./interface-esp32h2.yml md5sum a4343bd6a9a68319e4e3cc26aea38574 + * Generated from ./target/esp32h2/interface-esp32h2.yml md5sum da4c474a48c097d4ac9acad67f70fda6 * * Compatible with ROM where ECO version equal or greater to 0. * @@ -19,95 +18,95 @@ ***************************************/ /* Functions */ -__absvdi2 = 0x4000098c; -__absvsi2 = 0x40000990; -__adddf3 = 0x40000994; -__addsf3 = 0x40000998; -__addvdi3 = 0x4000099c; -__addvsi3 = 0x400009a0; -__ashldi3 = 0x400009a4; -__ashrdi3 = 0x400009a8; -__bswapdi2 = 0x400009ac; -__bswapsi2 = 0x400009b0; -__clear_cache = 0x400009b4; -__clrsbdi2 = 0x400009b8; -__clrsbsi2 = 0x400009bc; -__clzdi2 = 0x400009c0; -__clzsi2 = 0x400009c4; -__cmpdi2 = 0x400009c8; -__ctzdi2 = 0x400009cc; -__ctzsi2 = 0x400009d0; -__divdc3 = 0x400009d4; -__divdf3 = 0x400009d8; -__divdi3 = 0x400009dc; -__divsc3 = 0x400009e0; -__divsf3 = 0x400009e4; -__divsi3 = 0x400009e8; -__eqdf2 = 0x400009ec; -__eqsf2 = 0x400009f0; -__extendsfdf2 = 0x400009f4; -__ffsdi2 = 0x400009f8; -__ffssi2 = 0x400009fc; -__fixdfdi = 0x40000a00; -__fixdfsi = 0x40000a04; -__fixsfdi = 0x40000a08; -__fixsfsi = 0x40000a0c; -__fixunsdfsi = 0x40000a10; -__fixunssfdi = 0x40000a14; -__fixunssfsi = 0x40000a18; -__floatdidf = 0x40000a1c; -__floatdisf = 0x40000a20; -__floatsidf = 0x40000a24; -__floatsisf = 0x40000a28; -__floatundidf = 0x40000a2c; -__floatundisf = 0x40000a30; -__floatunsidf = 0x40000a34; -__floatunsisf = 0x40000a38; -__gcc_bcmp = 0x40000a3c; -__gedf2 = 0x40000a40; -__gesf2 = 0x40000a44; -__gtdf2 = 0x40000a48; -__gtsf2 = 0x40000a4c; -__ledf2 = 0x40000a50; -__lesf2 = 0x40000a54; -__lshrdi3 = 0x40000a58; -__ltdf2 = 0x40000a5c; -__ltsf2 = 0x40000a60; -__moddi3 = 0x40000a64; -__modsi3 = 0x40000a68; -__muldc3 = 0x40000a6c; -__muldf3 = 0x40000a70; -__muldi3 = 0x40000a74; -__mulsc3 = 0x40000a78; -__mulsf3 = 0x40000a7c; -__mulsi3 = 0x40000a80; -__mulvdi3 = 0x40000a84; -__mulvsi3 = 0x40000a88; -__nedf2 = 0x40000a8c; -__negdf2 = 0x40000a90; -__negdi2 = 0x40000a94; -__negsf2 = 0x40000a98; -__negvdi2 = 0x40000a9c; -__negvsi2 = 0x40000aa0; -__nesf2 = 0x40000aa4; -__paritysi2 = 0x40000aa8; -__popcountdi2 = 0x40000aac; -__popcountsi2 = 0x40000ab0; -__powidf2 = 0x40000ab4; -__powisf2 = 0x40000ab8; -__subdf3 = 0x40000abc; -__subsf3 = 0x40000ac0; -__subvdi3 = 0x40000ac4; -__subvsi3 = 0x40000ac8; -__truncdfsf2 = 0x40000acc; -__ucmpdi2 = 0x40000ad0; -__udivdi3 = 0x40000ad4; -__udivmoddi4 = 0x40000ad8; -__udivsi3 = 0x40000adc; -__udiv_w_sdiv = 0x40000ae0; -__umoddi3 = 0x40000ae4; -__umodsi3 = 0x40000ae8; -__unorddf2 = 0x40000aec; -__unordsf2 = 0x40000af0; -__extenddftf2 = 0x40000af4; -__trunctfdf2 = 0x40000af8; +__absvdi2 = 0x40000998; +__absvsi2 = 0x4000099c; +__adddf3 = 0x400009a0; +__addsf3 = 0x400009a4; +__addvdi3 = 0x400009a8; +__addvsi3 = 0x400009ac; +__ashldi3 = 0x400009b0; +__ashrdi3 = 0x400009b4; +__bswapdi2 = 0x400009b8; +__bswapsi2 = 0x400009bc; +__clear_cache = 0x400009c0; +__clrsbdi2 = 0x400009c4; +__clrsbsi2 = 0x400009c8; +__clzdi2 = 0x400009cc; +__clzsi2 = 0x400009d0; +__cmpdi2 = 0x400009d4; +__ctzdi2 = 0x400009d8; +__ctzsi2 = 0x400009dc; +__divdc3 = 0x400009e0; +__divdf3 = 0x400009e4; +__divdi3 = 0x400009e8; +__divsc3 = 0x400009ec; +__divsf3 = 0x400009f0; +__divsi3 = 0x400009f4; +__eqdf2 = 0x400009f8; +__eqsf2 = 0x400009fc; +__extendsfdf2 = 0x40000a00; +__ffsdi2 = 0x40000a04; +__ffssi2 = 0x40000a08; +__fixdfdi = 0x40000a0c; +__fixdfsi = 0x40000a10; +__fixsfdi = 0x40000a14; +__fixsfsi = 0x40000a18; +__fixunsdfsi = 0x40000a1c; +__fixunssfdi = 0x40000a20; +__fixunssfsi = 0x40000a24; +__floatdidf = 0x40000a28; +__floatdisf = 0x40000a2c; +__floatsidf = 0x40000a30; +__floatsisf = 0x40000a34; +__floatundidf = 0x40000a38; +__floatundisf = 0x40000a3c; +__floatunsidf = 0x40000a40; +__floatunsisf = 0x40000a44; +__gcc_bcmp = 0x40000a48; +__gedf2 = 0x40000a4c; +__gesf2 = 0x40000a50; +__gtdf2 = 0x40000a54; +__gtsf2 = 0x40000a58; +__ledf2 = 0x40000a5c; +__lesf2 = 0x40000a60; +__lshrdi3 = 0x40000a64; +__ltdf2 = 0x40000a68; +__ltsf2 = 0x40000a6c; +__moddi3 = 0x40000a70; +__modsi3 = 0x40000a74; +__muldc3 = 0x40000a78; +__muldf3 = 0x40000a7c; +__muldi3 = 0x40000a80; +__mulsc3 = 0x40000a84; +__mulsf3 = 0x40000a88; +__mulsi3 = 0x40000a8c; +__mulvdi3 = 0x40000a90; +__mulvsi3 = 0x40000a94; +__nedf2 = 0x40000a98; +__negdf2 = 0x40000a9c; +__negdi2 = 0x40000aa0; +__negsf2 = 0x40000aa4; +__negvdi2 = 0x40000aa8; +__negvsi2 = 0x40000aac; +__nesf2 = 0x40000ab0; +__paritysi2 = 0x40000ab4; +__popcountdi2 = 0x40000ab8; +__popcountsi2 = 0x40000abc; +__powidf2 = 0x40000ac0; +__powisf2 = 0x40000ac4; +__subdf3 = 0x40000ac8; +__subsf3 = 0x40000acc; +__subvdi3 = 0x40000ad0; +__subvsi3 = 0x40000ad4; +__truncdfsf2 = 0x40000ad8; +__ucmpdi2 = 0x40000adc; +__udivdi3 = 0x40000ae0; +__udivmoddi4 = 0x40000ae4; +__udivsi3 = 0x40000ae8; +__udiv_w_sdiv = 0x40000aec; +__umoddi3 = 0x40000af0; +__umodsi3 = 0x40000af4; +__unorddf2 = 0x40000af8; +__unordsf2 = 0x40000afc; +__extenddftf2 = 0x40000b00; +__trunctfdf2 = 0x40000b04; diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib-nano.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib-nano.ld index f6ba33d807..56c783e57f 100644 --- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib-nano.ld +++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib-nano.ld @@ -1,13 +1,12 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ - /* ROM function interface esp32h2.rom.newlib-nano.ld for esp32h2 * * - * Generated from ./interface-esp32h2.yml md5sum a4343bd6a9a68319e4e3cc26aea38574 + * Generated from ./target/esp32h2/interface-esp32h2.yml md5sum da4c474a48c097d4ac9acad67f70fda6 * * Compatible with ROM where ECO version equal or greater to 0. * @@ -19,30 +18,30 @@ ***************************************/ /* Functions */ -__sprint_r = 0x40000674; -_fiprintf_r = 0x40000678; -_fprintf_r = 0x4000067c; -_printf_common = 0x40000680; -_printf_i = 0x40000684; -_vfiprintf_r = 0x40000688; -_vfprintf_r = 0x4000068c; -fiprintf = 0x40000690; -fprintf = 0x40000694; -printf = 0x40000698; -vfiprintf = 0x4000069c; -vfprintf = 0x400006a0; -asprintf = 0x400006a4; -sprintf = 0x400006a8; -snprintf = 0x400006ac; -siprintf = 0x400006b0; -sniprintf = 0x400006b4; -vprintf = 0x400006b8; -viprintf = 0x400006bc; -vsnprintf = 0x400006c0; -vsniprintf = 0x400006c4; -__rom_printf_float = 0x400006c8; -__rom_scanf_float = 0x400006cc; -_scanf_i = 0x400006d0; -_scanf_chars = 0x400006d4; -sscanf = 0x400006d8; -siscanf = 0x400006dc; +__sprint_r = 0x40000684; +_fiprintf_r = 0x40000688; +_fprintf_r = 0x4000068c; +_printf_common = 0x40000690; +_printf_i = 0x40000694; +_vfiprintf_r = 0x40000698; +_vfprintf_r = 0x4000069c; +fiprintf = 0x400006a0; +fprintf = 0x400006a4; +printf = 0x400006a8; +vfiprintf = 0x400006ac; +vfprintf = 0x400006b0; +asprintf = 0x400006b4; +sprintf = 0x400006b8; +snprintf = 0x400006bc; +siprintf = 0x400006c0; +sniprintf = 0x400006c4; +vprintf = 0x400006c8; +viprintf = 0x400006cc; +vsnprintf = 0x400006d0; +vsniprintf = 0x400006d4; +__rom_printf_float = 0x400006d8; +__rom_scanf_float = 0x400006dc; +_scanf_i = 0x400006e0; +_scanf_chars = 0x400006e4; +sscanf = 0x400006e8; +siscanf = 0x400006ec; diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib.ld index 746ed1b771..d8ac6aabfc 100644 --- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib.ld +++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib.ld @@ -1,13 +1,12 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ - /* ROM function interface esp32h2.rom.newlib.ld for esp32h2 * * - * Generated from ./interface-esp32h2.yml md5sum a4343bd6a9a68319e4e3cc26aea38574 + * Generated from ./target/esp32h2/interface-esp32h2.yml md5sum da4c474a48c097d4ac9acad67f70fda6 * * Compatible with ROM where ECO version equal or greater to 0. * @@ -19,126 +18,130 @@ ***************************************/ /* Functions */ -esp_rom_newlib_init_common_mutexes = 0x40000484; -memset = 0x40000488; -memcpy = 0x4000048c; -memmove = 0x40000490; -memcmp = 0x40000494; -strcpy = 0x40000498; -strncpy = 0x4000049c; -strcmp = 0x400004a0; -strncmp = 0x400004a4; -strlen = 0x400004a8; -strstr = 0x400004ac; -bzero = 0x400004b0; -sbrk = 0x400004b8; -isalnum = 0x400004bc; -isalpha = 0x400004c0; -isascii = 0x400004c4; -isblank = 0x400004c8; -iscntrl = 0x400004cc; -isdigit = 0x400004d0; -islower = 0x400004d4; -isgraph = 0x400004d8; -isprint = 0x400004dc; -ispunct = 0x400004e0; -isspace = 0x400004e4; -isupper = 0x400004e8; -toupper = 0x400004ec; -tolower = 0x400004f0; -toascii = 0x400004f4; -memccpy = 0x400004f8; -memchr = 0x400004fc; -memrchr = 0x40000500; -strcasecmp = 0x40000504; -strcasestr = 0x40000508; -strcat = 0x4000050c; -strdup = 0x40000510; -strchr = 0x40000514; -strcspn = 0x40000518; -strcoll = 0x4000051c; -strlcat = 0x40000520; -strlcpy = 0x40000524; -strlwr = 0x40000528; -strncasecmp = 0x4000052c; -strncat = 0x40000530; -strndup = 0x40000534; -strnlen = 0x40000538; -strrchr = 0x4000053c; -strsep = 0x40000540; -strspn = 0x40000544; -strtok_r = 0x40000548; -strupr = 0x4000054c; -longjmp = 0x40000550; -setjmp = 0x40000554; -abs = 0x40000558; -div = 0x4000055c; -labs = 0x40000560; -ldiv = 0x40000564; -qsort = 0x40000568; -rand_r = 0x4000056c; -rand = 0x40000570; -srand = 0x40000574; -utoa = 0x40000578; -itoa = 0x4000057c; -atoi = 0x40000580; -atol = 0x40000584; -strtol = 0x40000588; -strtoul = 0x4000058c; -fflush = 0x40000590; -_fflush_r = 0x40000594; -_fwalk = 0x40000598; -_fwalk_reent = 0x4000059c; -__swbuf_r = 0x400005a8; -__swbuf = 0x400005ac; -_strtod_l = 0x400005b4; -_strtod_r = 0x400005b8; -strtod_l = 0x400005bc; -strtod = 0x400005c0; -strtof_l = 0x400005c4; -strtof = 0x400005c8; -_strtol_r = 0x400005cc; -strtol_l = 0x400005d0; -_strtoul_r = 0x400005d4; -strtoul_l = 0x400005d8; -__match = 0x400005dc; -__hexnan = 0x400005e0; -__hexdig_fun = 0x400005e4; -__gethex = 0x400005e8; -_Balloc = 0x400005ec; -_Bfree = 0x400005f0; -__multadd = 0x400005f4; -__s2b = 0x400005f8; -__hi0bits = 0x400005fc; -__lo0bits = 0x40000600; -__i2b = 0x40000604; -__multiply = 0x40000608; -__pow5mult = 0x4000060c; -__lshift = 0x40000610; -__mcmp = 0x40000614; -__mdiff = 0x40000618; -__ulp = 0x4000061c; -__b2d = 0x40000620; -__d2b = 0x40000624; -__ratio = 0x40000628; -_mprec_log10 = 0x4000062c; -__copybits = 0x40000630; -__any_on = 0x40000634; -asctime = 0x40000638; -asctime_r = 0x4000063c; -atof = 0x40000640; -atoff = 0x40000644; -_dtoa_r = 0x40000648; -_wctomb_r = 0x4000064c; -__ascii_wctomb = 0x40000650; -_mbtowc_r = 0x40000654; -__ascii_mbtowc = 0x40000658; -puts = 0x4000065c; -putc = 0x40000660; -putchar = 0x40000664; -nan = 0x40000668; -nanf = 0x4000066c; -__errno = 0x40000670; +esp_rom_newlib_init_common_mutexes = 0x40000494; +memset = 0x40000498; +memcpy = 0x4000049c; +memmove = 0x400004a0; +memcmp = 0x400004a4; +strcpy = 0x400004a8; +strncpy = 0x400004ac; +strcmp = 0x400004b0; +strncmp = 0x400004b4; +strlen = 0x400004b8; +strstr = 0x400004bc; +bzero = 0x400004c0; +_isatty_r = 0x400004c4; +sbrk = 0x400004c8; +isalnum = 0x400004cc; +isalpha = 0x400004d0; +isascii = 0x400004d4; +isblank = 0x400004d8; +iscntrl = 0x400004dc; +isdigit = 0x400004e0; +islower = 0x400004e4; +isgraph = 0x400004e8; +isprint = 0x400004ec; +ispunct = 0x400004f0; +isspace = 0x400004f4; +isupper = 0x400004f8; +toupper = 0x400004fc; +tolower = 0x40000500; +toascii = 0x40000504; +memccpy = 0x40000508; +memchr = 0x4000050c; +memrchr = 0x40000510; +strcasecmp = 0x40000514; +strcasestr = 0x40000518; +strcat = 0x4000051c; +strdup = 0x40000520; +strchr = 0x40000524; +strcspn = 0x40000528; +strcoll = 0x4000052c; +strlcat = 0x40000530; +strlcpy = 0x40000534; +strlwr = 0x40000538; +strncasecmp = 0x4000053c; +strncat = 0x40000540; +strndup = 0x40000544; +strnlen = 0x40000548; +strrchr = 0x4000054c; +strsep = 0x40000550; +strspn = 0x40000554; +strtok_r = 0x40000558; +strupr = 0x4000055c; +longjmp = 0x40000560; +setjmp = 0x40000564; +abs = 0x40000568; +div = 0x4000056c; +labs = 0x40000570; +ldiv = 0x40000574; +qsort = 0x40000578; +rand_r = 0x4000057c; +rand = 0x40000580; +srand = 0x40000584; +utoa = 0x40000588; +itoa = 0x4000058c; +atoi = 0x40000590; +atol = 0x40000594; +strtol = 0x40000598; +strtoul = 0x4000059c; +fflush = 0x400005a0; +_fflush_r = 0x400005a4; +_fwalk = 0x400005a8; +_fwalk_reent = 0x400005ac; +__smakebuf_r = 0x400005b0; +__swhatbuf_r = 0x400005b4; +__swbuf_r = 0x400005b8; +__swbuf = 0x400005bc; +__swsetup_r = 0x400005c0; +_strtod_l = 0x400005c4; +_strtod_r = 0x400005c8; +strtod_l = 0x400005cc; +strtod = 0x400005d0; +strtof_l = 0x400005d4; +strtof = 0x400005d8; +_strtol_r = 0x400005dc; +strtol_l = 0x400005e0; +_strtoul_r = 0x400005e4; +strtoul_l = 0x400005e8; +__match = 0x400005ec; +__hexnan = 0x400005f0; +__hexdig_fun = 0x400005f4; +__gethex = 0x400005f8; +_Balloc = 0x400005fc; +_Bfree = 0x40000600; +__multadd = 0x40000604; +__s2b = 0x40000608; +__hi0bits = 0x4000060c; +__lo0bits = 0x40000610; +__i2b = 0x40000614; +__multiply = 0x40000618; +__pow5mult = 0x4000061c; +__lshift = 0x40000620; +__mcmp = 0x40000624; +__mdiff = 0x40000628; +__ulp = 0x4000062c; +__b2d = 0x40000630; +__d2b = 0x40000634; +__ratio = 0x40000638; +_mprec_log10 = 0x4000063c; +__copybits = 0x40000640; +__any_on = 0x40000644; +asctime = 0x40000648; +asctime_r = 0x4000064c; +atof = 0x40000650; +atoff = 0x40000654; +_dtoa_r = 0x40000658; +_wctomb_r = 0x4000065c; +__ascii_wctomb = 0x40000660; +_mbtowc_r = 0x40000664; +__ascii_mbtowc = 0x40000668; +puts = 0x4000066c; +putc = 0x40000670; +putchar = 0x40000674; +nan = 0x40000678; +nanf = 0x4000067c; +__errno = 0x40000680; /* Data (.data, .bss, .rodata) */ -syscall_table_ptr = 0x3fcdffd8; -_global_impure_ptr = 0x3fcdffd4; +syscall_table_ptr = 0x3fcdffd4; +_global_impure_ptr = 0x3fcdffd0; diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.version.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.version.ld index 29e27a2d0a..c7330d8d1d 100644 --- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.version.ld +++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.version.ld @@ -1,9 +1,8 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ - /* ROM version variables for esp32h2 * * These addresses should be compatible with any ROM version for this chip. diff --git a/components/soc/esp32h2/include/rev2/soc/efuse_struct.h b/components/soc/esp32h2/include/rev2/soc/efuse_struct.h index 6a41ccd4eb..da8552b051 100644 --- a/components/soc/esp32h2/include/rev2/soc/efuse_struct.h +++ b/components/soc/esp32h2/include/rev2/soc/efuse_struct.h @@ -1,2176 +1,439 @@ -/** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD +/* + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#pragma once +#ifndef _SOC_EFUSE_STRUCT_H_ +#define _SOC_EFUSE_STRUCT_H_ + -#include #ifdef __cplusplus extern "C" { #endif -/** Group: PGM Data Register */ -/** Type of pgm_data0 register - * Register 0 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; - * The content of the 0th 32-bit data to be programmed. - */ - uint32_t pgm_data_0:32; - }; - uint32_t val; -} efuse_pgm_data0_reg_t; - -/** Type of pgm_data1 register - * Register 1 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; - * The content of the 1st 32-bit data to be programmed. - */ - uint32_t pgm_data_1:32; - }; - uint32_t val; -} efuse_pgm_data1_reg_t; - -/** Type of pgm_data2 register - * Register 2 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; - * The content of the 2nd 32-bit data to be programmed. - */ - uint32_t pgm_data_2:32; - }; - uint32_t val; -} efuse_pgm_data2_reg_t; - -/** Type of pgm_data3 register - * Register 3 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; - * The content of the 3rd 32-bit data to be programmed. - */ - uint32_t pgm_data_3:32; - }; - uint32_t val; -} efuse_pgm_data3_reg_t; - -/** Type of pgm_data4 register - * Register 4 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; - * The content of the 4th 32-bit data to be programmed. - */ - uint32_t pgm_data_4:32; - }; - uint32_t val; -} efuse_pgm_data4_reg_t; - -/** Type of pgm_data5 register - * Register 5 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; - * The content of the 5th 32-bit data to be programmed. - */ - uint32_t pgm_data_5:32; - }; - uint32_t val; -} efuse_pgm_data5_reg_t; - -/** Type of pgm_data6 register - * Register 6 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; - * The content of the 6th 32-bit data to be programmed. - */ - uint32_t pgm_data_6:32; - }; - uint32_t val; -} efuse_pgm_data6_reg_t; - -/** Type of pgm_data7 register - * Register 7 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; - * The content of the 7th 32-bit data to be programmed. - */ - uint32_t pgm_data_7:32; - }; - uint32_t val; -} efuse_pgm_data7_reg_t; - -/** Type of pgm_check_value0 register - * Register 0 that stores the RS code to be programmed. - */ -typedef union { - struct { - /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; - * The content of the 0th 32-bit RS code to be programmed. - */ - uint32_t pgm_rs_data_0:32; - }; - uint32_t val; -} efuse_pgm_check_value0_reg_t; - -/** Type of pgm_check_value1 register - * Register 1 that stores the RS code to be programmed. - */ -typedef union { - struct { - /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; - * The content of the 1st 32-bit RS code to be programmed. - */ - uint32_t pgm_rs_data_1:32; - }; - uint32_t val; -} efuse_pgm_check_value1_reg_t; - -/** Type of pgm_check_value2 register - * Register 2 that stores the RS code to be programmed. - */ -typedef union { - struct { - /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; - * The content of the 2nd 32-bit RS code to be programmed. - */ - uint32_t pgm_rs_data_2:32; - }; - uint32_t val; -} efuse_pgm_check_value2_reg_t; - - -/** Group: ******** Registers */ -/** Type of rd_wr_dis register - * BLOCK0 data register $n. - */ -typedef union { - struct { - /** wr_dis : RO; bitpos: [31:0]; default: 0; - * The value of WR_DIS. - */ - uint32_t wr_dis:32; - }; - uint32_t val; -} efuse_rd_wr_dis_reg_t; - -/** Type of rd_repeat_data0 register - * BLOCK0 data register $n. - */ -typedef union { - struct { - /** rd_dis : RO; bitpos: [6:0]; default: 0; - * The value of RD_DIS. - */ - uint32_t rd_dis:7; - /** rpt4_reserved5 : RO; bitpos: [7]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved5:1; - /** dis_icache : RO; bitpos: [8]; default: 0; - * The value of DIS_ICACHE. - */ - uint32_t dis_icache:1; - /** dis_usb_jtag : RO; bitpos: [9]; default: 0; - * The value of DIS_USB_JTAG. - */ - uint32_t dis_usb_jtag:1; - /** dis_download_icache : RO; bitpos: [10]; default: 0; - * The value of DIS_DOWNLOAD_ICACHE. - */ - uint32_t dis_download_icache:1; - /** dis_usb_device : RO; bitpos: [11]; default: 0; - * The value of DIS_USB_DEVICE. - */ - uint32_t dis_usb_device:1; - /** dis_force_download : RO; bitpos: [12]; default: 0; - * The value of DIS_FORCE_DOWNLOAD. - */ - uint32_t dis_force_download:1; - /** rpt4_reserved6 : RO; bitpos: [13]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved6:1; - /** dis_twai : RO; bitpos: [14]; default: 0; - * The value of DIS_TWAI. - */ - uint32_t dis_twai:1; - /** jtag_sel_enable : RO; bitpos: [15]; default: 0; - * The value of JTAG_SEL_ENABLE. - */ - uint32_t jtag_sel_enable:1; - /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; - * The value of SOFT_DIS_JTAG. - */ - uint32_t soft_dis_jtag:3; - /** dis_pad_jtag : RO; bitpos: [19]; default: 0; - * The value of DIS_PAD_JTAG. - */ - uint32_t dis_pad_jtag:1; - /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; - * The value of DIS_DOWNLOAD_MANUAL_ENCRYPT. - */ - uint32_t dis_download_manual_encrypt:1; - /** usb_drefh : RO; bitpos: [22:21]; default: 0; - * The value of USB_DREFH. - */ - uint32_t usb_drefh:2; - /** usb_drefl : RO; bitpos: [24:23]; default: 0; - * The value of USB_DREFL. - */ - uint32_t usb_drefl:2; - /** usb_exchg_pins : RO; bitpos: [25]; default: 0; - * The value of USB_EXCHG_PINS. - */ - uint32_t usb_exchg_pins:1; - /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0; - * The value of VDD_SPI_AS_GPIO. - */ - uint32_t vdd_spi_as_gpio:1; - /** btlc_gpio_enable : RO; bitpos: [28:27]; default: 0; - * The value of BTLC_GPIO_ENABLE. - */ - uint32_t btlc_gpio_enable:2; - /** powerglitch_en : RO; bitpos: [29]; default: 0; - * The value of POWERGLITCH_EN. - */ - uint32_t powerglitch_en:1; - /** power_glitch_dsense : RO; bitpos: [31:30]; default: 0; - * The value of POWER_GLITCH_DSENSE. - */ - uint32_t power_glitch_dsense:2; - }; - uint32_t val; -} efuse_rd_repeat_data0_reg_t; - -/** Type of rd_repeat_data1 register - * BLOCK0 data register $n. - */ -typedef union { - struct { - /** rpt4_reserved2 : RO; bitpos: [15:0]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved2:16; - /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; - * The value of WDT_DELAY_SEL. - */ - uint32_t wdt_delay_sel:2; - /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; - * The value of SPI_BOOT_CRYPT_CNT. - */ - uint32_t spi_boot_crypt_cnt:3; - /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; - * The value of SECURE_BOOT_KEY_REVOKE0. - */ - uint32_t secure_boot_key_revoke0:1; - /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; - * The value of SECURE_BOOT_KEY_REVOKE1. - */ - uint32_t secure_boot_key_revoke1:1; - /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; - * The value of SECURE_BOOT_KEY_REVOKE2. - */ - uint32_t secure_boot_key_revoke2:1; - /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; - * The value of KEY_PURPOSE_0. - */ - uint32_t key_purpose_0:4; - /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; - * The value of KEY_PURPOSE_1. - */ - uint32_t key_purpose_1:4; - }; - uint32_t val; -} efuse_rd_repeat_data1_reg_t; - -/** Type of rd_repeat_data2 register - * BLOCK0 data register $n. - */ -typedef union { - struct { - /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; - * The value of KEY_PURPOSE_2. - */ - uint32_t key_purpose_2:4; - /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; - * The value of KEY_PURPOSE_3. - */ - uint32_t key_purpose_3:4; - /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; - * The value of KEY_PURPOSE_4. - */ - uint32_t key_purpose_4:4; - /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; - * The value of KEY_PURPOSE_5. - */ - uint32_t key_purpose_5:4; - /** rpt4_reserved3 : RO; bitpos: [19:16]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved3:4; - /** secure_boot_en : RO; bitpos: [20]; default: 0; - * The value of SECURE_BOOT_EN. - */ - uint32_t secure_boot_en:1; - /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; - * The value of SECURE_BOOT_AGGRESSIVE_REVOKE. - */ - uint32_t secure_boot_aggressive_revoke:1; - /** rpt4_reserved0 : RO; bitpos: [27:22]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved0:6; - /** flash_tpuw : RO; bitpos: [31:28]; default: 0; - * The value of FLASH_TPUW. - */ - uint32_t flash_tpuw:4; - }; - uint32_t val; -} efuse_rd_repeat_data2_reg_t; - -/** Type of rd_repeat_data3 register - * BLOCK0 data register $n. - */ -typedef union { - struct { - /** dis_download_mode : RO; bitpos: [0]; default: 0; - * The value of DIS_DOWNLOAD_MODE. - */ - uint32_t dis_download_mode:1; - /** dis_legacy_spi_boot : RO; bitpos: [1]; default: 0; - * The value of DIS_LEGACY_SPI_BOOT. - */ - uint32_t dis_legacy_spi_boot:1; - /** uart_print_channel : RO; bitpos: [2]; default: 0; - * The value of UART_PRINT_CHANNEL. - */ - uint32_t uart_print_channel:1; - /** rpt4_reserved8 : RO; bitpos: [3]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved8:1; - /** dis_usb_download_mode : RO; bitpos: [4]; default: 0; - * The value of DIS_USB_DOWNLOAD_MODE. - */ - uint32_t dis_usb_download_mode:1; - /** enable_security_download : RO; bitpos: [5]; default: 0; - * The value of ENABLE_SECURITY_DOWNLOAD. - */ - uint32_t enable_security_download:1; - /** uart_print_control : RO; bitpos: [7:6]; default: 0; - * The value of UART_PRINT_CONTROL. - */ - uint32_t uart_print_control:2; - /** rpt4_reserved7 : RO; bitpos: [12:8]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved7:5; - /** force_send_resume : RO; bitpos: [13]; default: 0; - * The value of FORCE_SEND_RESUME. - */ - uint32_t force_send_resume:1; - /** secure_version : RO; bitpos: [29:14]; default: 0; - * The value of SECURE_VERSION. - */ - uint32_t secure_version:16; - /** rpt4_reserved1 : RO; bitpos: [31:30]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved1:2; - }; - uint32_t val; -} efuse_rd_repeat_data3_reg_t; - -/** Type of rd_repeat_data4 register - * BLOCK0 data register $n. - */ -typedef union { - struct { - /** rpt4_reserved4 : RO; bitpos: [23:0]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved4:24; - uint32_t reserved_24:8; - }; - uint32_t val; -} efuse_rd_repeat_data4_reg_t; - -/** Type of rd_mac_spi_sys_0 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** mac_0 : RO; bitpos: [31:0]; default: 0; - * Stores the low 32 bits of MAC address. - */ - uint32_t mac_0:32; - }; - uint32_t val; -} efuse_rd_mac_spi_sys_0_reg_t; - -/** Type of rd_mac_spi_sys_1 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** mac_1 : RO; bitpos: [15:0]; default: 0; - * Stores the high 16 bits of MAC address. - */ - uint32_t mac_1:16; - /** spi_pad_conf_0 : RO; bitpos: [31:16]; default: 0; - * Stores the zeroth part of SPI_PAD_CONF. - */ - uint32_t spi_pad_conf_0:16; - }; - uint32_t val; -} efuse_rd_mac_spi_sys_1_reg_t; - -/** Type of rd_mac_spi_sys_2 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** spi_pad_conf_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first part of SPI_PAD_CONF. - */ - uint32_t spi_pad_conf_1:32; - }; - uint32_t val; -} efuse_rd_mac_spi_sys_2_reg_t; - -/** Type of rd_mac_spi_sys_3 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** spi_pad_conf_2 : RO; bitpos: [17:0]; default: 0; - * Stores the second part of SPI_PAD_CONF. - */ - uint32_t spi_pad_conf_2:18; - uint32_t wafer_version:3; - uint32_t pkg_version:3; - uint32_t sys_data_part0_0:8; - }; - uint32_t val; -} efuse_rd_mac_spi_sys_3_reg_t; - -/** Type of rd_mac_spi_sys_4 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0; - * Stores the fist 32 bits of the zeroth part of system data. - */ - uint32_t sys_data_part0_1:32; - }; - uint32_t val; -} efuse_rd_mac_spi_sys_4_reg_t; - -/** Type of rd_mac_spi_sys_5 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the zeroth part of system data. - */ - uint32_t sys_data_part0_2:32; - }; - uint32_t val; -} efuse_rd_mac_spi_sys_5_reg_t; - -/** Type of rd_sys_part1_data0 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_0:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data0_reg_t; - -/** Type of rd_sys_part1_data1 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_1:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data1_reg_t; - -/** Type of rd_sys_part1_data2 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_2:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data2_reg_t; - -/** Type of rd_sys_part1_data3 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_3:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data3_reg_t; - -/** Type of rd_sys_part1_data4 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_4:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data4_reg_t; - -/** Type of rd_sys_part1_data5 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_5:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data5_reg_t; - -/** Type of rd_sys_part1_data6 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_6:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data6_reg_t; - -/** Type of rd_sys_part1_data7 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_7:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data7_reg_t; - -/** Type of rd_usr_data0 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of BLOCK3 (user). - */ - uint32_t usr_data0:32; - }; - uint32_t val; -} efuse_rd_usr_data0_reg_t; - -/** Type of rd_usr_data1 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of BLOCK3 (user). - */ - uint32_t usr_data1:32; - }; - uint32_t val; -} efuse_rd_usr_data1_reg_t; - -/** Type of rd_usr_data2 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of BLOCK3 (user). - */ - uint32_t usr_data2:32; - }; - uint32_t val; -} efuse_rd_usr_data2_reg_t; - -/** Type of rd_usr_data3 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of BLOCK3 (user). - */ - uint32_t usr_data3:32; - }; - uint32_t val; -} efuse_rd_usr_data3_reg_t; - -/** Type of rd_usr_data4 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of BLOCK3 (user). - */ - uint32_t usr_data4:32; - }; - uint32_t val; -} efuse_rd_usr_data4_reg_t; - -/** Type of rd_usr_data5 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of BLOCK3 (user). - */ - uint32_t usr_data5:32; - }; - uint32_t val; -} efuse_rd_usr_data5_reg_t; - -/** Type of rd_usr_data6 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of BLOCK3 (user). - */ - uint32_t usr_data6:32; - }; - uint32_t val; -} efuse_rd_usr_data6_reg_t; - -/** Type of rd_usr_data7 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of BLOCK3 (user). - */ - uint32_t usr_data7:32; - }; - uint32_t val; -} efuse_rd_usr_data7_reg_t; - -/** Type of rd_key0_data0 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY0. - */ - uint32_t key0_data0:32; - }; - uint32_t val; -} efuse_rd_key0_data0_reg_t; - -/** Type of rd_key0_data1 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY0. - */ - uint32_t key0_data1:32; - }; - uint32_t val; -} efuse_rd_key0_data1_reg_t; - -/** Type of rd_key0_data2 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY0. - */ - uint32_t key0_data2:32; - }; - uint32_t val; -} efuse_rd_key0_data2_reg_t; - -/** Type of rd_key0_data3 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY0. - */ - uint32_t key0_data3:32; - }; - uint32_t val; -} efuse_rd_key0_data3_reg_t; - -/** Type of rd_key0_data4 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY0. - */ - uint32_t key0_data4:32; - }; - uint32_t val; -} efuse_rd_key0_data4_reg_t; - -/** Type of rd_key0_data5 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY0. - */ - uint32_t key0_data5:32; - }; - uint32_t val; -} efuse_rd_key0_data5_reg_t; - -/** Type of rd_key0_data6 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY0. - */ - uint32_t key0_data6:32; - }; - uint32_t val; -} efuse_rd_key0_data6_reg_t; - -/** Type of rd_key0_data7 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY0. - */ - uint32_t key0_data7:32; - }; - uint32_t val; -} efuse_rd_key0_data7_reg_t; - -/** Type of rd_key1_data0 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY1. - */ - uint32_t key1_data0:32; - }; - uint32_t val; -} efuse_rd_key1_data0_reg_t; - -/** Type of rd_key1_data1 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY1. - */ - uint32_t key1_data1:32; - }; - uint32_t val; -} efuse_rd_key1_data1_reg_t; - -/** Type of rd_key1_data2 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY1. - */ - uint32_t key1_data2:32; - }; - uint32_t val; -} efuse_rd_key1_data2_reg_t; - -/** Type of rd_key1_data3 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY1. - */ - uint32_t key1_data3:32; - }; - uint32_t val; -} efuse_rd_key1_data3_reg_t; - -/** Type of rd_key1_data4 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY1. - */ - uint32_t key1_data4:32; - }; - uint32_t val; -} efuse_rd_key1_data4_reg_t; - -/** Type of rd_key1_data5 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY1. - */ - uint32_t key1_data5:32; - }; - uint32_t val; -} efuse_rd_key1_data5_reg_t; - -/** Type of rd_key1_data6 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY1. - */ - uint32_t key1_data6:32; - }; - uint32_t val; -} efuse_rd_key1_data6_reg_t; - -/** Type of rd_key1_data7 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY1. - */ - uint32_t key1_data7:32; - }; - uint32_t val; -} efuse_rd_key1_data7_reg_t; - -/** Type of rd_key2_data0 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY2. - */ - uint32_t key2_data0:32; - }; - uint32_t val; -} efuse_rd_key2_data0_reg_t; - -/** Type of rd_key2_data1 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY2. - */ - uint32_t key2_data1:32; - }; - uint32_t val; -} efuse_rd_key2_data1_reg_t; - -/** Type of rd_key2_data2 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY2. - */ - uint32_t key2_data2:32; - }; - uint32_t val; -} efuse_rd_key2_data2_reg_t; - -/** Type of rd_key2_data3 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY2. - */ - uint32_t key2_data3:32; - }; - uint32_t val; -} efuse_rd_key2_data3_reg_t; - -/** Type of rd_key2_data4 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY2. - */ - uint32_t key2_data4:32; - }; - uint32_t val; -} efuse_rd_key2_data4_reg_t; - -/** Type of rd_key2_data5 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY2. - */ - uint32_t key2_data5:32; - }; - uint32_t val; -} efuse_rd_key2_data5_reg_t; - -/** Type of rd_key2_data6 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY2. - */ - uint32_t key2_data6:32; - }; - uint32_t val; -} efuse_rd_key2_data6_reg_t; - -/** Type of rd_key2_data7 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY2. - */ - uint32_t key2_data7:32; - }; - uint32_t val; -} efuse_rd_key2_data7_reg_t; - -/** Type of rd_key3_data0 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY3. - */ - uint32_t key3_data0:32; - }; - uint32_t val; -} efuse_rd_key3_data0_reg_t; - -/** Type of rd_key3_data1 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY3. - */ - uint32_t key3_data1:32; - }; - uint32_t val; -} efuse_rd_key3_data1_reg_t; - -/** Type of rd_key3_data2 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY3. - */ - uint32_t key3_data2:32; - }; - uint32_t val; -} efuse_rd_key3_data2_reg_t; - -/** Type of rd_key3_data3 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY3. - */ - uint32_t key3_data3:32; - }; - uint32_t val; -} efuse_rd_key3_data3_reg_t; - -/** Type of rd_key3_data4 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY3. - */ - uint32_t key3_data4:32; - }; - uint32_t val; -} efuse_rd_key3_data4_reg_t; - -/** Type of rd_key3_data5 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY3. - */ - uint32_t key3_data5:32; - }; - uint32_t val; -} efuse_rd_key3_data5_reg_t; - -/** Type of rd_key3_data6 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY3. - */ - uint32_t key3_data6:32; - }; - uint32_t val; -} efuse_rd_key3_data6_reg_t; - -/** Type of rd_key3_data7 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY3. - */ - uint32_t key3_data7:32; - }; - uint32_t val; -} efuse_rd_key3_data7_reg_t; - -/** Type of rd_key4_data0 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY4. - */ - uint32_t key4_data0:32; - }; - uint32_t val; -} efuse_rd_key4_data0_reg_t; - -/** Type of rd_key4_data1 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY4. - */ - uint32_t key4_data1:32; - }; - uint32_t val; -} efuse_rd_key4_data1_reg_t; - -/** Type of rd_key4_data2 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY4. - */ - uint32_t key4_data2:32; - }; - uint32_t val; -} efuse_rd_key4_data2_reg_t; - -/** Type of rd_key4_data3 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY4. - */ - uint32_t key4_data3:32; - }; - uint32_t val; -} efuse_rd_key4_data3_reg_t; - -/** Type of rd_key4_data4 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY4. - */ - uint32_t key4_data4:32; - }; - uint32_t val; -} efuse_rd_key4_data4_reg_t; - -/** Type of rd_key4_data5 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY4. - */ - uint32_t key4_data5:32; - }; - uint32_t val; -} efuse_rd_key4_data5_reg_t; - -/** Type of rd_key4_data6 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY4. - */ - uint32_t key4_data6:32; - }; - uint32_t val; -} efuse_rd_key4_data6_reg_t; - -/** Type of rd_key4_data7 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY4. - */ - uint32_t key4_data7:32; - }; - uint32_t val; -} efuse_rd_key4_data7_reg_t; - -/** Type of rd_key5_data0 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY5. - */ - uint32_t key5_data0:32; - }; - uint32_t val; -} efuse_rd_key5_data0_reg_t; - -/** Type of rd_key5_data1 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY5. - */ - uint32_t key5_data1:32; - }; - uint32_t val; -} efuse_rd_key5_data1_reg_t; - -/** Type of rd_key5_data2 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY5. - */ - uint32_t key5_data2:32; - }; - uint32_t val; -} efuse_rd_key5_data2_reg_t; - -/** Type of rd_key5_data3 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY5. - */ - uint32_t key5_data3:32; - }; - uint32_t val; -} efuse_rd_key5_data3_reg_t; - -/** Type of rd_key5_data4 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY5. - */ - uint32_t key5_data4:32; - }; - uint32_t val; -} efuse_rd_key5_data4_reg_t; - -/** Type of rd_key5_data5 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY5. - */ - uint32_t key5_data5:32; - }; - uint32_t val; -} efuse_rd_key5_data5_reg_t; - -/** Type of rd_key5_data6 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY5. - */ - uint32_t key5_data6:32; - }; - uint32_t val; -} efuse_rd_key5_data6_reg_t; - -/** Type of rd_key5_data7 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY5. - */ - uint32_t key5_data7:32; - }; - uint32_t val; -} efuse_rd_key5_data7_reg_t; - -/** Type of rd_sys_part2_data0 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_0:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data0_reg_t; - -/** Type of rd_sys_part2_data1 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_1:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data1_reg_t; - -/** Type of rd_sys_part2_data2 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_2:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data2_reg_t; - -/** Type of rd_sys_part2_data3 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_3:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data3_reg_t; - -/** Type of rd_sys_part2_data4 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_4:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data4_reg_t; - -/** Type of rd_sys_part2_data5 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_5:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data5_reg_t; - -/** Type of rd_sys_part2_data6 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_6:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data6_reg_t; - -/** Type of rd_sys_part2_data7 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_7:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data7_reg_t; - -/** Type of rd_repeat_err0 register - * Programming error record register 0 of BLOCK0. - */ -typedef union { - struct { - /** rd_dis_err : RO; bitpos: [6:0]; default: 0; - * If any bit in RD_DIS is 1, then it indicates a programming error. - */ - uint32_t rd_dis_err:7; - /** rpt4_reserved5_err : RO; bitpos: [7]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved5_err:1; - /** dis_icache_err : RO; bitpos: [8]; default: 0; - * If DIS_ICACHE is 1, then it indicates a programming error. - */ - uint32_t dis_icache_err:1; - /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; - * If DIS_USB_JTAG is 1, then it indicates a programming error. - */ - uint32_t dis_usb_jtag_err:1; - /** dis_download_icache_err : RO; bitpos: [10]; default: 0; - * If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error. - */ - uint32_t dis_download_icache_err:1; - /** dis_usb_device_err : RO; bitpos: [11]; default: 0; - * If DIS_USB_DEVICE is 1, then it indicates a programming error. - */ - uint32_t dis_usb_device_err:1; - /** dis_force_download_err : RO; bitpos: [12]; default: 0; - * If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error. - */ - uint32_t dis_force_download_err:1; - /** rpt4_reserved6_err : RO; bitpos: [13]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved6_err:1; - /** dis_twai_err : RO; bitpos: [14]; default: 0; - * If DIS_TWAI is 1, then it indicates a programming error. - */ - uint32_t dis_twai_err:1; - /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; - * If JTAG_SEL_ENABLE is 1, then it indicates a programming error. - */ - uint32_t jtag_sel_enable_err:1; - /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; - * If SOFT_DIS_JTAG is 1, then it indicates a programming error. - */ - uint32_t soft_dis_jtag_err:3; - /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; - * If DIS_PAD_JTAG is 1, then it indicates a programming error. - */ - uint32_t dis_pad_jtag_err:1; - /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; - * If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error. - */ - uint32_t dis_download_manual_encrypt_err:1; - /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; - * If any bit in USB_DREFH is 1, then it indicates a programming error. - */ - uint32_t usb_drefh_err:2; - /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; - * If any bit in USB_DREFL is 1, then it indicates a programming error. - */ - uint32_t usb_drefl_err:2; - /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; - * If USB_EXCHG_PINS is 1, then it indicates a programming error. - */ - uint32_t usb_exchg_pins_err:1; - /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0; - * If VDD_SPI_AS_GPIO is 1, then it indicates a programming error. - */ - uint32_t vdd_spi_as_gpio_err:1; - /** btlc_gpio_enable_err : RO; bitpos: [28:27]; default: 0; - * If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error. - */ - uint32_t btlc_gpio_enable_err:2; - /** powerglitch_en_err : RO; bitpos: [29]; default: 0; - * If POWERGLITCH_EN is 1, then it indicates a programming error. - */ - uint32_t powerglitch_en_err:1; - /** power_glitch_dsense_err : RO; bitpos: [31:30]; default: 0; - * If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error. - */ - uint32_t power_glitch_dsense_err:2; - }; - uint32_t val; -} efuse_rd_repeat_err0_reg_t; - -/** Type of rd_repeat_err1 register - * Programming error record register 1 of BLOCK0. - */ -typedef union { - struct { - /** rpt4_reserved2_err : RO; bitpos: [15:0]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved2_err:16; - /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; - * If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error. - */ - uint32_t wdt_delay_sel_err:2; - /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; - * If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error. - */ - uint32_t spi_boot_crypt_cnt_err:3; - /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; - * If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error. - */ - uint32_t secure_boot_key_revoke0_err:1; - /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; - * If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error. - */ - uint32_t secure_boot_key_revoke1_err:1; - /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; - * If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error. - */ - uint32_t secure_boot_key_revoke2_err:1; - /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; - * If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error. - */ - uint32_t key_purpose_0_err:4; - /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; - * If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error. - */ - uint32_t key_purpose_1_err:4; - }; - uint32_t val; -} efuse_rd_repeat_err1_reg_t; - -/** Type of rd_repeat_err2 register - * Programming error record register 2 of BLOCK0. - */ -typedef union { - struct { - /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; - * If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error. - */ - uint32_t key_purpose_2_err:4; - /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; - * If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error. - */ - uint32_t key_purpose_3_err:4; - /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; - * If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error. - */ - uint32_t key_purpose_4_err:4; - /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; - * If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error. - */ - uint32_t key_purpose_5_err:4; - /** rpt4_reserved3_err : RO; bitpos: [19:16]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved3_err:4; - /** secure_boot_en_err : RO; bitpos: [20]; default: 0; - * If SECURE_BOOT_EN is 1, then it indicates a programming error. - */ - uint32_t secure_boot_en_err:1; - /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; - * If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error. - */ - uint32_t secure_boot_aggressive_revoke_err:1; - /** rpt4_reserved0_err : RO; bitpos: [27:22]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved0_err:6; - /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; - * If any bit in FLASH_TPUM is 1, then it indicates a programming error. - */ - uint32_t flash_tpuw_err:4; - }; - uint32_t val; -} efuse_rd_repeat_err2_reg_t; - -/** Type of rd_repeat_err3 register - * Programming error record register 3 of BLOCK0. - */ -typedef union { - struct { - /** dis_download_mode_err : RO; bitpos: [0]; default: 0; - * If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error. - */ - uint32_t dis_download_mode_err:1; - /** dis_legacy_spi_boot_err : RO; bitpos: [1]; default: 0; - * If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error. - */ - uint32_t dis_legacy_spi_boot_err:1; - /** uart_print_channel_err : RO; bitpos: [2]; default: 0; - * If UART_PRINT_CHANNEL is 1, then it indicates a programming error. - */ - uint32_t uart_print_channel_err:1; - /** rpt4_reserved8_err : RO; bitpos: [3]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved8_err:1; - /** dis_usb_download_mode_err : RO; bitpos: [4]; default: 0; - * If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error. - */ - uint32_t dis_usb_download_mode_err:1; - /** enable_security_download_err : RO; bitpos: [5]; default: 0; - * If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error. - */ - uint32_t enable_security_download_err:1; - /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; - * If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error. - */ - uint32_t uart_print_control_err:2; - /** rpt4_reserved7 : RO; bitpos: [12:8]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved7:5; - /** force_send_resume_err : RO; bitpos: [13]; default: 0; - * If FORCE_SEND_RESUME is 1, then it indicates a programming error. - */ - uint32_t force_send_resume_err:1; - /** secure_version_err : RO; bitpos: [29:14]; default: 0; - * If any bit in SECURE_VERSION is 1, then it indicates a programming error. - */ - uint32_t secure_version_err:16; - /** rpt4_reserved1_err : RO; bitpos: [31:30]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved1_err:2; - }; - uint32_t val; -} efuse_rd_repeat_err3_reg_t; - -/** Type of rd_repeat_err4 register - * Programming error record register 4 of BLOCK0. - */ -typedef union { - struct { - /** rpt4_reserved4_err : RO; bitpos: [23:0]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved4_err:24; - uint32_t reserved_24:8; - }; - uint32_t val; -} efuse_rd_repeat_err4_reg_t; - -/** Type of rd_rs_err0 register - * Programming error record register 0 of BLOCK1-10. - */ -typedef union { - struct { - /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t mac_spi_8m_err_num:3; - /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. - */ - uint32_t mac_spi_8m_fail:1; - /** sys_part1_num : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t sys_part1_num:3; - /** sys_part1_fail : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part1 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. - */ - uint32_t sys_part1_fail:1; - /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t usr_data_err_num:3; - /** usr_data_fail : RO; bitpos: [11]; default: 0; - * 0: Means no failure and that the user data is reliable 1: Means that programming - * user data failed and the number of error bytes is over 6. - */ - uint32_t usr_data_fail:1; - /** key0_err_num : RO; bitpos: [14:12]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key0_err_num:3; - /** key0_fail : RO; bitpos: [15]; default: 0; - * 0: Means no failure and that the data of key$n is reliable 1: Means that - * programming key$n failed and the number of error bytes is over 6. - */ - uint32_t key0_fail:1; - /** key1_err_num : RO; bitpos: [18:16]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key1_err_num:3; - /** key1_fail : RO; bitpos: [19]; default: 0; - * 0: Means no failure and that the data of key$n is reliable 1: Means that - * programming key$n failed and the number of error bytes is over 6. - */ - uint32_t key1_fail:1; - /** key2_err_num : RO; bitpos: [22:20]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key2_err_num:3; - /** key2_fail : RO; bitpos: [23]; default: 0; - * 0: Means no failure and that the data of key$n is reliable 1: Means that - * programming key$n failed and the number of error bytes is over 6. - */ - uint32_t key2_fail:1; - /** key3_err_num : RO; bitpos: [26:24]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key3_err_num:3; - /** key3_fail : RO; bitpos: [27]; default: 0; - * 0: Means no failure and that the data of key$n is reliable 1: Means that - * programming key$n failed and the number of error bytes is over 6. - */ - uint32_t key3_fail:1; - /** key4_err_num : RO; bitpos: [30:28]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key4_err_num:3; - /** key4_fail : RO; bitpos: [31]; default: 0; - * 0: Means no failure and that the data of key$n is reliable 1: Means that - * programming key$n failed and the number of error bytes is over 6. - */ - uint32_t key4_fail:1; - }; - uint32_t val; -} efuse_rd_rs_err0_reg_t; - -/** Type of rd_rs_err1 register - * Programming error record register 1 of BLOCK1-10. - */ -typedef union { - struct { - /** key5_err_num : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key5_err_num:3; - /** key5_fail : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of KEY5 is reliable 1: Means that programming - * user data failed and the number of error bytes is over 6. - */ - uint32_t key5_fail:1; - /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t sys_part2_err_num:3; - /** sys_part2_fail : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part2 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. - */ - uint32_t sys_part2_fail:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} efuse_rd_rs_err1_reg_t; - -/** Type of clk register - * eFuse clcok configuration register. - */ -typedef union { - struct { - /** mem_force_pd : R/W; bitpos: [0]; default: 0; - * Set this bit to force eFuse SRAM into power-saving mode. - */ - uint32_t mem_force_pd:1; - /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; - * Set this bit and force to activate clock signal of eFuse SRAM. - */ - uint32_t mem_clk_force_on:1; - /** mem_force_pu : R/W; bitpos: [2]; default: 0; - * Set this bit to force eFuse SRAM into working mode. - */ - uint32_t mem_force_pu:1; - uint32_t reserved_3:13; - /** clk_en : R/W; bitpos: [16]; default: 0; - * Set this bit and force to enable clock signal of eFuse memory. - */ - uint32_t clk_en:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} efuse_clk_reg_t; - -/** Type of conf register - * eFuse operation mode configuraiton register - */ -typedef union { - struct { - /** op_code : R/W; bitpos: [15:0]; default: 0; - * 0x5A5A: Operate programming command 0x5AA5: Operate read command. - */ - uint32_t op_code:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} efuse_conf_reg_t; - -/** Type of status register - * eFuse status register. - */ -typedef union { - struct { - /** state : RO; bitpos: [3:0]; default: 0; - * Indicates the state of the eFuse state machine. - */ - uint32_t state:4; - /** otp_load_sw : RO; bitpos: [4]; default: 0; - * The value of OTP_LOAD_SW. - */ - uint32_t otp_load_sw:1; - /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; - * The value of OTP_VDDQ_C_SYNC2. - */ - uint32_t otp_vddq_c_sync2:1; - /** otp_strobe_sw : RO; bitpos: [6]; default: 0; - * The value of OTP_STROBE_SW. - */ - uint32_t otp_strobe_sw:1; - /** otp_csb_sw : RO; bitpos: [7]; default: 0; - * The value of OTP_CSB_SW. - */ - uint32_t otp_csb_sw:1; - /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; - * The value of OTP_PGENB_SW. - */ - uint32_t otp_pgenb_sw:1; - /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; - * The value of OTP_VDDQ_IS_SW. - */ - uint32_t otp_vddq_is_sw:1; - /** repeat_err_cnt : RO; bitpos: [17:10]; default: 0; - * Indicates the number of error bits during programming BLOCK0. - */ - uint32_t repeat_err_cnt:8; - uint32_t reserved_18:14; - }; - uint32_t val; -} efuse_status_reg_t; - -/** Type of cmd register - * eFuse command register. - */ -typedef union { - struct { - /** read_cmd : R/W; bitpos: [0]; default: 0; - * Set this bit to send read command. - */ - uint32_t read_cmd:1; - /** pgm_cmd : R/W; bitpos: [1]; default: 0; - * Set this bit to send programming command. - */ - uint32_t pgm_cmd:1; - /** blk_num : R/W; bitpos: [5:2]; default: 0; - * The serial number of the block to be programmed. Value 0-10 corresponds to block - * number 0-10, respectively. - */ - uint32_t blk_num:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} efuse_cmd_reg_t; - -/** Type of int_raw register - * eFuse raw interrupt register. - */ -typedef union { - struct { - /** read_done_int_raw : RO; bitpos: [0]; default: 0; - * The raw bit signal for read_done interrupt. - */ - uint32_t read_done_int_raw:1; - /** pgm_done_int_raw : RO; bitpos: [1]; default: 0; - * The raw bit signal for pgm_done interrupt. - */ - uint32_t pgm_done_int_raw:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_raw_reg_t; - -/** Type of int_st register - * eFuse interrupt status register. - */ -typedef union { - struct { - /** read_done_int_st : RO; bitpos: [0]; default: 0; - * The status signal for read_done interrupt. - */ - uint32_t read_done_int_st:1; - /** pgm_done_int_st : RO; bitpos: [1]; default: 0; - * The status signal for pgm_done interrupt. - */ - uint32_t pgm_done_int_st:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_st_reg_t; - -/** Type of int_ena register - * eFuse interrupt enable register. - */ -typedef union { - struct { - /** read_done_int_ena : R/W; bitpos: [0]; default: 0; - * The enable signal for read_done interrupt. - */ - uint32_t read_done_int_ena:1; - /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; - * The enable signal for pgm_done interrupt. - */ - uint32_t pgm_done_int_ena:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_ena_reg_t; - -/** Type of int_clr register - * eFuse interrupt clear register. - */ -typedef union { - struct { - /** read_done_int_clr : WO; bitpos: [0]; default: 0; - * The clear signal for read_done interrupt. - */ - uint32_t read_done_int_clr:1; - /** pgm_done_int_clr : WO; bitpos: [1]; default: 0; - * The clear signal for pgm_done interrupt. - */ - uint32_t pgm_done_int_clr:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_clr_reg_t; - -/** Type of dac_conf register - * Controls the eFuse programming voltage. - */ -typedef union { - struct { - /** dac_clk_div : R/W; bitpos: [7:0]; default: 28; - * Controls the division factor of the rising clock of the programming voltage. - */ - uint32_t dac_clk_div:8; - /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; - * Don't care. - */ - uint32_t dac_clk_pad_sel:1; - /** dac_num : R/W; bitpos: [16:9]; default: 255; - * Controls the rising period of the programming voltage. - */ - uint32_t dac_num:8; - /** oe_clr : R/W; bitpos: [17]; default: 0; - * Reduces the power supply of the programming voltage. - */ - uint32_t oe_clr:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} efuse_dac_conf_reg_t; - -/** Type of rd_tim_conf register - * Configures read timing parameters. - */ -typedef union { - struct { - uint32_t reserved_0:24; - /** read_init_num : R/W; bitpos: [31:24]; default: 18; - * Configures the initial read time of eFuse. - */ - uint32_t read_init_num:8; - }; - uint32_t val; -} efuse_rd_tim_conf_reg_t; - -/** Type of wr_tim_conf1 register - * Configurarion register 1 of eFuse programming timing parameters. - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** pwr_on_num : R/W; bitpos: [23:8]; default: 10368; - * Configures the power up time for VDDQ. - */ - uint32_t pwr_on_num:16; - uint32_t reserved_24:8; - }; - uint32_t val; -} efuse_wr_tim_conf1_reg_t; - -/** Type of wr_tim_conf2 register - * Configurarion register 2 of eFuse programming timing parameters. - */ -typedef union { - struct { - /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; - * Configures the power outage time for VDDQ. - */ - uint32_t pwr_off_num:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} efuse_wr_tim_conf2_reg_t; - -/** Type of date register - * eFuse version register. - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 33583616; - * Stores eFuse version. - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} efuse_date_reg_t; - - -typedef struct { - volatile efuse_pgm_data0_reg_t pgm_data0; - volatile efuse_pgm_data1_reg_t pgm_data1; - volatile efuse_pgm_data2_reg_t pgm_data2; - volatile efuse_pgm_data3_reg_t pgm_data3; - volatile efuse_pgm_data4_reg_t pgm_data4; - volatile efuse_pgm_data5_reg_t pgm_data5; - volatile efuse_pgm_data6_reg_t pgm_data6; - volatile efuse_pgm_data7_reg_t pgm_data7; - volatile efuse_pgm_check_value0_reg_t pgm_check_value0; - volatile efuse_pgm_check_value1_reg_t pgm_check_value1; - volatile efuse_pgm_check_value2_reg_t pgm_check_value2; - volatile efuse_rd_wr_dis_reg_t rd_wr_dis; - volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; - volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; - volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; - volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; - volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; - volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0; - volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1; - volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2; - volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3; - volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4; - volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5; - volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; - volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; - volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; - volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; - volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; - volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; - volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; - volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; - volatile efuse_rd_usr_data0_reg_t rd_usr_data0; - volatile efuse_rd_usr_data1_reg_t rd_usr_data1; - volatile efuse_rd_usr_data2_reg_t rd_usr_data2; - volatile efuse_rd_usr_data3_reg_t rd_usr_data3; - volatile efuse_rd_usr_data4_reg_t rd_usr_data4; - volatile efuse_rd_usr_data5_reg_t rd_usr_data5; - volatile efuse_rd_usr_data6_reg_t rd_usr_data6; - volatile efuse_rd_usr_data7_reg_t rd_usr_data7; - volatile efuse_rd_key0_data0_reg_t rd_key0_data0; - volatile efuse_rd_key0_data1_reg_t rd_key0_data1; - volatile efuse_rd_key0_data2_reg_t rd_key0_data2; - volatile efuse_rd_key0_data3_reg_t rd_key0_data3; - volatile efuse_rd_key0_data4_reg_t rd_key0_data4; - volatile efuse_rd_key0_data5_reg_t rd_key0_data5; - volatile efuse_rd_key0_data6_reg_t rd_key0_data6; - volatile efuse_rd_key0_data7_reg_t rd_key0_data7; - volatile efuse_rd_key1_data0_reg_t rd_key1_data0; - volatile efuse_rd_key1_data1_reg_t rd_key1_data1; - volatile efuse_rd_key1_data2_reg_t rd_key1_data2; - volatile efuse_rd_key1_data3_reg_t rd_key1_data3; - volatile efuse_rd_key1_data4_reg_t rd_key1_data4; - volatile efuse_rd_key1_data5_reg_t rd_key1_data5; - volatile efuse_rd_key1_data6_reg_t rd_key1_data6; - volatile efuse_rd_key1_data7_reg_t rd_key1_data7; - volatile efuse_rd_key2_data0_reg_t rd_key2_data0; - volatile efuse_rd_key2_data1_reg_t rd_key2_data1; - volatile efuse_rd_key2_data2_reg_t rd_key2_data2; - volatile efuse_rd_key2_data3_reg_t rd_key2_data3; - volatile efuse_rd_key2_data4_reg_t rd_key2_data4; - volatile efuse_rd_key2_data5_reg_t rd_key2_data5; - volatile efuse_rd_key2_data6_reg_t rd_key2_data6; - volatile efuse_rd_key2_data7_reg_t rd_key2_data7; - volatile efuse_rd_key3_data0_reg_t rd_key3_data0; - volatile efuse_rd_key3_data1_reg_t rd_key3_data1; - volatile efuse_rd_key3_data2_reg_t rd_key3_data2; - volatile efuse_rd_key3_data3_reg_t rd_key3_data3; - volatile efuse_rd_key3_data4_reg_t rd_key3_data4; - volatile efuse_rd_key3_data5_reg_t rd_key3_data5; - volatile efuse_rd_key3_data6_reg_t rd_key3_data6; - volatile efuse_rd_key3_data7_reg_t rd_key3_data7; - volatile efuse_rd_key4_data0_reg_t rd_key4_data0; - volatile efuse_rd_key4_data1_reg_t rd_key4_data1; - volatile efuse_rd_key4_data2_reg_t rd_key4_data2; - volatile efuse_rd_key4_data3_reg_t rd_key4_data3; - volatile efuse_rd_key4_data4_reg_t rd_key4_data4; - volatile efuse_rd_key4_data5_reg_t rd_key4_data5; - volatile efuse_rd_key4_data6_reg_t rd_key4_data6; - volatile efuse_rd_key4_data7_reg_t rd_key4_data7; - volatile efuse_rd_key5_data0_reg_t rd_key5_data0; - volatile efuse_rd_key5_data1_reg_t rd_key5_data1; - volatile efuse_rd_key5_data2_reg_t rd_key5_data2; - volatile efuse_rd_key5_data3_reg_t rd_key5_data3; - volatile efuse_rd_key5_data4_reg_t rd_key5_data4; - volatile efuse_rd_key5_data5_reg_t rd_key5_data5; - volatile efuse_rd_key5_data6_reg_t rd_key5_data6; - volatile efuse_rd_key5_data7_reg_t rd_key5_data7; - volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; - volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; - volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; - volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; - volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; - volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; - volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; - volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; - volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; - volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; - volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; - volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; +typedef volatile struct { + uint32_t pgm_data0; + uint32_t pgm_data1; + uint32_t pgm_data2; + uint32_t pgm_data3; + uint32_t pgm_data4; + uint32_t pgm_data5; + uint32_t pgm_data6; + uint32_t pgm_data7; + uint32_t pgm_check_value0; + uint32_t pgm_check_value1; + uint32_t pgm_check_value2; + uint32_t rd_wr_dis; + union { + struct { + uint32_t rd_dis : 7; /*The value of RD_DIS.*/ + uint32_t dis_rtc_ram_boot : 1; /*The value of DIS_RTC_RAM_BOOT.*/ + uint32_t dis_icache : 1; /*The value of DIS_ICACHE.*/ + uint32_t dis_usb_jtag : 1; /*The value of DIS_USB_JTAG.*/ + uint32_t dis_download_icache : 1; /*The value of DIS_DOWNLOAD_ICACHE.*/ + uint32_t dis_usb_device : 1; /*The value of DIS_USB_DEVICE.*/ + uint32_t dis_force_download : 1; /*The value of DIS_FORCE_DOWNLOAD.*/ + uint32_t dis_usb : 1; /*The value of DIS_USB.*/ + uint32_t dis_can : 1; /*The value of DIS_CAN.*/ + uint32_t jtag_sel_enable : 1; /*The value of JTAG_SEL_ENABLE.*/ + uint32_t soft_dis_jtag : 3; /*The value of SOFT_DIS_JTAG.*/ + uint32_t dis_pad_jtag : 1; /*The value of DIS_PAD_JTAG.*/ + uint32_t dis_download_manual_encrypt : 1; /*The value of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/ + uint32_t usb_drefh : 2; /*The value of USB_DREFH.*/ + uint32_t usb_drefl : 2; /*The value of USB_DREFL.*/ + uint32_t usb_exchg_pins : 1; /*The value of USB_EXCHG_PINS.*/ + uint32_t vdd_spi_as_gpio : 1; /*The value of VDD_SPI_AS_GPIO.*/ + uint32_t btlc_gpio_enable : 2; /*The value of BTLC_GPIO_ENABLE.*/ + uint32_t powerglitch_en : 1; /*The value of POWERGLITCH_EN.*/ + uint32_t power_glitch_dsense : 2; /*The value of POWER_GLITCH_DSENSE.*/ + }; + uint32_t val; + } rd_repeat_data0; + union { + struct { + uint32_t rpt4_reserved2 : 16; /*Reserved.*/ + uint32_t wdt_delay_sel : 2; /*The value of WDT_DELAY_SEL.*/ + uint32_t spi_boot_crypt_cnt : 3; /*The value of SPI_BOOT_CRYPT_CNT.*/ + uint32_t secure_boot_key_revoke0 : 1; /*The value of SECURE_BOOT_KEY_REVOKE0.*/ + uint32_t secure_boot_key_revoke1 : 1; /*The value of SECURE_BOOT_KEY_REVOKE1.*/ + uint32_t secure_boot_key_revoke2 : 1; /*The value of SECURE_BOOT_KEY_REVOKE2.*/ + uint32_t key_purpose_0 : 4; /*The value of KEY_PURPOSE_0.*/ + uint32_t key_purpose_1 : 4; /*The value of KEY_PURPOSE_1.*/ + }; + uint32_t val; + } rd_repeat_data1; + union { + struct { + uint32_t key_purpose_2 : 4; /*The value of KEY_PURPOSE_2.*/ + uint32_t key_purpose_3 : 4; /*The value of KEY_PURPOSE_3.*/ + uint32_t key_purpose_4 : 4; /*The value of KEY_PURPOSE_4.*/ + uint32_t key_purpose_5 : 4; /*The value of KEY_PURPOSE_5.*/ + uint32_t rpt4_reserved3 : 4; /*Reserved.*/ + uint32_t secure_boot_en : 1; /*The value of SECURE_BOOT_EN.*/ + uint32_t secure_boot_aggressive_revoke : 1; /*The value of SECURE_BOOT_AGGRESSIVE_REVOKE.*/ + uint32_t rpt4_reserved0 : 6; /*Reserved.*/ + uint32_t flash_tpuw : 4; /*The value of FLASH_TPUW.*/ + }; + uint32_t val; + } rd_repeat_data2; + union { + struct { + uint32_t dis_download_mode : 1; /*The value of DIS_DOWNLOAD_MODE.*/ + uint32_t dis_direct_boot : 1; /*The value of DIS_DIRECT_BOOT.*/ + uint32_t dis_usb_print : 1; /*The value of DIS_USB_PRINT.*/ + uint32_t flash_ecc_mode : 1; /*The value of FLASH_ECC_MODE.*/ + uint32_t dis_usb_download_mode : 1; /*The value of DIS_USB_DOWNLOAD_MODE.*/ + uint32_t enable_security_download : 1; /*The value of ENABLE_SECURITY_DOWNLOAD.*/ + uint32_t uart_print_control : 2; /*The value of UART_PRINT_CONTROL.*/ + uint32_t pin_power_selection : 1; /*The value of PIN_POWER_SELECTION.*/ + uint32_t flash_type : 1; /*The value of FLASH_TYPE.*/ + uint32_t flash_page_size : 2; /*The value of FLASH_PAGE_SIZE.*/ + uint32_t flash_ecc_en : 1; /*The value of FLASH_ECC_EN.*/ + uint32_t force_send_resume : 1; /*The value of FORCE_SEND_RESUME.*/ + uint32_t secure_version : 16; /*The value of SECURE_VERSION.*/ + uint32_t rpt4_reserved1 : 2; /*Reserved.*/ + }; + uint32_t val; + } rd_repeat_data3; + union { + struct { + uint32_t rpt4_reserved4 : 24; /*Reserved.*/ + uint32_t reserved24 : 8; /*Reserved.*/ + }; + uint32_t val; + } rd_repeat_data4; + uint32_t rd_mac_spi_sys_0; + union { + struct { + uint32_t mac_1 : 16; /*Stores the high 16 bits of MAC address.*/ + uint32_t spi_pad_conf_0 : 16; /*Stores the zeroth part of SPI_PAD_CONF.*/ + }; + uint32_t val; + } rd_mac_spi_sys_1; + uint32_t rd_mac_spi_sys_2; + union { + struct { + uint32_t spi_pad_conf_2: 18; /*Stores the second part of SPI_PAD_CONF.*/ + uint32_t wafer_version: 3; + uint32_t pkg_version: 3; + uint32_t sys_data_part0_0: 8; /*Stores the fist 14 bits of the zeroth part of system data.*/ + }; + uint32_t val; + } rd_mac_spi_sys_3; + uint32_t rd_mac_spi_sys_4; + uint32_t rd_mac_spi_sys_5; + uint32_t rd_sys_part1_data0; + uint32_t rd_sys_part1_data1; + uint32_t rd_sys_part1_data2; + uint32_t rd_sys_part1_data3; + uint32_t rd_sys_part1_data4; + uint32_t rd_sys_part1_data5; + uint32_t rd_sys_part1_data6; + uint32_t rd_sys_part1_data7; + uint32_t rd_usr_data0; + uint32_t rd_usr_data1; + uint32_t rd_usr_data2; + uint32_t rd_usr_data3; + uint32_t rd_usr_data4; + uint32_t rd_usr_data5; + uint32_t rd_usr_data6; + uint32_t rd_usr_data7; + uint32_t rd_key0_data0; + uint32_t rd_key0_data1; + uint32_t rd_key0_data2; + uint32_t rd_key0_data3; + uint32_t rd_key0_data4; + uint32_t rd_key0_data5; + uint32_t rd_key0_data6; + uint32_t rd_key0_data7; + uint32_t rd_key1_data0; + uint32_t rd_key1_data1; + uint32_t rd_key1_data2; + uint32_t rd_key1_data3; + uint32_t rd_key1_data4; + uint32_t rd_key1_data5; + uint32_t rd_key1_data6; + uint32_t rd_key1_data7; + uint32_t rd_key2_data0; + uint32_t rd_key2_data1; + uint32_t rd_key2_data2; + uint32_t rd_key2_data3; + uint32_t rd_key2_data4; + uint32_t rd_key2_data5; + uint32_t rd_key2_data6; + uint32_t rd_key2_data7; + uint32_t rd_key3_data0; + uint32_t rd_key3_data1; + uint32_t rd_key3_data2; + uint32_t rd_key3_data3; + uint32_t rd_key3_data4; + uint32_t rd_key3_data5; + uint32_t rd_key3_data6; + uint32_t rd_key3_data7; + uint32_t rd_key4_data0; + uint32_t rd_key4_data1; + uint32_t rd_key4_data2; + uint32_t rd_key4_data3; + uint32_t rd_key4_data4; + uint32_t rd_key4_data5; + uint32_t rd_key4_data6; + uint32_t rd_key4_data7; + uint32_t rd_key5_data0; + uint32_t rd_key5_data1; + uint32_t rd_key5_data2; + uint32_t rd_key5_data3; + uint32_t rd_key5_data4; + uint32_t rd_key5_data5; + uint32_t rd_key5_data6; + uint32_t rd_key5_data7; + uint32_t rd_sys_part2_data0; + uint32_t rd_sys_part2_data1; + uint32_t rd_sys_part2_data2; + uint32_t rd_sys_part2_data3; + uint32_t rd_sys_part2_data4; + uint32_t rd_sys_part2_data5; + uint32_t rd_sys_part2_data6; + uint32_t rd_sys_part2_data7; + union { + struct { + uint32_t rd_dis_err : 7; /*If any bit in RD_DIS is 1, then it indicates a programming error.*/ + uint32_t dis_rtc_ram_boot_err : 1; /*If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.*/ + uint32_t dis_icache_err : 1; /*If DIS_ICACHE is 1, then it indicates a programming error.*/ + uint32_t dis_usb_jtag_err : 1; /*If DIS_USB_JTAG is 1, then it indicates a programming error.*/ + uint32_t dis_download_icache_err : 1; /*If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.*/ + uint32_t dis_usb_device_err : 1; /*If DIS_USB_DEVICE is 1, then it indicates a programming error.*/ + uint32_t dis_force_download_err : 1; /*If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.*/ + uint32_t dis_usb_err : 1; /*If DIS_USB is 1, then it indicates a programming error.*/ + uint32_t dis_can_err : 1; /*If DIS_CAN is 1, then it indicates a programming error.*/ + uint32_t jtag_sel_enable_err : 1; /*If JTAG_SEL_ENABLE is 1, then it indicates a programming error.*/ + uint32_t soft_dis_jtag_err : 3; /*If SOFT_DIS_JTAG is 1, then it indicates a programming error.*/ + uint32_t dis_pad_jtag_err : 1; /*If DIS_PAD_JTAG is 1, then it indicates a programming error.*/ + uint32_t dis_download_manual_encrypt_err: 1; /*If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.*/ + uint32_t usb_drefh_err : 2; /*If any bit in USB_DREFH is 1, then it indicates a programming error.*/ + uint32_t usb_drefl_err : 2; /*If any bit in USB_DREFL is 1, then it indicates a programming error.*/ + uint32_t usb_exchg_pins_err : 1; /*If USB_EXCHG_PINS is 1, then it indicates a programming error.*/ + uint32_t vdd_spi_as_gpio_err : 1; /*If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.*/ + uint32_t btlc_gpio_enable_err : 2; /*If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.*/ + uint32_t powerglitch_en_err : 1; /*If POWERGLITCH_EN is 1, then it indicates a programming error.*/ + uint32_t power_glitch_dsense_err : 2; /*If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.*/ + }; + uint32_t val; + } rd_repeat_err0; + union { + struct { + uint32_t rpt4_reserved2_err : 16; /*Reserved.*/ + uint32_t wdt_delay_sel_err : 2; /*If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.*/ + uint32_t spi_boot_crypt_cnt_err : 3; /*If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.*/ + uint32_t secure_boot_key_revoke0_err : 1; /*If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.*/ + uint32_t secure_boot_key_revoke1_err : 1; /*If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.*/ + uint32_t secure_boot_key_revoke2_err : 1; /*If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.*/ + uint32_t key_purpose_0_err : 4; /*If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.*/ + uint32_t key_purpose_1_err : 4; /*If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.*/ + }; + uint32_t val; + } rd_repeat_err1; + union { + struct { + uint32_t key_purpose_2_err : 4; /*If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.*/ + uint32_t key_purpose_3_err : 4; /*If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.*/ + uint32_t key_purpose_4_err : 4; /*If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.*/ + uint32_t key_purpose_5_err : 4; /*If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.*/ + uint32_t rpt4_reserved3_err : 4; /*Reserved.*/ + uint32_t secure_boot_en_err : 1; /*If SECURE_BOOT_EN is 1, then it indicates a programming error.*/ + uint32_t secure_boot_aggressive_revoke_err: 1; /*If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.*/ + uint32_t rpt4_reserved0_err : 6; /*Reserved.*/ + uint32_t flash_tpuw_err : 4; /*If any bit in FLASH_TPUM is 1, then it indicates a programming error.*/ + }; + uint32_t val; + } rd_repeat_err2; + union { + struct { + uint32_t dis_download_mode_err : 1; /*If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.*/ + uint32_t dis_direct_boot_err : 1; /*If DIS_DIRECT_BOOT is 1, then it indicates a programming error.*/ + uint32_t dis_usb_print_err : 1; /*If DIS_USB_PRINT is 1, then it indicates a programming error.*/ + uint32_t flash_ecc_mode_err : 1; /*If FLASH_ECC_MODE is 1, then it indicates a programming error.*/ + uint32_t dis_usb_download_mode_err : 1; /*If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.*/ + uint32_t enable_security_download_err : 1; /*If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.*/ + uint32_t uart_print_control_err : 2; /*If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.*/ + uint32_t pin_power_selection_err : 1; /*If PIN_POWER_SELECTION is 1, then it indicates a programming error.*/ + uint32_t flash_type_err : 1; /*If FLASH_TYPE is 1, then it indicates a programming error.*/ + uint32_t flash_page_size_err : 2; /*If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.*/ + uint32_t flash_ecc_en_err : 1; /*If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.*/ + uint32_t force_send_resume_err : 1; /*If FORCE_SEND_RESUME is 1, then it indicates a programming error.*/ + uint32_t secure_version_err : 16; /*If any bit in SECURE_VERSION is 1, then it indicates a programming error.*/ + uint32_t rpt4_reserved1_err : 2; /*Reserved.*/ + }; + uint32_t val; + } rd_repeat_err3; uint32_t reserved_18c; - volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; - uint32_t reserved_194[11]; - volatile efuse_rd_rs_err0_reg_t rd_rs_err0; - volatile efuse_rd_rs_err1_reg_t rd_rs_err1; - volatile efuse_clk_reg_t clk; - volatile efuse_conf_reg_t conf; - volatile efuse_status_reg_t status; - volatile efuse_cmd_reg_t cmd; - volatile efuse_int_raw_reg_t int_raw; - volatile efuse_int_st_reg_t int_st; - volatile efuse_int_ena_reg_t int_ena; - volatile efuse_int_clr_reg_t int_clr; - volatile efuse_dac_conf_reg_t dac_conf; - volatile efuse_rd_tim_conf_reg_t rd_tim_conf; - volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; - volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; + union { + struct { + uint32_t rpt4_reserved4_err : 24; /*Reserved.*/ + uint32_t reserved24 : 8; /*Reserved.*/ + }; + uint32_t val; + } rd_repeat_err4; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + union { + struct { + uint32_t mac_spi_8m_err_num : 3; /*The value of this signal means the number of error bytes.*/ + uint32_t mac_spi_8m_fail : 1; /*0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ + uint32_t sys_part1_num : 3; /*The value of this signal means the number of error bytes.*/ + uint32_t sys_part1_fail : 1; /*0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ + uint32_t usr_data_err_num : 3; /*The value of this signal means the number of error bytes.*/ + uint32_t usr_data_fail : 1; /*0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ + uint32_t key0_err_num : 3; /*The value of this signal means the number of error bytes.*/ + uint32_t key0_fail : 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ + uint32_t key1_err_num : 3; /*The value of this signal means the number of error bytes.*/ + uint32_t key1_fail : 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ + uint32_t key2_err_num : 3; /*The value of this signal means the number of error bytes.*/ + uint32_t key2_fail : 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ + uint32_t key3_err_num : 3; /*The value of this signal means the number of error bytes.*/ + uint32_t key3_fail : 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ + uint32_t key4_err_num : 3; /*The value of this signal means the number of error bytes.*/ + uint32_t key4_fail : 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ + }; + uint32_t val; + } rd_rs_err0; + union { + struct { + uint32_t key5_err_num : 3; /*The value of this signal means the number of error bytes.*/ + uint32_t key5_fail : 1; /*0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ + uint32_t sys_part2_err_num : 3; /*The value of this signal means the number of error bytes.*/ + uint32_t sys_part2_fail : 1; /*0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ + uint32_t reserved8 : 24; /*Reserved.*/ + }; + uint32_t val; + } rd_rs_err1; + union { + struct { + uint32_t mem_force_pd : 1; /*Set this bit to force eFuse SRAM into power-saving mode.*/ + uint32_t mem_clk_force_on : 1; /*Set this bit and force to activate clock signal of eFuse SRAM.*/ + uint32_t mem_force_pu : 1; /*Set this bit to force eFuse SRAM into working mode.*/ + uint32_t reserved3 : 13; /*Reserved.*/ + uint32_t clk_en : 1; /*Set this bit and force to enable clock signal of eFuse memory.*/ + uint32_t reserved17 : 15; /*Reserved.*/ + }; + uint32_t val; + } clk; + union { + struct { + uint32_t op_code : 16; /*0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ + uint32_t reserved16 : 16; /*Reserved.*/ + }; + uint32_t val; + } conf; + union { + struct { + uint32_t state : 4; /*Indicates the state of the eFuse state machine.*/ + uint32_t otp_load_sw : 1; /*The value of OTP_LOAD_SW.*/ + uint32_t otp_vddq_c_sync2 : 1; /*The value of OTP_VDDQ_C_SYNC2.*/ + uint32_t otp_strobe_sw : 1; /*The value of OTP_STROBE_SW.*/ + uint32_t otp_csb_sw : 1; /*The value of OTP_CSB_SW.*/ + uint32_t otp_pgenb_sw : 1; /*The value of OTP_PGENB_SW.*/ + uint32_t otp_vddq_is_sw : 1; /*The value of OTP_VDDQ_IS_SW.*/ + uint32_t repeat_err_cnt : 8; /*Indicates the number of error bits during programming BLOCK0.*/ + uint32_t reserved18 : 14; /*Reserved.*/ + }; + uint32_t val; + } status; + union { + struct { + uint32_t read_cmd : 1; /*Set this bit to send read command.*/ + uint32_t pgm_cmd : 1; /*Set this bit to send programming command.*/ + uint32_t blk_num : 4; /*The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively.*/ + uint32_t reserved6 : 26; /*Reserved.*/ + }; + uint32_t val; + } cmd; + union { + struct { + uint32_t read_done_int_raw : 1; /*The raw bit signal for read_done interrupt.*/ + uint32_t pgm_done_int_raw : 1; /*The raw bit signal for pgm_done interrupt.*/ + uint32_t reserved2 : 30; /*Reserved.*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t read_done_int_st : 1; /*The status signal for read_done interrupt.*/ + uint32_t pgm_done_int_st : 1; /*The status signal for pgm_done interrupt.*/ + uint32_t reserved2 : 30; /*Reserved.*/ + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t read_done_int_ena : 1; /*The enable signal for read_done interrupt.*/ + uint32_t pgm_done_int_ena : 1; /*The enable signal for pgm_done interrupt.*/ + uint32_t reserved2 : 30; /*Reserved.*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t read_done_int_clr : 1; /*The clear signal for read_done interrupt.*/ + uint32_t pgm_done_int_clr : 1; /*The clear signal for pgm_done interrupt.*/ + uint32_t reserved2 : 30; /*Reserved.*/ + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t dac_clk_div : 8; /*Controls the division factor of the rising clock of the programming voltage.*/ + uint32_t dac_clk_pad_sel : 1; /*Don't care.*/ + uint32_t dac_num : 8; /*Controls the rising period of the programming voltage.*/ + uint32_t oe_clr : 1; /*Reduces the power supply of the programming voltage.*/ + uint32_t reserved18 : 14; /*Reserved.*/ + }; + uint32_t val; + } dac_conf; + union { + struct { + uint32_t reserved0 : 24; /*Reserved.*/ + uint32_t read_init_num : 8; /*Configures the initial read time of eFuse.*/ + }; + uint32_t val; + } rd_tim_conf; + union { + struct { + uint32_t reserved0 : 8; /*Reserved.*/ + uint32_t pwr_on_num : 16; /*Configures the power up time for VDDQ.*/ + uint32_t reserved24 : 8; /*Reserved.*/ + }; + uint32_t val; + } wr_tim_conf1; + union { + struct { + uint32_t pwr_off_num : 16; /*Configures the power outage time for VDDQ.*/ + uint32_t reserved16 : 16; /*Reserved.*/ + }; + uint32_t val; + } wr_tim_conf2; uint32_t reserved_1f8; - volatile efuse_date_reg_t date; + union { + struct { + uint32_t date : 28; /*Stores eFuse version.*/ + uint32_t reserved28 : 4; /*Reserved.*/ + }; + uint32_t val; + } date; } efuse_dev_t; - - -#ifndef __cplusplus -_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); -#endif - +extern efuse_dev_t EFUSE; #ifdef __cplusplus } #endif + + + +#endif /*_SOC_EFUSE_STRUCT_H_ */