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https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
spi_slave: fix io re-config issue
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parent
30a46d0754
commit
cdd610cadc
@ -50,6 +50,7 @@ static const char *SPI_TAG = "spi_slave";
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typedef struct {
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typedef struct {
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int id;
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int id;
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spi_bus_config_t bus_config;
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spi_slave_interface_config_t cfg;
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spi_slave_interface_config_t cfg;
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intr_handle_t intr;
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intr_handle_t intr;
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spi_slave_hal_context_t hal;
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spi_slave_hal_context_t hal;
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@ -156,6 +157,7 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b
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}
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}
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memset(spihost[host], 0, sizeof(spi_slave_t));
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memset(spihost[host], 0, sizeof(spi_slave_t));
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memcpy(&spihost[host]->cfg, slave_config, sizeof(spi_slave_interface_config_t));
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memcpy(&spihost[host]->cfg, slave_config, sizeof(spi_slave_interface_config_t));
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memcpy(&spihost[host]->bus_config, bus_config, sizeof(spi_bus_config_t));
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spihost[host]->id = host;
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spihost[host]->id = host;
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bool use_dma = (dma_chan != SPI_DMA_DISABLED);
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bool use_dma = (dma_chan != SPI_DMA_DISABLED);
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@ -301,6 +303,7 @@ esp_err_t spi_slave_free(spi_host_device_t host)
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if (spihost[host]->dma_enabled) {
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if (spihost[host]->dma_enabled) {
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spicommon_dma_chan_free(host);
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spicommon_dma_chan_free(host);
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}
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}
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spicommon_bus_free_io_cfg(&spihost[host]->bus_config);
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free(spihost[host]->hal.dmadesc_tx);
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free(spihost[host]->hal.dmadesc_tx);
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free(spihost[host]->hal.dmadesc_rx);
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free(spihost[host]->hal.dmadesc_rx);
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esp_intr_free(spihost[host]->intr);
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esp_intr_free(spihost[host]->intr);
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@ -1,5 +1,5 @@
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/*
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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@ -8,7 +8,7 @@
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#include "unity_test_utils.h"
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#include "unity_test_utils.h"
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#include "esp_heap_caps.h"
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#include "esp_heap_caps.h"
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#define TEST_MEMORY_LEAK_THRESHOLD (100)
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#define TEST_MEMORY_LEAK_THRESHOLD (120)
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static size_t before_free_8bit;
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static size_t before_free_8bit;
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static size_t before_free_32bit;
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static size_t before_free_32bit;
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@ -736,14 +736,8 @@ TEST_CASE("test_slave_isr_pin_to_core","[spi]")
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slave_expect = 0;
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slave_expect = 0;
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for (int i = 0; i < TEST_ISR_CNT; i++) {
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for (int i = 0; i < TEST_ISR_CNT; i++) {
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TEST_ESP_OK(spi_slave_initialize(TEST_SPI_HOST, &buscfg, &slvcfg, SPI_DMA_CH_AUTO));
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TEST_ESP_OK(spi_slave_initialize(TEST_SPI_HOST, &buscfg, &slvcfg, SPI_DMA_CH_AUTO));
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TEST_ESP_OK(spi_slave_queue_trans(TEST_SPI_HOST, &trans_cfg, portMAX_DELAY));
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TEST_ESP_OK(spi_slave_queue_trans(TEST_SPI_HOST, &trans_cfg, portMAX_DELAY));
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// This two delay used for hardware to activate a interrupt after invoke
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vTaskDelay(1); // Waiting ISR on core 1 to be done.
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vTaskDelay(1);
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// to invoke a trans_done intr for spi slave without a master
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spi_ll_set_int_stat(SPI_LL_GET_HW(TEST_SPI_HOST));
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vTaskDelay(1);
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TEST_ESP_OK(spi_slave_free(TEST_SPI_HOST));
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TEST_ESP_OK(spi_slave_free(TEST_SPI_HOST));
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}
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}
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printf("Test Slave ISR Assign CPU1: %d : %ld\n", TEST_ISR_CNT, slave_expect);
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printf("Test Slave ISR Assign CPU1: %d : %ld\n", TEST_ISR_CNT, slave_expect);
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