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Renamed BAH

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This commit is contained in:
zwl 2022-12-13 18:02:19 +08:00
parent a83ee7d406
commit cdcdc50cfe
4 changed files with 24 additions and 24 deletions
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4
components/bt/controller/esp32h4/bt.c
View File

@ -235,8 +235,8 @@ struct ext_funcs_t ext_funcs_ro = {
static void IRAM_ATTR esp_reset_rpa_moudle(void)
{
DPORT_SET_PERI_REG_MASK(SYSTEM_MODEM_RST_EN_REG, SYSTEM_BLE_SEC_AAR_RST);
DPORT_CLEAR_PERI_REG_MASK(SYSTEM_MODEM_RST_EN_REG, SYSTEM_BLE_SEC_AAR_RST);
DPORT_SET_PERI_REG_MASK(SYSTEM_MODEM_RST_EN_REG, SYSTEM_BLE_SEC_BAH_RST);
DPORT_CLEAR_PERI_REG_MASK(SYSTEM_MODEM_RST_EN_REG, SYSTEM_BLE_SEC_BAH_RST);
}

4
components/hal/esp32h4/include/hal/clk_gate_ll.h
View File

@ -68,7 +68,7 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
case PERIPH_ETM_MODULE:
return SYSTEM_ETM_CLK_EN;
case PERIPH_MODEM_RPA_MODULE:
return SYSTEM_BLE_SEC_AAR_CLK_EN;
return SYSTEM_BLE_SEC_BAH_CLK_EN;
default:
return 0;
}
@ -145,7 +145,7 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
case PERIPH_ETM_MODULE:
return SYSTEM_ETM_RST;
case PERIPH_MODEM_RPA_MODULE:
return SYSTEM_BLE_SEC_AAR_RST;
return SYSTEM_BLE_SEC_BAH_RST;
default:
return 0;
}

20
components/soc/esp32h4/include/rev1/soc/clkrst_reg.h
View File

@ -171,12 +171,12 @@ extern "C" {
#define SYSTEM_BLE_SEC_CLK_EN_M (BIT(17))
#define SYSTEM_BLE_SEC_CLK_EN_V 0x1
#define SYSTEM_BLE_SEC_CLK_EN_S 17
/* SYSTEM_BLE_SEC_AAR_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
/* SYSTEM_BLE_SEC_BAH_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_BLE_SEC_AAR_CLK_EN (BIT(16))
#define SYSTEM_BLE_SEC_AAR_CLK_EN_M (BIT(16))
#define SYSTEM_BLE_SEC_AAR_CLK_EN_V 0x1
#define SYSTEM_BLE_SEC_AAR_CLK_EN_S 16
#define SYSTEM_BLE_SEC_BAH_CLK_EN (BIT(16))
#define SYSTEM_BLE_SEC_BAH_CLK_EN_M (BIT(16))
#define SYSTEM_BLE_SEC_BAH_CLK_EN_V 0x1
#define SYSTEM_BLE_SEC_BAH_CLK_EN_S 16
/* SYSTEM_BLE_SEC_CCM_CLK_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_BLE_SEC_CCM_CLK_EN (BIT(15))
@ -293,12 +293,12 @@ extern "C" {
#define SYSTEM_BLE_SEC_RST_M (BIT(18))
#define SYSTEM_BLE_SEC_RST_V 0x1
#define SYSTEM_BLE_SEC_RST_S 18
/* SYSTEM_BLE_SEC_AAR_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
/* SYSTEM_BLE_SEC_BAH_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_BLE_SEC_AAR_RST (BIT(17))
#define SYSTEM_BLE_SEC_AAR_RST_M (BIT(17))
#define SYSTEM_BLE_SEC_AAR_RST_V 0x1
#define SYSTEM_BLE_SEC_AAR_RST_S 17
#define SYSTEM_BLE_SEC_BAH_RST (BIT(17))
#define SYSTEM_BLE_SEC_BAH_RST_M (BIT(17))
#define SYSTEM_BLE_SEC_BAH_RST_V 0x1
#define SYSTEM_BLE_SEC_BAH_RST_S 17
/* SYSTEM_BLE_SEC_CCM_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_BLE_SEC_CCM_RST (BIT(16))

20
components/soc/esp32h4/include/rev2/soc/clkrst_reg.h
View File

@ -327,13 +327,13 @@ extern "C" {
#define SYSTEM_BLE_SEC_CCM_CLK_EN_M (SYSTEM_BLE_SEC_CCM_CLK_EN_V << SYSTEM_BLE_SEC_CCM_CLK_EN_S)
#define SYSTEM_BLE_SEC_CCM_CLK_EN_V 0x00000001U
#define SYSTEM_BLE_SEC_CCM_CLK_EN_S 15
/** SYSTEM_BLE_SEC_AAR_CLK_EN : R/W; bitpos: [16]; default: 0;
/** SYSTEM_BLE_SEC_BAH_CLK_EN : R/W; bitpos: [16]; default: 0;
* Need add description
*/
#define SYSTEM_BLE_SEC_AAR_CLK_EN (BIT(16))
#define SYSTEM_BLE_SEC_AAR_CLK_EN_M (SYSTEM_BLE_SEC_AAR_CLK_EN_V << SYSTEM_BLE_SEC_AAR_CLK_EN_S)
#define SYSTEM_BLE_SEC_AAR_CLK_EN_V 0x00000001U
#define SYSTEM_BLE_SEC_AAR_CLK_EN_S 16
#define SYSTEM_BLE_SEC_BAH_CLK_EN (BIT(16))
#define SYSTEM_BLE_SEC_BAH_CLK_EN_M (SYSTEM_BLE_SEC_BAH_CLK_EN_V << SYSTEM_BLE_SEC_BAH_CLK_EN_S)
#define SYSTEM_BLE_SEC_BAH_CLK_EN_V 0x00000001U
#define SYSTEM_BLE_SEC_BAH_CLK_EN_S 16
/** SYSTEM_BLE_SEC_CLK_EN : R/W; bitpos: [17]; default: 0;
* Need add description
*/
@ -500,13 +500,13 @@ extern "C" {
#define SYSTEM_BLE_SEC_CCM_RST_M (SYSTEM_BLE_SEC_CCM_RST_V << SYSTEM_BLE_SEC_CCM_RST_S)
#define SYSTEM_BLE_SEC_CCM_RST_V 0x00000001U
#define SYSTEM_BLE_SEC_CCM_RST_S 16
/** SYSTEM_BLE_SEC_AAR_RST : R/W; bitpos: [17]; default: 0;
/** SYSTEM_BLE_SEC_BAH_RST : R/W; bitpos: [17]; default: 0;
* Need add description
*/
#define SYSTEM_BLE_SEC_AAR_RST (BIT(17))
#define SYSTEM_BLE_SEC_AAR_RST_M (SYSTEM_BLE_SEC_AAR_RST_V << SYSTEM_BLE_SEC_AAR_RST_S)
#define SYSTEM_BLE_SEC_AAR_RST_V 0x00000001U
#define SYSTEM_BLE_SEC_AAR_RST_S 17
#define SYSTEM_BLE_SEC_BAH_RST (BIT(17))
#define SYSTEM_BLE_SEC_BAH_RST_M (SYSTEM_BLE_SEC_BAH_RST_V << SYSTEM_BLE_SEC_BAH_RST_S)
#define SYSTEM_BLE_SEC_BAH_RST_V 0x00000001U
#define SYSTEM_BLE_SEC_BAH_RST_S 17
/** SYSTEM_BLE_SEC_RST : R/W; bitpos: [18]; default: 0;
* Need add description
*/