alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-09-19 14:26:01 -04:00
Code Issues Actions 3 Packages Projects Releases Wiki Activity

feat(uart): support uart on ESP32C61

Browse Source
This commit is contained in:
gaoxu 2024-08-05 15:06:51 +08:00
parent 7e2bc478d7
commit cd9d8bf2e9
11 changed files with 83 additions and 81 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
components/esp_driver_uart/test_apps/.build-test-rules.yml
View File

@ -3,9 +3,6 @@
components/esp_driver_uart/test_apps/rs485: components/esp_driver_uart/test_apps/rs485:
disable: disable:
- if: SOC_UART_SUPPORTED != 1 - if: SOC_UART_SUPPORTED != 1
- if: IDF_TARGET in ["esp32c61"]
temporary: true
reason: IDF-9320 uart driver
disable_test: disable_test:
- if: IDF_TARGET != "esp32" - if: IDF_TARGET != "esp32"
temporary: true temporary: true
@ -17,9 +14,6 @@ components/esp_driver_uart/test_apps/rs485:
components/esp_driver_uart/test_apps/uart: components/esp_driver_uart/test_apps/uart:
disable: disable:
- if: SOC_UART_SUPPORTED != 1 - if: SOC_UART_SUPPORTED != 1
- if: IDF_TARGET in ["esp32c61"]
temporary: true
reason: IDF-9320 uart driver
disable_test: disable_test:
- if: IDF_TARGET == "esp32p4" - if: IDF_TARGET == "esp32p4"
temporary: true temporary: true

4
components/esp_driver_uart/test_apps/rs485/README.md
View File

@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

4
components/esp_driver_uart/test_apps/uart/README.md
View File

@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

75
components/hal/esp32c61/include/hal/uart_ll.h
View File

@ -19,8 +19,7 @@
#include "soc/pcr_struct.h" #include "soc/pcr_struct.h"
#include "soc/pcr_reg.h" #include "soc/pcr_reg.h"
#include "esp_attr.h" #include "esp_attr.h"
#include "hal/assert.h"
// TODO: [ESP32C61] IDF-9320, inherit from c6
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -29,7 +28,7 @@ extern "C" {
// The default fifo depth // The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN) #define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num // Get UART hardware instance with giving uart num
#define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (&UART1)) #define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (((num) == UART_NUM_1) ? (&UART1) : (&UART2)))
#define UART_LL_MIN_WAKEUP_THRESH (2) #define UART_LL_MIN_WAKEUP_THRESH (2)
#define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask #define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask
@ -40,24 +39,30 @@ extern "C" {
#define UART_LL_PCR_REG_U32_SET(hw, reg_suffix, field_suffix, val) \ #define UART_LL_PCR_REG_U32_SET(hw, reg_suffix, field_suffix, val) \
if ((hw) == &UART0) { \ if ((hw) == &UART0) { \
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart0_##reg_suffix, uart0_##field_suffix, (val)) \ HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart0_##reg_suffix, uart0_##field_suffix, (val)) \
} else { \ } else if ((hw) == &UART1) { \
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart1_##reg_suffix, uart1_##field_suffix, (val)) \ HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart1_##reg_suffix, uart1_##field_suffix, (val)) \
} else { \
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart2_##reg_suffix, uart2_##field_suffix, (val)) \
} }
#define UART_LL_PCR_REG_U32_GET(hw, reg_suffix, field_suffix) \ #define UART_LL_PCR_REG_U32_GET(hw, reg_suffix, field_suffix) \
(((hw) == &UART0) ? \ (((hw) == &UART0) ? HAL_FORCE_READ_U32_REG_FIELD(PCR.uart0_##reg_suffix, uart0_##field_suffix) : \
HAL_FORCE_READ_U32_REG_FIELD(PCR.uart0_##reg_suffix, uart0_##field_suffix) : \ ((hw) == &UART1) ? HAL_FORCE_READ_U32_REG_FIELD(PCR.uart1_##reg_suffix, uart1_##field_suffix) : \
HAL_FORCE_READ_U32_REG_FIELD(PCR.uart1_##reg_suffix, uart1_##field_suffix)) HAL_FORCE_READ_U32_REG_FIELD(PCR.uart2_##reg_suffix, uart2_##field_suffix))
#define UART_LL_PCR_REG_SET(hw, reg_suffix, field_suffix, val) \ #define UART_LL_PCR_REG_SET(hw, reg_suffix, field_suffix, val) \
if ((hw) == &UART0) { \ if ((hw) == &UART0) { \
PCR.uart0_##reg_suffix.uart0_##field_suffix = (val); \ PCR.uart0_##reg_suffix.uart0_##field_suffix = (val); \
} else { \ } else if ((hw) == &UART1) { \
PCR.uart1_##reg_suffix.uart1_##field_suffix = (val); \ PCR.uart1_##reg_suffix.uart1_##field_suffix = (val); \
} else { \
PCR.uart2_##reg_suffix.uart2_##field_suffix = (val); \
} }
#define UART_LL_PCR_REG_GET(hw, reg_suffix, field_suffix) \ #define UART_LL_PCR_REG_GET(hw, reg_suffix, field_suffix) \
(((hw) == &UART0) ? PCR.uart0_##reg_suffix.uart0_##field_suffix : PCR.uart1_##reg_suffix.uart1_##field_suffix) (((hw) == &UART0) ? PCR.uart0_##reg_suffix.uart0_##field_suffix : \
((hw) == &UART1) ? PCR.uart1_##reg_suffix.uart1_##field_suffix : \
PCR.uart2_##reg_suffix.uart2_##field_suffix)
// Define UART interrupts // Define UART interrupts
typedef enum { typedef enum {
@ -92,14 +97,18 @@ typedef enum {
*/ */
FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num) FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
{ {
uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG : switch (uart_num) {
(uart_num == 1) ? PCR_UART1_CONF_REG : 0); case 0:
uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN : return PCR.uart0_conf.uart0_clk_en && !PCR.uart0_conf.uart0_rst_en;
(uart_num == 1) ? PCR_UART1_RST_EN : 0); case 1: // UART_1
uint32_t uart_en_bit = ((uart_num == 0) ? PCR_UART0_CLK_EN : return PCR.uart1_conf.uart1_clk_en && !PCR.uart1_conf.uart1_rst_en;
(uart_num == 1) ? PCR_UART1_CLK_EN : 0); case 2: // UART_2
return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 && return PCR.uart2_conf.uart2_clk_en && !PCR.uart2_conf.uart2_rst_en;
REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0; default:
HAL_ASSERT(false);
return false;
}
} }
/** /**
@ -116,6 +125,9 @@ static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
case 1: case 1:
PCR.uart1_conf.uart1_clk_en = enable; PCR.uart1_conf.uart1_clk_en = enable;
break; break;
case 2:
PCR.uart2_conf.uart2_clk_en = enable;
break;
default: default:
abort(); abort();
break; break;
@ -137,6 +149,10 @@ static inline void uart_ll_reset_register(uart_port_t uart_num)
PCR.uart1_conf.uart1_rst_en = 1; PCR.uart1_conf.uart1_rst_en = 1;
PCR.uart1_conf.uart1_rst_en = 0; PCR.uart1_conf.uart1_rst_en = 0;
break; break;
case 2:
PCR.uart2_conf.uart2_rst_en = 1;
PCR.uart2_conf.uart2_rst_en = 0;
break;
default: default:
abort(); abort();
break; break;
@ -191,20 +207,22 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
*/ */
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk) FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
{ {
uint32_t sel_value = 0;
switch (source_clk) { switch (source_clk) {
case UART_SCLK_PLL_F80M: case UART_SCLK_XTAL:
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 1); sel_value = 0;
break; break;
case UART_SCLK_RTC: case UART_SCLK_RTC:
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 2); sel_value = 1;
break; break;
case UART_SCLK_XTAL: case UART_SCLK_PLL_F80M:
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 3); sel_value = 2;
break; break;
default: default:
// Invalid UART clock source // Invalid UART clock source
abort(); abort();
} }
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, sel_value);
} }
/** /**
@ -219,14 +237,14 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
{ {
switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) { switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) {
default: default:
case 1: case 0:
*source_clk = (soc_module_clk_t)UART_SCLK_PLL_F80M; *source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
break; break;
case 2: case 1:
*source_clk = (soc_module_clk_t)UART_SCLK_RTC; *source_clk = (soc_module_clk_t)UART_SCLK_RTC;
break; break;
case 3: case 2:
*source_clk = (soc_module_clk_t)UART_SCLK_XTAL; *source_clk = (soc_module_clk_t)UART_SCLK_PLL_F80M;
break; break;
} }
} }
@ -270,7 +288,8 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr
{ {
typeof(hw->clkdiv_sync) div_reg; typeof(hw->clkdiv_sync) div_reg;
div_reg.val = hw->clkdiv_sync.val; div_reg.val = hw->clkdiv_sync.val;
return ((sclk_freq << 4)) / (((div_reg.clkdiv_int << 4) | div_reg.clkdiv_frag) * (UART_LL_PCR_REG_U32_GET(hw, sclk_conf, sclk_div_num) + 1)); int sclk_div = UART_LL_PCR_REG_U32_GET(hw, sclk_conf, sclk_div_num) + 1;
return ((sclk_freq << 4)) / (((div_reg.clkdiv_int << 4) | div_reg.clkdiv_frag) * sclk_div);
} }
/** /**

4
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
View File

@ -495,10 +495,6 @@ config SOC_UART_FIFO_LEN
int int
default 128 default 128
config SOC_LP_UART_FIFO_LEN
int
default 16
config SOC_UART_BITRATE_MAX config SOC_UART_BITRATE_MAX
int int
default 5000000 default 5000000

5
components/soc/esp32c61/include/soc/soc_caps.h
View File

@ -19,7 +19,7 @@
/*-------------------------- COMMON CAPS ---------------------------------------*/ /*-------------------------- COMMON CAPS ---------------------------------------*/
// \#define SOC_ADC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9302, IDF-9303, IDF-9304 // \#define SOC_ADC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9302, IDF-9303, IDF-9304
// \#define SOC_DEDICATED_GPIO_SUPPORTED 1 //TODO: [ESP32C61] IDF-9321 // \#define SOC_DEDICATED_GPIO_SUPPORTED 1 //TODO: [ESP32C61] IDF-9321
#define SOC_UART_SUPPORTED 1 //TODO: [ESP32C61] IDF-9320 #define SOC_UART_SUPPORTED 1
// \#define SOC_GDMA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9310, IDF-9311 // \#define SOC_GDMA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9310, IDF-9311
// \#define SOC_AHB_GDMA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9310, IDF-9311 // \#define SOC_AHB_GDMA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9310, IDF-9311
#define SOC_GPTIMER_SUPPORTED 1 #define SOC_GPTIMER_SUPPORTED 1
@ -70,7 +70,6 @@
// \#define SOC_SDIO_SLAVE_SUPPORTED 0 // \#define SOC_SDIO_SLAVE_SUPPORTED 0
// \#define SOC_PAU_SUPPORTED 0 // \#define SOC_PAU_SUPPORTED 0
// \#define SOC_LP_I2C_SUPPORTED 0 //TODO: [ESP32C61] IDF-9330, IDF-9337 // \#define SOC_LP_I2C_SUPPORTED 0 //TODO: [ESP32C61] IDF-9330, IDF-9337
// \#define SOC_ULP_LP_UART_SUPPORTED 0 //TODO: [ESP32C61] IDF-9329, IDF-9341
// \#define SOC_PM_SUPPORTED 1 // \#define SOC_PM_SUPPORTED 1
/*-------------------------- XTAL CAPS ---------------------------------------*/ /*-------------------------- XTAL CAPS ---------------------------------------*/
@ -422,9 +421,7 @@
// ESP32-C61 has 3 UARTs (3 HP UART) // ESP32-C61 has 3 UARTs (3 HP UART)
#define SOC_UART_NUM (3) #define SOC_UART_NUM (3)
#define SOC_UART_HP_NUM (3) #define SOC_UART_HP_NUM (3)
// \#define SOC_UART_LP_NUM (1U) //TODO: IDF-9341
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */ #define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */

12
components/soc/esp32c61/include/soc/uart_channel.h
View File

@ -9,10 +9,10 @@
#pragma once #pragma once
//UART channels //UART channels
#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_0 #define UART_GPIO11_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 16 #define UART_NUM_0_TXD_DIRECT_GPIO_NUM 11
#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_0 #define UART_GPIO10_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 17 #define UART_NUM_0_RXD_DIRECT_GPIO_NUM 10
#define UART_TXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL #define UART_TXD_GPIO11_DIRECT_CHANNEL UART_GPIO11_DIRECT_CHANNEL
#define UART_RXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL #define UART_RXD_GPIO10_DIRECT_CHANNEL UART_GPIO10_DIRECT_CHANNEL

18
components/soc/esp32c61/include/soc/uart_pins.h
View File

@ -22,10 +22,10 @@
#define U1RTS_GPIO_NUM (-1) #define U1RTS_GPIO_NUM (-1)
#define U1CTS_GPIO_NUM (-1) #define U1CTS_GPIO_NUM (-1)
#define LP_U0RXD_GPIO_NUM 4 #define U2RXD_GPIO_NUM (-1)
#define LP_U0TXD_GPIO_NUM 5 #define U2TXD_GPIO_NUM (-1)
#define LP_U0RTS_GPIO_NUM 2 #define U2RTS_GPIO_NUM (-1)
#define LP_U0CTS_GPIO_NUM 3 #define U2CTS_GPIO_NUM (-1)
/* The following defines are necessary for reconfiguring the UART /* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */ * to use IOMUX, at runtime. */
@ -39,8 +39,8 @@
#define U1RXD_MUX_FUNC (-1) #define U1RXD_MUX_FUNC (-1)
#define U1RTS_MUX_FUNC (-1) #define U1RTS_MUX_FUNC (-1)
#define U1CTS_MUX_FUNC (-1) #define U1CTS_MUX_FUNC (-1)
/* Same goes for UART2 */
#define LP_U0TXD_MUX_FUNC (1) #define U2TXD_MUX_FUNC (-1)
#define LP_U0RXD_MUX_FUNC (1) #define U2RXD_MUX_FUNC (-1)
#define LP_U0RTS_MUX_FUNC (1) #define U2RTS_MUX_FUNC (-1)
#define LP_U0CTS_MUX_FUNC (1) #define U2CTS_MUX_FUNC (-1)

5
components/soc/esp32c61/include/soc/uart_struct.h
View File

@ -16,12 +16,11 @@ extern "C" {
*/ */
typedef union { typedef union {
struct { struct {
/** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; /** rxfifo_rd_byte : RO; bitpos: [31:0]; default: 0;
* Represents the data UART $n read from FIFO.\\ * Represents the data UART $n read from FIFO.\\
* Measurement unit: byte. * Measurement unit: byte.
*/ */
uint32_t rxfifo_rd_byte:8; uint32_t rxfifo_rd_byte:32;
uint32_t reserved_8:24;
}; };
uint32_t val; uint32_t val;
} uart_fifo_reg_t; } uart_fifo_reg_t;

30
components/soc/esp32c61/uart_periph.c
View File

@ -75,38 +75,36 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
}, },
.irq = ETS_UART1_INTR_SOURCE, .irq = ETS_UART1_INTR_SOURCE,
}, },
#if 0 //TODO: [ESP32C61] IDF-9329, IDF-9341 { // HP UART2
{ // LP UART0
.pins = { .pins = {
[SOC_UART_TX_PIN_IDX] = { [SOC_UART_TX_PIN_IDX] = {
.default_gpio = LP_U0TXD_GPIO_NUM, .default_gpio = U2TXD_GPIO_NUM,
.iomux_func = LP_U0TXD_MUX_FUNC, .iomux_func = U2TXD_MUX_FUNC,
.input = 0, .input = 0,
.signal = UINT8_MAX, // Signal not available in signal map .signal = U2TXD_OUT_IDX,
}, },
[SOC_UART_RX_PIN_IDX] = { [SOC_UART_RX_PIN_IDX] = {
.default_gpio = LP_U0RXD_GPIO_NUM, .default_gpio = U2RXD_GPIO_NUM,
.iomux_func = LP_U0RXD_MUX_FUNC, .iomux_func = U2RXD_MUX_FUNC,
.input = 1, .input = 1,
.signal = UINT8_MAX, // Signal not available in signal map .signal = U2RXD_IN_IDX,
}, },
[SOC_UART_RTS_PIN_IDX] = { [SOC_UART_RTS_PIN_IDX] = {
.default_gpio = LP_U0RTS_GPIO_NUM, .default_gpio = U2RTS_GPIO_NUM,
.iomux_func = LP_U0RTS_MUX_FUNC, .iomux_func = U2RTS_MUX_FUNC,
.input = 0, .input = 0,
.signal = UINT8_MAX, // Signal not available in signal map .signal = U2RTS_OUT_IDX,
}, },
[SOC_UART_CTS_PIN_IDX] = { [SOC_UART_CTS_PIN_IDX] = {
.default_gpio = LP_U0CTS_GPIO_NUM, .default_gpio = U2CTS_GPIO_NUM,
.iomux_func = LP_U0CTS_MUX_FUNC, .iomux_func = U2CTS_MUX_FUNC,
.input = 1, .input = 1,
.signal = UINT8_MAX, // Signal not available in signal map .signal = U2CTS_IN_IDX,
}, },
}, },
.irq = ETS_LP_UART_INTR_SOURCE, .irq = ETS_UART2_INTR_SOURCE,
}, },
#endif
}; };

1
docs/docs_not_updated/esp32c61.txt
View File

@ -124,7 +124,6 @@ api-reference/peripherals/sd_pullup_requirements.rst
api-reference/peripherals/spi_master.rst api-reference/peripherals/spi_master.rst
api-reference/peripherals/index.rst api-reference/peripherals/index.rst
api-reference/peripherals/sdmmc_host.rst api-reference/peripherals/sdmmc_host.rst
api-reference/peripherals/uart.rst
api-reference/peripherals/ecdsa.rst api-reference/peripherals/ecdsa.rst
api-reference/peripherals/ldo_regulator.rst api-reference/peripherals/ldo_regulator.rst
api-reference/peripherals/jpeg.rst api-reference/peripherals/jpeg.rst