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change(cp_dma): check cache line by cache level
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@ -21,6 +21,7 @@
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#include "esp_async_memcpy_priv.h"
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#include "hal/dma_types.h"
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#include "hal/cache_hal.h"
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#include "hal/cache_ll.h"
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#include "rom/cache.h"
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static const char *TAG = "async_mcp.gdma";
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@ -161,13 +162,20 @@ static esp_err_t esp_async_memcpy_install_gdma_template(const async_memcpy_confi
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portMUX_INITIALIZE(&mcp_gdma->spin_lock);
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atomic_init(&mcp_gdma->fsm, MCP_FSM_IDLE);
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mcp_gdma->gdma_bus_id = gdma_bus_id;
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uint32_t psram_cache_line_size = cache_hal_get_cache_line_size(CACHE_TYPE_DATA, CACHE_LL_LEVEL_EXT_MEM);
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uint32_t sram_cache_line_size = 0;
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#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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sram_cache_line_size = cache_hal_get_cache_line_size(CACHE_TYPE_DATA, CACHE_LL_LEVEL_INT_MEM);
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#endif
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// if the psram_trans_align is configured to zero, we should fall back to use the data cache line size
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uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_TYPE_DATA);
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size_t psram_trans_align = MAX(data_cache_line_size, config->psram_trans_align);
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size_t trans_align = MAX(config->sram_trans_align, psram_trans_align);
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size_t psram_trans_align = MAX(psram_cache_line_size, config->psram_trans_align);
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size_t sram_trans_align = MAX(sram_cache_line_size, config->sram_trans_align);
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size_t trans_align = MAX(sram_trans_align, psram_trans_align);
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mcp_gdma->max_single_dma_buffer = ALIGN_DOWN(DMA_DESCRIPTOR_BUFFER_MAX_SIZE, trans_align);
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mcp_gdma->psram_trans_align = psram_trans_align;
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mcp_gdma->sram_trans_align = config->sram_trans_align;
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mcp_gdma->sram_trans_align = sram_trans_align;
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mcp_gdma->parent.del = mcp_gdma_del;
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mcp_gdma->parent.memcpy = mcp_gdma_memcpy;
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#if SOC_GDMA_SUPPORT_ETM
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@ -322,6 +330,7 @@ static bool check_buffer_aligned(async_memcpy_gdma_context_t *mcp_gdma, void *sr
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{
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bool valid = true;
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uint32_t align_mask = 0;
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if (esp_ptr_external_ram(dst)) {
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if (mcp_gdma->psram_trans_align) {
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align_mask = mcp_gdma->psram_trans_align - 1;
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@ -331,12 +340,7 @@ static bool check_buffer_aligned(async_memcpy_gdma_context_t *mcp_gdma, void *sr
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align_mask = mcp_gdma->sram_trans_align - 1;
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}
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}
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#if CONFIG_IDF_TARGET_ESP32P4
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uint32_t data_cache_line_mask = cache_hal_get_cache_line_size(CACHE_TYPE_DATA) - 1;
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if (data_cache_line_mask > align_mask) {
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align_mask = data_cache_line_mask;
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}
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#endif
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// destination address must be cache line aligned
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valid = valid && (((uint32_t)dst & align_mask) == 0);
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valid = valid && ((n & align_mask) == 0);
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