From cb0f517fe3dfd9af61b97ce503110282972a7066 Mon Sep 17 00:00:00 2001 From: jingli Date: Wed, 21 Sep 2022 17:19:27 +0800 Subject: [PATCH] soc/soc_caps: update soc caps for chips that support power-down of modem hardware Closes WIFI-4424 --- components/bt/controller/esp32c3/bt.c | 9 ++++---- .../include/esp_private/esp_pmu.h | 1 + .../esp_hw_support/port/esp32/rtc_init.c | 12 ++++++++++- .../esp_hw_support/port/esp32/rtc_sleep.c | 6 ++++-- .../esp_hw_support/port/esp32c3/rtc_init.c | 10 +++++++++ .../esp_hw_support/port/esp32c3/rtc_sleep.c | 4 ++++ .../esp_hw_support/port/esp32s2/rtc_init.c | 10 +++++++++ .../esp_hw_support/port/esp32s2/rtc_sleep.c | 2 ++ .../esp_hw_support/port/esp32s3/rtc_init.c | 12 ++++++++++- .../esp_hw_support/port/esp32s3/rtc_sleep.c | 15 +++++-------- components/esp_hw_support/sleep_modes.c | 16 ++++++++------ components/esp_phy/src/phy_init.c | 21 +++++++++++++------ .../soc/esp32/include/soc/Kconfig.soc_caps.in | 4 ++++ components/soc/esp32/include/soc/rtc.h | 7 ++++--- components/soc/esp32/include/soc/soc_caps.h | 1 + .../esp32c2/include/soc/Kconfig.soc_caps.in | 12 ----------- components/soc/esp32c2/include/soc/soc_caps.h | 3 --- .../esp32h2/include/soc/Kconfig.soc_caps.in | 4 ---- components/soc/esp32h2/include/soc/soc_caps.h | 1 - .../esp32s2/include/soc/Kconfig.soc_caps.in | 8 +++---- components/soc/esp32s2/include/soc/soc_caps.h | 4 ++-- .../esp32s3/include/soc/Kconfig.soc_caps.in | 4 ++++ components/soc/esp32s3/include/soc/rtc.h | 6 ++---- .../soc/esp32s3/include/soc/rtc_cntl_reg.h | 6 ------ components/soc/esp32s3/include/soc/soc_caps.h | 2 +- 25 files changed, 110 insertions(+), 70 deletions(-) diff --git a/components/bt/controller/esp32c3/bt.c b/components/bt/controller/esp32c3/bt.c index 1294117824..34e9e7714f 100644 --- a/components/bt/controller/esp32c3/bt.c +++ b/components/bt/controller/esp32c3/bt.c @@ -30,6 +30,7 @@ #include "esp_ipc.h" #include "esp_private/periph_ctrl.h" #include "esp_private/esp_clk.h" +#include "soc/soc_caps.h" #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" #include "soc/soc_memory_layout.h" @@ -405,7 +406,7 @@ static DRAM_ATTR esp_pm_lock_handle_t s_light_sleep_pm_lock; void IRAM_ATTR btdm_hw_mac_power_down_wrapper(void) { #if CONFIG_MAC_BB_PD -#if CONFIG_IDF_TARGET_ESP32C3 +#if SOC_PM_SUPPORT_BT_PD // Bluetooth module power down SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_ISO); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PD); @@ -417,7 +418,7 @@ void IRAM_ATTR btdm_hw_mac_power_down_wrapper(void) void IRAM_ATTR btdm_hw_mac_power_up_wrapper(void) { #if CONFIG_MAC_BB_PD -#if CONFIG_IDF_TARGET_ESP32C3 +#if SOC_PM_SUPPORT_BT_PD // Bluetooth module power up CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PD); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_ISO); @@ -436,7 +437,7 @@ void IRAM_ATTR btdm_backup_dma_copy_wrapper(uint32_t reg, uint32_t mem_addr, uin static inline void esp_bt_power_domain_on(void) { // Bluetooth module power up -#if CONFIG_IDF_TARGET_ESP32C3 +#if SOC_PM_SUPPORT_BT_PD CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PD); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_ISO); #endif @@ -446,7 +447,7 @@ static inline void esp_bt_power_domain_on(void) static inline void esp_bt_power_domain_off(void) { // Bluetooth module power down -#if CONFIG_IDF_TARGET_ESP32C3 +#if SOC_PM_SUPPORT_BT_PD SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_ISO); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PD); #endif diff --git a/components/esp_hw_support/include/esp_private/esp_pmu.h b/components/esp_hw_support/include/esp_private/esp_pmu.h index d9ea2d483a..a97cbd7053 100644 --- a/components/esp_hw_support/include/esp_private/esp_pmu.h +++ b/components/esp_hw_support/include/esp_private/esp_pmu.h @@ -29,6 +29,7 @@ extern "C" { #define RTC_SLEEP_PD_DIG_PERIPH PMU_SLEEP_PD_HP_PERIPH //!< Power down DIG peripherals #define RTC_SLEEP_PD_INT_8M PMU_SLEEP_PD_RC_FAST //!< Power down Internal 20M oscillator #define RTC_SLEEP_PD_XTAL PMU_SLEEP_PD_XTAL //!< Power down main XTAL +#define RTC_SLEEP_PD_MODEM PMU_SLEEP_PD_MODEM //!< Power down modem(include wifi, ble and 15.4) //These flags are not power domains, but will affect some sleep parameters #define RTC_SLEEP_DIG_USE_8M BIT(16) diff --git a/components/esp_hw_support/port/esp32/rtc_init.c b/components/esp_hw_support/port/esp32/rtc_init.c index 45f20b2814..ab0fa4bd1d 100644 --- a/components/esp_hw_support/port/esp32/rtc_init.c +++ b/components/esp_hw_support/port/esp32/rtc_init.c @@ -19,6 +19,16 @@ void rtc_init(rtc_config_t cfg) { + /** + * When run rtc_init, it maybe deep sleep reset. Since we power down modem in deep sleep, after wakeup + * from deep sleep, these fields are changed and not reset. We will access two BB regs(BBPD_CTRL and + * NRXPD_CTRL) in rtc_sleep_pu. If PD modem and no iso, CPU will stuck when access these two BB regs + * and finally triggle RTC WDT. So need to clear modem Force PD. + * + * No worry about the power consumption, Because modem Force PD will be set at the end of this function. + */ + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD); + CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU | RTC_CNTL_TXRF_I2C_PU | RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU); @@ -91,7 +101,7 @@ void rtc_init(rtc_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO); } - /* force power down wifi and bt power domain */ + /* force power down modem(wifi and btdm) power domain */ SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD); diff --git a/components/esp_hw_support/port/esp32/rtc_sleep.c b/components/esp_hw_support/port/esp32/rtc_sleep.c index a4d4ed9ec9..16dc0ef977 100644 --- a/components/esp_hw_support/port/esp32/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32/rtc_sleep.c @@ -91,7 +91,7 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_ .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, - .wifi_pd_en = 0, + .modem_pd_en = (sleep_flags & RTC_SLEEP_PD_MODEM) ? 1 : 0, .int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, .rom_mem_pd_en = 0, .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, @@ -182,7 +182,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN); } - if (cfg.wifi_pd_en) { + if (cfg.modem_pd_en) { + REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | RTC_CNTL_WIFI_FORCE_ISO); + REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); } else { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); diff --git a/components/esp_hw_support/port/esp32c3/rtc_init.c b/components/esp_hw_support/port/esp32c3/rtc_init.c index e3f75bb0ff..a88adda43f 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_init.c +++ b/components/esp_hw_support/port/esp32c3/rtc_init.c @@ -31,6 +31,16 @@ static void set_rtc_dig_dbias(void); void rtc_init(rtc_config_t cfg) { + /** + * When run rtc_init, it maybe deep sleep reset. Since we power down modem in deep sleep, after wakeup + * from deep sleep, these fields are changed and not reset. We will access two BB regs(BBPD_CTRL and + * NRXPD_CTRL) in rtc_sleep_pu. If PD modem and no iso, CPU will stuck when access these two BB regs + * and finally triggle RTC WDT. So need to clear modem Force PD. + * + * No worry about the power consumption, Because modem Force PD will be set at the end of this function. + */ + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0); diff --git a/components/esp_hw_support/port/esp32c3/rtc_sleep.c b/components/esp_hw_support/port/esp32c3/rtc_sleep.c index df47391408..8652c1ef6d 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32c3/rtc_sleep.c @@ -116,11 +116,15 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) rtc_sleep_pu(pu_cfg); } if (cfg.wifi_pd_en) { + REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | RTC_CNTL_WIFI_FORCE_ISO); + REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); } else { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); } if (cfg.bt_pd_en) { + REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO | RTC_CNTL_BT_FORCE_ISO); + REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN); } else { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN); diff --git a/components/esp_hw_support/port/esp32s2/rtc_init.c b/components/esp_hw_support/port/esp32s2/rtc_init.c index a4c401a5ef..5674123f79 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_init.c +++ b/components/esp_hw_support/port/esp32s2/rtc_init.c @@ -28,6 +28,16 @@ static void calibrate_ocode(void); void rtc_init(rtc_config_t cfg) { + /** + * When run rtc_init, it maybe deep sleep reset. Since we power down modem in deep sleep, after wakeup + * from deep sleep, these fields are changed and not reset. We will access two BB regs(BBPD_CTRL and + * NRXPD_CTRL) in rtc_sleep_pu. If PD modem and no iso, CPU will stuck when access these two BB regs + * and finally triggle RTC WDT. So need to clear modem Force PD. + * + * No worry about the power consumption, Because modem Force PD will be set at the end of this function. + */ + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD); + CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU); REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait); REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait); diff --git a/components/esp_hw_support/port/esp32s2/rtc_sleep.c b/components/esp_hw_support/port/esp32s2/rtc_sleep.c index 578a6a5c62..334efd8c3c 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32s2/rtc_sleep.c @@ -131,6 +131,8 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) } if (cfg.wifi_pd_en) { + REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | RTC_CNTL_WIFI_FORCE_ISO); + REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); } else { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); diff --git a/components/esp_hw_support/port/esp32s3/rtc_init.c b/components/esp_hw_support/port/esp32s3/rtc_init.c index 3a3600440c..7bff7b2d2d 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_init.c +++ b/components/esp_hw_support/port/esp32s3/rtc_init.c @@ -45,6 +45,16 @@ uint32_t g_rtc_dbias_pvt_non_240m = 27; void rtc_init(rtc_config_t cfg) { + /** + * When run rtc_init, it maybe deep sleep reset. Since we power down modem in deep sleep, after wakeup + * from deep sleep, these fields are changed and not reset. We will access two BB regs(BBPD_CTRL and + * NRXPD_CTRL) in rtc_sleep_pu. If PD modem and no iso, CPU will stuck when access these two BB regs + * and finally triggle RTC WDT. So need to clear modem Force PD. + * + * No worry about the power consumption, Because modem Force PD will be set at the end of this function. + */ + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU); @@ -187,7 +197,7 @@ void rtc_init(rtc_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO); } - /* force power down wifi and bt power domain */ + /* force power down modem(wifi and ble) power domain */ SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD); diff --git a/components/esp_hw_support/port/esp32s3/rtc_sleep.c b/components/esp_hw_support/port/esp32s3/rtc_sleep.c index cc9d24fa2b..41f4c71232 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32s3/rtc_sleep.c @@ -59,8 +59,7 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_ .rtc_fastmem_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, .rtc_slowmem_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, .rtc_peri_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, - .wifi_pd_en = (sleep_flags & RTC_SLEEP_PD_WIFI) ? 1 : 0, - .bt_pd_en = (sleep_flags & RTC_SLEEP_PD_BT) ? 1 : 0, + .modem_pd_en = (sleep_flags & RTC_SLEEP_PD_MODEM) ? 1 : 0, .cpu_pd_en = (sleep_flags & RTC_SLEEP_PD_CPU) ? 1 : 0, .int_8m_pd_en = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? 1 : 0, .dig_peri_pd_en = (sleep_flags & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, @@ -157,20 +156,14 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) rtc_sleep_pu(pu_cfg); } - if (cfg.wifi_pd_en) { + if (cfg.modem_pd_en) { REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | RTC_CNTL_WIFI_FORCE_ISO); REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); } else { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); } - if (cfg.bt_pd_en) { - REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO | RTC_CNTL_BT_FORCE_ISO); - REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU); - SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN); - } else { - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN); - } + if (cfg.cpu_pd_en) { REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO | RTC_CNTL_CPU_TOP_FORCE_ISO); REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU); @@ -178,6 +171,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) } else { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN); } + if (cfg.dig_peri_pd_en) { REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO | RTC_CNTL_DG_PERI_FORCE_ISO); REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU); @@ -185,6 +179,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) } else { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN); } + if (cfg.rtc_peri_pd_en) { REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_NOISO | RTC_CNTL_FORCE_ISO | RTC_CNTL_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN); diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index eab81b1bcb..875299a3b0 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -692,18 +692,22 @@ void IRAM_ATTR esp_deep_sleep_start(void) uint32_t force_pd_flags = RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_VDDSDIO | RTC_SLEEP_PD_INT_8M | RTC_SLEEP_PD_XTAL; #endif - - + /** + * If all wireless modules share one power domain, we name this power domain "modem". + * If wireless modules have their own power domain, we give these power domains separate + * names. + */ #if SOC_PM_SUPPORT_MODEM_PD - force_pd_flags |= PMU_SLEEP_PD_MODEM; -#else // !SOC_PM_SUPPORT_MODEM_PD + force_pd_flags |= RTC_SLEEP_PD_MODEM; +#endif + #if SOC_PM_SUPPORT_WIFI_PD force_pd_flags |= RTC_SLEEP_PD_WIFI; #endif + #if SOC_PM_SUPPORT_BT_PD force_pd_flags |= RTC_SLEEP_PD_BT; #endif -#endif // !SOC_PM_SUPPORT_MODEM_PD // Enter sleep esp_sleep_start(force_pd_flags | pd_flags, ESP_SLEEP_MODE_DEEP_SLEEP); @@ -1621,7 +1625,7 @@ static uint32_t get_power_down_flags(void) #if SOC_PM_SUPPORT_MODEM_PD if (s_config.domain[ESP_PD_DOMAIN_MODEM].pd_option != ESP_PD_OPTION_ON) { - pd_flags |= PMU_SLEEP_PD_MODEM; + pd_flags |= RTC_SLEEP_PD_MODEM; } #endif diff --git a/components/esp_phy/src/phy_init.c b/components/esp_phy/src/phy_init.c index 7dcb8763bd..62ea775656 100644 --- a/components/esp_phy/src/phy_init.c +++ b/components/esp_phy/src/phy_init.c @@ -56,12 +56,14 @@ static const char* TAG = "phy_init"; static _lock_t s_phy_access_lock; -#if !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6 // TODO - WIFI-4424 +#if SOC_PM_SUPPORT_MODEM_PD || SOC_PM_SUPPORT_WIFI_PD +#if !SOC_PMU_SUPPORTED static DRAM_ATTR struct { int count; /* power on count of wifi and bt power domain */ _lock_t lock; } s_wifi_bt_pd_controller = { .count = 0 }; -#endif +#endif // !SOC_PMU_SUPPORTED +#endif // SOC_PM_SUPPORT_MODEM_PD || SOC_PM_SUPPORT_WIFI_PD /* Reference count of enabling PHY */ static uint8_t s_phy_access_ref = 0; @@ -308,30 +310,37 @@ void esp_phy_disable(void) void IRAM_ATTR esp_wifi_bt_power_domain_on(void) { -#if !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6 // TODO - WIFI-4424 +#if SOC_PM_SUPPORT_MODEM_PD || SOC_PM_SUPPORT_WIFI_PD +#if !SOC_PMU_SUPPORTED _lock_acquire(&s_wifi_bt_pd_controller.lock); if (s_wifi_bt_pd_controller.count++ == 0) { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD); + #if !CONFIG_IDF_TARGET_ESP32 + // modem reset when power on SET_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, MODEM_RESET_FIELD_WHEN_PU); CLEAR_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, MODEM_RESET_FIELD_WHEN_PU); #endif + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO); } _lock_release(&s_wifi_bt_pd_controller.lock); -#endif +#endif // !SOC_PMU_SUPPORTED +#endif // SOC_PM_SUPPORT_MODEM_PD || SOC_PM_SUPPORT_WIFI_PD } void esp_wifi_bt_power_domain_off(void) { -#if !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6 // TODO - WIFI-4424 +#if SOC_PM_SUPPORT_MODEM_PD || SOC_PM_SUPPORT_WIFI_PD +#if !SOC_PMU_SUPPORTED _lock_acquire(&s_wifi_bt_pd_controller.lock); if (--s_wifi_bt_pd_controller.count == 0) { SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD); } _lock_release(&s_wifi_bt_pd_controller.lock); -#endif +#endif // !SOC_PMU_SUPPORTED +#endif // SOC_PM_SUPPORT_MODEM_PD || SOC_PM_SUPPORT_WIFI_PD } void esp_phy_modem_init(void) diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in index e5cabe3a06..4cba9a1aad 100644 --- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in @@ -759,6 +759,10 @@ config SOC_PM_SUPPORT_VDDSDIO_PD bool default y +config SOC_PM_SUPPORT_MODEM_PD + bool + default y + config SOC_CONFIGURABLE_VDDSDIO_SUPPORTED bool default y diff --git a/components/soc/esp32/include/soc/rtc.h b/components/soc/esp32/include/soc/rtc.h index 4881a174a2..813c98d9f1 100644 --- a/components/soc/esp32/include/soc/rtc.h +++ b/components/soc/esp32/include/soc/rtc.h @@ -493,7 +493,7 @@ typedef struct rtc_sleep_config_s { uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals - uint32_t wifi_pd_en : 1; //!< power down WiFi + uint32_t modem_pd_en : 1; //!< power down Modem(wifi and btdm) uint32_t int_8m_pd_en : 1; //!< Power down Internal 8M oscillator uint32_t rom_mem_pd_en : 1; //!< power down main RAM and ROM uint32_t deep_slp : 1; //!< power down digital domain @@ -516,8 +516,9 @@ typedef struct rtc_sleep_config_s { #define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory #define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU #define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator -#define RTC_SLEEP_PD_XTAL BIT(6) //!< Power down main XTAL -#define RTC_SLEEP_PD_INT_8M BIT(7) //!< Power down Internal 8M oscillator +#define RTC_SLEEP_PD_MODEM BIT(6) //!< Power down Modem(wifi and btdm) +#define RTC_SLEEP_PD_XTAL BIT(7) //!< Power down main XTAL +#define RTC_SLEEP_PD_INT_8M BIT(8) //!< Power down Internal 8M oscillator //These flags are not power domains, but will affect some sleep parameters #define RTC_SLEEP_DIG_USE_8M BIT(16) diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 73084e087b..31a7ab8305 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -376,6 +376,7 @@ #define SOC_PM_SUPPORT_RTC_SLOW_MEM_PD (1) #define SOC_PM_SUPPORT_RC_FAST_PD (1) #define SOC_PM_SUPPORT_VDDSDIO_PD (1) +#define SOC_PM_SUPPORT_MODEM_PD (1) /*!