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esp32h4: removed esp32h4 related files

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laokaiyao 2023-04-13 11:00:21 +08:00
parent 8f24b34f21
commit cae47ce37e
91 changed files with 0 additions and 11132 deletions
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240
components/bootloader/subproject/main/ld/esp32h4/bootloader.ld
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/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/** Simplified memory map for the bootloader.
* Make sure the bootloader can load into main memory without overwriting itself.
*
* ESP32-H4 ROM static data usage is as follows:
* - 0x3fccb900 - 0x3fcdd210: Shared buffers, used in UART/USB/SPI download mode only
* - 0x3fcdd210 - 0x3fcdf210: PRO CPU stack, can be reclaimed as heap after RTOS startup
* - 0x3fcdf210 - 0x3fce0000: ROM .bss and .data (not easily reclaimable)
*
* The 2nd stage bootloader can take space up to the end of ROM shared
* buffers area (0x3fce9704). For alignment purpose we shall use value (0x3fce9700).
*/
/* The offset between Dbus and Ibus. Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. */
iram_dram_offset = 0x700000;
/* We consider 0x3fce9700 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
* and work out iram_seg and iram_loader_seg addresses from there, backwards.
*/
/* These lengths can be adjusted, if necessary: */
bootloader_usable_dram_end = 0x3fcdd120;
bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
bootloader_dram_seg_len = 0x5000;
bootloader_iram_loader_seg_len = 0x7000;
bootloader_iram_seg_len = 0x2000;
/* Start of the lower region is determined by region size and the end of the higher region */
bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len + iram_dram_offset;
bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
MEMORY
{
iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
}
/* Default entry point: */
ENTRY(call_start_cpu0);
SECTIONS
{
.iram_loader.text :
{
. = ALIGN (16);
_loader_text_start = ABSOLUTE(.);
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
*liblog.a:(.literal .text .literal.* .text.*)
*libgcc.a:(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
*libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
*libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
*libspi_flash.a:*.*(.literal .text .literal.* .text.*)
*libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
*libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
*libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
*libefuse.a:*.*(.literal .text .literal.* .text.*)
*(.fini.literal)
*(.fini)
*(.gnu.version)
_loader_text_end = ABSOLUTE(.);
} > iram_loader_seg
.iram.text :
{
. = ALIGN (16);
*(.entry.text)
*(.init.literal)
*(.init)
} > iram_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
. = ALIGN (8);
_dram_start = ABSOLUTE(.);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
} > dram_seg
.dram0.data :
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.gnu.linkonce.s2.*)
*(.jcr)
_data_end = ABSOLUTE(.);
} > dram_seg
.dram0.rodata :
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
*(.sdata2 .sdata2.* .srodata .srodata.*)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
*(.eh_frame)
. = (. + 3) & ~ 3;
/* C++ constructor and destructor tables, properly ordered: */
__init_array_start = ABSOLUTE(.);
KEEP (*crtbegin.*(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__init_array_end = ABSOLUTE(.);
KEEP (*crtbegin.*(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
_rodata_end = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
_dram_end = ABSOLUTE(.);
} > dram_seg
.iram.text :
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram .iram.*) /* catch stray IRAM_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
/** CPU will try to prefetch up to 16 bytes of
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
* safe access to up to 16 bytes after the last real instruction, add
* dummy bytes to ensure this
*/
. += 16;
_text_end = ABSOLUTE(.);
_etext = .;
} > iram_seg
}
/**
* Appendix: Memory Usage of ROM bootloader
*
* 0x3fccb81c ------------------> _dram0_0_start
* | |
* | |
* | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h
* | |
* | |
* 0x3fcdd120 ------------------> __stack_sentry
* | |
* | | 2. Startup pro cpu stack (freed when IDF app is running)
* | |
* 0x3fcdf120 ------------------> __stack (pro cpu)
* | |
* | |
* | | 3. Shared memory only used in startup code or nonos/early boot*
* | | (can be freed when IDF runs)
* | |
* | |
* 0x3fcdfa6c ------------------> _dram0_rtos_reserved_start
* | |
* | |
* | | 4. Shared memory used in startup code and when IDF runs
* | |
* | |
* 0x3fcdfe40 ------------------> _dram0_rtos_reserved_end
* | |
* 0x3fcdfe4c ------------------> _data_start_interface
* | |
* | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
* | |
* 0x3fce0000 ------------------> _data_end_interface
*/

6
components/bootloader/subproject/main/ld/esp32h4/bootloader.rom.ld
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/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* No definition for ESP32-H4 target */

24
components/bootloader_support/src/bootloader_random_esp32h4.c
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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "bootloader_random.h"
#include "esp_log.h"
#include "soc/syscon_reg.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_saradc_reg.h"
#include "soc/system_reg.h"
#include "esp_private/regi2c_ctrl.h"
// ESP32H4-TODO: IDF-3381
void bootloader_random_enable(void)
{
}
void bootloader_random_disable(void)
{
}

54
components/efuse/esp32h4/esp_efuse_fields.c
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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "esp_efuse.h"
#include "esp_efuse_utility.h"
#include "esp_efuse_table.h"
#include "stdlib.h"
#include "esp_types.h"
#include "esp32h4/rom/efuse.h"
#include "assert.h"
#include "esp_err.h"
#include "esp_log.h"
#include "soc/efuse_periph.h"
#include "sys/param.h"
static __attribute__((unused)) const char *TAG = "efuse";
// Contains functions that provide access to efuse fields which are often used in IDF.
// Returns chip package from efuse
uint32_t esp_efuse_get_pkg_ver(void)
{
uint32_t pkg_ver = 0;
esp_efuse_read_field_blob(ESP_EFUSE_PKG_VERSION, &pkg_ver, ESP_EFUSE_PKG_VERSION[0]->bit_count);
return pkg_ver;
}
esp_err_t esp_efuse_set_rom_log_scheme(esp_efuse_rom_log_scheme_t log_scheme)
{
int cur_log_scheme = 0;
esp_efuse_read_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &cur_log_scheme, 2);
if (!cur_log_scheme) { // not burned yet
return esp_efuse_write_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &log_scheme, 2);
} else {
return ESP_ERR_INVALID_STATE;
}
}
esp_err_t esp_efuse_disable_rom_download_mode(void)
{
return esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE);
}
esp_err_t esp_efuse_enable_rom_secure_download_mode(void)
{
if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) {
return ESP_ERR_INVALID_STATE;
}
return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD);
}

94
components/efuse/esp32h4/esp_efuse_rtc_calib.c
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/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <esp_bit_defs.h>
#include "esp_efuse.h"
#include "esp_efuse_table.h"
int esp_efuse_rtc_calib_get_ver(void)
{
uint32_t result = 0;
esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &result, 3);
return result;
}
uint16_t esp_efuse_rtc_calib_get_init_code(int version, int atten)
{
assert(version == 1);
const esp_efuse_desc_t** init_code_efuse;
assert(atten < 4);
if (atten == 0) {
init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0;
} else if (atten == 1) {
init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN1;
} else if (atten == 2) {
init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN2;
} else {
init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN3;
}
int init_code_size = esp_efuse_get_field_size(init_code_efuse);
assert(init_code_size == 10);
uint32_t init_code = 0;
ESP_ERROR_CHECK(esp_efuse_read_field_blob(init_code_efuse, &init_code, init_code_size));
return init_code + 1000; // version 1 logic
}
esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv)
{
const esp_efuse_desc_t** cal_vol_efuse;
uint32_t calib_vol_expected_mv;
if (version != 1) {
return ESP_ERR_INVALID_ARG;
}
if (atten >= 4) {
return ESP_ERR_INVALID_ARG;
}
if (atten == 0) {
cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN0;
calib_vol_expected_mv = 400;
} else if (atten == 1) {
cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN1;
calib_vol_expected_mv = 550;
} else if (atten == 2) {
cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN2;
calib_vol_expected_mv = 750;
} else {
cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN3;
calib_vol_expected_mv = 1370;
}
assert(cal_vol_efuse[0]->bit_count == 10);
uint32_t cal_vol = 0;
ESP_ERROR_CHECK(esp_efuse_read_field_blob(cal_vol_efuse, &cal_vol, cal_vol_efuse[0]->bit_count));
*out_digi = 2000 + ((cal_vol & BIT(9))? -(cal_vol & ~BIT9): cal_vol);
*out_vol_mv = calib_vol_expected_mv;
return ESP_OK;
}
esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal)
{
uint32_t version = esp_efuse_rtc_calib_get_ver();
if (version != 1) {
*tsens_cal = 0.0;
return ESP_ERR_NOT_SUPPORTED;
}
const esp_efuse_desc_t** cal_temp_efuse;
cal_temp_efuse = ESP_EFUSE_TEMP_CALIB;
int cal_temp_size = esp_efuse_get_field_size(cal_temp_efuse);
assert(cal_temp_size == 9);
uint32_t cal_temp = 0;
esp_err_t err = esp_efuse_read_field_blob(cal_temp_efuse, &cal_temp, cal_temp_size);
assert(err == ESP_OK);
(void)err;
// BIT(8) stands for sign: 1: negtive, 0: positive
*tsens_cal = ((cal_temp & BIT(8)) != 0)? -(uint8_t)cal_temp: (uint8_t)cal_temp;
return ESP_OK;
}

1049
components/efuse/esp32h4/esp_efuse_table.c
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156
components/efuse/esp32h4/esp_efuse_table.csv
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# field_name, | efuse_block, | bit_start, | bit_count, |comment #
# | (EFUSE_BLK0 | (0..255) | (1..-) | #
# | EFUSE_BLK1 | |MAX_BLK_LEN*| #
# | ... | | | #
# | EFUSE_BLK10)| | | #
##########################################################################
# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128.
# !!!!!!!!!!! #
# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table"
# this will generate new source files, next rebuild all the sources.
# !!!!!!!!!!! #
# ESP32H4-TODO: IDF-3390
# EFUSE_RD_REPEAT_DATA BLOCK #
##############################
# EFUSE_RD_WR_DIS_REG #
WR_DIS, EFUSE_BLK0, 0, 32, Write protection
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE
WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_TWAI SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for WDT_DELAY_SEL
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT
WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0
WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1
WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2
WR_DIS.KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0
WR_DIS.KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1
WR_DIS.KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2
WR_DIS.KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3
WR_DIS.KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4
WR_DIS.KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
WR_DIS.GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_TINY_BASIC DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
WR_DIS.BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1
WR_DIS.USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA
WR_DIS.KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0
WR_DIS.KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1
WR_DIS.KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2
WR_DIS.KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3
WR_DIS.KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4
WR_DIS.KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5
WR_DIS.SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2
# EFUSE_RD_REPEAT_DATA0_REG #
RD_DIS, EFUSE_BLK0, 32, 7, Read protection
RD_DIS.KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0
RD_DIS.KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1
RD_DIS.KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2
RD_DIS.KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3
RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4
RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5
RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2
DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache
DIS_USB_JTAG, EFUSE_BLK0, 41, 1, Disable USB JTAG
DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode
DIS_USB_DEVICE, EFUSE_BLK0, 43, 1, Disable USB_DEVICE
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function
DIS_TWAI, EFUSE_BLK0, 46, 1, Disable TWAI function
JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.
DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, Disable JTAG in the hard way. JTAG is disabled permanently.
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encryption when in download boot modes.
USB_DREFH, EFUSE_BLK0, 53, 2, Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.
USB_DREFL, EFUSE_BLK0, 55, 2, Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.
USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins
VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, Set this bit to vdd spi pin function as gpio
BTLC_GPIO_ENABLE, EFUSE_BLK0, 59, 2, Enable btlc gpio
POWERGLITCH_EN, EFUSE_BLK0, 61, 1, Set this bit to enable power glitch function
POWER_GLITCH_DSENSE, EFUSE_BLK0, 62, 2, Sample delay configuration of power glitch
# EFUSE_RD_REPEAT_DATA1_REG #
WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key
KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose
KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose
# EFUSE_RD_REPEAT_DATA2_REG #
KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke
FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
# EFUSE_RD_REPEAT_DATA3_REG #
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, Disable direct boot mode
DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, Disable usb serial jtag print during rom boot
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,EFUSE_BLK0, 132, 1, Disable download through USB-Serial-JTAG
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.
FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot
SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback
BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 158, 1, Fast verify on wake option in ROM for Secure Boot
# EFUSE_RD_REPEAT_DATA4_REG #
# MAC_SPI_SYS BLOCK#
#######################
MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0]
, EFUSE_BLK1, 32, 8, Factory MAC addr [1]
, EFUSE_BLK1, 24, 8, Factory MAC addr [2]
, EFUSE_BLK1, 16, 8, Factory MAC addr [3]
, EFUSE_BLK1, 8, 8, Factory MAC addr [4]
, EFUSE_BLK1, 0, 8, Factory MAC addr [5]
MAC_EXT, EFUSE_BLK1, 123, 8, Extend MAC addr [0]
, EFUSE_BLK1, 131, 8, Extend MAC addr [1]
SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK
SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1)
SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0)
SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS
SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3)
SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2)
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version
PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32H4
BLOCK1_VERSION, EFUSE_BLK1, 120, 3, BLOCK1 efuse version
# SYS_DATA_PART1 BLOCK# - System configuration
#######################
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
BLOCK2_VERSION, EFUSE_BLK2, 128, 3, Version of BLOCK2
TEMP_CALIB, EFUSE_BLK2, 131, 9, Temperature calibration data
OCODE, EFUSE_BLK2, 140, 8, ADC OCode
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, ADC1 init code at atten0
ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, ADC1 init code at atten1
ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, ADC1 init code at atten2
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, ADC1 init code at atten3
ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, ADC1 calibration voltage at atten0
ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 198, 10, ADC1 calibration voltage at atten1
ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 208, 10, ADC1 calibration voltage at atten2
ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 218, 10, ADC1 calibration voltage at atten3
################
USER_DATA, EFUSE_BLK3, 0, 256, User data
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, Custom MAC
################
KEY0, EFUSE_BLK4, 0, 256, Key0 or user data
KEY1, EFUSE_BLK5, 0, 256, Key1 or user data
KEY2, EFUSE_BLK6, 0, 256, Key2 or user data
KEY3, EFUSE_BLK7, 0, 256, Key3 or user data
KEY4, EFUSE_BLK8, 0, 256, Key4 or user data
KEY5, EFUSE_BLK9, 0, 256, Key5 or user data
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration
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components/efuse/esp32h4/esp_efuse_utility.c
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/*
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <sys/param.h>
#include "sdkconfig.h"
#include "esp_log.h"
#include "assert.h"
#include "esp_efuse_utility.h"
#include "soc/efuse_periph.h"
#include "hal/efuse_hal.h"
static const char *TAG = "efuse";
#ifdef CONFIG_EFUSE_VIRTUAL
extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK];
#endif // CONFIG_EFUSE_VIRTUAL
/*Range addresses to read blocks*/
const esp_efuse_range_addr_t range_read_addr_blocks[] = {
{EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT
{EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_RD_MAC_SPI_SYS_5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M
{EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA
{EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA
{EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0
{EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1
{EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2
{EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3
{EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4
{EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5
{EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG} // range address of EFUSE_BLK10 KEY6
};
static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 };
/*Range addresses to write blocks (it is not real regs, it is buffer) */
const esp_efuse_range_addr_t range_write_addr_blocks[] = {
{(uint32_t) &write_mass_blocks[EFUSE_BLK0][0], (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK1][0], (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK2][0], (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK3][0], (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK4][0], (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK5][0], (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK6][0], (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK7][0], (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK8][0], (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK9][0], (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]},
};
#ifndef CONFIG_EFUSE_VIRTUAL
// Update Efuse timing configuration
static esp_err_t esp_efuse_set_timing(void)
{
// efuse clock is fixed.
// An argument (0) is for compatibility and will be ignored.
efuse_hal_set_timing(0);
return ESP_OK;
}
#endif // ifndef CONFIG_EFUSE_VIRTUAL
// Efuse read operation: copies data from physical efuses to efuse read registers.
void esp_efuse_utility_clear_program_registers(void)
{
efuse_hal_read();
efuse_hal_clear_program_registers();
}
esp_err_t esp_efuse_utility_check_errors(void)
{
return ESP_OK;
}
// Burn values written to the efuse write registers
esp_err_t esp_efuse_utility_burn_chip(void)
{
esp_err_t error = ESP_OK;
#ifdef CONFIG_EFUSE_VIRTUAL
ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses");
for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
int subblock = 0;
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block);
}
}
#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
esp_efuse_utility_write_efuses_to_flash();
#endif
#else // CONFIG_EFUSE_VIRTUAL
if (esp_efuse_set_timing() != ESP_OK) {
ESP_LOGE(TAG, "Efuse fields are not burnt");
} else {
// Permanently update values written to the efuse write registers
// It is necessary to process blocks in the order from MAX-> EFUSE_BLK0, because EFUSE_BLK0 has protection bits for other blocks.
for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
bool need_burn_block = false;
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
if (REG_READ(addr_wr_block) != 0) {
need_burn_block = true;
break;
}
}
if (!need_burn_block) {
continue;
}
if (error) {
// It is done for a use case: BLOCK2 (Flash encryption key) could have an error (incorrect written data)
// in this case we can not burn any data into BLOCK0 because it might set read/write protections of BLOCK2.
ESP_LOGE(TAG, "BLOCK%d can not be burned because a previous block got an error, skipped.", num_block);
continue;
}
efuse_hal_clear_program_registers();
if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
uint8_t block_rs[12];
efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs);
hal_memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs));
}
unsigned r_data_len = (range_read_addr_blocks[num_block].end - range_read_addr_blocks[num_block].start) + sizeof(uint32_t);
unsigned data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t);
memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len);
uint32_t backup_write_data[8 + 3]; // 8 words are data and 3 words are RS coding data
hal_memcpy(backup_write_data, (void *)EFUSE_PGM_DATA0_REG, sizeof(backup_write_data));
int repeat_burn_op = 1;
bool correct_written_data;
bool coding_error_before = efuse_hal_is_coding_error_in_block(num_block);
if (coding_error_before) {
ESP_LOGW(TAG, "BLOCK%d already has a coding error", num_block);
}
bool coding_error_occurred;
do {
ESP_LOGI(TAG, "BURN BLOCK%d", num_block);
efuse_hal_program(num_block); // BURN a block
bool coding_error_after;
for (unsigned i = 0; i < 5; i++) {
efuse_hal_read();
coding_error_after = efuse_hal_is_coding_error_in_block(num_block);
if (coding_error_after == true) {
break;
}
}
coding_error_occurred = (coding_error_before != coding_error_after) && coding_error_before == false;
if (coding_error_occurred) {
ESP_LOGW(TAG, "BLOCK%d got a coding error", num_block);
}
correct_written_data = esp_efuse_utility_is_correct_written_data(num_block, r_data_len);
if (!correct_written_data || coding_error_occurred) {
ESP_LOGW(TAG, "BLOCK%d: next retry to fix an error [%d/3]...", num_block, repeat_burn_op);
hal_memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)backup_write_data, sizeof(backup_write_data));
}
} while ((!correct_written_data || coding_error_occurred) && repeat_burn_op++ < 3);
if (coding_error_occurred) {
ESP_LOGW(TAG, "Coding error was not fixed");
if (num_block == 0) {
ESP_LOGE(TAG, "BLOCK0 got a coding error, which might be critical for security");
error = ESP_FAIL;
}
}
if (!correct_written_data) {
ESP_LOGE(TAG, "Written data are incorrect");
error = ESP_FAIL;
}
}
}
#endif // CONFIG_EFUSE_VIRTUAL
esp_efuse_utility_reset();
return error;
}
// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values.
// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme.
// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this.
// They will be filled during the burn operation.
esp_err_t esp_efuse_utility_apply_new_coding_scheme()
{
// start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE.
for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) {
if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
if (REG_READ(addr_wr_block)) {
int num_reg = 0;
for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) {
if (esp_efuse_utility_read_reg(num_block, num_reg)) {
ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden.");
return ESP_ERR_CODING;
}
}
break;
}
}
}
}
return ESP_OK;
}

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components/efuse/esp32h4/include/esp_efuse_chip.h
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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Type of eFuse blocks ESP32H4
*/
typedef enum {
EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */
EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */
EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA*/
EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA*/
EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */
EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */
EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */
EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */
EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */
EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */
EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */
EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */
EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */
EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */
EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */
EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */
EFUSE_BLK_KEY_MAX = 10,
EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
EFUSE_BLK_MAX
} esp_efuse_block_t;
/**
* @brief Type of coding scheme
*/
typedef enum {
EFUSE_CODING_SCHEME_NONE = 0, /**< None */
EFUSE_CODING_SCHEME_RS = 3, /**< Reed-Solomon coding */
} esp_efuse_coding_scheme_t;
/**
* @brief Type of key purpose
*/
typedef enum {
ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */
ESP_EFUSE_KEY_PURPOSE_RESERVED = 1, /**< Reserved */
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Digital Signature peripheral key (uses HMAC Downstream mode) */
ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8, /**< HMAC Upstream mode */
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */
ESP_EFUSE_KEY_PURPOSE_MAX, /**< MAX PURPOSE */
} esp_efuse_purpose_t;
#ifdef __cplusplus
}
#endif

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components/efuse/esp32h4/include/esp_efuse_rtc_calib.h
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/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <esp_types.h>
#include <esp_err.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Get the RTC calibration efuse version
*
* @return Version of the stored efuse
*/
int esp_efuse_rtc_calib_get_ver(void);
/**
* @brief Get the init code in the efuse, for the corresponding attenuation.
*
* @param version Version of the stored efuse
* @param atten Attenuation of the init code
* @return The init code stored in efuse
*/
uint16_t esp_efuse_rtc_calib_get_init_code(int version, int atten);
/**
* @brief Get the calibration digits stored in the efuse, and the corresponding voltage.
*
* @param version Version of the stored efuse
* @param atten Attenuation to use
* @param out_digi Output buffer of the digits
* @param out_vol_mv Output of the voltage, in mV
* @return
* - ESP_ERR_INVALID_ARG: If efuse version or attenuation is invalid
* - ESP_OK: if success
*/
esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv);
/**
* @brief Get the temperature sensor calibration number delta_T stored in the efuse.
*
* @param tsens_cal Pointer of the specification of temperature sensor calibration number in efuse.
*
* @return ESP_OK if get the calibration value successfully.
* ESP_ERR_INVALID_ARG if can't get the calibration value.
*/
esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal);
#ifdef __cplusplus
}
#endif

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components/efuse/esp32h4/include/esp_efuse_table.h
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/*
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifdef __cplusplus
extern "C" {
#endif
#include "esp_efuse.h"
// md5_digest_table 4561606695cfe94477d259619fd723ef
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
// To show efuse_table run the command 'show_efuse_table'.
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DEVICE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[];
extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[];
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[];
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[];
extern const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_DSENSE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BOOT_DISABLE_FAST_WAKE[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
#ifdef __cplusplus
}
#endif

21
components/efuse/esp32h4/private_include/esp_efuse_utility.h
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@ -1,21 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define COUNT_EFUSE_REG_PER_BLOCK 8 /* The number of registers per block. */
#define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK0
#define ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(scheme, max_num_bit)
#ifdef __cplusplus
}
#endif

4
components/efuse/esp32h4/sources.cmake
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@ -1,4 +0,0 @@
set(EFUSE_SOC_SRCS "esp_efuse_table.c"
"esp_efuse_fields.c"
"esp_efuse_rtc_calib.c"
"esp_efuse_utility.c")

15
components/esp_adc/esp32h4/include/adc_cali_schemes.h
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@ -1,15 +0,0 @@
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @file adc_cali_schemes.h
*
* @brief Supported calibration schemes
*/
//Now no scheme supported

13
components/esp_pm/include/esp32h4/pm.h
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@ -1,13 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#warning "esp_pm_config_esp32h4_t is deprecated, please include esp_pm.h and use esp_pm_config_t instead"
/* backward compatibility */
#include "esp_pm.h"

60
components/esp_rom/esp32h4/Kconfig.soc_caps.in
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@ -1,60 +0,0 @@
#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config ESP_ROM_HAS_CRC_LE
bool
default y
config ESP_ROM_HAS_CRC_BE
bool
default y
config ESP_ROM_HAS_MZ_CRC32
bool
default y
config ESP_ROM_HAS_JPEG_DECODE
bool
default y
config ESP_ROM_UART_CLK_IS_XTAL
bool
default y
config ESP_ROM_USB_SERIAL_DEVICE_NUM
int
default 3
config ESP_ROM_HAS_RETARGETABLE_LOCKING
bool
default y
config ESP_ROM_HAS_ERASE_0_REGION_BUG
bool
default y
config ESP_ROM_GET_CLK_FREQ
bool
default y
config ESP_ROM_HAS_LAYOUT_TABLE
bool
default y
config ESP_ROM_HAS_ETS_PRINTF_BUG
bool
default y
config ESP_ROM_HAS_NEWLIB_NANO_FORMAT
bool
default y
config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
bool
default y
config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
bool
default y

22
components/esp_rom/esp32h4/esp_rom_caps.h
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@ -1,22 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian
#define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian
#define ESP_ROM_HAS_MZ_CRC32 (1) // ROM has mz_crc32 function
#define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library
#define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM
#define ESP_ROM_USB_SERIAL_DEVICE_NUM (3) // UART uses USB_SERIAL_JTAG port in ROM.
#define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking
#define ESP_ROM_HAS_ERASE_0_REGION_BUG (1) // ROM has esp_flash_erase_region(size=0) bug
#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table
#define ESP_ROM_HAS_ETS_PRINTF_BUG (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register
#define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions
#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap
#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init

62
components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld
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@ -1,62 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/** ROM APIs
*/
PROVIDE ( esp_rom_crc32_le = crc32_le );
PROVIDE ( esp_rom_crc16_le = crc16_le );
PROVIDE ( esp_rom_crc8_le = crc8_le );
PROVIDE ( esp_rom_crc32_be = crc32_be );
PROVIDE ( esp_rom_crc16_be = crc16_be );
PROVIDE ( esp_rom_crc8_be = crc8_be );
PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio );
PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup );
PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv );
PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold );
PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in );
PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );
PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 );
PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig );
PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled );
PROVIDE ( esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad );
PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush );
PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char );
PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle );
PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char );
PROVIDE ( esp_rom_uart_rx_string = UartRxString );
PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
PROVIDE ( esp_rom_uart_putc = ets_write_char_uart );
PROVIDE ( esp_rom_md5_init = MD5Init );
PROVIDE ( esp_rom_md5_update = MD5Update );
PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_software_reset_system = software_reset );
PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);
PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea );
PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix );
PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs);
PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction );
PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command );
PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg );
PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask );
PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg );
PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask );

723
components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.ld
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@ -1,723 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32b1z.rom.ld for esp32b1z
*
*
* Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group common
***************************************/
/* Functions */
rtc_get_reset_reason = 0x40000018;
analog_super_wdt_reset_happened = 0x4000001c;
jtag_cpu_reset_happened = 0x40000020;
rtc_get_wakeup_cause = 0x40000024;
rtc_select_apb_bridge = 0x40000028;
rtc_unhold_all_pads = 0x4000002c;
ets_is_print_boot = 0x40000030;
ets_printf = 0x40000034;
ets_install_putc1 = 0x40000038;
ets_install_uart_printf = 0x4000003c;
ets_install_putc2 = 0x40000040;
PROVIDE( ets_delay_us = 0x40000044 );
ets_get_stack_info = 0x40000048;
ets_install_lock = 0x4000004c;
ets_backup_dma_copy = 0x40000050;
ets_apb_backup_init_lock_func = 0x40000054;
UartRxString = 0x40000058;
uart_tx_one_char = 0x4000005c;
uart_tx_one_char2 = 0x40000060;
uart_rx_one_char = 0x40000064;
uart_rx_one_char_block = 0x40000068;
uart_rx_readbuff = 0x4000006c;
uartAttach = 0x40000070;
uart_tx_flush = 0x40000074;
uart_tx_wait_idle = 0x40000078;
uart_div_modify = 0x4000007c;
multofup = 0x40000080;
software_reset = 0x40000084;
software_reset_cpu = 0x40000088;
assist_debug_clock_enable = 0x4000008c;
assist_debug_record_enable = 0x40000090;
clear_super_wdt_reset_flag = 0x40000094;
disable_default_watchdog = 0x40000098;
esp_rom_set_rtc_wake_addr = 0x4000009c;
esp_rom_get_rtc_wake_addr = 0x400000a0;
send_packet = 0x400000a4;
recv_packet = 0x400000a8;
GetUartDevice = 0x400000ac;
UartDwnLdProc = 0x400000b0;
Uart_Init = 0x400000b4;
ets_set_user_start = 0x400000b8;
/* Data (.data, .bss, .rodata) */
ets_rom_layout_p = 0x3ff1fffc;
ets_ops_table_ptr = 0x3fcdfffc;
/***************************************
Group miniz
***************************************/
/* Functions */
mz_adler32 = 0x400000bc;
mz_crc32 = 0x400000c0;
mz_free = 0x400000c4;
tdefl_compress = 0x400000c8;
tdefl_compress_buffer = 0x400000cc;
tdefl_compress_mem_to_heap = 0x400000d0;
tdefl_compress_mem_to_mem = 0x400000d4;
tdefl_compress_mem_to_output = 0x400000d8;
tdefl_get_adler32 = 0x400000dc;
tdefl_get_prev_return_status = 0x400000e0;
tdefl_init = 0x400000e4;
tdefl_write_image_to_png_file_in_memory = 0x400000e8;
tdefl_write_image_to_png_file_in_memory_ex = 0x400000ec;
tinfl_decompress = 0x400000f0;
tinfl_decompress_mem_to_callback = 0x400000f4;
tinfl_decompress_mem_to_heap = 0x400000f8;
tinfl_decompress_mem_to_mem = 0x400000fc;
/***************************************
Group tjpgd
***************************************/
/* Functions */
PROVIDE( jd_prepare = 0x40000100 );
PROVIDE( jd_decomp = 0x40000104 );
/***************************************
Group esp-dsp
***************************************/
/* Data (.data, .bss, .rodata) */
dsps_fft2r_w_table_fc32_1024 = 0x3fcdfff8;
/***************************************
Group spiflash_legacy
***************************************/
/* Functions */
PROVIDE( esp_rom_spiflash_wait_idle = 0x40000108 );
PROVIDE( esp_rom_spiflash_write_encrypted = 0x4000010c );
PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000110 );
PROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000114 );
PROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x40000118 );
PROVIDE( esp_rom_spiflash_erase_chip = 0x4000011c );
PROVIDE( esp_rom_spiflash_erase_block = 0x40000120 );
PROVIDE( esp_rom_spiflash_erase_sector = 0x40000124 );
PROVIDE( esp_rom_spiflash_write = 0x40000128 );
PROVIDE( esp_rom_spiflash_read = 0x4000012c );
PROVIDE( esp_rom_spiflash_config_param = 0x40000130 );
PROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000134 );
PROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000138 );
PROVIDE( esp_rom_spiflash_unlock = 0x4000013c );
PROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000140 );
PROVIDE( esp_rom_spi_flash_send_resume = 0x40000144 );
PROVIDE( esp_rom_spi_flash_update_id = 0x40000148 );
PROVIDE( esp_rom_spiflash_config_clk = 0x4000014c );
PROVIDE( esp_rom_spiflash_config_readmode = 0x40000150 );
PROVIDE( esp_rom_spiflash_read_status = 0x40000154 );
PROVIDE( esp_rom_spiflash_read_statushigh = 0x40000158 );
PROVIDE( esp_rom_spiflash_write_status = 0x4000015c );
PROVIDE( spi_flash_attach = 0x40000160 );
PROVIDE( spi_flash_get_chip_size = 0x40000164 );
PROVIDE( spi_flash_guard_set = 0x40000168 );
PROVIDE( spi_flash_guard_get = 0x4000016c );
PROVIDE( spi_flash_write_config_set = 0x40000170 );
PROVIDE( spi_flash_write_config_get = 0x40000174 );
PROVIDE( spi_flash_safe_write_address_func_set = 0x40000178 );
PROVIDE( spi_flash_unlock = 0x4000017c );
PROVIDE( spi_flash_erase_range = 0x40000180 );
PROVIDE( spi_flash_erase_sector = 0x40000184 );
PROVIDE( spi_flash_write = 0x40000188 );
PROVIDE( spi_flash_read = 0x4000018c );
PROVIDE( spi_flash_write_encrypted = 0x40000190 );
PROVIDE( spi_flash_read_encrypted = 0x40000194 );
PROVIDE( spi_flash_mmap_os_func_set = 0x40000198 );
PROVIDE( spi_flash_mmap_page_num_init = 0x4000019c );
PROVIDE( spi_flash_mmap = 0x400001a0 );
PROVIDE( spi_flash_mmap_pages = 0x400001a4 );
PROVIDE( spi_flash_munmap = 0x400001a8 );
PROVIDE( spi_flash_mmap_dump = 0x400001ac );
PROVIDE( spi_flash_check_and_flush_cache = 0x400001b0 );
PROVIDE( spi_flash_mmap_get_free_pages = 0x400001b4 );
PROVIDE( spi_flash_cache2phys = 0x400001b8 );
PROVIDE( spi_flash_phys2cache = 0x400001bc );
PROVIDE( spi_flash_disable_cache = 0x400001c0 );
PROVIDE( spi_flash_restore_cache = 0x400001c4 );
PROVIDE( spi_flash_cache_enabled = 0x400001c8 );
PROVIDE( spi_flash_enable_cache = 0x400001cc );
PROVIDE( spi_cache_mode_switch = 0x400001d0 );
PROVIDE( spi_common_set_dummy_output = 0x400001d4 );
PROVIDE( spi_common_set_flash_cs_timing = 0x400001d8 );
PROVIDE( esp_enable_cache_flash_wrap = 0x400001dc );
PROVIDE( SPIEraseArea = 0x400001e0 );
PROVIDE( SPILock = 0x400001e4 );
PROVIDE( SPIMasterReadModeCnfig = 0x400001e8 );
PROVIDE( SPI_Common_Command = 0x400001ec );
PROVIDE( SPI_WakeUp = 0x400001f0 );
PROVIDE( SPI_block_erase = 0x400001f4 );
PROVIDE( SPI_chip_erase = 0x400001f8 );
PROVIDE( SPI_init = 0x400001fc );
PROVIDE( SPI_page_program = 0x40000200 );
PROVIDE( SPI_read_data = 0x40000204 );
PROVIDE( SPI_sector_erase = 0x40000208 );
PROVIDE( SPI_write_enable = 0x4000020c );
PROVIDE( SelectSpiFunction = 0x40000210 );
PROVIDE( SetSpiDrvs = 0x40000214 );
PROVIDE( Wait_SPI_Idle = 0x40000218 );
PROVIDE( spi_dummy_len_fix = 0x4000021c );
PROVIDE( Disable_QMode = 0x40000220 );
PROVIDE( Enable_QMode = 0x40000224 );
/* Data (.data, .bss, .rodata) */
PROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff0 );
PROVIDE( rom_spiflash_legacy_data = 0x3fcdffec );
PROVIDE( g_flash_guard_ops = 0x3fcdfff4 );
/***************************************
Group hal_soc
***************************************/
/* Functions */
PROVIDE( spi_flash_hal_poll_cmd_done = 0x40000228 );
PROVIDE( spi_flash_hal_device_config = 0x4000022c );
PROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000230 );
PROVIDE( spi_flash_hal_common_command = 0x40000234 );
PROVIDE( spi_flash_hal_read = 0x40000238 );
PROVIDE( spi_flash_hal_erase_chip = 0x4000023c );
PROVIDE( spi_flash_hal_erase_sector = 0x40000240 );
PROVIDE( spi_flash_hal_erase_block = 0x40000244 );
PROVIDE( spi_flash_hal_program_page = 0x40000248 );
PROVIDE( spi_flash_hal_set_write_protect = 0x4000024c );
PROVIDE( spi_flash_hal_host_idle = 0x40000250 );
/***************************************
Group spi_flash_chips
***************************************/
/* Functions */
PROVIDE( spi_flash_chip_generic_probe = 0x40000254 );
PROVIDE( spi_flash_chip_generic_detect_size = 0x40000258 );
PROVIDE( spi_flash_chip_generic_write = 0x4000025c );
PROVIDE( spi_flash_chip_generic_write_encrypted = 0x40000260 );
PROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000264 );
PROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000268 );
PROVIDE( spi_flash_chip_generic_reset = 0x4000026c );
PROVIDE( spi_flash_chip_generic_erase_chip = 0x40000270 );
PROVIDE( spi_flash_chip_generic_erase_sector = 0x40000274 );
PROVIDE( spi_flash_chip_generic_erase_block = 0x40000278 );
PROVIDE( spi_flash_chip_generic_page_program = 0x4000027c );
PROVIDE( spi_flash_chip_generic_get_write_protect = 0x40000280 );
PROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x40000284 );
PROVIDE( spi_flash_chip_generic_read_reg = 0x40000288 );
PROVIDE( spi_flash_chip_generic_yield = 0x4000028c );
PROVIDE( spi_flash_generic_wait_host_idle = 0x40000290 );
PROVIDE( spi_flash_chip_generic_wait_idle = 0x40000294 );
PROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x40000298 );
PROVIDE( spi_flash_chip_generic_read = 0x4000029c );
PROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400002a0 );
PROVIDE( spi_flash_chip_generic_get_io_mode = 0x400002a4 );
PROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400002a8 );
PROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400002ac );
PROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400002b0 );
PROVIDE( spi_flash_common_set_io_mode = 0x400002b4 );
PROVIDE( spi_flash_chip_generic_set_io_mode = 0x400002b8 );
PROVIDE( spi_flash_chip_gd_get_io_mode = 0x400002bc );
PROVIDE( spi_flash_chip_gd_probe = 0x400002c0 );
PROVIDE( spi_flash_chip_gd_set_io_mode = 0x400002c4 );
/* Data (.data, .bss, .rodata) */
PROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 );
/***************************************
Group memspi_host
***************************************/
/* Functions */
PROVIDE( memspi_host_read_id_hs = 0x400002c8 );
PROVIDE( memspi_host_read_status_hs = 0x400002cc );
PROVIDE( memspi_host_flush_cache = 0x400002d0 );
PROVIDE( memspi_host_erase_chip = 0x400002d4 );
PROVIDE( memspi_host_erase_sector = 0x400002d8 );
PROVIDE( memspi_host_erase_block = 0x400002dc );
PROVIDE( memspi_host_program_page = 0x400002e0 );
PROVIDE( memspi_host_read = 0x400002e4 );
PROVIDE( memspi_host_set_write_protect = 0x400002e8 );
PROVIDE( memspi_host_set_max_read_len = 0x400002ec );
PROVIDE( memspi_host_read_data_slicer = 0x400002f0 );
PROVIDE( memspi_host_write_data_slicer = 0x400002f4 );
/***************************************
Group esp_flash
***************************************/
/* Functions */
PROVIDE( esp_flash_chip_driver_initialized = 0x400002f8 );
PROVIDE( esp_flash_read_id = 0x400002fc );
PROVIDE( esp_flash_get_size = 0x40000300 );
PROVIDE( esp_flash_erase_chip = 0x40000304 );
PROVIDE( rom_esp_flash_erase_region = 0x40000308 );
PROVIDE( esp_flash_get_chip_write_protect = 0x4000030c );
PROVIDE( esp_flash_set_chip_write_protect = 0x40000310 );
PROVIDE( esp_flash_get_protectable_regions = 0x40000314 );
PROVIDE( esp_flash_get_protected_region = 0x40000318 );
PROVIDE( esp_flash_set_protected_region = 0x4000031c );
PROVIDE( esp_flash_read = 0x40000320 );
PROVIDE( esp_flash_write = 0x40000324 );
PROVIDE( esp_flash_write_encrypted = 0x40000328 );
PROVIDE( esp_flash_read_encrypted = 0x4000032c );
PROVIDE( esp_flash_get_io_mode = 0x40000330 );
PROVIDE( esp_flash_set_io_mode = 0x40000334 );
PROVIDE( spi_flash_boot_attach = 0x40000338 );
PROVIDE( spi_flash_dump_counters = 0x4000033c );
PROVIDE( spi_flash_get_counters = 0x40000340 );
PROVIDE( spi_flash_op_counters_config = 0x40000344 );
PROVIDE( spi_flash_reset_counters = 0x40000348 );
PROVIDE( esp_flash_read_chip_id = 0x4000034c );
PROVIDE( detect_spi_flash_chip = 0x40000350 );
PROVIDE( esp_rom_spiflash_write_disable = 0x40000354 );
/* Data (.data, .bss, .rodata) */
PROVIDE( esp_flash_default_chip = 0x3fcdffe4 );
PROVIDE( esp_flash_api_funcs = 0x3fcdffe0 );
/***************************************
Group cache
***************************************/
/* Functions */
PROVIDE( Cache_Get_ICache_Line_Size = 0x400004b8 );
PROVIDE( Cache_Get_Mode = 0x400004bc );
PROVIDE( Cache_Address_Through_IBus = 0x400004c0 );
PROVIDE( Cache_Address_Through_DBus = 0x400004c4 );
PROVIDE( Cache_Set_Default_Mode = 0x400004c8 );
PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400004cc );
PROVIDE( ROM_Boot_Cache_Init = 0x400004d0 );
PROVIDE( Cache_Invalidate_ICache_Items = 0x400004d4 );
PROVIDE( Cache_Op_Addr = 0x400004d8 );
PROVIDE( Cache_Invalidate_Addr = 0x400004dc );
PROVIDE( Cache_Invalidate_ICache_All = 0x400004e0 );
PROVIDE( Cache_Mask_All = 0x400004e4 );
PROVIDE( Cache_UnMask_Dram0 = 0x400004e8 );
PROVIDE( Cache_Suspend_ICache_Autoload = 0x400004ec );
PROVIDE( Cache_Resume_ICache_Autoload = 0x400004f0 );
PROVIDE( Cache_Start_ICache_Preload = 0x400004f4 );
PROVIDE( Cache_ICache_Preload_Done = 0x400004f8 );
PROVIDE( Cache_End_ICache_Preload = 0x400004fc );
PROVIDE( Cache_Config_ICache_Autoload = 0x40000500 );
PROVIDE( Cache_Enable_ICache_Autoload = 0x40000504 );
PROVIDE( Cache_Disable_ICache_Autoload = 0x40000508 );
PROVIDE( Cache_Enable_ICache_PreLock = 0x4000050c );
PROVIDE( Cache_Disable_ICache_PreLock = 0x40000510 );
PROVIDE( Cache_Lock_ICache_Items = 0x40000514 );
PROVIDE( Cache_Unlock_ICache_Items = 0x40000518 );
PROVIDE( Cache_Lock_Addr = 0x4000051c );
PROVIDE( Cache_Unlock_Addr = 0x40000520 );
PROVIDE( Cache_Disable_ICache = 0x40000524 );
PROVIDE( Cache_Enable_ICache = 0x40000528 );
PROVIDE( Cache_Suspend_ICache = 0x4000052c );
PROVIDE( Cache_Resume_ICache = 0x40000530 );
PROVIDE( Cache_Freeze_ICache_Enable = 0x40000534 );
PROVIDE( Cache_Freeze_ICache_Disable = 0x40000538 );
PROVIDE( Cache_Pms_Lock = 0x4000053c );
PROVIDE( Cache_Ibus_Pms_Set_Addr = 0x40000540 );
PROVIDE( Cache_Ibus_Pms_Set_Attr = 0x40000544 );
PROVIDE( Cache_Dbus_Pms_Set_Addr = 0x40000548 );
PROVIDE( Cache_Dbus_Pms_Set_Attr = 0x4000054c );
PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000550 );
PROVIDE( Cache_Get_IROM_MMU_End = 0x40000554 );
PROVIDE( Cache_Get_DROM_MMU_End = 0x40000558 );
PROVIDE( Cache_Owner_Init = 0x4000055c );
PROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000560 );
PROVIDE( Cache_MMU_Init = 0x40000564 );
PROVIDE( Cache_Ibus_MMU_Set = 0x40000568 );
PROVIDE( Cache_Dbus_MMU_Set = 0x4000056c );
PROVIDE( Cache_Count_Flash_Pages = 0x40000570 );
PROVIDE( Cache_Travel_Tag_Memory = 0x40000574 );
PROVIDE( Cache_Get_Virtual_Addr = 0x40000578 );
PROVIDE( Cache_Get_Memory_BaseAddr = 0x4000057c );
PROVIDE( Cache_Get_Memory_Addr = 0x40000580 );
PROVIDE( Cache_Get_Memory_value = 0x40000584 );
/* Data (.data, .bss, .rodata) */
PROVIDE( rom_cache_op_cb = 0x3fcdffd4 );
PROVIDE( rom_cache_internal_table_ptr = 0x3fcdffd0 );
/***************************************
Group clock
***************************************/
/* Functions */
ets_get_apb_freq = 0x40000588;
ets_get_cpu_frequency = 0x4000058c;
ets_update_cpu_frequency = 0x40000590;
ets_get_printf_channel = 0x40000594;
ets_get_xtal_div = 0x40000598;
ets_set_xtal_div = 0x4000059c;
ets_get_xtal_freq = 0x400005a0;
/***************************************
Group gpio
***************************************/
/* Functions */
gpio_input_get = 0x400005a4;
gpio_matrix_in = 0x400005a8;
gpio_matrix_out = 0x400005ac;
gpio_output_disable = 0x400005b0;
gpio_output_enable = 0x400005b4;
gpio_output_set = 0x400005b8;
gpio_pad_hold = 0x400005bc;
gpio_pad_input_disable = 0x400005c0;
gpio_pad_input_enable = 0x400005c4;
gpio_pad_pulldown = 0x400005c8;
gpio_pad_pullup = 0x400005cc;
gpio_pad_select_gpio = 0x400005d0;
gpio_pad_set_drv = 0x400005d4;
gpio_pad_unhold = 0x400005d8;
gpio_pin_wakeup_disable = 0x400005dc;
gpio_pin_wakeup_enable = 0x400005e0;
gpio_bypass_matrix_in = 0x400005e4;
/***************************************
Group interrupts
***************************************/
/* Functions */
esprv_intc_int_set_priority = 0x400005e8;
esprv_intc_int_set_threshold = 0x400005ec;
esprv_intc_int_enable = 0x400005f0;
esprv_intc_int_disable = 0x400005f4;
esprv_intc_int_set_type = 0x400005f8;
intr_matrix_set = 0x400005fc;
ets_intr_lock = 0x40000600;
ets_intr_unlock = 0x40000604;
PROVIDE( intr_handler_set = 0x40000608 );
ets_isr_attach = 0x4000060c;
ets_isr_mask = 0x40000610;
ets_isr_unmask = 0x40000614;
/***************************************
Group crypto
***************************************/
/* Functions */
md5_vector = 0x40000618;
MD5Init = 0x4000061c;
MD5Update = 0x40000620;
MD5Final = 0x40000624;
hmac_md5_vector = 0x40000628;
hmac_md5 = 0x4000062c;
crc32_le = 0x40000630;
crc32_be = 0x40000634;
crc16_le = 0x40000638;
crc16_be = 0x4000063c;
crc8_le = 0x40000640;
crc8_be = 0x40000644;
esp_crc8 = 0x40000648;
ets_sha_enable = 0x4000064c;
ets_sha_disable = 0x40000650;
ets_sha_get_state = 0x40000654;
ets_sha_init = 0x40000658;
ets_sha_process = 0x4000065c;
ets_sha_starts = 0x40000660;
ets_sha_update = 0x40000664;
ets_sha_finish = 0x40000668;
ets_sha_clone = 0x4000066c;
ets_hmac_enable = 0x40000670;
ets_hmac_disable = 0x40000674;
ets_hmac_calculate_message = 0x40000678;
ets_hmac_calculate_downstream = 0x4000067c;
ets_hmac_invalidate_downstream = 0x40000680;
ets_jtag_enable_temporarily = 0x40000684;
ets_aes_enable = 0x40000688;
ets_aes_disable = 0x4000068c;
ets_aes_setkey = 0x40000690;
ets_aes_block = 0x40000694;
ets_bigint_enable = 0x40000698;
ets_bigint_disable = 0x4000069c;
ets_bigint_multiply = 0x400006a0;
ets_bigint_modmult = 0x400006a4;
ets_bigint_modexp = 0x400006a8;
ets_bigint_wait_finish = 0x400006ac;
ets_bigint_getz = 0x400006b0;
ets_ds_enable = 0x400006b4;
ets_ds_disable = 0x400006b8;
ets_ds_start_sign = 0x400006bc;
ets_ds_is_busy = 0x400006c0;
ets_ds_finish_sign = 0x400006c4;
ets_ds_encrypt_params = 0x400006c8;
ets_aes_setkey_dec = 0x400006cc;
ets_aes_setkey_enc = 0x400006d0;
ets_mgf1_sha256 = 0x400006d4;
/***************************************
Group efuse
***************************************/
/* Functions */
ets_efuse_read = 0x400006d8;
ets_efuse_program = 0x400006dc;
ets_efuse_clear_program_registers = 0x400006e0;
ets_efuse_write_key = 0x400006e4;
ets_efuse_get_read_register_address = 0x400006e8;
ets_efuse_get_key_purpose = 0x400006ec;
ets_efuse_key_block_unused = 0x400006f0;
ets_efuse_find_unused_key_block = 0x400006f4;
ets_efuse_rs_calculate = 0x400006f8;
ets_efuse_count_unused_key_blocks = 0x400006fc;
ets_efuse_secure_boot_enabled = 0x40000700;
ets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000704;
ets_efuse_cache_encryption_enabled = 0x40000708;
ets_efuse_download_modes_disabled = 0x4000070c;
ets_efuse_find_purpose = 0x40000710;
ets_efuse_flash_opi_5pads_power_sel_vddspi = 0x40000714;
ets_efuse_force_send_resume = 0x40000718;
ets_efuse_get_flash_delay_us = 0x4000071c;
ets_efuse_get_mac = 0x40000720;
ets_efuse_get_spiconfig = 0x40000724;
ets_efuse_usb_print_is_disabled = 0x40000728;
/*ets_efuse_get_uart_print_channel = 0x4000072c;*/
ets_efuse_usb_serial_jtag_print_is_disabled = 0x4000072c;
ets_efuse_get_uart_print_control = 0x40000730;
ets_efuse_get_wp_pad = 0x40000734;
ets_efuse_direct_boot_mode_disabled = 0x40000738;
ets_efuse_security_download_modes_enabled = 0x4000073c;
ets_efuse_set_timing = 0x40000740;
ets_efuse_jtag_disabled = 0x40000744;
ets_efuse_usb_download_mode_disabled = 0x40000748;
ets_efuse_usb_module_disabled = 0x4000074c;
ets_efuse_usb_device_disabled = 0x40000750;
ets_efuse_secure_boot_fast_wake_enabled = 0x40000754;
/***************************************
Group secureboot
***************************************/
/* Functions */
ets_emsa_pss_verify = 0x40000758;
ets_rsa_pss_verify = 0x4000075c;
ets_secure_boot_verify_bootloader_with_keys = 0x40000760;
ets_secure_boot_verify_signature = 0x40000764;
ets_secure_boot_read_key_digests = 0x40000768;
ets_secure_boot_revoke_public_key_digest = 0x4000076c;
/***************************************
Group usb_uart
***************************************/
/* Functions */
PROVIDE( usb_uart_device_rx_one_char = 0x400008d8 );
PROVIDE( usb_uart_device_rx_one_char_block = 0x400008dc );
PROVIDE( usb_uart_device_tx_flush = 0x400008e0 );
PROVIDE( usb_uart_device_tx_one_char = 0x400008e4 );
/* Data (.data, .bss, .rodata) */
PROVIDE( g_uart_print = 0x3fcdffcd );
PROVIDE( g_usb_print = 0x3fcdffcc );
/***************************************
Group rom_phy
***************************************/
/* Functions */
phy_get_romfuncs = 0x400008e8;
rom_abs_temp = 0x400008ec;
rom_bb_bss_cbw40_dig = 0x400008f0;
rom_bb_wdg_test_en = 0x400008f4;
rom_bb_wdt_get_status = 0x400008f8;
rom_bb_wdt_int_enable = 0x400008fc;
rom_bb_wdt_rst_enable = 0x40000900;
rom_bb_wdt_timeout_clear = 0x40000904;
rom_cbw2040_cfg = 0x40000908;
rom_check_noise_floor = 0x4000090c;
rom_chip_i2c_readReg = 0x40000910;
rom_chip_i2c_writeReg = 0x40000914;
rom_correct_rf_ana_gain = 0x40000918;
rom_dc_iq_est = 0x4000091c;
rom_disable_agc = 0x40000920;
rom_en_pwdet = 0x40000924;
rom_enable_agc = 0x40000928;
rom_get_bbgain_db = 0x4000092c;
rom_get_data_sat = 0x40000930;
rom_get_i2c_read_mask = 0x40000934;
rom_get_pwctrl_correct = 0x40000938;
rom_get_rf_gain_qdb = 0x4000093c;
rom_i2c_readReg = 0x40000940;
rom_i2c_readReg_Mask = 0x40000944;
rom_i2c_writeReg = 0x40000948;
rom_i2c_writeReg_Mask = 0x4000094c;
rom_index_to_txbbgain = 0x40000950;
rom_iq_est_disable = 0x40000954;
rom_iq_est_enable = 0x40000958;
rom_linear_to_db = 0x4000095c;
rom_loopback_mode_en = 0x40000960;
rom_mhz2ieee = 0x40000964;
rom_noise_floor_auto_set = 0x40000968;
rom_pbus_debugmode = 0x4000096c;
rom_pbus_force_mode = 0x40000970;
rom_pbus_force_test = 0x40000974;
rom_pbus_rd = 0x40000978;
rom_pbus_rd_addr = 0x4000097c;
rom_pbus_rd_shift = 0x40000980;
rom_pbus_set_dco = 0x40000984;
rom_pbus_set_rxgain = 0x40000988;
rom_pbus_workmode = 0x4000098c;
rom_pbus_xpd_rx_off = 0x40000990;
rom_pbus_xpd_rx_on = 0x40000994;
rom_pbus_xpd_tx_off = 0x40000998;
rom_pbus_xpd_tx_on = 0x4000099c;
rom_phy_byte_to_word = 0x400009a0;
rom_phy_disable_cca = 0x400009a4;
rom_phy_enable_cca = 0x400009a8;
rom_phy_get_noisefloor = 0x400009ac;
rom_phy_get_rx_freq = 0x400009b0;
rom_phy_set_bbfreq_init = 0x400009b4;
rom_pow_usr = 0x400009b8;
rom_pwdet_sar2_init = 0x400009bc;
rom_read_hw_noisefloor = 0x400009c0;
rom_read_sar_dout = 0x400009c4;
rom_set_cal_rxdc = 0x400009c8;
rom_set_chan_cal_interp = 0x400009cc;
rom_set_loopback_gain = 0x400009d0;
rom_set_noise_floor = 0x400009d4;
rom_set_rxclk_en = 0x400009d8;
rom_set_tx_dig_gain = 0x400009dc;
rom_set_txcap_reg = 0x400009e0;
rom_set_txclk_en = 0x400009e4;
rom_spur_cal = 0x400009e8;
rom_spur_reg_write_one_tone = 0x400009ec;
rom_target_power_add_backoff = 0x400009f0;
rom_tx_pwctrl_bg_init = 0x400009f4;
rom_txbbgain_to_index = 0x400009f8;
rom_wifi_11g_rate_chg = 0x400009fc;
rom_write_gain_mem = 0x40000a00;
chip726_phyrom_version = 0x40000a04;
rom_disable_wifi_agc = 0x40000a08;
rom_enable_wifi_agc = 0x40000a0c;
rom_set_tx_gain_table = 0x40000a10;
rom_bt_index_to_bb = 0x40000a14;
rom_bt_bb_to_index = 0x40000a18;
rom_wr_bt_tx_atten = 0x40000a1c;
rom_wr_bt_tx_gain_mem = 0x40000a20;
rom_spur_coef_cfg = 0x40000a24;
rom_bb_bss_cbw40 = 0x40000a28;
rom_set_cca = 0x40000a2c;
rom_tx_paon_set = 0x40000a30;
rom_i2cmst_reg_init = 0x40000a34;
rom_iq_corr_enable = 0x40000a38;
rom_fe_reg_init = 0x40000a3c;
rom_agc_reg_init = 0x40000a40;
rom_bb_reg_init = 0x40000a44;
rom_mac_enable_bb = 0x40000a48;
rom_bb_wdg_cfg = 0x40000a4c;
rom_force_txon = 0x40000a50;
rom_fe_txrx_reset = 0x40000a54;
rom_set_rx_comp = 0x40000a58;
rom_set_pbus_reg = 0x40000a5c;
rom_write_chan_freq = 0x40000a60;
rom_phy_xpd_rf = 0x40000a64;
rom_set_xpd_sar = 0x40000a68;
rom_write_dac_gain2 = 0x40000a6c;
rom_rtc_sar2_init = 0x40000a70;
rom_get_target_power_offset = 0x40000a74;
rom_write_txrate_power_offset = 0x40000a78;
rom_get_rate_fcc_index = 0x40000a7c;
rom_get_rate_target_power = 0x40000a80;
rom_write_wifi_dig_gain = 0x40000a84;
rom_bt_correct_rf_ana_gain = 0x40000a88;
rom_pkdet_vol_start = 0x40000a8c;
rom_read_sar2_code = 0x40000a90;
rom_get_sar2_vol = 0x40000a94;
rom_get_pll_vol = 0x40000a98;
rom_get_phy_target_power = 0x40000a9c;
rom_temp_to_power = 0x40000aa0;
rom_phy_track_pll_cap = 0x40000aa4;
rom_phy_pwdet_always_en = 0x40000aa8;
rom_phy_pwdet_onetime_en = 0x40000aac;
rom_get_i2c_mst0_mask = 0x40000ab0;
rom_get_i2c_hostid = 0x40000ab4;
rom_enter_critical_phy = 0x40000ab8;
rom_exit_critical_phy = 0x40000abc;
rom_chip_i2c_readReg_org = 0x40000ac0;
rom_i2c_paral_set_mst0 = 0x40000ac4;
rom_i2c_paral_set_read = 0x40000ac8;
rom_i2c_paral_read = 0x40000acc;
rom_i2c_paral_write = 0x40000ad0;
rom_i2c_paral_write_num = 0x40000ad4;
rom_i2c_paral_write_mask = 0x40000ad8;
rom_bb_bss_cbw40_ana = 0x40000adc;
rom_chan_to_freq = 0x40000ae0;
rom_open_i2c_xpd = 0x40000ae4;
rom_dac_rate_set = 0x40000ae8;
rom_tsens_read_init = 0x40000aec;
rom_tsens_code_read = 0x40000af0;
rom_tsens_index_to_dac = 0x40000af4;
rom_tsens_index_to_offset = 0x40000af8;
rom_tsens_dac_cal = 0x40000afc;
rom_code_to_temp = 0x40000b00;
rom_write_pll_cap_mem = 0x40000b04;
rom_pll_correct_dcap = 0x40000b08;
rom_phy_en_hw_set_freq = 0x40000b0c;
rom_phy_dis_hw_set_freq = 0x40000b10;
rom_pll_vol_cal = 0x40000b14;
rom_wrtie_pll_cap = 0x40000b18;
rom_set_tx_gain_mem = 0x40000b1c;
rom_bt_tx_dig_gain = 0x40000b20;
rom_bt_get_tx_gain = 0x40000b24;
rom_get_chan_target_power = 0x40000b28;
rom_get_tx_gain_value = 0x40000b2c;
rom_wifi_tx_dig_gain = 0x40000b30;
rom_wifi_get_tx_gain = 0x40000b34;
rom_fe_i2c_reg_renew = 0x40000b38;
rom_wifi_agc_sat_gain = 0x40000b3c;
rom_i2c_master_reset = 0x40000b40;
rom_bt_filter_reg = 0x40000b44;
rom_phy_bbpll_cal = 0x40000b48;
rom_i2c_sar2_init_code = 0x40000b4c;
rom_phy_param_addr = 0x40000b50;
rom_phy_reg_init = 0x40000b54;
rom_set_chan_reg = 0x40000b58;
rom_phy_wakeup_init = 0x40000b5c;
rom_phy_i2c_init1 = 0x40000b60;
rom_tsens_temp_read = 0x40000b64;
rom_bt_track_pll_cap = 0x40000b68;
rom_wifi_track_pll_cap = 0x40000b6c;
rom_wifi_set_tx_gain = 0x40000b70;
rom_txpwr_cal_track = 0x40000b74;
rom_tx_pwctrl_background = 0x40000b78;
rom_bt_set_tx_gain = 0x40000b7c;
rom_noise_check_loop = 0x40000b80;
rom_phy_close_rf = 0x40000b84;
rom_phy_xpd_tsens = 0x40000b88;
rom_phy_freq_mem_backup = 0x40000b8c;
rom_phy_ant_init = 0x40000b90;
rom_bt_track_tx_power = 0x40000b94;
rom_wifi_track_tx_power = 0x40000b98;
rom_phy_dig_reg_backup = 0x40000b9c;
chip726_phyrom_version_num = 0x40000ba0;
/* Data (.data, .bss, .rodata) */
phy_param_rom = 0x3fcdffc8;

111
components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.libgcc.ld
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@ -1,111 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32b1z.rom.libgcc.ld for esp32b1z
*
*
* Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group libgcc
***************************************/
/* Functions */
__absvdi2 = 0x40000770;
__absvsi2 = 0x40000774;
__adddf3 = 0x40000778;
__addsf3 = 0x4000077c;
__addvdi3 = 0x40000780;
__addvsi3 = 0x40000784;
__ashldi3 = 0x40000788;
__ashrdi3 = 0x4000078c;
__bswapdi2 = 0x40000790;
__bswapsi2 = 0x40000794;
__clear_cache = 0x40000798;
__clrsbdi2 = 0x4000079c;
__clrsbsi2 = 0x400007a0;
__clzdi2 = 0x400007a4;
__clzsi2 = 0x400007a8;
__cmpdi2 = 0x400007ac;
__ctzdi2 = 0x400007b0;
__ctzsi2 = 0x400007b4;
__divdc3 = 0x400007b8;
__divdf3 = 0x400007bc;
__divdi3 = 0x400007c0;
__divsc3 = 0x400007c4;
__divsf3 = 0x400007c8;
__divsi3 = 0x400007cc;
__eqdf2 = 0x400007d0;
__eqsf2 = 0x400007d4;
__extendsfdf2 = 0x400007d8;
__ffsdi2 = 0x400007dc;
__ffssi2 = 0x400007e0;
__fixdfdi = 0x400007e4;
__fixdfsi = 0x400007e8;
__fixsfdi = 0x400007ec;
__fixsfsi = 0x400007f0;
__fixunsdfsi = 0x400007f4;
__fixunssfdi = 0x400007f8;
__fixunssfsi = 0x400007fc;
__floatdidf = 0x40000800;
__floatdisf = 0x40000804;
__floatsidf = 0x40000808;
__floatsisf = 0x4000080c;
__floatundidf = 0x40000810;
__floatundisf = 0x40000814;
__floatunsidf = 0x40000818;
__floatunsisf = 0x4000081c;
__gcc_bcmp = 0x40000820;
__gedf2 = 0x40000824;
__gesf2 = 0x40000828;
__gtdf2 = 0x4000082c;
__gtsf2 = 0x40000830;
__ledf2 = 0x40000834;
__lesf2 = 0x40000838;
__lshrdi3 = 0x4000083c;
__ltdf2 = 0x40000840;
__ltsf2 = 0x40000844;
__moddi3 = 0x40000848;
__modsi3 = 0x4000084c;
__muldc3 = 0x40000850;
__muldf3 = 0x40000854;
__muldi3 = 0x40000858;
__mulsc3 = 0x4000085c;
__mulsf3 = 0x40000860;
__mulsi3 = 0x40000864;
__mulvdi3 = 0x40000868;
__mulvsi3 = 0x4000086c;
__nedf2 = 0x40000870;
__negdf2 = 0x40000874;
__negdi2 = 0x40000878;
__negsf2 = 0x4000087c;
__negvdi2 = 0x40000880;
__negvsi2 = 0x40000884;
__nesf2 = 0x40000888;
__paritysi2 = 0x4000088c;
__popcountdi2 = 0x40000890;
__popcountsi2 = 0x40000894;
__powidf2 = 0x40000898;
__powisf2 = 0x4000089c;
__subdf3 = 0x400008a0;
__subsf3 = 0x400008a4;
__subvdi3 = 0x400008a8;
__subvsi3 = 0x400008ac;
__truncdfsf2 = 0x400008b0;
__ucmpdi2 = 0x400008b4;
__udivdi3 = 0x400008b8;
__udivmoddi4 = 0x400008bc;
__udivsi3 = 0x400008c0;
__udiv_w_sdiv = 0x400008c4;
__umoddi3 = 0x400008c8;
__umodsi3 = 0x400008cc;
__unorddf2 = 0x400008d0;
__unordsf2 = 0x400008d4;

33
components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.newlib-nano.ld
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@ -1,33 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32b1z.rom.newlib-nano.ld for esp32b1z
*
*
* Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group newlib_nano_format
***************************************/
/* Functions */
__sprint_r = 0x40000488;
_fiprintf_r = 0x4000048c;
_fprintf_r = 0x40000490;
_printf_common = 0x40000494;
_printf_i = 0x40000498;
_vfiprintf_r = 0x4000049c;
_vfprintf_r = 0x400004a0;
fiprintf = 0x400004a4;
fprintf = 0x400004a8;
printf = 0x400004ac;
vfiprintf = 0x400004b0;
vfprintf = 0x400004b4;

96
components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.newlib.ld
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/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32b1z.rom.newlib.ld for esp32b1z
*
*
* Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group newlib
***************************************/
/* Functions */
esp_rom_newlib_init_common_mutexes = 0x40000358;
memset = 0x4000035c;
memcpy = 0x40000360;
memmove = 0x40000364;
memcmp = 0x40000368;
strcpy = 0x4000036c;
strncpy = 0x40000370;
strcmp = 0x40000374;
strncmp = 0x40000378;
strlen = 0x4000037c;
strstr = 0x40000380;
bzero = 0x40000384;
sbrk = 0x4000038c;
isalnum = 0x40000390;
isalpha = 0x40000394;
isascii = 0x40000398;
isblank = 0x4000039c;
iscntrl = 0x400003a0;
isdigit = 0x400003a4;
islower = 0x400003a8;
isgraph = 0x400003ac;
isprint = 0x400003b0;
ispunct = 0x400003b4;
isspace = 0x400003b8;
isupper = 0x400003bc;
toupper = 0x400003c0;
tolower = 0x400003c4;
toascii = 0x400003c8;
memccpy = 0x400003cc;
memchr = 0x400003d0;
memrchr = 0x400003d4;
strcasecmp = 0x400003d8;
strcasestr = 0x400003dc;
strcat = 0x400003e0;
strdup = 0x400003e4;
strchr = 0x400003e8;
strcspn = 0x400003ec;
strcoll = 0x400003f0;
strlcat = 0x400003f4;
strlcpy = 0x400003f8;
strlwr = 0x400003fc;
strncasecmp = 0x40000400;
strncat = 0x40000404;
strndup = 0x40000408;
strnlen = 0x4000040c;
strrchr = 0x40000410;
strsep = 0x40000414;
strspn = 0x40000418;
strtok_r = 0x4000041c;
strupr = 0x40000420;
longjmp = 0x40000424;
setjmp = 0x40000428;
abs = 0x4000042c;
div = 0x40000430;
labs = 0x40000434;
ldiv = 0x40000438;
qsort = 0x4000043c;
rand_r = 0x40000440;
rand = 0x40000444;
srand = 0x40000448;
utoa = 0x4000044c;
itoa = 0x40000450;
atoi = 0x40000454;
atol = 0x40000458;
strtol = 0x4000045c;
strtoul = 0x40000460;
PROVIDE( fflush = 0x40000464 );
PROVIDE( _fflush_r = 0x40000468 );
PROVIDE( _fwalk = 0x4000046c );
PROVIDE( _fwalk_reent = 0x40000470 );
PROVIDE( __swbuf_r = 0x4000047c );
__swbuf = 0x40000480;
/* Data (.data, .bss, .rodata) */
syscall_table_ptr = 0x3fcdffdc;
_global_impure_ptr = 0x3fcdffd8;

14
components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.version.ld
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@ -1,14 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM version variables for esp32b1z
*
* These addresses should be compatible with any ROM version for this chip.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
_rom_chip_id = 0x40000010;
_rom_eco_version = 0x40000014;

61
components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.api.ld
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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/** ROM APIs
*/
PROVIDE ( esp_rom_crc32_le = crc32_le );
PROVIDE ( esp_rom_crc16_le = crc16_le );
PROVIDE ( esp_rom_crc8_le = crc8_le );
PROVIDE ( esp_rom_crc32_be = crc32_be );
PROVIDE ( esp_rom_crc16_be = crc16_be );
PROVIDE ( esp_rom_crc8_be = crc8_be );
PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio );
PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup );
PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv );
PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold );
PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in );
PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );
PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 );
PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig );
PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled );
PROVIDE ( esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad );
PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush );
PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char );
PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle );
PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char );
PROVIDE ( esp_rom_uart_rx_string = UartRxString );
PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
PROVIDE ( esp_rom_uart_putc = ets_write_char_uart );
PROVIDE ( esp_rom_md5_init = MD5Init );
PROVIDE ( esp_rom_md5_update = MD5Update );
PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_software_reset_system = software_reset );
PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);
PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea );
PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix );
PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs);
PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction );
PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command );
PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg );
PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask );
PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg );
PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask );

1707
components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.ld
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112
components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.libgcc.ld
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@ -1,112 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32h4.rom.libgcc.ld for esp32h4
*
*
* Generated from ./target/esp32h4/interface-esp32h4.yml md5sum da4c474a48c097d4ac9acad67f70fda6
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group libgcc
***************************************/
/* Functions */
__absvdi2 = 0x40000998;
__absvsi2 = 0x4000099c;
__adddf3 = 0x400009a0;
__addsf3 = 0x400009a4;
__addvdi3 = 0x400009a8;
__addvsi3 = 0x400009ac;
__ashldi3 = 0x400009b0;
__ashrdi3 = 0x400009b4;
__bswapdi2 = 0x400009b8;
__bswapsi2 = 0x400009bc;
__clear_cache = 0x400009c0;
__clrsbdi2 = 0x400009c4;
__clrsbsi2 = 0x400009c8;
__clzdi2 = 0x400009cc;
__clzsi2 = 0x400009d0;
__cmpdi2 = 0x400009d4;
__ctzdi2 = 0x400009d8;
__ctzsi2 = 0x400009dc;
__divdc3 = 0x400009e0;
__divdf3 = 0x400009e4;
__divdi3 = 0x400009e8;
__divsc3 = 0x400009ec;
__divsf3 = 0x400009f0;
__divsi3 = 0x400009f4;
__eqdf2 = 0x400009f8;
__eqsf2 = 0x400009fc;
__extendsfdf2 = 0x40000a00;
__ffsdi2 = 0x40000a04;
__ffssi2 = 0x40000a08;
__fixdfdi = 0x40000a0c;
__fixdfsi = 0x40000a10;
__fixsfdi = 0x40000a14;
__fixsfsi = 0x40000a18;
__fixunsdfsi = 0x40000a1c;
__fixunssfdi = 0x40000a20;
__fixunssfsi = 0x40000a24;
__floatdidf = 0x40000a28;
__floatdisf = 0x40000a2c;
__floatsidf = 0x40000a30;
__floatsisf = 0x40000a34;
__floatundidf = 0x40000a38;
__floatundisf = 0x40000a3c;
__floatunsidf = 0x40000a40;
__floatunsisf = 0x40000a44;
__gcc_bcmp = 0x40000a48;
__gedf2 = 0x40000a4c;
__gesf2 = 0x40000a50;
__gtdf2 = 0x40000a54;
__gtsf2 = 0x40000a58;
__ledf2 = 0x40000a5c;
__lesf2 = 0x40000a60;
__lshrdi3 = 0x40000a64;
__ltdf2 = 0x40000a68;
__ltsf2 = 0x40000a6c;
__moddi3 = 0x40000a70;
__modsi3 = 0x40000a74;
__muldc3 = 0x40000a78;
__muldf3 = 0x40000a7c;
__muldi3 = 0x40000a80;
__mulsc3 = 0x40000a84;
__mulsf3 = 0x40000a88;
__mulsi3 = 0x40000a8c;
__mulvdi3 = 0x40000a90;
__mulvsi3 = 0x40000a94;
__nedf2 = 0x40000a98;
__negdf2 = 0x40000a9c;
__negdi2 = 0x40000aa0;
__negsf2 = 0x40000aa4;
__negvdi2 = 0x40000aa8;
__negvsi2 = 0x40000aac;
__nesf2 = 0x40000ab0;
__paritysi2 = 0x40000ab4;
__popcountdi2 = 0x40000ab8;
__popcountsi2 = 0x40000abc;
__powidf2 = 0x40000ac0;
__powisf2 = 0x40000ac4;
__subdf3 = 0x40000ac8;
__subsf3 = 0x40000acc;
__subvdi3 = 0x40000ad0;
__subvsi3 = 0x40000ad4;
__truncdfsf2 = 0x40000ad8;
__ucmpdi2 = 0x40000adc;
__udivdi3 = 0x40000ae0;
__udivmoddi4 = 0x40000ae4;
__udivsi3 = 0x40000ae8;
__udiv_w_sdiv = 0x40000aec;
__umoddi3 = 0x40000af0;
__umodsi3 = 0x40000af4;
__unorddf2 = 0x40000af8;
__unordsf2 = 0x40000afc;
__extenddftf2 = 0x40000b00;
__trunctfdf2 = 0x40000b04;

47
components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.newlib-nano.ld
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@ -1,47 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32h4.rom.newlib-nano.ld for esp32h4
*
*
* Generated from ./target/esp32h4/interface-esp32h4.yml md5sum da4c474a48c097d4ac9acad67f70fda6
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group newlib_nano_format
***************************************/
/* Functions */
__sprint_r = 0x40000684;
_fiprintf_r = 0x40000688;
_fprintf_r = 0x4000068c;
_printf_common = 0x40000690;
_printf_i = 0x40000694;
_vfiprintf_r = 0x40000698;
_vfprintf_r = 0x4000069c;
fiprintf = 0x400006a0;
fprintf = 0x400006a4;
printf = 0x400006a8;
vfiprintf = 0x400006ac;
vfprintf = 0x400006b0;
asprintf = 0x400006b4;
sprintf = 0x400006b8;
snprintf = 0x400006bc;
siprintf = 0x400006c0;
sniprintf = 0x400006c4;
vprintf = 0x400006c8;
viprintf = 0x400006cc;
vsnprintf = 0x400006d0;
vsniprintf = 0x400006d4;
_printf_float = 0x400006d8;
_scanf_float = 0x400006dc;
_scanf_i = 0x400006e0;
_scanf_chars = 0x400006e4;
sscanf = 0x400006e8;
siscanf = 0x400006ec;

143
components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.newlib.ld
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@ -1,143 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32h4.rom.newlib.ld for esp32h4
*
*
* Generated from ./target/esp32h4/interface-esp32h4.yml md5sum da4c474a48c097d4ac9acad67f70fda6
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group newlib
***************************************/
/* Functions */
esp_rom_newlib_init_common_mutexes = 0x40000494;
memset = 0x40000498;
memcpy = 0x4000049c;
memmove = 0x400004a0;
memcmp = 0x400004a4;
strcpy = 0x400004a8;
strncpy = 0x400004ac;
strcmp = 0x400004b0;
strncmp = 0x400004b4;
strlen = 0x400004b8;
strstr = 0x400004bc;
bzero = 0x400004c0;
sbrk = 0x400004c8;
isalnum = 0x400004cc;
isalpha = 0x400004d0;
isascii = 0x400004d4;
isblank = 0x400004d8;
iscntrl = 0x400004dc;
isdigit = 0x400004e0;
islower = 0x400004e4;
isgraph = 0x400004e8;
isprint = 0x400004ec;
ispunct = 0x400004f0;
isspace = 0x400004f4;
isupper = 0x400004f8;
toupper = 0x400004fc;
tolower = 0x40000500;
toascii = 0x40000504;
memccpy = 0x40000508;
memchr = 0x4000050c;
memrchr = 0x40000510;
strcasecmp = 0x40000514;
strcasestr = 0x40000518;
strcat = 0x4000051c;
strdup = 0x40000520;
strchr = 0x40000524;
strcspn = 0x40000528;
strcoll = 0x4000052c;
strlcat = 0x40000530;
strlcpy = 0x40000534;
strlwr = 0x40000538;
strncasecmp = 0x4000053c;
strncat = 0x40000540;
strndup = 0x40000544;
strnlen = 0x40000548;
strrchr = 0x4000054c;
strsep = 0x40000550;
strspn = 0x40000554;
strtok_r = 0x40000558;
strupr = 0x4000055c;
longjmp = 0x40000560;
setjmp = 0x40000564;
abs = 0x40000568;
div = 0x4000056c;
labs = 0x40000570;
ldiv = 0x40000574;
qsort = 0x40000578;
rand_r = 0x4000057c;
rand = 0x40000580;
srand = 0x40000584;
utoa = 0x40000588;
itoa = 0x4000058c;
atoi = 0x40000590;
atol = 0x40000594;
strtol = 0x40000598;
strtoul = 0x4000059c;
fflush = 0x400005a0;
_fflush_r = 0x400005a4;
_fwalk = 0x400005a8;
_fwalk_reent = 0x400005ac;
__swbuf_r = 0x400005b8;
__swbuf = 0x400005bc;
_strtod_l = 0x400005c4;
_strtod_r = 0x400005c8;
strtod_l = 0x400005cc;
strtod = 0x400005d0;
strtof_l = 0x400005d4;
strtof = 0x400005d8;
_strtol_r = 0x400005dc;
strtol_l = 0x400005e0;
_strtoul_r = 0x400005e4;
strtoul_l = 0x400005e8;
__match = 0x400005ec;
__hexnan = 0x400005f0;
__hexdig_fun = 0x400005f4;
__gethex = 0x400005f8;
_Balloc = 0x400005fc;
_Bfree = 0x40000600;
__multadd = 0x40000604;
__s2b = 0x40000608;
__hi0bits = 0x4000060c;
__lo0bits = 0x40000610;
__i2b = 0x40000614;
__multiply = 0x40000618;
__pow5mult = 0x4000061c;
__lshift = 0x40000620;
__mcmp = 0x40000624;
__mdiff = 0x40000628;
__ulp = 0x4000062c;
__b2d = 0x40000630;
__d2b = 0x40000634;
__ratio = 0x40000638;
_mprec_log10 = 0x4000063c;
__copybits = 0x40000640;
__any_on = 0x40000644;
asctime = 0x40000648;
asctime_r = 0x4000064c;
atof = 0x40000650;
atoff = 0x40000654;
_dtoa_r = 0x40000658;
_wctomb_r = 0x4000065c;
__ascii_wctomb = 0x40000660;
_mbtowc_r = 0x40000664;
__ascii_mbtowc = 0x40000668;
puts = 0x4000066c;
putc = 0x40000670;
putchar = 0x40000674;
nan = 0x40000678;
nanf = 0x4000067c;
__errno = 0x40000680;
/* Data (.data, .bss, .rodata) */
syscall_table_ptr = 0x3fcdffd4;
_global_impure_ptr = 0x3fcdffd0;

13
components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.version.ld
View File

@ -1,13 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM version variables for esp32h4
*
* These addresses should be compatible with any ROM version for this chip.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
_rom_chip_id = 0x40000010;
_rom_eco_version = 0x40000014;

46
components/esp_rom/include/esp32h4/rom/aes.h
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@ -1,46 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_AES_H_
#define _ROM_AES_H_
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
#define AES_BLOCK_SIZE 16
enum AES_TYPE {
AES_ENC,
AES_DEC,
};
enum AES_BITS {
AES128,
AES192,
AES256
};
void ets_aes_enable(void);
void ets_aes_disable(void);
int ets_aes_setkey(enum AES_TYPE type, const void *key, enum AES_BITS bits);
int ets_aes_setkey_enc(const void *key, enum AES_BITS bits);
int ets_aes_setkey_dec(const void *key, enum AES_BITS bits);
void ets_aes_block(const void *input, void *output);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_AES_H_ */

17
components/esp_rom/include/esp32h4/rom/apb_backup_dma.h
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@ -1,17 +0,0 @@
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
void ets_apb_backup_init_lock_func(void(* _apb_backup_lock)(void), void(* _apb_backup_unlock)(void));
#ifdef __cplusplus
}
#endif

35
components/esp_rom/include/esp32h4/rom/bigint.h
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@ -1,35 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_BIGINT_H_
#define _ROM_BIGINT_H_
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
void ets_bigint_enable(void);
void ets_bigint_disable(void);
int ets_bigint_multiply(const uint32_t *x, const uint32_t *y, uint32_t len_words);
int ets_bigint_modmult(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, uint32_t len_words);
int ets_bigint_modexp(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, bool constant_time, uint32_t len_words);
void ets_bigint_wait_finish(void);
int ets_bigint_getz(uint32_t *z, uint32_t len_words);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_BIGINT_H_ */

750
components/esp_rom/include/esp32h4/rom/cache.h
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@ -1,750 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_CACHE_H_
#define _ROM_CACHE_H_
#include <stdint.h>
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup cache_apis, cache operation related apis
* @brief cache apis
*/
/** @addtogroup cache_apis
* @{
*/
#define MIN_ICACHE_SIZE 16384
#define MAX_ICACHE_SIZE 16384
#define MIN_ICACHE_WAYS 8
#define MAX_ICACHE_WAYS 8
#define MAX_CACHE_WAYS 8
#define MIN_CACHE_LINE_SIZE 32
#define TAG_SIZE 4
#define MIN_ICACHE_BANK_NUM 1
#define MAX_ICACHE_BANK_NUM 1
#define CACHE_MEMORY_BANK_NUM 1
#define CACHE_MEMORY_IBANK_SIZE 0x4000
#define MAX_ITAG_BANK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MIN_CACHE_LINE_SIZE)
#define MAX_ITAG_BLOCK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MAX_ICACHE_WAYS / MIN_CACHE_LINE_SIZE)
#define MAX_ITAG_BANK_SIZE (MAX_ITAG_BANK_ITEMS * TAG_SIZE)
#define MAX_ITAG_BLOCK_SIZE (MAX_ITAG_BLOCK_ITEMS * TAG_SIZE)
typedef enum {
CACHE_DCACHE = 0,
CACHE_ICACHE0 = 1,
CACHE_ICACHE1 = 2,
} cache_t;
typedef enum {
CACHE_MEMORY_INVALID = 0,
CACHE_MEMORY_IBANK0 = BIT(0),
CACHE_MEMORY_IBANK1 = BIT(1),
CACHE_MEMORY_IBANK2 = BIT(2),
CACHE_MEMORY_IBANK3 = BIT(3),
CACHE_MEMORY_DBANK0 = BIT(0),
CACHE_MEMORY_DBANK1 = BIT(1),
CACHE_MEMORY_DBANK2 = BIT(2),
CACHE_MEMORY_DBANK3 = BIT(3),
} cache_array_t;
#define ICACHE_SIZE_16KB CACHE_SIZE_HALF
#define ICACHE_SIZE_32KB CACHE_SIZE_FULL
#define DCACHE_SIZE_32KB CACHE_SIZE_HALF
#define DCACHE_SIZE_64KB CACHE_SIZE_FULL
typedef enum {
CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */
CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */
} cache_size_t;
typedef enum {
CACHE_4WAYS_ASSOC = 0, /*!< 4 way associated cache */
CACHE_8WAYS_ASSOC = 1, /*!< 8 way associated cache */
} cache_ways_t;
typedef enum {
CACHE_LINE_SIZE_16B = 0, /*!< 16 Byte cache line size */
CACHE_LINE_SIZE_32B = 1, /*!< 32 Byte cache line size */
CACHE_LINE_SIZE_64B = 2, /*!< 64 Byte cache line size */
} cache_line_size_t;
typedef enum {
CACHE_AUTOLOAD_POSITIVE = 0, /*!< cache autoload step is positive */
CACHE_AUTOLOAD_NEGATIVE = 1, /*!< cache autoload step is negative */
} cache_autoload_order_t;
#define CACHE_AUTOLOAD_STEP(i) ((i) - 1)
typedef enum {
CACHE_AUTOLOAD_MISS_TRIGGER = 0, /*!< autoload only triggered by cache miss */
CACHE_AUTOLOAD_HIT_TRIGGER = 1, /*!< autoload only triggered by cache hit */
CACHE_AUTOLOAD_BOTH_TRIGGER = 2, /*!< autoload triggered both by cache miss and hit */
} cache_autoload_trigger_t;
typedef enum {
CACHE_FREEZE_ACK_BUSY = 0, /*!< in this mode, cache ack busy to CPU if a cache miss happens*/
CACHE_FREEZE_ACK_ERROR = 1, /*!< in this mode, cache ack wrong data to CPU and trigger an error if a cache miss happens */
} cache_freeze_mode_t;
struct cache_mode {
uint32_t cache_size; /*!< cache size in byte */
uint16_t cache_line_size; /*!< cache line size in byte */
uint8_t cache_ways; /*!< cache ways, always 4 */
uint8_t ibus; /*!< the cache index, 0 for dcache, 1 for icache */
};
struct icache_tag_item {
uint32_t valid:1; /*!< the tag item is valid or not */
uint32_t lock:1; /*!< the cache line is locked or not */
uint32_t fifo_cnt:3; /*!< fifo cnt, 0 ~ 3 for 4 ways cache */
uint32_t tag:13; /*!< the tag is the high part of the cache address, however is only 16MB (8MB Ibus + 8MB Dbus) range, and without low part */
uint32_t reserved:14;
};
struct autoload_config {
uint8_t order; /*!< autoload step is positive or negative */
uint8_t trigger; /*!< autoload trigger */
uint8_t ena0; /*!< autoload region0 enable */
uint8_t ena1; /*!< autoload region1 enable */
uint32_t addr0; /*!< autoload region0 start address */
uint32_t size0; /*!< autoload region0 size */
uint32_t addr1; /*!< autoload region1 start address */
uint32_t size1; /*!< autoload region1 size */
};
struct tag_group_info {
struct cache_mode mode; /*!< cache and cache mode */
uint32_t filter_addr; /*!< the address that used to generate the struct */
uint32_t vaddr_offset; /*!< virtual address offset of the cache ways */
uint32_t tag_addr[MAX_CACHE_WAYS]; /*!< tag memory address, only [0~mode.ways-1] is valid to use */
uint32_t cache_memory_offset[MAX_CACHE_WAYS]; /*!< cache memory address, only [0~mode.ways-1] is valid to use */
};
struct lock_config {
uint32_t addr; /*!< manual lock address*/
uint16_t size; /*!< manual lock size*/
uint16_t group; /*!< manual lock group, 0 or 1*/
};
struct cache_internal_stub_table {
uint32_t (* icache_line_size)(void);
uint32_t (* icache_addr)(uint32_t addr);
uint32_t (* dcache_addr)(uint32_t addr);
void (* invalidate_icache_items)(uint32_t addr, uint32_t items);
void (* lock_icache_items)(uint32_t addr, uint32_t items);
void (* unlock_icache_items)(uint32_t addr, uint32_t items);
uint32_t (* suspend_icache_autoload)(void);
void (* resume_icache_autoload)(uint32_t autoload);
void (* freeze_icache_enable)(cache_freeze_mode_t mode);
void (* freeze_icache_disable)(void);
int (* op_addr)(uint32_t start_addr, uint32_t size, uint32_t cache_line_size, uint32_t max_sync_num, void(* cache_Iop)(uint32_t, uint32_t));
};
/* Defined in the interface file, default value is rom_default_cache_internal_table */
extern const struct cache_internal_stub_table* rom_cache_internal_table_ptr;
typedef void (* cache_op_start)(void);
typedef void (* cache_op_end)(void);
typedef struct {
cache_op_start start;
cache_op_end end;
} cache_op_cb_t;
/* Defined in the interface file, default value is NULL */
extern const cache_op_cb_t* rom_cache_op_cb;
#define ESP_ROM_ERR_INVALID_ARG 1
#define MMU_SET_ADDR_ALIGNED_ERROR 2
#define MMU_SET_PASE_SIZE_ERROR 3
#define MMU_SET_VADDR_OUT_RANGE 4
#define CACHE_OP_ICACHE_Y 1
#define CACHE_OP_ICACHE_N 0
/**
* @brief Initialise cache mmu, mark all entries as invalid.
* Please do not call this function in your SDK application.
*
* @param None
*
* @return None
*/
void Cache_MMU_Init(void);
/**
* @brief Set ICache mmu mapping.
* Please do not call this function in your SDK application.
*
* @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In
* esp32h4, external memory is always flash
*
* @param uint32_t vaddr : virtual address in CPU address space.
* Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address.
* Should be aligned by psize.
*
* @param uint32_t paddr : physical address in external memory.
* Should be aligned by psize.
*
* @param uint32_t psize : page size of ICache, in kilobytes. Should be 64 here.
*
* @param uint32_t num : pages to be set.
*
* @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page.
*
* @return uint32_t: error status
* 0 : mmu set success
* 2 : vaddr or paddr is not aligned
* 3 : psize error
* 4 : vaddr is out of range
*/
int Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed);
/**
* @brief Set DCache mmu mapping.
* Please do not call this function in your SDK application.
*
* @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In
* esp32h4, external memory is always flash
*
* @param uint32_t vaddr : virtual address in CPU address space.
* Can be DRam0, DRam1, DRom0, DPort and AHB buses address.
* Should be aligned by psize.
*
* @param uint32_t paddr : physical address in external memory.
* Should be aligned by psize.
*
* @param uint32_t psize : page size of DCache, in kilobytes. Should be 64 here.
*
* @param uint32_t num : pages to be set.
* @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page.
*
* @return uint32_t: error status
* 0 : mmu set success
* 2 : vaddr or paddr is not aligned
* 3 : psize error
* 4 : vaddr is out of range
*/
int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed);
/**
* @brief Count the pages in the bus room address which map to Flash.
* Please do not call this function in your SDK application.
*
* @param uint32_t bus : the bus to count with.
*
* @param uint32_t * page0_mapped : value should be initial by user, 0 for not mapped, other for mapped count.
*
* return uint32_t : the number of pages which map to Flash.
*/
uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped);
/**
* @brief allocate memory to used by ICache.
* Please do not call this function in your SDK application.
*
* @param cache_array_t icache_low : the data array bank used by icache low part. Due to timing constraint, can only be CACHE_MEMORY_INVALID, CACHE_MEMORY_IBANK0
*
* return none
*/
void Cache_Occupy_ICache_MEMORY(cache_array_t icache_low);
/**
* @brief Get cache mode of ICache or DCache.
* Please do not call this function in your SDK application.
*
* @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field
*
* return none
*/
void Cache_Get_Mode(struct cache_mode * mode);
/**
* @brief Init Cache for ROM boot, including resetting the Icache, initializing Owner, MMU, setting ICache mode, Enabling ICache, unmasking bus.
*
* @param None
*
* @return None
*/
void ROM_Boot_Cache_Init(void);
/**
* @brief Init mmu owner register to make i/d cache use half mmu entries.
*
* @param None
*
* @return None
*/
void Cache_Owner_Init(void);
/**
* @brief Invalidate the cache items for ICache.
* Operation will be done CACHE_LINE_SIZE aligned.
* If the region is not in ICache addr room, nothing will be done.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr: start address to invalidate
*
* @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB)
*
* @return None
*/
void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t items);
/**
* @brief Invalidate the Cache items in the region from ICache or DCache.
* If the region is not in Cache addr room, nothing will be done.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr : invalidated region start address.
*
* @param uint32_t size : invalidated region size.
*
* @return 0 for success
* 1 for invalid argument
*/
int Cache_Invalidate_Addr(uint32_t addr, uint32_t size);
/**
* @brief Invalidate all cache items in ICache.
* Please do not call this function in your SDK application.
*
* @param None
*
* @return None
*/
void Cache_Invalidate_ICache_All(void);
/**
* @brief Mask all buses through ICache and DCache.
* Please do not call this function in your SDK application.
*
* @param None
*
* @return None
*/
void Cache_Mask_All(void);
/**
* @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations.
* Please do not call this function in your SDK application.
*
* @param None
*
* @return uint32_t : 0 for ICache not auto preload before suspend.
*/
uint32_t Cache_Suspend_ICache_Autoload(void);
/**
* @brief Resume ICache auto preload operation after some ICache operations.
* Please do not call this function in your SDK application.
*
* @param uint32_t autoload : 0 for ICache not auto preload before suspend.
*
* @return None.
*/
void Cache_Resume_ICache_Autoload(uint32_t autoload);
/**
* @brief Start an ICache manual preload, will suspend auto preload of ICache.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr : start address of the preload region.
*
* @param uint32_t size : size of the preload region, should not exceed the size of ICache.
*
* @param uint32_t order : the preload order, 0 for positive, other for negative
*
* @return uint32_t : 0 for ICache not auto preload before manual preload.
*/
uint32_t Cache_Start_ICache_Preload(uint32_t addr, uint32_t size, uint32_t order);
/**
* @brief Return if the ICache manual preload done.
* Please do not call this function in your SDK application.
*
* @param None
*
* @return uint32_t : 0 for ICache manual preload not done.
*/
uint32_t Cache_ICache_Preload_Done(void);
/**
* @brief End the ICache manual preload to resume auto preload of ICache.
* Please do not call this function in your SDK application.
*
* @param uint32_t autoload : 0 for ICache not auto preload before manual preload.
*
* @return None
*/
void Cache_End_ICache_Preload(uint32_t autoload);
/**
* @brief Config autoload parameters of ICache.
* Please do not call this function in your SDK application.
*
* @param struct autoload_config * config : autoload parameters.
*
* @return None
*/
void Cache_Config_ICache_Autoload(const struct autoload_config * config);
/**
* @brief Enable auto preload for ICache.
* Please do not call this function in your SDK application.
*
* @param None
*
* @return None
*/
void Cache_Enable_ICache_Autoload(void);
/**
* @brief Disable auto preload for ICache.
* Please do not call this function in your SDK application.
*
* @param None
*
* @return None
*/
void Cache_Disable_ICache_Autoload(void);
/**
* @brief Config a group of prelock parameters of ICache.
* Please do not call this function in your SDK application.
*
* @param struct lock_config * config : a group of lock parameters.
*
* @return None
*/
void Cache_Enable_ICache_PreLock(const struct lock_config *config);
/**
* @brief Disable a group of prelock parameters for ICache.
* However, the locked data will not be released.
* Please do not call this function in your SDK application.
*
* @param uint16_t group : 0 for group0, 1 for group1.
*
* @return None
*/
void Cache_Disable_ICache_PreLock(uint16_t group);
/**
* @brief Lock the cache items for ICache.
* Operation will be done CACHE_LINE_SIZE aligned.
* If the region is not in ICache addr room, nothing will be done.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr: start address to lock
*
* @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB)
*
* @return None
*/
void Cache_Lock_ICache_Items(uint32_t addr, uint32_t items);
/**
* @brief Unlock the cache items for ICache.
* Operation will be done CACHE_LINE_SIZE aligned.
* If the region is not in ICache addr room, nothing will be done.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr: start address to unlock
*
* @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB)
*
* @return None
*/
void Cache_Unlock_ICache_Items(uint32_t addr, uint32_t items);
/**
* @brief Lock the cache items in tag memory for ICache or DCache.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr : start address of lock region.
*
* @param uint32_t size : size of lock region.
*
* @return 0 for success
* 1 for invalid argument
*/
int Cache_Lock_Addr(uint32_t addr, uint32_t size);
/**
* @brief Unlock the cache items in tag memory for ICache or DCache.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr : start address of unlock region.
*
* @param uint32_t size : size of unlock region.
*
* @return 0 for success
* 1 for invalid argument
*/
int Cache_Unlock_Addr(uint32_t addr, uint32_t size);
/**
* @brief Disable ICache access for the cpu.
* This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle.
* Please do not call this function in your SDK application.
*
* @return uint32_t : auto preload enabled before
*/
uint32_t Cache_Disable_ICache(void);
/**
* @brief Enable ICache access for the cpu.
* Please do not call this function in your SDK application.
*
* @param uint32_t autoload : ICache will preload then.
*
* @return None
*/
void Cache_Enable_ICache(uint32_t autoload);
/**
* @brief Suspend ICache access for the cpu.
* The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle.
* Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case).
* Please do not call this function in your SDK application.
*
* @param None
*
* @return uint32_t : auto preload enabled before
*/
uint32_t Cache_Suspend_ICache(void);
/**
* @brief Resume ICache access for the cpu.
* Please do not call this function in your SDK application.
*
* @param uint32_t autoload : ICache will preload then.
*
* @return None
*/
void Cache_Resume_ICache(uint32_t autoload);
/**
* @brief Get ICache cache line size
*
* @param None
*
* @return uint32_t: 16, 32, 64 Byte
*/
uint32_t Cache_Get_ICache_Line_Size(void);
/**
* @brief Set default mode from boot, 8KB ICache, 16Byte cache line size.
*
* @param None
*
* @return None
*/
void Cache_Set_Default_Mode(void);
/**
* @brief Set default mode from boot, 8KB ICache, 16Byte cache line size.
*
* @param None
*
* @return None
*/
void Cache_Enable_Defalut_ICache_Mode(void);
/**
* @brief Enable freeze for ICache.
* Any miss request will be rejected, including cpu miss and preload/autoload miss.
* Please do not call this function in your SDK application.
*
* @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit
*
* @return None
*/
void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode);
/**
* @brief Disable freeze for ICache.
* Please do not call this function in your SDK application.
*
* @return None
*/
void Cache_Freeze_ICache_Disable(void);
/**
* @brief Travel tag memory to run a call back function.
* ICache and DCache are suspend when doing this.
* The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses.
* Please do not call this function in your SDK application.
*
* @param struct cache_mode * mode : the cache to check and the cache mode.
*
* @param uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function.
* 0 for do not filter, all cache lines will be returned.
*
* @param void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time.
*
* @return None
*/
void Cache_Travel_Tag_Memory(struct cache_mode * mode, uint32_t filter_addr, void (* process)(struct tag_group_info *));
/**
* @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways.
* Please do not call this function in your SDK application.
*
* @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode.
*
* @param uint32_t tag : the tag part fo a tag item, 12-14 bits.
*
* @param uint32_t addr_offset : the virtual address offset of the cache ways.
*
* @return uint32_t : the virtual address.
*/
uint32_t Cache_Get_Virtual_Addr(struct cache_mode *mode, uint32_t tag, uint32_t vaddr_offset);
/**
* @brief Get cache memory block base address.
* Please do not call this function in your SDK application.
*
* @param uint32_t icache : 0 for dcache, other for icache.
*
* @param uint32_t bank_no : 0 ~ 3 bank.
*
* @return uint32_t : the cache memory block base address, 0 if the block not used.
*/
uint32_t Cache_Get_Memory_BaseAddr(uint32_t icache, uint32_t bank_no);
/**
* @brief Get the cache memory address from cache mode, cache memory offset and the virtual address offset of cache ways.
* Please do not call this function in your SDK application.
*
* @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode.
*
* @param uint32_t cache_memory_offset : the cache memory offset of the whole cache (ICache or DCache) for the cache line.
*
* @param uint32_t addr_offset : the virtual address offset of the cache ways.
*
* @return uint32_t : the virtual address.
*/
uint32_t Cache_Get_Memory_Addr(struct cache_mode *mode, uint32_t cache_memory_offset, uint32_t vaddr_offset);
/**
* @brief Get the cache memory value by DRAM address.
* Please do not call this function in your SDK application.
*
* @param uint32_t cache_memory_addr : DRAM address for the cache memory, should be 4 byte aligned for IBus address.
*
* @return uint32_t : the word value of the address.
*/
uint32_t Cache_Get_Memory_value(uint32_t cache_memory_addr);
/**
* @}
*/
/**
* @brief Get the cache MMU IROM end address.
* Please do not call this function in your SDK application.
*
* @param void
*
* @return uint32_t : the word value of the address.
*/
uint32_t Cache_Get_IROM_MMU_End(void);
/**
* @brief Get the cache MMU DROM end address.
* Please do not call this function in your SDK application.
*
* @param void
*
* @return uint32_t : the word value of the address.
*/
uint32_t Cache_Get_DROM_MMU_End(void);
/**
* @brief Configure cache MMU page size according to instruction and rodata size
*
* @param irom_size The instruction cache MMU page size
* @param drom_size The rodata data cache MMU page size
*/
void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
/**
* @brief Lock the permission control section configuration. After lock, any
* configuration modification will be bypass. Digital reset will clear the lock!
* Please do not call this function in your SDK application.
*
* @param int ibus : 1 for lock ibus pms, 0 for lock dbus pms
*
* @return None
*/
void Cache_Pms_Lock(int ibus);
/**
* @brief Set three ibus pms boundary address, which will determine pms reject section and section 1/2.
* Please do not call this function in your SDK application.
*
* @param uint32_t ibus_boundary0_addr : vaddress for split line0
*
* @param uint32_t ibus_boundary1_addr : vaddress for split line1
*
* @param uint32_t ibus_boundary2_addr : vaddress for split line2
*
* @return int : ESP_ROM_ERR_INVALID_ARG for invalid address, 0 for success
*/
int Cache_Ibus_Pms_Set_Addr(uint32_t ibus_boundary0_addr, uint32_t ibus_boundary1_addr, uint32_t ibus_boundary2_addr);
/**
* @brief Set three ibus pms attribute, which will determine pms in different section and world.
* Please do not call this function in your SDK application.
*
* @param uint32_t ibus_pms_sct2_attr : attr for section2
*
* @param uint32_t ibus_pms_sct1_attr : attr for section1
*
* @return None
*/
void Cache_Ibus_Pms_Set_Attr(uint32_t ibus_pms_sct2_attr, uint32_t ibus_pms_sct1_attr);
/**
* @brief Set three dbus pms boundary address, which will determine pms reject section and section 1/2.
* Please do not call this function in your SDK application.
*
* @param uint32_t dbus_boundary0_addr : vaddress for split line0
*
* @param uint32_t dbus_boundary1_addr : vaddress for split line1
*
* @param uint32_t dbus_boundary2_addr : vaddress for split line2
*
* @return int : ESP_ROM_ERR_INVALID_ARG for invalid address, 0 for success
*/
int Cache_Dbus_Pms_Set_Addr(uint32_t dbus_boundary0_addr, uint32_t dbus_boundary1_addr, uint32_t dbus_boundary2_addr);
/**
* @brief Set three dbus pms attribute, which will determine pms in different section and world.
* Please do not call this function in your SDK application.
*
* @param uint32_t dbus_pms_sct2_attr : attr for section2
*
* @param uint32_t dbus_pms_sct1_attr : attr for section1
*
* @return None
*/
void Cache_Dbus_Pms_Set_Attr(uint32_t dbus_pms_sct2_attr, uint32_t dbus_pms_sct1_attr);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_CACHE_H_ */

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components/esp_rom/include/esp32h4/rom/crc.h
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/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ROM_CRC_H
#define ROM_CRC_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup crc_apis, uart configuration and communication related apis
* @brief crc apis
*/
/** @addtogroup crc_apis
* @{
*/
/* Standard CRC8/16/32 algorithms. */
// CRC-8 x8+x2+x1+1 0x07
// CRC16-CCITT x16+x12+x5+1 1021 ISO HDLC, ITU X.25, V.34/V.41/V.42, PPP-FCS
// CRC32:
//G(x) = x32 +x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1
//If your buf is not continuous, you can use the first result to be the second parameter.
/**
* @brief Crc32 value that is in little endian.
*
* @param uint32_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc32 value that is in big endian.
*
* @param uint32_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc16 value that is in little endian.
*
* @param uint16_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc16 value that is in big endian.
*
* @param uint16_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc8 value that is in little endian.
*
* @param uint8_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc8 value that is in big endian.
*
* @param uint32_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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components/esp_rom/include/esp32h4/rom/digital_signature.h
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/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#define ETS_DS_MAX_BITS 3072
#define ETS_DS_IV_LEN 16
/* Length of parameter 'C' stored in flash (not including IV)
Comprises encrypted Y, M, rinv, md (32), mprime (4), length (4), padding (8)
Note that if ETS_DS_MAX_BITS<4096, 'C' needs to be split up when writing to hardware
*/
#define ETS_DS_C_LEN ((ETS_DS_MAX_BITS * 3 / 8) + 32 + 8 + 8)
/* Encrypted ETS data. Recommended to store in flash in this format.
*/
typedef struct {
/* RSA LENGTH register parameters
* (number of words in RSA key & operands, minus one).
*
*
* This value must match the length field encrypted and stored in 'c',
* or invalid results will be returned. (The DS peripheral will
* always use the value in 'c', not this value, so an attacker can't
* alter the DS peripheral results this way, it will just truncate or
* extend the message and the resulting signature in software.)
*/
unsigned rsa_length;
/* IV value used to encrypt 'c' */
uint8_t iv[ETS_DS_IV_LEN];
/* Encrypted Digital Signature parameters. Result of AES-CBC encryption
of plaintext values. Includes an encrypted message digest.
*/
uint8_t c[ETS_DS_C_LEN];
} ets_ds_data_t;
typedef enum {
ETS_DS_OK,
ETS_DS_INVALID_PARAM, /* Supplied parameters are invalid */
ETS_DS_INVALID_KEY, /* HMAC peripheral failed to supply key */
ETS_DS_INVALID_PADDING, /* 'c' decrypted with invalid padding */
ETS_DS_INVALID_DIGEST, /* 'c' decrypted with invalid digest */
} ets_ds_result_t;
void ets_ds_enable(void);
void ets_ds_disable(void);
/*
* @brief Start signing a message (or padded message digest) using the Digital Signature peripheral
*
* - @param message Pointer to message (or padded digest) containing the message to sign. Should be
* (data->rsa_length + 1)*4 bytes long. @param data Pointer to DS data. Can be a pointer to data
* in flash.
*
* Caller must have already called ets_ds_enable() and ets_hmac_calculate_downstream() before calling
* this function, and is responsible for calling ets_ds_finish_sign() and then
* ets_hmac_invalidate_downstream() afterwards.
*
* @return ETS_DS_OK if signature is in progress, ETS_DS_INVALID_PARAM if param is invalid,
* EST_DS_INVALID_KEY if key or HMAC peripheral is configured incorrectly.
*/
ets_ds_result_t ets_ds_start_sign(const void *message, const ets_ds_data_t *data);
/*
* @brief Returns true if the DS peripheral is busy following a call to ets_ds_start_sign()
*
* A result of false indicates that a call to ets_ds_finish_sign() will not block.
*
* Only valid if ets_ds_enable() has been called.
*/
bool ets_ds_is_busy(void);
/* @brief Finish signing a message using the Digital Signature peripheral
*
* Must be called after ets_ds_start_sign(). Can use ets_ds_busy() to wait until
* peripheral is no longer busy.
*
* - @param signature Pointer to buffer to contain the signature. Should be
* (data->rsa_length + 1)*4 bytes long.
* - @param data Should match the 'data' parameter passed to ets_ds_start_sign()
*
* @param ETS_DS_OK if signing succeeded, ETS_DS_INVALID_PARAM if param is invalid,
* ETS_DS_INVALID_DIGEST or ETS_DS_INVALID_PADDING if there is a problem with the
* encrypted data digest or padding bytes (in case of ETS_DS_INVALID_PADDING, a
* digest is produced anyhow.)
*/
ets_ds_result_t ets_ds_finish_sign(void *signature, const ets_ds_data_t *data);
/* Plaintext parameters used by Digital Signature.
Not used for signing with DS peripheral, but can be encrypted
in-device by calling ets_ds_encrypt_params()
*/
typedef struct {
uint32_t Y[ETS_DS_MAX_BITS / 32];
uint32_t M[ETS_DS_MAX_BITS / 32];
uint32_t Rb[ETS_DS_MAX_BITS / 32];
uint32_t M_prime;
uint32_t length;
} ets_ds_p_data_t;
typedef enum {
ETS_DS_KEY_HMAC, /* The HMAC key (as stored in efuse) */
ETS_DS_KEY_AES, /* The AES key (as derived from HMAC key by HMAC peripheral in downstream mode) */
} ets_ds_key_t;
/* @brief Encrypt DS parameters suitable for storing and later use with DS peripheral
*
* @param data Output buffer to store encrypted data, suitable for later use generating signatures.
* @param iv Pointer to 16 byte IV buffer, will be copied into 'data'. Should be randomly generated bytes each time.
* @param p_data Pointer to input plaintext key data. The expectation is this data will be deleted after this process is done and 'data' is stored.
* @param key Pointer to 32 bytes of key data. Type determined by key_type parameter. The expectation is the corresponding HMAC key will be stored to efuse and then permanently erased.
* @param key_type Type of key stored in 'key' (either the AES-256 DS key, or an HMAC DS key from which the AES DS key is derived using HMAC peripheral)
*
* @return ETS_DS_INVALID_PARAM if any parameter is invalid, or ETS_DS_OK if 'data' is successfully generated from the input parameters.
*/
ets_ds_result_t ets_ds_encrypt_params(ets_ds_data_t *data, const void *iv, const ets_ds_p_data_t *p_data, const void *key, ets_ds_key_t key_type);
#ifdef __cplusplus
}
#endif

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components/esp_rom/include/esp32h4/rom/efuse.h
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/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_EFUSE_H_
#define _ROM_EFUSE_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
/** \defgroup efuse_APIs efuse APIs
* @brief ESP32 efuse read/write APIs
* @attention
*
*/
/** @addtogroup efuse_APIs
* @{
*/
typedef enum {
ETS_EFUSE_KEY_PURPOSE_USER = 0,
ETS_EFUSE_KEY_PURPOSE_RESERVED = 1,
ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4,
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5,
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6,
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7,
ETS_EFUSE_KEY_PURPOSE_HMAC_UP = 8,
ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9,
ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10,
ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11,
ETS_EFUSE_KEY_PURPOSE_MAX,
} ets_efuse_purpose_t;
typedef enum {
ETS_EFUSE_BLOCK0 = 0,
ETS_EFUSE_MAC_SPI_SYS_0 = 1,
ETS_EFUSE_BLOCK_SYS_DATA = 2,
ETS_EFUSE_BLOCK_USR_DATA = 3,
ETS_EFUSE_BLOCK_KEY0 = 4,
ETS_EFUSE_BLOCK_KEY1 = 5,
ETS_EFUSE_BLOCK_KEY2 = 6,
ETS_EFUSE_BLOCK_KEY3 = 7,
ETS_EFUSE_BLOCK_KEY4 = 8,
ETS_EFUSE_BLOCK_KEY5 = 9,
ETS_EFUSE_BLOCK_KEY6 = 10,
ETS_EFUSE_BLOCK_MAX,
} ets_efuse_block_t;
/**
* @brief set timing accroding the apb clock, so no read error or write error happens.
*
* @param clock: apb clock in HZ, only accept 5M(in FPGA), 10M(in FPGA), 20M, 40M, 80M.
*
* @return : 0 if success, others if clock not accepted
*/
int ets_efuse_set_timing(uint32_t clock);
/**
* @brief Efuse read operation: copies data from physical efuses to efuse read registers.
*
* @param null
*
* @return : 0 if success, others if apb clock is not accepted
*/
int ets_efuse_read(void);
/**
* @brief Efuse write operation: Copies data from efuse write registers to efuse. Operates on a single block of efuses at a time.
*
* @note This function does not update read efuses, call ets_efuse_read() once all programming is complete.
*
* @return : 0 if success, others if apb clock is not accepted
*/
int ets_efuse_program(ets_efuse_block_t block);
/**
* @brief Set all Efuse program registers to zero.
*
* Call this before writing new data to the program registers.
*/
void ets_efuse_clear_program_registers(void);
/**
* @brief Program a block of key data to an efuse block
*
* @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. Key block must be unused (@ref ets_efuse_key_block_unused).
* @param purpose Purpose to set for this key. Purpose must be already unset.
* @param data Pointer to data to write.
* @param data_len Length of data to write.
*
* @note This function also calls ets_efuse_program() for the specified block, and for block 0 (setting the purpose)
*/
int ets_efuse_write_key(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose, const void *data, size_t data_len);
/* @brief Return the address of a particular efuse block's first read register
*
* @param block Index of efuse block to look up
*
* @return 0 if block is invalid, otherwise a numeric read register address
* of the first word in the block.
*/
uint32_t ets_efuse_get_read_register_address(ets_efuse_block_t block);
/**
* @brief Return the current purpose set for an efuse key block
*
* @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6.
*/
ets_efuse_purpose_t ets_efuse_get_key_purpose(ets_efuse_block_t key_block);
/**
* @brief Find a key block with the particular purpose set
*
* @param purpose Purpose to search for.
* @param[out] key_block Pointer which will be set to the key block if found. Can be NULL, if only need to test the key block exists.
* @return true if found, false if not found. If false, value at key_block pointer is unchanged.
*/
bool ets_efuse_find_purpose(ets_efuse_purpose_t purpose, ets_efuse_block_t *key_block);
/**
* Return true if the key block is unused, false otherwise.
*
* An unused key block is all zero content, not read or write protected,
* and has purpose 0 (ETS_EFUSE_KEY_PURPOSE_USER)
*
* @param key_block key block to check.
*
* @return true if key block is unused, false if key block or used
* or the specified block index is not a key block.
*/
bool ets_efuse_key_block_unused(ets_efuse_block_t key_block);
/**
* @brief Search for an unused key block and return the first one found.
*
* See @ref ets_efuse_key_block_unused for a description of an unused key block.
*
* @return First unused key block, or ETS_EFUSE_BLOCK_MAX if no unused key block is found.
*/
ets_efuse_block_t ets_efuse_find_unused_key_block(void);
/**
* @brief Return the number of unused efuse key blocks (0-6)
*/
unsigned ets_efuse_count_unused_key_blocks(void);
/**
* @brief Calculate Reed-Solomon Encoding values for a block of efuse data.
*
* @param data Pointer to data buffer (length 32 bytes)
* @param rs_values Pointer to write encoded data to (length 12 bytes)
*/
void ets_efuse_rs_calculate(const void *data, void *rs_values);
/**
* @brief Read spi flash pads configuration from Efuse
*
* @return
* - 0 for default SPI pins.
* - 1 for default HSPI pins.
* - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK,
* EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros.
* WP pin (for quad I/O modes) is not saved in efuse and not returned by this function.
*/
uint32_t ets_efuse_get_spiconfig(void);
/**
* @brief Read spi flash wp pad from Efuse
*
* @return
* - 0x3f for invalid.
* - 0~46 is valid.
*/
uint32_t ets_efuse_get_wp_pad(void);
/**
* @brief Read if download mode disabled from Efuse
*
* @return
* - true for efuse disable download mode.
* - false for efuse doesn't disable download mode.
*/
bool ets_efuse_download_modes_disabled(void);
/**
* @brief Read if uart print control value from Efuse
*
* @return
* - 0 for uart force print.
* - 1 for uart print when GPIO8 is low when digital reset.
* 2 for uart print when GPIO8 is high when digital reset.
* 3 for uart force slient
*/
uint32_t ets_efuse_get_uart_print_control(void);
/**
* @brief Read if USB-Serial-JTAG print during rom boot is disabled from Efuse
*
* @return
* - 1 for efuse disable USB-Serial-JTAG print during rom boot.
* - 0 for efuse doesn't disable USB-Serial-JTAG print during rom boot.
*/
uint32_t ets_efuse_usb_serial_jtag_print_is_disabled(void);
/**
* @brief Read if usb download mode disabled from Efuse
*
* (Also returns true if security download mode is enabled, as this mode
* disables USB download.)
*
* @return
* - true for efuse disable usb download mode.
* - false for efuse doesn't disable usb download mode.
*/
bool ets_efuse_usb_download_mode_disabled(void);
/**
* @brief Read if usb module disabled from Efuse
*
* @return
* - true for efuse disable usb module.
* - false for efuse doesn't disable usb module.
*/
bool ets_efuse_usb_module_disabled(void);
/**
* @brief Read if security download modes enabled from Efuse
*
* @return
* - true for efuse enable security download mode.
* - false for efuse doesn't enable security download mode.
*/
bool ets_efuse_security_download_modes_enabled(void);
/**
* @brief Return true if secure boot is enabled in EFuse
*/
bool ets_efuse_secure_boot_enabled(void);
/**
* @brief Return true if secure boot aggressive revoke is enabled in EFuse
*/
bool ets_efuse_secure_boot_aggressive_revoke_enabled(void);
/**
* @brief Return true if cache encryption (flash, etc) is enabled from boot via EFuse
*/
bool ets_efuse_cache_encryption_enabled(void);
/**
* @brief Return true if OPI pins GPIO33-37 are powered by VDDSPI, otherwise by VDD33CPU
*/
bool ets_efuse_flash_opi_5pads_power_sel_vddspi(void);
/**
* @brief Return true if EFuse indicates to send a flash resume command.
*/
bool ets_efuse_force_send_resume(void);
/**
* @brief return the time in us ROM boot need wait flash to power on from Efuse
*
* @return
* - uint32_t the time in us.
*/
uint32_t ets_efuse_get_flash_delay_us(void);
#define EFUSE_SPICONFIG_SPI_DEFAULTS 0
#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1
#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0
#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK)
#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6
#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK)
#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12
#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK)
#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18
#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK)
#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24
#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK)
/**
* @brief Enable JTAG temporarily by writing a JTAG HMAC "key" into
* the JTAG_CTRL registers.
*
* Works if JTAG has been "soft" disabled by burning the EFUSE_SOFT_DIS_JTAG efuse.
*
* Will enable the HMAC module to generate a "downstream" HMAC value from a key already saved in efuse, and then write the JTAG HMAC "key" which will enable JTAG if the two keys match.
*
* @param jtag_hmac_key Pointer to a 32 byte array containing a valid key. Supplied by user.
* @param key_block Index of a key block containing the source for this key.
*
* @return ETS_FAILED if HMAC operation fails or invalid parameter, ETS_OK otherwise. ETS_OK doesn't necessarily mean that JTAG was enabled.
*/
int ets_jtag_enable_temporarily(const uint8_t *jtag_hmac_key, ets_efuse_block_t key_block);
/**
* @brief A crc8 algorithm used for MAC addresses in efuse
*
* @param unsigned char const *p : Pointer to original data.
*
* @param unsigned int len : Data length in byte.
*
* @return unsigned char: Crc value.
*/
unsigned char esp_crc8(unsigned char const *p, unsigned int len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_EFUSE_H_ */

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components/esp_rom/include/esp32h4/rom/esp_flash.h
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/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Note: Most of esp_flash APIs in ROM are compatible with headers in ESP-IDF, this function
just adds ROM-specific parts
*/
struct spi_flash_chip_t;
typedef struct esp_flash_t esp_flash_t;
/* Structure to wrap "global" data used by esp_flash in ROM */
typedef struct {
/* Default SPI flash chip, ie main chip attached to the MCU
This chip is used if the 'chip' argument passed to esp_flash_xxx API functions is ever NULL
*/
esp_flash_t *default_chip;
/* Global API OS notification start/end/chip_check functions
These are used by ROM if no other host functions are configured.
*/
struct {
esp_err_t (*start)(esp_flash_t *chip);
esp_err_t (*end)(esp_flash_t *chip, esp_err_t err);
esp_err_t (*chip_check)(esp_flash_t **inout_chip);
} api_funcs;
} esp_flash_rom_global_data_t;
/** Access a pointer to the global data used by the ROM spi_flash driver
*/
esp_flash_rom_global_data_t *esp_flash_get_rom_global_data(void);
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_ETS_SYS_H_
#define _ROM_ETS_SYS_H_
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup ets_sys_apis, ets system related apis
* @brief ets system apis
*/
/** @addtogroup ets_sys_apis
* @{
*/
/************************************************************************
* NOTE
* Many functions in this header files can't be run in FreeRTOS.
* Please see the comment of the Functions.
* There are also some functions that doesn't work on FreeRTOS
* without listed in the header, such as:
* xtos functions start with "_xtos_" in ld file.
*
***********************************************************************
*/
/** \defgroup ets_apis, Espressif Task Scheduler related apis
* @brief ets apis
*/
/** @addtogroup ets_apis
* @{
*/
typedef enum {
ETS_OK = 0, /**< return successful in ets*/
ETS_FAILED = 1, /**< return failed in ets*/
ETS_PENDING = 2,
ETS_BUSY = 3,
ETS_CANCEL = 4,
} ETS_STATUS;
typedef ETS_STATUS ets_status_t;
typedef uint32_t ETSSignal;
typedef uint32_t ETSParam;
typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/
struct ETSEventTag {
ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/
ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/
};
typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/
typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/
/**
* @}
*/
/** \defgroup ets_boot_apis, Boot routing related apis
* @brief ets boot apis
*/
/** @addtogroup ets_apis
* @{
*/
extern const char *const exc_cause_table[40]; ///**< excption cause that defined by the core.*/
/**
* @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed.
* When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL.
*
* @param uint32_t start : the PRO Entry code address value in uint32_t
*
* @return None
*/
void ets_set_user_start(uint32_t start);
/**
* @}
*/
/** \defgroup ets_printf_apis, ets_printf related apis used in ets
* @brief ets printf apis
*/
/** @addtogroup ets_printf_apis
* @{
*/
/**
* @brief Printf the strings to uart or other devices, similar with printf, simple than printf.
* Can not print float point data format, or longlong data format.
* So we maybe only use this in ROM.
*
* @param const char *fmt : See printf.
*
* @param ... : See printf.
*
* @return int : the length printed to the output device.
*/
int ets_printf(const char *fmt, ...);
/**
* @brief Get the uart channel of ets_printf(uart_tx_one_char).
*
* @return uint8_t uart channel used by ets_printf(uart_tx_one_char).
*/
uint8_t ets_get_printf_channel(void);
/**
* @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function.
* Can not print float point data format, or longlong data format
*
* @param char c : char to output.
*
* @return None
*/
void ets_write_char_uart(char c);
/**
* @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput.
* To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode.
*
* @param void (*)(char) p: Output function to install.
*
* @return None
*/
void ets_install_putc1(void (*p)(char c));
/**
* @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput.
* To install putc2, which is defaulted installed as NULL.
*
* @param void (*)(char) p: Output function to install.
*
* @return None
*/
void ets_install_putc2(void (*p)(char c));
/**
* @brief Install putc1 as ets_write_char_uart.
* In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok.
*
* @param None
*
* @return None
*/
void ets_install_uart_printf(void);
#define ETS_PRINTF(...) ets_printf(...)
#define ETS_ASSERT(v) do { \
if (!(v)) { \
ets_printf("%s %u \n", __FILE__, __LINE__); \
while (1) {}; \
} \
} while (0);
/**
* @}
*/
/** \defgroup ets_timer_apis, ets_timer related apis used in ets
* @brief ets timer apis
*/
/** @addtogroup ets_timer_apis
* @{
*/
typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/
typedef struct _ETSTIMER_ {
struct _ETSTIMER_ *timer_next; /**< timer linker*/
uint32_t timer_expire; /**< abstruct time when timer expire*/
uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/
ETSTimerFunc *timer_func; /**< timer handler*/
void *timer_arg; /**< timer handler argument*/
} ETSTimer;
/**
* @brief Init ets timer, this timer range is 640 us to 429496 ms
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_timer_init(void);
/**
* @brief In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_timer_deinit(void);
/**
* @brief Arm an ets timer, this timer range is 640 us to 429496 ms.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @param uint32_t tmout : Timer value in ms, range is 1 to 429496.
*
* @param bool repeat : Timer is periodic repeated.
*
* @return None
*/
void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat);
/**
* @brief Arm an ets timer, this timer range is 640 us to 429496 ms.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @param uint32_t tmout : Timer value in us, range is 1 to 429496729.
*
* @param bool repeat : Timer is periodic repeated.
*
* @return None
*/
void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat);
/**
* @brief Disarm an ets timer.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @return None
*/
void ets_timer_disarm(ETSTimer *timer);
/**
* @brief Set timer callback and argument.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @param ETSTimerFunc *pfunction : Timer callback.
*
* @param void *parg : Timer callback argument.
*
* @return None
*/
void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg);
/**
* @brief Unset timer callback and argument to NULL.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @return None
*/
void ets_timer_done(ETSTimer *ptimer);
/**
* @brief CPU do while loop for some time.
* In FreeRTOS task, please call FreeRTOS apis.
*
* @param uint32_t us : Delay time in us.
*
* @return None
*/
void ets_delay_us(uint32_t us);
/**
* @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
* Call this function when CPU frequency is changed.
*
* @param uint32_t ticks_per_us : CPU ticks per us.
*
* @return None
*/
void ets_update_cpu_frequency(uint32_t ticks_per_us);
/**
* @brief Get the real CPU ticks per us to the ets.
* This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency.
*
* @param None
*
* @return uint32_t : CPU ticks per us record in ets.
*/
uint32_t ets_get_cpu_frequency(void);
/**
* @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store.
*
* @param None
*
* @return uint32_t : if stored in efuse(not 0)
* clock = ets_efuse_get_xtal_freq() * 1000000;
* else if analog_8M in efuse
* clock = ets_get_xtal_scale() * 625 / 16 * ets_efuse_get_8M_clock();
* else clock = 40M.
*/
uint32_t ets_get_xtal_freq(void);
/**
* @brief Get the apb divior by xtal frequency.
* When any types of reset happen, the default value is 2.
*
* @param None
*
* @return uint32_t : 1 or 2.
*/
uint32_t ets_get_xtal_div(void);
/**
* @brief Get apb_freq value, If value not stored in RTC_STORE5, than store.
*
* @param None
*
* @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register.
* clock = (REG_READ(RTC_STORE5) & 0xffff) << 12;
* else store ets_get_detected_xtal_freq() in.
*/
uint32_t ets_get_apb_freq(void);
/**
* @}
*/
/** \defgroup ets_intr_apis, ets interrupt configure related apis
* @brief ets intr apis
*/
/** @addtogroup ets_intr_apis
* @{
*/
typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/
/**
* @brief Attach a interrupt handler to a CPU interrupt number.
* This function equals to _xtos_set_interrupt_handler_arg(i, func, arg).
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param int i : CPU interrupt number.
*
* @param ets_isr_t func : Interrupt handler.
*
* @param void *arg : argument of the handler.
*
* @return None
*/
void ets_isr_attach(int i, ets_isr_t func, void *arg);
/**
* @brief Mask the interrupts which show in mask bits.
* This function equals to _xtos_ints_off(mask).
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param uint32_t mask : BIT(i) means mask CPU interrupt number i.
*
* @return None
*/
void ets_isr_mask(uint32_t mask);
/**
* @brief Unmask the interrupts which show in mask bits.
* This function equals to _xtos_ints_on(mask).
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param uint32_t mask : BIT(i) means mask CPU interrupt number i.
*
* @return None
*/
void ets_isr_unmask(uint32_t unmask);
/**
* @brief Lock the interrupt to level 2.
* This function direct set the CPU registers.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_intr_lock(void);
/**
* @brief Unlock the interrupt to level 0.
* This function direct set the CPU registers.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_intr_unlock(void);
/**
* @brief Attach an CPU interrupt to a hardware source.
* We have 4 steps to use an interrupt:
* 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM);
* 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL);
* 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM);
* 4.Enable interrupt in the module.
*
* @param int cpu_no : The CPU which the interrupt number belongs.
*
* @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table.
*
* @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table.
*
* @return None
*/
void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
/**
* @}
*/
#ifndef MAC2STR
#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
#endif
#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" )
#ifdef ESP_PLATFORM
// Remove in IDF v6.0 (IDF-7044)
typedef enum {
OK = 0,
FAIL,
PENDING,
BUSY,
CANCEL,
} STATUS __attribute__((deprecated("Use ETS_STATUS instead")));
#endif
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_ETS_SYS_H_ */

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components/esp_rom/include/esp32h4/rom/gpio.h
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/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "soc/gpio_reg.h"
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup gpio_apis, uart configuration and communication related apis
* @brief gpio apis
*/
/** @addtogroup gpio_apis
* @{
*/
#define GPIO_REG_READ(reg) READ_PERI_REG(reg)
#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val)
#define GPIO_ID_PIN0 0
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4)
#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1
#define GPIO_FUNC_IN_HIGH 0x38
#define GPIO_FUNC_IN_LOW 0x3C
#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2
#define GPIO_FUNC_IN_HIGH 0x1E
#define GPIO_FUNC_IN_LOW 0x1F
#endif
#define GPIO_ID_IS_PIN_REGISTER(reg_id) \
((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1)))
#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0)
typedef enum {
GPIO_PIN_INTR_DISABLE = 0,
GPIO_PIN_INTR_POSEDGE = 1,
GPIO_PIN_INTR_NEGEDGE = 2,
GPIO_PIN_INTR_ANYEDGE = 3,
GPIO_PIN_INTR_LOLEVEL = 4,
GPIO_PIN_INTR_HILEVEL = 5
} GPIO_INT_TYPE;
/**
* @brief Change GPIO(0-31) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
* There is no particular ordering guaranteed; so if the order of writes is significant,
* calling code should divide a single call into multiple calls.
*
* @param uint32_t set_mask : the gpios that need high level.
*
* @param uint32_t clear_mask : the gpios that need low level.
*
* @param uint32_t enable_mask : the gpios that need be changed.
*
* @param uint32_t disable_mask : the gpios that need diable output.
*
* @return None
*/
void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
/**
* @brief Sample the value of GPIO input pins(0-31) and returns a bitmask.
*
* @param None
*
* @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0.
*/
uint32_t gpio_input_get(void);
/**
* @brief Set GPIO to wakeup the ESP32.
* Please do not call this function in SDK.
*
* @param uint32_t i: gpio number.
*
* @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used
*
* @return None
*/
void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
/**
* @brief disable GPIOs to wakeup the ESP32.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void gpio_pin_wakeup_disable(void);
/**
* @brief set gpio input to a signal, one gpio can input to several signals.
*
* @param uint32_t gpio : gpio number, 0~0x2f
* gpio == 0x3C, input 0 to signal
* gpio == 0x3A, input nothing to signal
* gpio == 0x38, input 1 to signal
*
* @param uint32_t signal_idx : signal index.
*
* @param bool inv : the signal is inv or not
*
* @return None
*/
void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
/**
* @brief set signal output to gpio, one signal can output to several gpios.
*
* @param uint32_t gpio : gpio number, 0~0x2f
*
* @param uint32_t signal_idx : signal index.
* signal_idx == 0x100, cancel output put to the gpio
*
* @param bool out_inv : the signal output is invert or not
*
* @param bool oen_inv : the signal output enable is invert or not
*
* @return None
*/
void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv);
/**
* @brief Select pad as a gpio function from IOMUX.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
*
* @return None
*/
void gpio_pad_select_gpio(uint32_t gpio_num);
/**
* @brief Set pad driver capability.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
*
* @param uint32_t drv : 0-3
*
* @return None
*/
void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv);
/**
* @brief Pull up the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
*
* @return None
*/
void gpio_pad_pullup(uint32_t gpio_num);
/**
* @brief Pull down the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
*
* @return None
*/
void gpio_pad_pulldown(uint32_t gpio_num);
/**
* @brief Unhold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
*
* @return None
*/
void gpio_pad_unhold(uint32_t gpio_num);
/**
* @brief Hold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
*
* @return None
*/
void gpio_pad_hold(uint32_t gpio_num);
/**
* @brief enable gpio pad input.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
*
* @return None
*/
void gpio_pad_input_enable(uint32_t gpio_num);
/**
* @brief disable gpio pad input.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
*
* @return None
*/
void gpio_pad_input_disable(uint32_t gpio_num);
/**
* @}
*/
#ifdef __cplusplus
}
#endif

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components/esp_rom/include/esp32h4/rom/hmac.h
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/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_HMAC_H_
#define _ROM_HMAC_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdlib.h>
#include "efuse.h"
void ets_hmac_enable(void);
void ets_hmac_disable(void);
/* Use the "upstream" HMAC key (ETS_EFUSE_KEY_PURPOSE_HMAC_UP)
to digest a message.
*/
int ets_hmac_calculate_message(ets_efuse_block_t key_block, const void *message, size_t message_len, uint8_t *hmac);
/* Calculate a downstream HMAC message to temporarily enable JTAG, or
to generate a Digital Signature data decryption key.
- purpose must be ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE
or ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG
- key_block must be in range ETS_EFUSE_BLOCK_KEY0 toETS_EFUSE_BLOCK_KEY6.
This efuse block must have the corresponding purpose set in "purpose", or
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL.
The result of this HMAC calculation is only made available "downstream" to the
corresponding hardware module, and cannot be accessed by software.
*/
int ets_hmac_calculate_downstream(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose);
/* Invalidate a downstream HMAC value previously calculated by ets_hmac_calculate_downstream().
*
* - purpose must match a previous call to ets_hmac_calculate_downstream().
*
* After this function is called, the corresponding internal operation (JTAG or DS) will no longer
* have access to the generated key.
*/
int ets_hmac_invalidate_downstream(ets_efuse_purpose_t purpose);
#ifdef __cplusplus
}
#endif
#endif // _ROM_HMAC_H_

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components/esp_rom/include/esp32h4/rom/libc_stubs.h
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/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_LIBC_STUBS_H_
#define _ROM_LIBC_STUBS_H_
#include <sys/lock.h>
#include <stddef.h>
#include <stdint.h>
#include <stdio.h>
#include <stdarg.h>
#include <reent.h>
#include <errno.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
ESP32 ROM code contains implementations of some of C library functions.
Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall
implementation defined in the following struct.
The table itself, by default, is not allocated in RAM. A global pointer syscall_table_ptr is used to
set the address
So, before using any of the C library functions (except for pure functions and memcpy/memset functions),
application must allocate syscall table structure for each CPU being used, and populate it with pointers
to actual implementations of corresponding syscalls.
*/
struct syscall_stub_table
{
struct _reent* (*__getreent)(void);
void* (*_malloc_r)(struct _reent *r, size_t);
void (*_free_r)(struct _reent *r, void*);
void* (*_realloc_r)(struct _reent *r, void*, size_t);
void* (*_calloc_r)(struct _reent *r, size_t, size_t);
void (*_abort)(void);
int (*_system_r)(struct _reent *r, const char*);
int (*_rename_r)(struct _reent *r, const char*, const char*);
clock_t (*_times_r)(struct _reent *r, struct tms *);
int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *);
void (*_raise_r)(struct _reent *r);
int (*_unlink_r)(struct _reent *r, const char*);
int (*_link_r)(struct _reent *r, const char*, const char*);
int (*_stat_r)(struct _reent *r, const char*, struct stat *);
int (*_fstat_r)(struct _reent *r, int, struct stat *);
void* (*_sbrk_r)(struct _reent *r, ptrdiff_t);
int (*_getpid_r)(struct _reent *r);
int (*_kill_r)(struct _reent *r, int, int);
void (*_exit_r)(struct _reent *r, int);
int (*_close_r)(struct _reent *r, int);
int (*_open_r)(struct _reent *r, const char *, int, int);
int (*_write_r)(struct _reent *r, int, const void *, int);
int (*_lseek_r)(struct _reent *r, int, int, int);
int (*_read_r)(struct _reent *r, int, void *, int);
#ifdef _RETARGETABLE_LOCKING
void (*_retarget_lock_init)(_LOCK_T *lock);
void (*_retarget_lock_init_recursive)(_LOCK_T *lock);
void (*_retarget_lock_close)(_LOCK_T lock);
void (*_retarget_lock_close_recursive)(_LOCK_T lock);
void (*_retarget_lock_acquire)(_LOCK_T lock);
void (*_retarget_lock_acquire_recursive)(_LOCK_T lock);
int (*_retarget_lock_try_acquire)(_LOCK_T lock);
int (*_retarget_lock_try_acquire_recursive)(_LOCK_T lock);
void (*_retarget_lock_release)(_LOCK_T lock);
void (*_retarget_lock_release_recursive)(_LOCK_T lock);
#else
void (*_lock_init)(_lock_t *lock);
void (*_lock_init_recursive)(_lock_t *lock);
void (*_lock_close)(_lock_t *lock);
void (*_lock_close_recursive)(_lock_t *lock);
void (*_lock_acquire)(_lock_t *lock);
void (*_lock_acquire_recursive)(_lock_t *lock);
int (*_lock_try_acquire)(_lock_t *lock);
int (*_lock_try_acquire_recursive)(_lock_t *lock);
void (*_lock_release)(_lock_t *lock);
void (*_lock_release_recursive)(_lock_t *lock);
#endif
int (*_printf_float)(struct _reent *data, void *pdata, FILE * fp, int (*pfunc) (struct _reent *, FILE *, const char *, size_t len), va_list * ap);
int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap);
void (*__assert_func) (const char *file, int line, const char * func, const char *failedexpr) __attribute__((noreturn));
void (*__sinit) (struct _reent *r);
void (*_cleanup_r) (struct _reent* r);
};
extern struct syscall_stub_table *syscall_table_ptr;
#ifdef __cplusplus
} // extern "C"
#endif
#endif /* _ROM_LIBC_STUBS_H_ */

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components/esp_rom/include/esp32h4/rom/lldesc.h
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/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_LLDESC_H_
#define _ROM_LLDESC_H_
#include <stdint.h>
#include "sys/queue.h"
#include "esp_rom_lldesc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define LLDESC_TX_MBLK_SIZE 268 /* */
#define LLDESC_RX_SMBLK_SIZE 64 /* small block size, for small mgmt frame */
#define LLDESC_RX_MBLK_SIZE 524 /* rx is large sinec we want to contain mgmt frame in one block*/
#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE 64 /* it is a small buffer which is a cycle link*/
#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE 256 /*for ampdu entry*/
#ifdef ESP_MAC_5
#define LLDESC_TX_MBLK_NUM 116 /* 64K / 256 */
#define LLDESC_RX_MBLK_NUM 82 /* 64K / 512 MAX 172*/
#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4
#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 12
#else
#ifdef SBUF_RXTX
#define LLDESC_TX_MBLK_NUM_MAX (2 * 48) /* 23K / 260 - 8 */
#define LLDESC_RX_MBLK_NUM_MAX (2 * 48) /* 23K / 524 */
#define LLDESC_TX_MBLK_NUM_MIN (2 * 16) /* 23K / 260 - 8 */
#define LLDESC_RX_MBLK_NUM_MIN (2 * 16) /* 23K / 524 */
#endif
#define LLDESC_TX_MBLK_NUM 10 //(2 * 32) /* 23K / 260 - 8 */
#ifdef IEEE80211_RX_AMPDU
#define LLDESC_RX_MBLK_NUM 30
#else
#define LLDESC_RX_MBLK_NUM 10
#endif /*IEEE80211_RX_AMPDU*/
#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4
#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 8
#endif /* !ESP_MAC_5 */
typedef struct tx_ampdu_entry_s {
uint32_t sub_len : 12,
dili_num : 7,
: 1,
null_byte: 2,
data : 1,
enc : 1,
seq : 8;
} tx_ampdu_entry_t;
typedef struct lldesc_chain_s {
lldesc_t *head;
lldesc_t *tail;
} lldesc_chain_t;
#ifdef SBUF_RXTX
enum sbuf_mask_s {
SBUF_MOVE_NO = 0,
SBUF_MOVE_TX2RX,
SBUF_MOVE_RX2TX,
} ;
#define SBUF_MOVE_STEP 8
#endif
#define LLDESC_SIZE sizeof(struct lldesc_s)
/* SLC Descriptor */
#define LLDESC_OWNER_MASK 0x80000000
#define LLDESC_OWNER_SHIFT 31
#define LLDESC_SW_OWNED 0
#define LLDESC_HW_OWNED 1
#define LLDESC_EOF_MASK 0x40000000
#define LLDESC_EOF_SHIFT 30
#define LLDESC_SOSF_MASK 0x20000000
#define LLDESC_SOSF_SHIFT 29
#define LLDESC_LENGTH_MASK 0x00fff000
#define LLDESC_LENGTH_SHIFT 12
#define LLDESC_SIZE_MASK 0x00000fff
#define LLDESC_SIZE_SHIFT 0
#define LLDESC_ADDR_MASK 0x000fffff
static inline uint32_t lldesc_get_chain_length(lldesc_t *head)
{
lldesc_t *ds = head;
uint32_t len = 0;
while (ds) {
len += ds->length;
ds = STAILQ_NEXT(ds, qe);
}
return len;
}
static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len)
{
ds->owner = owner;
ds->eof = eof;
ds->sosf = sosf;
ds->length = len;
}
#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len) do { \
(_desc)->owner = (_owner); \
(_desc)->eof = (_eof); \
(_desc)->sosf = (_sosf); \
(_desc)->length = (_len); \
} while(0)
#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size)
#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
#ifdef __cplusplus
}
#endif
#endif /* _ROM_LLDESC_H_ */

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components/esp_rom/include/esp32h4/rom/md5_hash.h
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/*
* SPDX-FileCopyrightText: 2003-2005, Jouni Malinen <j@w1.fi>
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* MD5 internal definitions
* Copyright (c) 2003-2005, Jouni Malinen <j@w1.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Alternatively, this software may be distributed under the terms of BSD
* license.
*
* See README and COPYING for more details.
*/
#ifndef _ROM_MD5_HASH_H_
#define _ROM_MD5_HASH_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
struct MD5Context {
uint32_t buf[4];
uint32_t bits[2];
uint8_t in[64];
};
void MD5Init(struct MD5Context *context);
void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len);
void MD5Final(unsigned char digest[16], struct MD5Context *context);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_MD5_HASH_H_ */

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components/esp_rom/include/esp32h4/rom/miniz.h
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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#warning "{target}/rom/miniz.h is deprecated, please use (#include "miniz.h") instead"
#include "../../miniz.h"

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components/esp_rom/include/esp32h4/rom/rom_layout.h
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/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Structure and functions for returning ROM global layout
*
* This is for address symbols defined in the linker script, which may change during ECOs.
*/
typedef struct {
void *dram0_stack_shared_mem_start;
void *dram0_rtos_reserved_start;
void *stack_sentry;
void *stack;
/* BTDM data */
void *data_start_btdm;
void *data_end_btdm;
void *bss_start_btdm;
void *bss_end_btdm;
void *data_start_btdm_rom;
void *data_end_btdm_rom;
void *data_start_interface_btdm;
void *data_end_interface_btdm;
void *bss_start_interface_btdm;
void *bss_end_interface_btdm;
void *dram_start_phyrom;
void *dram_end_phyrom;
void *dram_start_usbdev_rom;
void *dram_end_usbdev_rom;
void *dram_start_uart_rom;
void *dram_end_uart_rom;
} ets_rom_layout_t;
extern const ets_rom_layout_t * const ets_rom_layout_p;
#ifdef __cplusplus
}
#endif

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components/esp_rom/include/esp32h4/rom/rsa_pss.h
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/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_RSA_PSS_H_
#define _ROM_RSA_PSS_H_
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#ifdef __cplusplus
extern "C" {
#endif
#define ETS_SIG_LEN 384 /* Bytes */
#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */
typedef struct {
uint8_t n[384]; /* Public key modulus */
uint32_t e; /* Public key exponent */
uint8_t rinv[384];
uint32_t mdash;
} ets_rsa_pubkey_t;
bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest, uint8_t *verified_digest);
void ets_mgf1_sha256(const uint8_t *mgfSeed, size_t seedLen, size_t maskLen, uint8_t *mask);
bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash);
#ifdef __cplusplus
}
#endif
#endif

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components/esp_rom/include/esp32h4/rom/rtc.h
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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include <stdint.h>
#include "esp_assert.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/reset_reasons.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup rtc_apis, rtc registers and memory related apis
* @brief rtc apis
*/
/** @addtogroup rtc_apis
* @{
*/
/**************************************************************************************
* Note: *
* Some Rtc memory and registers are used, in ROM or in internal library. *
* Please do not use reserved or used rtc memory or registers. *
* *
*************************************************************************************
* RTC Memory & Store Register usage
*************************************************************************************
* rtc memory addr type size usage
* 0x3f421000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry
* 0x3f421000+SIZE_CP Slow 8192-SIZE_CP
*
* 0x3ff80000(0x40070000) Fast 8192 deep sleep entry code
*
*************************************************************************************
* RTC store registers usage
* RTC_CNTL_STORE0_REG Reserved
* RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value
* RTC_CNTL_STORE2_REG Boot time, low word
* RTC_CNTL_STORE3_REG Boot time, high word
* RTC_CNTL_STORE4_REG External XTAL frequency
* RTC_CNTL_STORE5_REG APB bus frequency
* RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY
* RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
*************************************************************************************
*/
#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG
#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG
#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG
#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG
#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG
#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
typedef enum {
AWAKE = 0, //<CPU ON
LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.
DEEP_SLEEP = BIT1 //CPU OFF, PLL OFF, only specific timer could wake up
} SLEEP_MODE;
typedef enum {
NO_MEAN = 0,
POWERON_RESET = 1, /**<1, Vbat power on reset*/
RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core*/
DEEPSLEEP_RESET = 5, /**<5, Deep Sleep reset digital core*/
TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/
RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/
TG0WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/
RTC_SW_CPU_RESET = 12, /**<12, Software reset CPU*/
RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
EFUSE_RESET = 20, /**<20, efuse reset digital core*/
USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core */
USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core */
POWER_GLITCH_RESET = 23, /**<23, power glitch reset digital core and rtc module*/
JTAG_RESET = 24, /**<24, jtag reset CPU*/
} RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
ESP_STATIC_ASSERT((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
ESP_STATIC_ASSERT((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
ESP_STATIC_ASSERT((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
ESP_STATIC_ASSERT((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
ESP_STATIC_ASSERT((soc_reset_reason_t)POWER_GLITCH_RESET == RESET_REASON_CORE_PWR_GLITCH, "POWER_GLITCH_RESET != RESET_REASON_CORE_PWR_GLITCH");
ESP_STATIC_ASSERT((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU0_JTAG, "JTAG_RESET != RESET_REASON_CPU0_JTAG");
typedef enum {
NO_SLEEP = 0,
EXT_EVENT0_TRIG = BIT0,
EXT_EVENT1_TRIG = BIT1,
GPIO_TRIG = BIT2,
TIMER_EXPIRE = BIT3,
SDIO_TRIG = BIT4,
MAC_TRIG = BIT5,
UART0_TRIG = BIT6,
UART1_TRIG = BIT7,
TOUCH_TRIG = BIT8,
SAR_TRIG = BIT9,
BT_TRIG = BIT10,
RISCV_TRIG = BIT11,
XTAL_DEAD_TRIG = BIT12,
RISCV_TRAP_TRIG = BIT13,
USB_TRIG = BIT14
} WAKEUP_REASON;
typedef enum {
DISEN_WAKEUP = NO_SLEEP,
EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
GPIO_TRIG_EN = GPIO_TRIG,
TIMER_EXPIRE_EN = TIMER_EXPIRE,
SDIO_TRIG_EN = SDIO_TRIG,
MAC_TRIG_EN = MAC_TRIG,
UART0_TRIG_EN = UART0_TRIG,
UART1_TRIG_EN = UART1_TRIG,
TOUCH_TRIG_EN = TOUCH_TRIG,
SAR_TRIG_EN = SAR_TRIG,
BT_TRIG_EN = BT_TRIG,
RISCV_TRIG_EN = RISCV_TRIG,
XTAL_DEAD_TRIG_EN = XTAL_DEAD_TRIG,
RISCV_TRAP_TRIG_EN = RISCV_TRAP_TRIG,
USB_TRIG_EN = USB_TRIG
} WAKEUP_ENABLE;
/**
* @brief Get the reset reason for CPU.
*
* @param int cpu_no : CPU no.
*
* @return RESET_REASON
*/
RESET_REASON rtc_get_reset_reason(int cpu_no);
/**
* @brief Get the wakeup cause for CPU.
*
* @param int cpu_no : CPU no.
*
* @return WAKEUP_REASON
*/
WAKEUP_REASON rtc_get_wakeup_cause(void);
typedef void (* esp_rom_wake_func_t)(void);
/**
* @brief Read stored RTC wake function address
*
* Returns pointer to wake address if a value is set in RTC registers, and stored length & CRC all valid.
* valid means that both stored stub length and stored wake function address are four-byte aligned non-zero values
* and the crc check passes
*
* @param None
*
* @return esp_rom_wake_func_t : Returns pointer to wake address if a value is set in RTC registers
*/
esp_rom_wake_func_t esp_rom_get_rtc_wake_addr(void);
/**
* @brief Store new RTC wake function address
*
* Set a new RTC wake address function. If a non-NULL function pointer is set then the function
* memory is calculated and stored also.
*
* @param entry_addr Address of function. should be 4-bytes aligned otherwise it will not start from the stub after wake from deepsleep，
* if NULL length will be ignored and all registers are cleared to 0.
*
* @param length length of function in RTC fast memory. should be less than RTC Fast memory size and aligned to 4-bytes.
* otherwise all registers are cleared to 0.
*
* @return None
*/
void esp_rom_set_rtc_wake_addr(esp_rom_wake_func_t entry_addr, size_t length);
/**
* @brief Suppress ROM log by setting specific RTC control register.
* @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
*
* @param None
*
* @return None
*/
static inline void rtc_suppress_rom_log(void)
{
/* To disable logging in the ROM, only the least significant bit of the register is used,
* but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
* you need to write to this register in the same format.
* Namely, the upper 16 bits and lower should be the same.
*/
REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
}
/**
* @brief Software Reset digital core.
*
* It is not recommended to use this function in esp-idf, use
* esp_restart() instead.
*
* @param None
*
* @return None
*/
void software_reset(void);
/**
* @brief Software Reset digital core.
*
* It is not recommended to use this function in esp-idf, use
* esp_restart() instead.
*
* @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
*
* @return None
*/
void software_reset_cpu(int cpu_no);
/**
* @}
*/
#ifdef __cplusplus
}
#endif

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components/esp_rom/include/esp32h4/rom/secure_boot.h
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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "ets_sys.h"
#include "rsa_pss.h"
#include "esp_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct ets_secure_boot_sig_block ets_secure_boot_sig_block_t;
typedef struct ets_secure_boot_signature ets_secure_boot_signature_t;
typedef struct ets_secure_boot_key_digests ets_secure_boot_key_digests_t;
/* Anti-FI measure: use full words for success/fail, instead of
0/non-zero
*/
typedef enum {
SB_SUCCESS = 0x3A5A5AA5,
SB_FAILED = 0x7533885E,
} ets_secure_boot_status_t;
/* Verify bootloader image (reconfigures cache to map),
with key digests provided as parameters.)
Can be used to verify secure boot status before enabling
secure boot permanently.
If stage_load parameter is true, bootloader is copied into staging
buffer in RAM at the same time.
If result is SB_SUCCESS, the "simple hash" of the bootloader is
copied into verified_hash.
*/
ets_secure_boot_status_t ets_secure_boot_verify_bootloader_with_keys(uint8_t *verified_hash, const ets_secure_boot_key_digests_t *trusted_keys, bool stage_load);
/* Read key digests from efuse. Any revoked/missing digests will be
marked as NULL
*/
ETS_STATUS ets_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *trusted_keys);
/* Verify supplied signature against supplied digest, using
supplied trusted key digests.
Doesn't reconfigure cache or any other hardware access except for RSA peripheral.
If result is SB_SUCCESS, the image_digest value is copied into verified_digest.
*/
ets_secure_boot_status_t ets_secure_boot_verify_signature(const ets_secure_boot_signature_t *sig, const uint8_t *image_digest, const ets_secure_boot_key_digests_t *trusted_keys, uint8_t *verified_digest);
/* Revoke a public key digest in efuse.
@param index Digest to revoke. Must be 0, 1 or 2.
*/
void ets_secure_boot_revoke_public_key_digest(int index);
#define CRC_SIGN_BLOCK_LEN 1196
#define SIG_BLOCK_PADDING 4096
#define ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC 0xE7
/* Secure Boot V2 signature block
(Up to 3 in a signature sector are appended to the image)
*/
struct ets_secure_boot_sig_block {
uint8_t magic_byte;
uint8_t version;
uint8_t _reserved1;
uint8_t _reserved2;
uint8_t image_digest[32];
ets_rsa_pubkey_t key;
uint8_t signature[384];
uint32_t block_crc;
uint8_t _padding[16];
};
ESP_STATIC_ASSERT(sizeof(ets_secure_boot_sig_block_t) == 1216, "invalid sig block size");
#define SECURE_BOOT_NUM_BLOCKS 3
/* V2 Secure boot signature sector (up to 3 blocks) */
struct ets_secure_boot_signature {
ets_secure_boot_sig_block_t block[SECURE_BOOT_NUM_BLOCKS];
uint8_t _padding[4096 - (sizeof(ets_secure_boot_sig_block_t) * SECURE_BOOT_NUM_BLOCKS)];
};
ESP_STATIC_ASSERT(sizeof(ets_secure_boot_signature_t) == 4096, "invalid sig sector size");
#define MAX_KEY_DIGESTS 3
struct ets_secure_boot_key_digests {
const void *key_digests[MAX_KEY_DIGESTS];
bool allow_key_revoke;
};
#ifdef __cplusplus
}
#endif

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components/esp_rom/include/esp32h4/rom/sha.h
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/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_SHA_H_
#define _ROM_SHA_H_
#include <stdint.h>
#include <stdbool.h>
#include "ets_sys.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
SHA1 = 0,
SHA2_224,
SHA2_256,
SHA_TYPE_MAX
} SHA_TYPE;
typedef struct SHAContext {
bool start;
bool in_hardware; // Is this context currently in peripheral? Needs to be manually cleared if multiple SHAs are interleaved
SHA_TYPE type;
uint32_t state[16]; // For SHA1/SHA224/SHA256, used 8, other used 16
unsigned char buffer[128]; // For SHA1/SHA224/SHA256, used 64, other used 128
uint32_t total_bits[4];
} SHA_CTX;
void ets_sha_enable(void);
void ets_sha_disable(void);
ets_status_t ets_sha_init(SHA_CTX *ctx, SHA_TYPE type);
ets_status_t ets_sha_starts(SHA_CTX *ctx, uint16_t sha512_t);
void ets_sha_get_state(SHA_CTX *ctx);
void ets_sha_process(SHA_CTX *ctx, const unsigned char *input);
void ets_sha_update(SHA_CTX *ctx, const unsigned char *input, uint32_t input_bytes, bool update_ctx);
ets_status_t ets_sha_finish(SHA_CTX *ctx, unsigned char *output);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_SHA_H_ */

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components/esp_rom/include/esp32h4/rom/spi_flash.h
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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "esp_rom_spiflash.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1)
#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1)
#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1)
#define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1)
#define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1)
#define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1)
#define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1)
#define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1)
#define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1)
#define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1)
#define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1)
#define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1)
#define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1)
#define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1)
#define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1)
#define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1)
#define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1)
#define SPI0_R_QIO_DUMMY_CYCLELEN 5
#define SPI0_R_QIO_ADDR_BITSLEN 23
#define SPI0_R_FAST_DUMMY_CYCLELEN 7
#define SPI0_R_DIO_DUMMY_CYCLELEN 3
#define SPI0_R_FAST_ADDR_BITSLEN 23
#define SPI0_R_SIO_ADDR_BITSLEN 23
#define SPI1_R_QIO_DUMMY_CYCLELEN 5
#define SPI1_R_QIO_ADDR_BITSLEN 23
#define SPI1_R_FAST_DUMMY_CYCLELEN 7
#define SPI1_R_DIO_DUMMY_CYCLELEN 3
#define SPI1_R_DIO_ADDR_BITSLEN 23
#define SPI1_R_FAST_ADDR_BITSLEN 23
#define SPI1_R_SIO_ADDR_BITSLEN 23
#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23
#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_MEM_WRSR_2B
//SPI address register
#define ESP_ROM_SPIFLASH_BYTES_LEN 24
#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf
typedef void (* spi_flash_func_t)(void);
typedef esp_rom_spiflash_result_t (* spi_flash_op_t)(void);
typedef esp_rom_spiflash_result_t (* spi_flash_erase_t)(uint32_t);
typedef esp_rom_spiflash_result_t (* spi_flash_rd_t)(uint32_t, uint32_t*, int);
typedef esp_rom_spiflash_result_t (* spi_flash_wr_t)(uint32_t, const uint32_t*, int);
typedef esp_rom_spiflash_result_t (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t);
typedef esp_rom_spiflash_result_t (* spi_flash_wren_t)(void*);
typedef esp_rom_spiflash_result_t (* spi_flash_erase_area_t)(uint32_t, uint32_t);
typedef struct {
uint8_t pp_addr_bit_len;
uint8_t se_addr_bit_len;
uint8_t be_addr_bit_len;
uint8_t rd_addr_bit_len;
uint32_t read_sub_len;
uint32_t write_sub_len;
spi_flash_op_t unlock;
spi_flash_erase_t erase_sector;
spi_flash_erase_t erase_block;
spi_flash_rd_t read;
spi_flash_wr_t write;
spi_flash_ewr_t encrypt_write;
spi_flash_func_t check_sus;
spi_flash_wren_t wren;
spi_flash_op_t wait_idle;
spi_flash_erase_area_t erase_area;
} spiflash_legacy_funcs_t;
typedef struct {
uint8_t data_length;
uint8_t read_cmd0;
uint8_t read_cmd1;
uint8_t write_cmd;
uint16_t data_mask;
uint16_t data;
} esp_rom_spiflash_common_cmd_t;
/**
* @brief SPI Read Flash status register. We use CMD 0x05 (RDSR).
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t *status : The pointer to which to return the Flash status value.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status);
/**
* @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2).
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t *status : The pointer to which to return the Flash status value.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status);
/**
* @brief Write status to Flash status register.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t status_value : Value to .
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : write OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : write error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value);
/**
* @brief Use a command to Read Flash status register.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t*status : The pointer to which to return the Flash status value.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd);
/**
* @brief Config SPI Flash read mode when init.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
*
* This function does not try to set the QIO Enable bit in the status register, caller is responsible for this.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : config error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode);
/**
* @brief Config SPI Flash clock divisor.
* Please do not call this function in SDK.
*
* @param uint8_t freqdiv: clock divisor.
*
* @param uint8_t spi: 0 for SPI0, 1 for SPI1.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : config error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi);
/**
* @brief Clear all SR bits except QE bit.
* Please do not call this function in SDK.
*
* @param None.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void);
/**
* @brief Clear all SR bits except QE bit.
* Please do not call this function in SDK.
*
* @param None.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void);
/**
* @brief Update SPI Flash parameter.
* Please do not call this function in SDK.
*
* @param uint32_t deviceId : Device ID read from SPI, the low 32 bit.
*
* @param uint32_t chip_size : The Flash size.
*
* @param uint32_t block_size : The Flash block size.
*
* @param uint32_t sector_size : The Flash sector size.
*
* @param uint32_t page_size : The Flash page size.
*
* @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD).
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Update error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size,
uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
/**
* @brief Erase whole flash chip.
* Please do not call this function in SDK.
*
* @param None
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void);
/**
* @brief Erase a 64KB block of flash
* Uses SPI flash command D8H.
* Please do not call this function in SDK.
*
* @param uint32_t block_num : Which block to erase.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num);
/**
* @brief Erase a sector of flash.
* Uses SPI flash command 20H.
* Please do not call this function in SDK.
*
* @param uint32_t sector_num : Which sector to erase.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num);
/**
* @brief Erase some sectors.
* Please do not call this function in SDK.
*
* @param uint32_t start_addr : Start addr to erase, should be sector aligned.
*
* @param uint32_t area_len : Length to erase, should be sector aligned.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len);
/**
* @brief Write Data to Flash, you should Erase it yourself if need.
* Please do not call this function in SDK.
*
* @param uint32_t dest_addr : Address to write, should be 4 bytes aligned.
*
* @param const uint32_t *src : The pointer to data which is to write.
*
* @param uint32_t len : Length to write, should be 4 bytes aligned.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Write error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len);
/**
* @brief Read Data from Flash, you should Erase it yourself if need.
* Please do not call this function in SDK.
*
* @param uint32_t src_addr : Address to read, should be 4 bytes aligned.
*
* @param uint32_t *dest : The buf to read the data.
*
* @param uint32_t len : Length to read, should be 4 bytes aligned.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Read error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len);
/**
* @brief SPI1 go into encrypto mode.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void esp_rom_spiflash_write_encrypted_enable(void);
/**
* @brief SPI1 go out of encrypto mode.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void esp_rom_spiflash_write_encrypted_disable(void);
/**
* @brief Write data to flash with transparent encryption.
* @note Sectors to be written should already be erased.
*
* @note Please do not call this function in SDK.
*
* @param uint32_t flash_addr : Address to write, should be 32 byte aligned.
*
* @param uint32_t *data : The pointer to data to write. Note, this pointer must
* be 32 bit aligned and the content of the data will be
* modified by the encryption function.
*
* @param uint32_t len : Length to write, should be 32 bytes aligned.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully.
* ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len);
/** @brief Wait until SPI flash write operation is complete
*
* @note Please do not call this function in SDK.
*
* Reads the Write In Progress bit of the SPI flash status register,
* repeats until this bit is zero (indicating write complete).
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete
* ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi);
/** @brief Enable Quad I/O pin functions
*
* @note Please do not call this function in SDK.
*
* Sets the HD & WP pin functions for Quad I/O modes, based on the
* efuse SPI pin configuration.
*
* @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O.
*
* @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig().
* - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored.
* - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored.
* - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used
* to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI).
* Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral.
*/
void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig);
/**
* @brief Clear WEL bit unconditionally.
*
* @return always ESP_ROM_SPIFLASH_RESULT_OK
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void);
/**
* @brief Set WREN bit.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @return always ESP_ROM_SPIFLASH_RESULT_OK
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi);
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
#ifdef __cplusplus
}
#endif

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components/esp_rom/include/esp32h4/rom/tjpgd.h
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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*----------------------------------------------------------------------------/
/ TJpgDec - Tiny JPEG Decompressor include file (C)ChaN, 2012
/----------------------------------------------------------------------------*/
#ifndef _TJPGDEC
#define _TJPGDEC
/*---------------------------------------------------------------------------*/
/* System Configurations */
#define JD_SZBUF 512 /* Size of stream input buffer */
#define JD_FORMAT 0 /* Output pixel format 0:RGB888 (3 BYTE/pix), 1:RGB565 (1 WORD/pix) */
#define JD_USE_SCALE 1 /* Use descaling feature for output */
#define JD_TBLCLIP 1 /* Use table for saturation (might be a bit faster but increases 1K bytes of code size) */
/*---------------------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif
/* These types must be 16-bit, 32-bit or larger integer */
typedef int INT;
typedef unsigned int UINT;
/* These types must be 8-bit integer */
typedef char CHAR;
typedef unsigned char UCHAR;
typedef unsigned char BYTE;
/* These types must be 16-bit integer */
typedef short SHORT;
typedef unsigned short USHORT;
typedef unsigned short WORD;
typedef unsigned short WCHAR;
/* These types must be 32-bit integer */
typedef long LONG;
typedef unsigned long ULONG;
typedef unsigned long DWORD;
/* Error code */
typedef enum {
JDR_OK = 0, /* 0: Succeeded */
JDR_INTR, /* 1: Interrupted by output function */
JDR_INP, /* 2: Device error or wrong termination of input stream */
JDR_MEM1, /* 3: Insufficient memory pool for the image */
JDR_MEM2, /* 4: Insufficient stream input buffer */
JDR_PAR, /* 5: Parameter error */
JDR_FMT1, /* 6: Data format error (may be damaged data) */
JDR_FMT2, /* 7: Right format but not supported */
JDR_FMT3 /* 8: Not supported JPEG standard */
} JRESULT;
/* Rectangular structure */
typedef struct {
WORD left, right, top, bottom;
} JRECT;
/* Decompressor object structure */
typedef struct JDEC JDEC;
struct JDEC {
UINT dctr; /* Number of bytes available in the input buffer */
BYTE *dptr; /* Current data read ptr */
BYTE *inbuf; /* Bit stream input buffer */
BYTE dmsk; /* Current bit in the current read byte */
BYTE scale; /* Output scaling ratio */
BYTE msx, msy; /* MCU size in unit of block (width, height) */
BYTE qtid[3]; /* Quantization table ID of each component */
SHORT dcv[3]; /* Previous DC element of each component */
WORD nrst; /* Restart inverval */
UINT width, height; /* Size of the input image (pixel) */
BYTE *huffbits[2][2]; /* Huffman bit distribution tables [id][dcac] */
WORD *huffcode[2][2]; /* Huffman code word tables [id][dcac] */
BYTE *huffdata[2][2]; /* Huffman decoded data tables [id][dcac] */
LONG *qttbl[4]; /* Dequaitizer tables [id] */
void *workbuf; /* Working buffer for IDCT and RGB output */
BYTE *mcubuf; /* Working buffer for the MCU */
void *pool; /* Pointer to available memory pool */
UINT sz_pool; /* Size of momory pool (bytes available) */
UINT (*infunc)(JDEC *, BYTE *, UINT); /* Pointer to jpeg stream input function */
void *device; /* Pointer to I/O device identifiler for the session */
};
/* TJpgDec API functions */
JRESULT jd_prepare (JDEC *, UINT(*)(JDEC *, BYTE *, UINT), void *, UINT, void *);
JRESULT jd_decomp (JDEC *, UINT(*)(JDEC *, void *, JRECT *), BYTE);
#ifdef __cplusplus
}
#endif
#endif /* _TJPGDEC */

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components/esp_rom/include/esp32h4/rom/uart.h
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/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_UART_H_
#define _ROM_UART_H_
#include "esp_types.h"
#include "esp_attr.h"
#include "ets_sys.h"
#include "soc/soc.h"
#include "soc/uart_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup uart_apis, uart configuration and communication related apis
* @brief uart apis
*/
/** @addtogroup uart_apis
* @{
*/
#define RX_BUFF_SIZE 0x400
#define TX_BUFF_SIZE 100
//uart int enalbe register ctrl bits
#define UART_RCV_INTEN BIT0
#define UART_TRX_INTEN BIT1
#define UART_LINE_STATUS_INTEN BIT2
//uart int identification ctrl bits
#define UART_INT_FLAG_MASK 0x0E
//uart fifo ctrl bits
#define UART_CLR_RCV_FIFO BIT1
#define UART_CLR_TRX_FIFO BIT2
#define UART_RCVFIFO_TRG_LVL_BITS BIT6
//uart line control bits
#define UART_DIV_LATCH_ACCESS_BIT BIT7
//uart line status bits
#define UART_RCV_DATA_RDY_FLAG BIT0
#define UART_RCV_OVER_FLOW_FLAG BIT1
#define UART_RCV_PARITY_ERR_FLAG BIT2
#define UART_RCV_FRAME_ERR_FLAG BIT3
#define UART_BRK_INT_FLAG BIT4
#define UART_TRX_FIFO_EMPTY_FLAG BIT5
#define UART_TRX_ALL_EMPTY_FLAG BIT6 // include fifo and shift reg
#define UART_RCV_ERR_FLAG BIT7
//send and receive message frame head
#define FRAME_FLAG 0x7E
typedef enum {
UART_LINE_STATUS_INT_FLAG = 0x06,
UART_RCV_FIFO_INT_FLAG = 0x04,
UART_RCV_TMOUT_INT_FLAG = 0x0C,
UART_TXBUFF_EMPTY_INT_FLAG = 0x02
} UartIntType; //consider bit0 for int_flag
typedef enum {
RCV_ONE_BYTE = 0x0,
RCV_FOUR_BYTE = 0x1,
RCV_EIGHT_BYTE = 0x2,
RCV_FOURTEEN_BYTE = 0x3
} UartRcvFifoTrgLvl;
typedef enum {
FIVE_BITS = 0x0,
SIX_BITS = 0x1,
SEVEN_BITS = 0x2,
EIGHT_BITS = 0x3
} UartBitsNum4Char;
typedef enum {
ONE_STOP_BIT = 1,
ONE_HALF_STOP_BIT = 2,
TWO_STOP_BIT = 3
} UartStopBitsNum;
typedef enum {
NONE_BITS = 0,
ODD_BITS = 2,
EVEN_BITS = 3
} UartParityMode;
typedef enum {
STICK_PARITY_DIS = 0,
STICK_PARITY_EN = 2
} UartExistParity;
typedef enum {
BIT_RATE_9600 = 9600,
BIT_RATE_19200 = 19200,
BIT_RATE_38400 = 38400,
BIT_RATE_57600 = 57600,
BIT_RATE_115200 = 115200,
BIT_RATE_230400 = 230400,
BIT_RATE_460800 = 460800,
BIT_RATE_921600 = 921600
} UartBautRate;
typedef enum {
NONE_CTRL,
HARDWARE_CTRL,
XON_XOFF_CTRL
} UartFlowCtrl;
typedef enum {
EMPTY,
UNDER_WRITE,
WRITE_OVER
} RcvMsgBuffState;
typedef struct {
uint8_t *pRcvMsgBuff;
uint8_t *pWritePos;
uint8_t *pReadPos;
uint8_t TrigLvl;
RcvMsgBuffState BuffState;
} RcvMsgBuff;
typedef struct {
uint32_t TrxBuffSize;
uint8_t *pTrxBuff;
} TrxMsgBuff;
typedef enum {
BAUD_RATE_DET,
WAIT_SYNC_FRM,
SRCH_MSG_HEAD,
RCV_MSG_BODY,
RCV_ESC_CHAR,
} RcvMsgState;
typedef struct {
UartBautRate baut_rate;
UartBitsNum4Char data_bits;
UartExistParity exist_parity;
UartParityMode parity; // chip size in byte
UartStopBitsNum stop_bits;
UartFlowCtrl flow_ctrl;
uint8_t buff_uart_no; //indicate which uart use tx/rx buffer
RcvMsgBuff rcv_buff;
// TrxMsgBuff trx_buff;
RcvMsgState rcv_state;
int received;
} UartDevice;
/**
* @brief Init uart device struct value and reset uart0/uart1 rx.
* Please do not call this function in SDK.
*
* @param rxBuffer, must be a pointer to RX_BUFF_SIZE bytes or NULL
*
* @return None
*/
void uartAttach(void *rxBuffer);
/**
* @brief Init uart0 or uart1 for UART download booting mode.
* Please do not call this function in SDK.
*
* @param uint8_t uart_no : 0 for UART0, else for UART1.
*
* @param uint32_t clock : clock used by uart module, to adjust baudrate.
*
* @return None
*/
void Uart_Init(uint8_t uart_no, uint32_t clock);
/**
* @brief Modify uart baudrate.
* This function will reset RX/TX fifo for uart.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @param uint32_t DivLatchValue : (clock << 4)/baudrate.
*
* @return None
*/
void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue);
/**
* @brief Switch printf channel of uart_tx_one_char.
* Please do not call this function when printf.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @return None
*/
void uart_tx_switch(uint8_t uart_no);
/**
* @brief Output a char to printf channel, wait until fifo not full.
*
* @param None
*
* @return OK.
*/
ETS_STATUS uart_tx_one_char(uint8_t TxChar);
/**
* @brief Output a char to message exchange channel, wait until fifo not full.
* Please do not call this function in SDK.
*
* @param None
*
* @return OK.
*/
ETS_STATUS uart_tx_one_char2(uint8_t TxChar);
/**
* @brief Wait until uart tx full empty.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @return None.
*/
void uart_tx_flush(uint8_t uart_no);
/**
* @brief Wait until uart tx full empty and the last char send ok.
*
* @param uart_no : 0 for UART0, 1 for UART1, 2 for UART2
*
* The function defined in ROM code has a bug, so we define the correct version
* here for compatibility.
*/
void uart_tx_wait_idle(uint8_t uart_no);
/**
* @brief Get an input char from message channel.
* Please do not call this function in SDK.
*
* @param uint8_t *pRxChar : the pointer to store the char.
*
* @return OK for successful.
* FAIL for failed.
*/
ETS_STATUS uart_rx_one_char(uint8_t *pRxChar);
/**
* @brief Get an input char from message channel, wait until successful.
* Please do not call this function in SDK.
*
* @param None
*
* @return char : input char value.
*/
char uart_rx_one_char_block(void);
/**
* @brief Get an input string line from message channel.
* Please do not call this function in SDK.
*
* @param uint8_t *pString : the pointer to store the string.
*
* @param uint8_t MaxStrlen : the max string length, incude '\0'.
*
* @return OK.
*/
ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen);
/**
* @brief Get an char from receive buffer.
* Please do not call this function in SDK.
*
* @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer.
*
* @param uint8_t *pRxByte : the pointer to store the char.
*
* @return OK for successful.
* FAIL for failed.
*/
ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte);
/**
* @brief Get all chars from receive buffer.
* Please do not call this function in SDK.
*
* @param uint8_t *pCmdLn : the pointer to store the string.
*
* @return OK for successful.
* FAIL for failed.
*/
ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn);
/**
* @brief Get uart configuration struct.
* Please do not call this function in SDK.
*
* @param None
*
* @return UartDevice * : uart configuration struct pointer.
*/
UartDevice *GetUartDevice(void);
/**
* @brief Send an packet to download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *p : the pointer to output string.
*
* @param int len : the string length.
*
* @return None.
*/
void send_packet(uint8_t *p, int len);
/**
* @brief Receive an packet from download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *p : the pointer to input string.
*
* @param int len : If string length > len, the string will be truncated.
*
* @param uint8_t is_sync : 0, only one UART module;
* 1, two UART modules.
*
* @return int : the length of the string.
*/
int recv_packet(uint8_t *p, int len, uint8_t is_sync);
extern UartDevice UartDev;
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_UART_H_ */

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components/esp_system/ld/esp32h4/memory.ld.in
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/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* ESP32-H4 Linker Script Memory Layout
* This file describes the memory layout (memory blocks) by virtual memory addresses.
* This linker script is passed through the C preprocessor to include configuration options.
* Please use preprocessor features sparingly!
* Restrict to simple macros with numeric values, and/or #if/#endif blocks.
*/
#include "sdkconfig.h"
#include "ld.common"
#if CONFIG_BOOTLOADER_RESERVE_RTC_MEM
#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC
#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE)
#else
#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE)
#endif // not CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC
#else
#define ESP_BOOTLOADER_RESERVE_RTC 0
#endif // not CONFIG_BOOTLOADER_RESERVE_RTC_MEM
#define SRAM_IRAM_START 0x4037C000
#define SRAM_DRAM_START 0x3FC7C000
#define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C3 */
#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START)
#define SRAM_DRAM_END 0x403D0000 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */
#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE)
#define SRAM_DRAM_ORG (SRAM_DRAM_START + ICACHE_SIZE)
#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG
#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
MEMORY
{
/**
* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
* of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
* are connected to the data port of the CPU and eg allow byte-wise access.
*/
/* IRAM for PRO CPU. */
iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* Flash mapped instruction data */
iram0_2_seg (RX) : org = 0x42000020, len = 0x800000-0x20
/**
* (0x20 offset above is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).)
*/
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/**
* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
* Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
*/
dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* Flash mapped constant data */
drom0_0_seg (R) : org = 0x3C000020, len = 0x800000-0x20
/* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/**
* RTC fast memory (executable). Persists over deep sleep.
*/
rtc_iram_seg(RWX) : org = 0x50000000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC
}
/* Heap ends at top of dram0_0_seg */
_heap_end = 0x40000000;
_data_seg_org = ORIGIN(rtc_data_seg);
/**
* The lines below define location alias for .rtc.data section
* As C3 only has RTC fast memory, this is not configurable like on other targets
*/
REGION_ALIAS("rtc_data_seg", rtc_iram_seg );
REGION_ALIAS("rtc_slow_seg", rtc_iram_seg );
REGION_ALIAS("rtc_data_location", rtc_iram_seg );
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
REGION_ALIAS("default_code_seg", iram0_2_seg);
#else
REGION_ALIAS("default_code_seg", iram0_0_seg);
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
REGION_ALIAS("default_rodata_seg", drom0_0_seg);
#else
REGION_ALIAS("default_rodata_seg", dram0_0_seg);
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/**
* If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
* also be first in the segment.
*/
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg),
".flash_rodata_dummy section must be placed at the beginning of the rodata segment.")
#endif
#if CONFIG_ESP_SYSTEM_USE_EH_FRAME
ASSERT ((__eh_frame_end > __eh_frame), "Error: eh_frame size is null!");
ASSERT ((__eh_frame_hdr_end > __eh_frame_hdr), "Error: eh_frame_hdr size is null!");
#endif

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components/esp_system/ld/esp32h4/sections.ld.in
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/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Default entry point */
ENTRY(call_start_cpu0);
SECTIONS
{
/**
* RTC fast memory holds RTC wake stub code,
* including from any source file named rtc_wake_stub*.c
*/
.rtc.text :
{
. = ALIGN(4);
_rtc_fast_start = ABSOLUTE(.);
mapping[rtc_text]
*rtc_wake_stub*.*(.literal .text .literal.* .text.*)
*(.rtc_text_end_test)
/* 16B padding for possible CPU prefetch and 4B alignment for PMS split lines */
. += _esp_memprot_prefetch_pad_size;
. = ALIGN(4);
_rtc_text_end = ABSOLUTE(.);
} > rtc_iram_seg
/**
* This section located in RTC FAST Memory area.
* It holds data marked with RTC_FAST_ATTR attribute.
* See the file "esp_attr.h" for more information.
*/
.rtc.force_fast :
{
. = ALIGN(4);
_rtc_force_fast_start = ABSOLUTE(.);
mapping[rtc_force_fast]
*(.rtc.force_fast .rtc.force_fast.*)
. = ALIGN(4) ;
_rtc_force_fast_end = ABSOLUTE(.);
} > rtc_data_seg
/**
* RTC data section holds RTC wake stub
* data/rodata, including from any source file
* named rtc_wake_stub*.c and the data marked with
* RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
* The memory location of the data is dependent on
* CONFIG_ESP32H4_RTCDATA_IN_FAST_MEM option.
*/
.rtc.data :
{
_rtc_data_start = ABSOLUTE(.);
mapping[rtc_data]
*rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .srodata.*)
_rtc_data_end = ABSOLUTE(.);
} > rtc_data_location
/* RTC bss, from any source file named rtc_wake_stub*.c */
.rtc.bss (NOLOAD) :
{
_rtc_bss_start = ABSOLUTE(.);
*rtc_wake_stub*.*(.bss .bss.* .sbss .sbss.*)
*rtc_wake_stub*.*(COMMON)
mapping[rtc_bss]
_rtc_bss_end = ABSOLUTE(.);
} > rtc_data_location
/**
* This section holds data that should not be initialized at power up
* and will be retained during deep sleep.
* User data marked with RTC_NOINIT_ATTR will be placed
* into this section. See the file "esp_attr.h" for more information.
* The memory location of the data is dependent on CONFIG_ESP32H4_RTCDATA_IN_FAST_MEM option.
*/
.rtc_noinit (NOLOAD):
{
. = ALIGN(4);
_rtc_noinit_start = ABSOLUTE(.);
*(.rtc_noinit .rtc_noinit.*)
. = ALIGN(4) ;
_rtc_noinit_end = ABSOLUTE(.);
} > rtc_data_location
/**
* This section located in RTC SLOW Memory area.
* It holds data marked with RTC_SLOW_ATTR attribute.
* See the file "esp_attr.h" for more information.
*/
.rtc.force_slow :
{
. = ALIGN(4);
_rtc_force_slow_start = ABSOLUTE(.);
*(.rtc.force_slow .rtc.force_slow.*)
. = ALIGN(4) ;
_rtc_force_slow_end = ABSOLUTE(.);
} > rtc_slow_seg
/* Get size of rtc slow data based on rtc_data_location alias */
_rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
? (_rtc_force_slow_end - _rtc_data_start)
: (_rtc_force_slow_end - _rtc_force_slow_start);
_rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
? (_rtc_force_fast_end - _rtc_fast_start)
: (_rtc_noinit_end - _rtc_fast_start);
ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)),
"RTC_SLOW segment data does not fit.")
ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)),
"RTC_FAST segment data does not fit.")
.iram0.text :
{
_iram_start = ABSOLUTE(.);
/* Vectors go to start of IRAM */
ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned");
KEEP(*(.exception_vectors.text));
. = ALIGN(4);
_invalid_pc_placeholder = ABSOLUTE(.);
/* Code marked as running out of IRAM */
_iram_text_start = ABSOLUTE(.);
mapping[iram0_text]
} > iram0_0_seg
/**
* This section is required to skip .iram0.text area because iram0_0_seg and
* dram0_0_seg reflect the same address space on different buses.
*/
.dram0.dummy (NOLOAD):
{
. = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
} > dram0_0_seg
.dram0.data :
{
_data_start = ABSOLUTE(.);
*(.gnu.linkonce.d.*)
*(.data1)
__global_pointer$ = . + 0x800;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.gnu.linkonce.s2.*)
*(.jcr)
mapping[dram0_data]
_data_end = ABSOLUTE(.);
. = ALIGN(4);
} > dram0_0_seg
/**
* This section holds data that should not be initialized at power up.
* The section located in Internal SRAM memory region. The macro _NOINIT
* can be used as attribute to place data into this section.
* See the "esp_attr.h" file for more information.
*/
.noinit (NOLOAD):
{
. = ALIGN(4);
_noinit_start = ABSOLUTE(.);
*(.noinit .noinit.*)
. = ALIGN(4) ;
_noinit_end = ABSOLUTE(.);
} > dram0_0_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
mapping[dram0_bss]
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.share.mem)
*(.gnu.linkonce.b.*)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
} > dram0_0_seg
ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.")
.flash.text :
{
_stext = .;
_instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */
_text_start = ABSOLUTE(.);
mapping[flash_text]
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
/** CPU will try to prefetch up to 16 bytes of
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
* safe access to up to 16 bytes after the last real instruction, add
* dummy bytes to ensure this
*/
. += 16;
_text_end = ABSOLUTE(.);
_instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */
_etext = .;
/**
* Similar to _iram_start, this symbol goes here so it is
* resolved by addr2line in preference to the first symbol in
* the flash.text segment.
*/
_flash_cache_start = ABSOLUTE(0);
} > default_code_seg
/**
* This dummy section represents the .flash.text section but in default_rodata_seg.
* Thus, it must have its alignment and (at least) its size.
*/
.flash_rodata_dummy (NOLOAD):
{
_flash_rodata_dummy_start = .;
/* Start at the same alignment constraint than .flash.text */
. = ALIGN(ALIGNOF(.flash.text));
/* Create an empty gap as big as .flash.text section */
. = . + SIZEOF(.flash.text);
/* Prepare the alignment of the section above. Few bytes (0x20) must be
* added for the mapping header. */
. = ALIGN(_esp_mmu_block_size) + 0x20;
} > default_rodata_seg
.flash.appdesc : ALIGN(0x10)
{
_rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */
_rodata_start = ABSOLUTE(.);
*(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */
*(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */
/* Create an empty gap within this section. Thanks to this, the end of this
* section will match .flash.rodata's begin address. Thus, both sections
* will be merged when creating the final bin image. */
. = ALIGN(ALIGNOF(.flash.rodata));
} >default_rodata_seg
.flash.rodata : ALIGN(0x10)
{
_flash_rodata_start = ABSOLUTE(.);
mapping[flash_rodata]
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table .gcc_except_table.*)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
. = (. + 7) & ~ 3;
/*
* C++ constructor and destructor tables
* Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt.
*
* RISC-V gcc is configured with --enable-initfini-array so it emits an .init_array section instead.
* But the init_priority sections will be sorted for iteration in ascending order during startup.
* The rest of the init_array sections is sorted for iteration in descending order during startup, however.
* Hence a different section is generated for the init_priority functions which is iterated in
* ascending order during startup. The corresponding code can be found in startup.c.
*/
__init_priority_array_start = ABSOLUTE(.);
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))
__init_priority_array_end = ABSOLUTE(.);
__init_array_start = ABSOLUTE(.);
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))
__init_array_end = ABSOLUTE(.);
KEEP (*crtbegin.*(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
/* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */
soc_reserved_memory_region_start = ABSOLUTE(.);
KEEP (*(.reserved_memory_address))
soc_reserved_memory_region_end = ABSOLUTE(.);
/* System init functions registered via ESP_SYSTEM_INIT_FN */
_esp_system_init_fn_array_start = ABSOLUTE(.);
KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*)))
_esp_system_init_fn_array_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
_thread_local_start = ABSOLUTE(.);
*(.tdata)
*(.tdata.*)
*(.tbss)
*(.tbss.*)
_thread_local_end = ABSOLUTE(.);
. = ALIGN(ALIGNOF(.eh_frame));
} > default_rodata_seg
/* Keep this section shall be at least aligned on 4 */
.eh_frame : ALIGN(4)
{
__eh_frame = ABSOLUTE(.);
KEEP (*(.eh_frame))
__eh_frame_end = ABSOLUTE(.);
/* Guarantee that this section and the next one will be merged by making
* them adjacent. */
. = ALIGN(ALIGNOF(.eh_frame_hdr));
} > default_rodata_seg
/* To avoid any exception in C++ exception frame unwinding code, this section
* shall be aligned on 8. */
.eh_frame_hdr : ALIGN(8)
{
__eh_frame_hdr = ABSOLUTE(.);
KEEP (*(.eh_frame_hdr))
__eh_frame_hdr_end = ABSOLUTE(.);
} > default_rodata_seg
/*
This section is a place where we dump all the rodata which aren't used at runtime,
so as to avoid binary size increase
*/
.flash.rodata_noload (NOLOAD) :
{
/*
This is a symbol marking the flash.rodata end, this can be used for mmu driver to maintain virtual address
We don't need to include the noload rodata in this section
*/
_rodata_reserved_end = ABSOLUTE(.);
. = ALIGN (4);
} > default_rodata_seg
/* Marks the end of IRAM code segment */
.iram0.text_end (NOLOAD) :
{
/* iram_end_test section exists for use by memprot unit tests only */
*(.iram_end_test)
/* ESP32-H4 memprot requires 16B padding for possible CPU prefetch and 512B alignment for PMS split lines */
. += _esp_memprot_prefetch_pad_size;
. = ALIGN(_esp_memprot_align_size);
_iram_text_end = ABSOLUTE(.);
} > iram0_0_seg
.iram0.data :
{
. = ALIGN(16);
_iram_data_start = ABSOLUTE(.);
mapping[iram0_data]
_iram_data_end = ABSOLUTE(.);
} > iram0_0_seg
.iram0.bss (NOLOAD) :
{
. = ALIGN(16);
_iram_bss_start = ABSOLUTE(.);
mapping[iram0_bss]
_iram_bss_end = ABSOLUTE(.);
. = ALIGN(16);
_iram_end = ABSOLUTE(.);
} > iram0_0_seg
/* Marks the end of data, bss and possibly rodata */
.dram0.heap_start (NOLOAD) :
{
. = ALIGN (16);
_heap_start = ABSOLUTE(.);
} > dram0_0_seg
}
ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
"IRAM0 segment data does not fit.")
ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
"DRAM segment data does not fit.")

13
components/esp_system/port/soc/esp32h4/CMakeLists.txt
View File

@ -1,13 +0,0 @@
set(srcs "clk.c"
"reset_reason.c"
"system_internal.c"
"cache_err_int.c"
"apb_backup_dma.c"
"../../arch/riscv/expression_with_stack.c"
"../../arch/riscv/expression_with_stack_asm.S"
"../../arch/riscv/panic_arch.c"
"../../arch/riscv/debug_stubs.c")
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" ${srcs})
target_sources(${COMPONENT_LIB} PRIVATE ${srcs})

27
components/esp_system/port/soc/esp32h4/Kconfig.cpu
View File

@ -1,27 +0,0 @@
choice ESP_DEFAULT_CPU_FREQ_MHZ
prompt "CPU frequency"
default ESP_DEFAULT_CPU_FREQ_MHZ_64 if IDF_ENV_FPGA
default ESP_DEFAULT_CPU_FREQ_MHZ_96 if !IDF_ENV_FPGA
help
CPU frequency to be set on application startup.
config ESP_DEFAULT_CPU_FREQ_MHZ_16
bool "16 MHz"
depends on IDF_ENV_FPGA #ESP32H4-TODO: IDF-3786
config ESP_DEFAULT_CPU_FREQ_MHZ_32
bool "32 MHz"
depends on IDF_ENV_FPGA #ESP32H4-TODO: IDF-3786
config ESP_DEFAULT_CPU_FREQ_MHZ_64
bool "64 MHz"
depends on IDF_ENV_FPGA #ESP32H4-TODO: IDF-3786
config ESP_DEFAULT_CPU_FREQ_MHZ_96
bool "96 MHz"
depends on !IDF_ENV_FPGA
endchoice
config ESP_DEFAULT_CPU_FREQ_MHZ
int
default 16 if ESP_DEFAULT_CPU_FREQ_MHZ_16
default 32 if ESP_DEFAULT_CPU_FREQ_MHZ_32
default 64 if ESP_DEFAULT_CPU_FREQ_MHZ_64
default 96 if ESP_DEFAULT_CPU_FREQ_MHZ_96

45
components/esp_system/port/soc/esp32h4/Kconfig.system
View File

@ -1,45 +0,0 @@
menu "Brownout Detector"
config ESP_BROWNOUT_DET
bool "Hardware brownout detect & reset"
default y
help
The ESP32-H4 has a built-in brownout detector which can detect if the voltage is lower than
a specific value. If this happens, it will reset the chip in order to prevent unintended
behaviour.
choice ESP_BROWNOUT_DET_LVL_SEL
prompt "Brownout voltage level"
depends on ESP_BROWNOUT_DET
default ESP_BROWNOUT_DET_LVL_SEL_7
help
The brownout detector will reset the chip when the supply voltage is approximately
below this level. Note that there may be some variation of brownout voltage level
between each chip.
#The voltage levels here are estimates, more work needs to be done to figure out the exact voltages
#of the brownout threshold levels.
config ESP_BROWNOUT_DET_LVL_SEL_7
bool "2.51V"
config ESP_BROWNOUT_DET_LVL_SEL_6
bool "2.64V"
config ESP_BROWNOUT_DET_LVL_SEL_5
bool "2.76V"
config ESP_BROWNOUT_DET_LVL_SEL_4
bool "2.92V"
config ESP_BROWNOUT_DET_LVL_SEL_3
bool "3.10V"
config ESP_BROWNOUT_DET_LVL_SEL_2
bool "3.27V"
endchoice
config ESP_BROWNOUT_DET_LVL
int
default 2 if ESP_BROWNOUT_DET_LVL_SEL_2
default 3 if ESP_BROWNOUT_DET_LVL_SEL_3
default 4 if ESP_BROWNOUT_DET_LVL_SEL_4
default 5 if ESP_BROWNOUT_DET_LVL_SEL_5
default 6 if ESP_BROWNOUT_DET_LVL_SEL_6
default 7 if ESP_BROWNOUT_DET_LVL_SEL_7
endmenu

40
components/esp_system/port/soc/esp32h4/apb_backup_dma.c
View File

@ -1,40 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc_caps.h"
#if SOC_APB_BACKUP_DMA
#include "esp_attr.h"
#include "freertos/FreeRTOS.h"
#include "freertos/portmacro.h"
#include "esp32h4/rom/apb_backup_dma.h"
static portMUX_TYPE s_apb_backup_dma_mutex = portMUX_INITIALIZER_UNLOCKED;
static void IRAM_ATTR apb_backup_dma_lock(void)
{
if (xPortInIsrContext()) {
portENTER_CRITICAL_ISR(&s_apb_backup_dma_mutex);
} else {
portENTER_CRITICAL(&s_apb_backup_dma_mutex);
}
}
static void IRAM_ATTR apb_backup_dma_unlock(void)
{
if (xPortInIsrContext()) {
portEXIT_CRITICAL_ISR(&s_apb_backup_dma_mutex);
} else {
portEXIT_CRITICAL(&s_apb_backup_dma_mutex);
}
}
void esp_apb_backup_dma_lock_init(void)
{
ets_apb_backup_init_lock_func(apb_backup_dma_lock, apb_backup_dma_unlock);
}
#endif

78
components/esp_system/port/soc/esp32h4/cache_err_int.c
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@ -1,78 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
The cache has an interrupt that can be raised as soon as an access to a cached
region (flash) is done without the cache being enabled. We use that here
to panic the CPU, which from a debugging perspective is better than grabbing bad
data from the bus.
*/
#include "esp_rom_sys.h"
#include "esp_attr.h"
#include "esp_log.h"
#include "esp_intr_alloc.h"
#include "soc/periph_defs.h"
#include "riscv/interrupt.h"
#include "hal/cache_ll.h"
static const char *TAG = "CACHE_ERR";
void esp_cache_err_int_init(void)
{
const uint32_t core_id = 0;
/* Disable cache interrupts if enabled. */
ESP_INTR_DISABLE(ETS_CACHEERR_INUM);
/**
* Bind all cache errors to ETS_CACHEERR_INUM interrupt. we will deal with
* them in handler by different types
* I) Cache access error
* 1. dbus trying to write to icache
* 2. dbus authentication fail
* 3. cpu access icache while dbus is disabled [1]
* 4. ibus authentication fail
* 5. ibus trying to write icache
* 6. cpu access icache while ibus is disabled
* II) Cache illegal error
* 1. dbus counter overflow
* 2. ibus counter overflow
* 3. mmu entry fault
* 4. icache preload configurations fault
* 5. icache sync configuration fault
*
* [1]: On ESP32H4 boards, the caches are shared but buses are still
* distinct. So, we have an ibus and a dbus sharing the same cache.
* This error can occur if the dbus performs a request but the icache
* (or simply cache) is disabled.
*/
esp_rom_route_intr_matrix(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
/* Set the type and priority to cache error interrupts. */
esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
/* On the hardware side, start by clearing all the bits reponsible for cache access error */
cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
/* Then enable cache access error interrupts. */
cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
/* Same goes for cache illegal error: start by clearing the bits and then
* set them back. */
ESP_DRAM_LOGV(TAG, "illegal error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ILG_EVENT_MASK);
cache_ll_l1_clear_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK);
cache_ll_l1_enable_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK);
/* Enable the interrupts for cache error. */
ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
}
int esp_cache_err_get_cpuid(void)
{
return 0;
}

286
components/esp_system/port/soc/esp32h4/clk.c
View File

@ -1,286 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <sys/cdefs.h>
#include <sys/time.h>
#include <sys/param.h>
#include "sdkconfig.h"
#include "esp_attr.h"
#include "esp_log.h"
#include "esp_cpu.h"
#include "esp_clk_internal.h"
#include "esp32h4/rom/ets_sys.h"
#include "esp32h4/rom/uart.h"
#include "esp32h4/rom/rtc.h"
#include "soc/system_reg.h"
#include "soc/soc.h"
#include "soc/rtc.h"
#include "soc/rtc_periph.h"
#include "soc/i2s_reg.h"
#include "hal/wdt_hal.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_clk.h"
#include "bootloader_clock.h"
#include "soc/syscon_reg.h"
#include "esp_rom_uart.h"
/* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
* Larger values increase startup delay. Smaller values may cause false positive
* detection (i.e. oscillator runs for a few cycles and then stops).
*/
#define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
#define MHZ (1000000)
/* Indicates that this 32k oscillator gets input from external oscillator, rather
* than a crystal.
*/
#define EXT_OSC_FLAG BIT(3)
/* This is almost the same as soc_rtc_slow_clk_src_t, except that we define
* an extra enum member for the external 32k oscillator.
* For convenience, lower 2 bits should correspond to soc_rtc_slow_clk_src_t values.
*/
typedef enum {
SLOW_CLK_RTC = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150 kHz RC oscillator
SLOW_CLK_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32 kHz XTAL
SLOW_CLK_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32 KHz RC oscillator
SLOW_CLK_32K_EXT_OSC = SOC_RTC_SLOW_CLK_SRC_XTAL32K | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin
} slow_clk_sel_t;
static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
static const char *TAG = "clk";
__attribute__((weak)) void esp_clk_init(void)
{
rtc_config_t cfg = RTC_CONFIG_DEFAULT();
soc_reset_reason_t rst_reas;
rst_reas = esp_rom_get_reset_reason(0);
if (rst_reas == RESET_REASON_CHIP_POWER_ON) {
cfg.cali_ocode = 1;
}
rtc_init(cfg);
assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_32M);
rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
#ifdef CONFIG_BOOTLOADER_WDT_ENABLE
// WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
// If the frequency changes from 150kHz to 32kHz, then the timeout set for the WDT will increase 4.6 times.
// Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec).
// This prevents excessive delay before resetting in case the supply voltage is drawdown.
// (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 1.6sec * 150/32 = 7.5 sec).
wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
wdt_hal_feed(&rtc_wdt_ctx);
//Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same
wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
#endif
#if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
#elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
#elif defined(CONFIG_RTC_CLK_SRC_INT_RC32K)
select_rtc_slow_clk(SLOW_CLK_RC32K);
#else
select_rtc_slow_clk(SLOW_CLK_RTC);
#endif
#ifdef CONFIG_BOOTLOADER_WDT_ENABLE
// After changing a frequency WDT timeout needs to be set for new frequency.
stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000);
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
wdt_hal_feed(&rtc_wdt_ctx);
wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
#endif
rtc_cpu_freq_config_t old_config, new_config;
rtc_clk_cpu_freq_get_config(&old_config);
const uint32_t old_freq_mhz = old_config.freq_mhz;
const uint32_t new_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ;
bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
assert(res);
// Wait for UART TX to finish, otherwise some UART output will be lost
// when switching APB frequency
esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
if (res) {
rtc_clk_cpu_freq_set_config(&new_config);
}
// Re calculate the ccount to make time calculation correct.
esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz );
}
static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
{
soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V;
uint32_t cal_val = 0;
/* number of times to repeat 32k XTAL calibration
* before giving up and switching to the internal RC
*/
int retry_32k_xtal = 3;
do {
if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
/* 32k XTAL oscillator needs to be enabled and running before it can
* be used. Hardware doesn't have a direct way of checking if the
* oscillator is running. Here we use rtc_clk_cal function to count
* the number of main XTAL cycles in the given number of 32k XTAL
* oscillator cycles. If the 32k XTAL has not started up, calibration
* will time out, returning 0.
*/
ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
if (slow_clk == SLOW_CLK_32K_XTAL) {
rtc_clk_32k_enable(true);
} else if (slow_clk == SLOW_CLK_32K_EXT_OSC) {
rtc_clk_32k_enable_external();
}
// When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
if (SLOW_CLK_CAL_CYCLES > 0) {
cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES);
if (cal_val == 0) {
if (retry_32k_xtal-- > 0) {
continue;
}
ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 150 kHz oscillator");
rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
}
}
} else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
rtc_clk_rc32k_enable(true);
}
rtc_clk_slow_src_set(rtc_slow_clk_src);
if (SLOW_CLK_CAL_CYCLES > 0) {
/* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable.
*/
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
} else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
}
} while (cal_val == 0);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
esp_clk_slowclk_cal_set(cal_val);
}
void rtc_clk_select_rtc_slow_clk(void)
{
select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
}
/* This function is not exposed as an API at this point.
* All peripheral clocks are default enabled after chip is powered on.
* This function disables some peripheral clocks when cpu starts.
* These peripheral clocks are enabled when the peripherals are initialized
* and disabled when they are de-initialized.
*/
__attribute__((weak)) void esp_perip_clk_init(void)
{
uint32_t common_perip_clk, hwcrypto_perip_clk = 0;
uint32_t common_perip_clk1 = 0;
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
*/
if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW ||
rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1 ||
rst_reason == RESET_REASON_CPU0_JTAG) {
common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
} else {
common_perip_clk = SYSTEM_WDG_CLK_EN |
SYSTEM_I2S0_CLK_EN |
#if CONFIG_ESP_CONSOLE_UART_NUM != 0
SYSTEM_UART_CLK_EN |
#endif
#if CONFIG_ESP_CONSOLE_UART_NUM != 1
SYSTEM_UART1_CLK_EN |
#endif
SYSTEM_SPI2_CLK_EN |
SYSTEM_I2C_EXT0_CLK_EN |
SYSTEM_UHCI0_CLK_EN |
SYSTEM_RMT_CLK_EN |
SYSTEM_LEDC_CLK_EN |
SYSTEM_TIMERGROUP1_CLK_EN |
SYSTEM_SPI3_CLK_EN |
SYSTEM_SPI4_CLK_EN |
SYSTEM_TWAI_CLK_EN |
SYSTEM_I2S1_CLK_EN |
SYSTEM_SPI2_DMA_CLK_EN |
SYSTEM_SPI3_DMA_CLK_EN;
common_perip_clk1 = 0;
hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN |
SYSTEM_CRYPTO_SHA_CLK_EN |
SYSTEM_CRYPTO_RSA_CLK_EN;
}
//Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
common_perip_clk |= SYSTEM_I2S0_CLK_EN |
#if CONFIG_ESP_CONSOLE_UART_NUM != 0
SYSTEM_UART_CLK_EN |
#endif
#if CONFIG_ESP_CONSOLE_UART_NUM != 1
SYSTEM_UART1_CLK_EN |
#endif
SYSTEM_SPI2_CLK_EN |
SYSTEM_I2C_EXT0_CLK_EN |
SYSTEM_UHCI0_CLK_EN |
SYSTEM_RMT_CLK_EN |
SYSTEM_UHCI1_CLK_EN |
SYSTEM_SPI3_CLK_EN |
SYSTEM_SPI4_CLK_EN |
SYSTEM_I2C_EXT1_CLK_EN |
SYSTEM_I2S1_CLK_EN |
SYSTEM_SPI2_DMA_CLK_EN |
SYSTEM_SPI3_DMA_CLK_EN;
common_perip_clk1 = 0;
/* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
* the current is not reduced when disable I2S clock.
*/
// TOCK(check replacement)
// REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
// REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
/* Disable some peripheral clocks. */
CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk);
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk);
CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1);
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, common_perip_clk1);
/* Disable hardware crypto clocks. */
CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
/* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE);
/* Enable TimerGroup 0 clock to ensure its reference counter will never
* be decremented to 0 during normal operation and preventing it from
* being disabled.
* If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
* registers (Flashboot protection included) will be reenabled, and some
* seconds later, will trigger an unintended reset.
*/
periph_module_enable(PERIPH_TIMG0_MODULE);
}

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/*
* SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "esp_system.h"
#include "esp_rom_sys.h"
#include "esp_private/system_internal.h"
#include "soc/rtc_periph.h"
#include "esp32h4/rom/rtc.h"
static void esp_reset_reason_clear_hint(void);
static esp_reset_reason_t s_reset_reason;
static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
{
switch (rtc_reset_reason) {
case RESET_REASON_CHIP_POWER_ON:
return ESP_RST_POWERON;
case RESET_REASON_CPU0_SW:
case RESET_REASON_CORE_SW:
if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
return reset_reason_hint;
}
return ESP_RST_SW;
case RESET_REASON_CORE_DEEP_SLEEP:
return ESP_RST_DEEPSLEEP;
case RESET_REASON_CORE_MWDT0:
return ESP_RST_TASK_WDT;
case RESET_REASON_CORE_MWDT1:
return ESP_RST_INT_WDT;
case RESET_REASON_CORE_RTC_WDT:
case RESET_REASON_SYS_RTC_WDT:
case RESET_REASON_SYS_SUPER_WDT:
case RESET_REASON_CPU0_RTC_WDT:
case RESET_REASON_CPU0_MWDT0:
case RESET_REASON_CPU0_MWDT1:
return ESP_RST_WDT;
case RESET_REASON_SYS_BROWN_OUT:
return ESP_RST_BROWNOUT;
default:
return ESP_RST_UNKNOWN;
}
}
static void __attribute__((constructor)) esp_reset_reason_init(void)
{
esp_reset_reason_t hint = esp_reset_reason_get_hint();
s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint);
if (hint != ESP_RST_UNKNOWN) {
esp_reset_reason_clear_hint();
}
}
esp_reset_reason_t esp_reset_reason(void)
{
return s_reset_reason;
}
/* Reset reason hint is stored in RTC_RESET_CAUSE_REG, a.k.a. RTC_CNTL_STORE6_REG,
* a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the
* deep sleep wake stub entry address and for reset reason hint, since wake stub
* is only used for deep sleep reset, and in this case the reason provided by
* esp_rom_get_reset_reason is unambiguous.
*
* Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG):
* the value is replicated in low and high half-words. In addition to that,
* MSB is set to 1, which doesn't happen when RTC_CNTL_STORE6_REG contains
* deep sleep wake stub address.
*/
#define RST_REASON_BIT 0x80000000
#define RST_REASON_MASK 0x7FFF
#define RST_REASON_SHIFT 16
/* in IRAM, can be called from panic handler */
void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
{
assert((hint & (~RST_REASON_MASK)) == 0);
uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;
REG_WRITE(RTC_RESET_CAUSE_REG, val);
}
/* in IRAM, can be called from panic handler */
esp_reset_reason_t esp_reset_reason_get_hint(void)
{
uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG);
uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK;
uint32_t low = reset_reason_hint & RST_REASON_MASK;
if ((reset_reason_hint & RST_REASON_BIT) == 0 || high != low) {
return ESP_RST_UNKNOWN;
}
return (esp_reset_reason_t) low;
}
static inline void esp_reset_reason_clear_hint(void)
{
REG_WRITE(RTC_RESET_CAUSE_REG, 0);
}

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/*
* SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include "sdkconfig.h"
#include "esp_system.h"
#include "esp_private/system_internal.h"
#include "esp_attr.h"
#include "esp_efuse.h"
#include "esp_log.h"
#include "riscv/rv_utils.h"
#include "esp_rom_uart.h"
#include "soc/gpio_reg.h"
#include "soc/timer_group_reg.h"
#include "esp_cpu.h"
#include "soc/rtc.h"
#include "esp_private/rtc_clk.h"
#include "soc/rtc_periph.h"
#include "soc/syscon_reg.h"
#include "soc/system_reg.h"
#include "hal/wdt_hal.h"
#include "esp_private/cache_err_int.h"
#include "esp32h4/rom/cache.h"
#include "esp32h4/rom/rtc.h"
/* "inner" restart function for after RTOS, interrupts & anything else on this
* core are already stopped. Stalls other core, resets hardware,
* triggers restart.
*/
void IRAM_ATTR esp_restart_noos(void)
{
// Disable interrupts
rv_utils_intr_global_disable();
// Enable RTC watchdog for 1 second
wdt_hal_context_t rtc_wdt_ctx;
wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
//Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
// Disable TG0/TG1 watchdogs
wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
wdt_hal_write_protect_disable(&wdt0_context);
wdt_hal_disable(&wdt0_context);
wdt_hal_write_protect_enable(&wdt0_context);
wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
wdt_hal_write_protect_disable(&wdt1_context);
wdt_hal_disable(&wdt1_context);
wdt_hal_write_protect_enable(&wdt1_context);
// Flush any data left in UART FIFOs
esp_rom_uart_tx_wait_idle(0);
esp_rom_uart_tx_wait_idle(1);
// Disable cache
Cache_Disable_ICache();
// 2nd stage bootloader reconfigures SPI flash signals.
// Reset them to the defaults expected by ROM.
WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
// Reset timer/spi/uart
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST);
SET_PERI_REG_MASK(SYSTEM_MODEM_RST_EN_REG,
SYSTEM_IEEE802154BB_RST | SYSTEM_IEEE802154MAC_RST |
SYSTEM_BT_RST | SYSTEM_BTMAC_RST |
SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST |
SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST
);
REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
REG_WRITE(SYSTEM_MODEM_RST_EN_REG, 0);
// Reset dma
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
// Set CPU back to XTAL source, same as hard reset, but keep BBPLL on so that USB Serial JTAG can log at 1st stage bootloader.
#if !CONFIG_IDF_ENV_FPGA
rtc_clk_cpu_set_to_default_config();
#endif
// Reset CPU
esp_rom_software_reset_cpu(0);
while (true) {
;
}
}

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components/heap/port/esp32h4/memory_layout.c
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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <stdlib.h>
#include "esp_attr.h"
#include "sdkconfig.h"
#include "soc/soc.h"
#include "heap_memory_layout.h"
#include "esp_heap_caps.h"
/**
* @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
* Each type of memory map consists of one or more regions in the address space.
* Each type contains an array of prioritized capabilities.
* Types with later entries are only taken if earlier ones can't fulfill the memory request.
*
* - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory.
* - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
* - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
* - Most other malloc caps only fit in one region anyway.
*
*/
/* Index of memory in `soc_memory_types[]` */
enum {
SOC_MEMORY_TYPE_DRAM = 0,
SOC_MEMORY_TYPE_STACK_DRAM = 1,
SOC_MEMORY_TYPE_DIRAM = 2,
SOC_MEMORY_TYPE_STACK_DIRAM = 3,
SOC_MEMORY_TYPE_RTCRAM = 4,
SOC_MEMORY_TYPE_NUM,
};
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
// Type 0: DRAM
[SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
// Type 1: DRAM used for startup stacks
[SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
// Type 2: DRAM which has an alias on the I-port
[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
// Type 3: DIRAM used for startup stacks
[SOC_MEMORY_TYPE_STACK_DIRAM] = { "STACK/DIRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, true},
// Type 4: RTCRAM
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT }, false, false},
};
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM
#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DRAM
#else
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM
#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DIRAM
#endif
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
/**
* @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
*
* @note Because of requirements in the coalescing code which merges adjacent regions,
* this list should always be sorted from low to high by start address.
*
*/
/**
* Register the shared buffer area of the last memory block into the heap during heap initialization
*/
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
const soc_memory_region_t soc_memory_regions[] = {
{ 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1, can be used as trace memory
{ 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level2, can be used as trace memory
{ 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DEFAULT, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory
#endif
};
const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end;
/**
* Reserved memory regions.
* These are removed from the soc_memory_regions array when heaps are created.
*
*/
// Static data region. DRAM used by data+bss and possibly rodata
SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data);
// Target has a big D/IRAM region, the part used by code is reserved
// The address of the D/I bus are in the same order, directly shift IRAM address to get reserved DRAM address
#define I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_end - I_D_OFFSET, iram_code);
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
/* We use _rtc_force_slow_end not _rtc_noinit_end here, as rtc "fast" memory ends up in RTC SLOW
region on H4, no differentiation. And _rtc_force_slow_end is the end of all the static RTC sections.
*/
SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data);
#endif

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components/idf_test/include/esp32h4/idf_performance_target.h
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/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define IDF_PERFORMANCE_MIN_AES_CBC_THROUGHPUT_MBSEC 43
// SHA256 hardware throughput at 160 MHz, threshold set lower than worst case
#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 90
// esp_sha() time to process 32KB of input data from RAM
#define IDF_PERFORMANCE_MAX_TIME_SHA1_32KB 560
#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 19000
#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 210000
#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PUBLIC_OP 45000
#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PRIVATE_OP 670000
#define IDF_PERFORMANCE_MAX_ECP_P192_POINT_MULTIPLY_OP 9000
#define IDF_PERFORMANCE_MAX_ECP_P192_POINT_VERIFY_OP 300
#define IDF_PERFORMANCE_MAX_ECP_P256_POINT_MULTIPLY_OP 14000
#define IDF_PERFORMANCE_MAX_ECP_P256_POINT_VERIFY_OP 300
#define IDF_PERFORMANCE_MAX_ECDSA_P192_VERIFY_OP 32000
#define IDF_PERFORMANCE_MAX_ECDSA_P256_VERIFY_OP 49000
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 26*1000*1000
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30
// floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround)
#define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70
#define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT 140

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components/mbedtls/port/esp32h4/bignum.c
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/*
* Multi-precision integer library
* ESP32 H4 hardware accelerated parts based on mbedTLS implementation
*
* SPDX-FileCopyrightText: The Mbed TLS Contributors
*
* SPDX-License-Identifier: Apache-2.0
*
* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
*/
#include <string.h>
#include <sys/param.h>
#include "soc/hwcrypto_periph.h"
#include "esp_private/periph_ctrl.h"
#include "mbedtls/bignum.h"
#include "bignum_impl.h"
#include "soc/system_reg.h"
#include "soc/periph_defs.h"
#include "esp_crypto_lock.h"
size_t esp_mpi_hardware_words(size_t words)
{
return words;
}
void esp_mpi_enable_hardware_hw_op( void )
{
esp_crypto_mpi_lock_acquire();
/* Enable RSA hardware */
periph_module_enable(PERIPH_RSA_MODULE);
REG_CLR_BIT(SYSTEM_RSA_PD_CTRL_REG, SYSTEM_RSA_MEM_PD);
while (REG_READ(RSA_QUERY_CLEAN_REG) != 1) {
}
// Note: from enabling RSA clock to here takes about 1.3us
REG_WRITE(RSA_INTERRUPT_REG, 0);
}
void esp_mpi_disable_hardware_hw_op( void )
{
REG_SET_BIT(SYSTEM_RSA_PD_CTRL_REG, SYSTEM_RSA_MEM_PD);
/* Disable RSA hardware */
periph_module_disable(PERIPH_RSA_MODULE);
esp_crypto_mpi_lock_release();
}
void esp_mpi_interrupt_enable( bool enable )
{
REG_WRITE(RSA_INTERRUPT_REG, enable);
}
void esp_mpi_interrupt_clear( void )
{
REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1);
}
/* Copy mbedTLS MPI bignum 'mpi' to hardware memory block at 'mem_base'.
If num_words is higher than the number of words in the bignum then
these additional words will be zeroed in the memory buffer.
*/
static inline void mpi_to_mem_block(uint32_t mem_base, const mbedtls_mpi *mpi, size_t num_words)
{
uint32_t *pbase = (uint32_t *)mem_base;
uint32_t copy_words = MIN(num_words, mpi->MBEDTLS_PRIVATE(n));
/* Copy MPI data to memory block registers */
for (int i = 0; i < copy_words; i++) {
pbase[i] = mpi->MBEDTLS_PRIVATE(p)[i];
}
/* Zero any remaining memory block data */
for (int i = copy_words; i < num_words; i++) {
pbase[i] = 0;
}
}
/* Read mbedTLS MPI bignum back from hardware memory block.
Reads num_words words from block.
*/
static inline void mem_block_to_mpi(mbedtls_mpi *x, uint32_t mem_base, int num_words)
{
/* Copy data from memory block registers */
const size_t REG_WIDTH = sizeof(uint32_t);
for (size_t i = 0; i < num_words; i++) {
x->MBEDTLS_PRIVATE(p)[i] = REG_READ(mem_base + (i * REG_WIDTH));
}
/* Zero any remaining limbs in the bignum, if the buffer is bigger
than num_words */
for (size_t i = num_words; i < x->MBEDTLS_PRIVATE(n); i++) {
x->MBEDTLS_PRIVATE(p)[i] = 0;
}
}
/* Begin an RSA operation. op_reg specifies which 'START' register
to write to.
*/
static inline void start_op(uint32_t op_reg)
{
/* Clear interrupt status */
REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1);
/* Note: above REG_WRITE includes a memw, so we know any writes
to the memory blocks are also complete. */
REG_WRITE(op_reg, 1);
}
/* Wait for an RSA operation to complete.
*/
static inline void wait_op_complete(void)
{
while (REG_READ(RSA_QUERY_INTERRUPT_REG) != 1)
{ }
/* clear the interrupt */
REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1);
}
/* Read result from last MPI operation */
void esp_mpi_read_result_hw_op(mbedtls_mpi *Z, size_t z_words)
{
wait_op_complete();
mem_block_to_mpi(Z, RSA_MEM_Z_BLOCK_BASE, z_words);
}
/* Z = (X * Y) mod M
Not an mbedTLS function
*/
void esp_mpi_mul_mpi_mod_hw_op(const mbedtls_mpi *X, const mbedtls_mpi *Y, const mbedtls_mpi *M, const mbedtls_mpi *Rinv, mbedtls_mpi_uint Mprime, size_t num_words)
{
REG_WRITE(RSA_LENGTH_REG, (num_words - 1));
/* Load M, X, Rinv, Mprime (Mprime is mod 2^32) */
mpi_to_mem_block(RSA_MEM_X_BLOCK_BASE, X, num_words);
mpi_to_mem_block(RSA_MEM_Y_BLOCK_BASE, Y, num_words);
mpi_to_mem_block(RSA_MEM_M_BLOCK_BASE, M, num_words);
mpi_to_mem_block(RSA_MEM_RB_BLOCK_BASE, Rinv, num_words);
REG_WRITE(RSA_M_DASH_REG, Mprime);
start_op(RSA_MOD_MULT_START_REG);
}
/* Z = (X ^ Y) mod M
*/
void esp_mpi_exp_mpi_mod_hw_op(const mbedtls_mpi *X, const mbedtls_mpi *Y, const mbedtls_mpi *M, const mbedtls_mpi *Rinv, mbedtls_mpi_uint Mprime, size_t num_words)
{
size_t y_bits = mbedtls_mpi_bitlen(Y);
REG_WRITE(RSA_LENGTH_REG, (num_words - 1));
/* Load M, X, Rinv, Mprime (Mprime is mod 2^32) */
mpi_to_mem_block(RSA_MEM_X_BLOCK_BASE, X, num_words);
mpi_to_mem_block(RSA_MEM_Y_BLOCK_BASE, Y, num_words);
mpi_to_mem_block(RSA_MEM_M_BLOCK_BASE, M, num_words);
mpi_to_mem_block(RSA_MEM_RB_BLOCK_BASE, Rinv, num_words);
REG_WRITE(RSA_M_DASH_REG, Mprime);
/* Enable acceleration options */
REG_WRITE(RSA_CONSTANT_TIME_REG, 0);
REG_WRITE(RSA_SEARCH_ENABLE_REG, 1);
REG_WRITE(RSA_SEARCH_POS_REG, y_bits - 1);
/* Execute first stage montgomery multiplication */
start_op(RSA_MODEXP_START_REG);
REG_WRITE(RSA_SEARCH_ENABLE_REG, 0);
}
/* Z = X * Y */
void esp_mpi_mul_mpi_hw_op(const mbedtls_mpi *X, const mbedtls_mpi *Y, size_t num_words)
{
/* Copy X (right-extended) & Y (left-extended) to memory block */
mpi_to_mem_block(RSA_MEM_X_BLOCK_BASE, X, num_words);
mpi_to_mem_block(RSA_MEM_Z_BLOCK_BASE + num_words * 4, Y, num_words);
/* NB: as Y is left-extended, we don't zero the bottom words_mult words of Y block.
This is OK for now because zeroing is done by hardware when we do esp_mpi_acquire_hardware().
*/
REG_WRITE(RSA_LENGTH_REG, (num_words * 2 - 1));
start_op(RSA_MULT_START_REG);
}
/**
* @brief Special-case of (X * Y), where we use hardware montgomery mod
multiplication to calculate result where either A or B are >2048 bits so
can't use the standard multiplication method.
*
*/
void esp_mpi_mult_mpi_failover_mod_mult_hw_op(const mbedtls_mpi *X, const mbedtls_mpi *Y, size_t num_words)
{
/* M = 2^num_words - 1, so block is entirely FF */
for (int i = 0; i < num_words; i++) {
REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4, UINT32_MAX);
}
/* Mprime = 1 */
REG_WRITE(RSA_M_DASH_REG, 1);
REG_WRITE(RSA_LENGTH_REG, num_words - 1);
/* Load X & Y */
mpi_to_mem_block(RSA_MEM_X_BLOCK_BASE, X, num_words);
mpi_to_mem_block(RSA_MEM_Y_BLOCK_BASE, Y, num_words);
/* Rinv = 1, write first word */
REG_WRITE(RSA_MEM_RB_BLOCK_BASE, 1);
/* Zero out rest of the Rinv words */
for (int i = 1; i < num_words; i++) {
REG_WRITE(RSA_MEM_RB_BLOCK_BASE + i * 4, 0);
}
start_op(RSA_MOD_MULT_START_REG);
}

8
examples/bluetooth/bluedroid/ble/ble_ancs/sdkconfig.defaults.esp32h4
View File

@ -1,8 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set
CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set

10
examples/bluetooth/bluedroid/ble/ble_compatibility_test/sdkconfig.defaults.esp32h4
View File

@ -1,10 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set
CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set
CONFIG_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_RTC_CLK_CAL_CYCLES=576

10
examples/bluetooth/bluedroid/ble/ble_eddystone/sdkconfig.defaults.esp32h4
View File

@ -1,10 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set
CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set
CONFIG_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_RTC_CLK_CAL_CYCLES=576

10
examples/bluetooth/bluedroid/ble/ble_hid_device_demo/sdkconfig.defaults.esp32h4
View File

@ -1,10 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set
CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set
CONFIG_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_RTC_CLK_CAL_CYCLES=576

10
examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.defaults.esp32h4
View File

@ -1,10 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set
CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set
CONFIG_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_RTC_CLK_CAL_CYCLES=576

10
examples/bluetooth/bluedroid/ble/ble_spp_client/sdkconfig.defaults.esp32h4
View File

@ -1,10 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set
CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set
CONFIG_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_RTC_CLK_CAL_CYCLES=576

10
examples/bluetooth/bluedroid/ble/ble_spp_server/sdkconfig.defaults.esp32h4
View File

@ -1,10 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set
CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set
CONFIG_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_RTC_CLK_CAL_CYCLES=576

10
examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.defaults.esp32h4
View File

@ -1,10 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set
CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set
CONFIG_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_RTC_CLK_CAL_CYCLES=576

10
examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.defaults.esp32h4
View File

@ -1,10 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set
CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set
CONFIG_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_RTC_CLK_CAL_CYCLES=576

10
examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults.esp32h4
View File

@ -1,10 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set
CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set
CONFIG_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_RTC_CLK_CAL_CYCLES=576

10
examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.defaults.esp32h4
View File

@ -1,10 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set
CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set
CONFIG_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_RTC_CLK_CAL_CYCLES=576

10
examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.defaults.esp32h4
View File

@ -1,10 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set
CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set
CONFIG_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_RTC_CLK_CAL_CYCLES=576

10
examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults.esp32h4
View File

@ -1,10 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set
CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set
CONFIG_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_RTC_CLK_CAL_CYCLES=576

10
examples/bluetooth/bluedroid/ble/gatt_server_service_table/sdkconfig.defaults.esp32h4
View File

@ -1,10 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set
CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set
CONFIG_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_RTC_CLK_CAL_CYCLES=576

10
examples/bluetooth/bluedroid/ble/gattc_multi_connect/sdkconfig.defaults.esp32h4
View File

@ -1,10 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set
CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set
CONFIG_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_RTC_CLK_CAL_CYCLES=576

7
examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.defaults.esp32h4
View File

@ -1,7 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
CONFIG_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_RTC_CLK_CAL_CYCLES=576

7
examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.defaults.esp32h4
View File

@ -1,7 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
CONFIG_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_RTC_CLK_CAL_CYCLES=576

7
examples/bluetooth/bluedroid/ble_50/multi-adv/sdkconfig.defaults.esp32h4
View File

@ -1,7 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
CONFIG_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_RTC_CLK_CAL_CYCLES=576

7
examples/bluetooth/bluedroid/ble_50/peroidic_adv/sdkconfig.defaults.esp32h4
View File

@ -1,7 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
CONFIG_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_RTC_CLK_CAL_CYCLES=576

7
examples/bluetooth/bluedroid/ble_50/peroidic_sync/sdkconfig.defaults.esp32h4
View File

@ -1,7 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
CONFIG_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_RTC_CLK_CAL_CYCLES=576

10
examples/bluetooth/nimble/blecent/sdkconfig.defaults.esp32h4
View File

@ -1,10 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_ESPTOOLPY_FLASHMODE_QIO=y
CONFIG_BT_ENABLED=y
CONFIG_BT_NIMBLE_ENABLED=y
CONFIG_BT_NIMBLE_EXT_ADV=y
CONFIG_ESP32H4_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_ESP32H4_RTC_CLK_CAL_CYCLES=576

8
examples/bluetooth/nimble/bleprph/sdkconfig.defaults.esp32h4
View File

@ -1,8 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_BT_ENABLED=y
CONFIG_BT_NIMBLE_ENABLED=y
CONFIG_BT_NIMBLE_HCI_EVT_BUF_SIZE=70
CONFIG_BT_NIMBLE_EXT_ADV=y

10
examples/bluetooth/nimble/throughput_app/blecent_throughput/sdkconfig.defaults.esp32h4
View File

@ -1,10 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_ESPTOOLPY_FLASHMODE_QIO=y
CONFIG_BT_ENABLED=y
CONFIG_BT_NIMBLE_ENABLED=y
CONFIG_BT_NIMBLE_USE_ESP_TIMER=n
CONFIG_ESP32H4_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_ESP32H4_RTC_CLK_CAL_CYCLES=576

10
examples/bluetooth/nimble/throughput_app/bleprph_throughput/sdkconfig.defaults.esp32h4
View File

@ -1,10 +0,0 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32h4"
CONFIG_ESPTOOLPY_FLASHMODE_QIO=y
CONFIG_BT_ENABLED=y
CONFIG_BT_NIMBLE_ENABLED=y
CONFIG_BT_NIMBLE_USE_ESP_TIMER=n
CONFIG_ESP32H4_RTC_CLK_SRC_EXT_CRYS=y
CONFIG_ESP32H4_RTC_CLK_CAL_CYCLES=576

15
examples/common_components/env_caps/esp32h4/Kconfig.env_caps
View File

@ -1,15 +0,0 @@
config ENV_GPIO_RANGE_MIN
int
default 0
config ENV_GPIO_RANGE_MAX
int
default 25
config ENV_GPIO_IN_RANGE_MAX
int
default ENV_GPIO_RANGE_MAX
config ENV_GPIO_OUT_RANGE_MAX
int
default ENV_GPIO_RANGE_MAX

18
tools/cmake/toolchain-esp32h4.cmake
View File

@ -1,18 +0,0 @@
include($ENV{IDF_PATH}/tools/cmake/utilities.cmake)
set(CMAKE_SYSTEM_NAME Generic)
set(CMAKE_C_COMPILER riscv32-esp-elf-gcc)
set(CMAKE_CXX_COMPILER riscv32-esp-elf-g++)
set(CMAKE_ASM_COMPILER riscv32-esp-elf-gcc)
set(_CMAKE_TOOLCHAIN_PREFIX riscv32-esp-elf-)
remove_duplicated_flags("-march=rv32imc_zicsr_zifencei ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS)
set(CMAKE_C_FLAGS "${UNIQ_CMAKE_C_FLAGS}" CACHE STRING "C Compiler Base Flags" FORCE)
remove_duplicated_flags("-march=rv32imc_zicsr_zifencei ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS)
set(CMAKE_CXX_FLAGS "${UNIQ_CMAKE_CXX_FLAGS}" CACHE STRING "C++ Compiler Base Flags" FORCE)
remove_duplicated_flags("-nostartfiles -march=rv32imc_zicsr_zifencei --specs=nosys.specs \
${CMAKE_EXE_LINKER_FLAGS}"
UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS)
set(CMAKE_EXE_LINKER_FLAGS "${UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS}" CACHE STRING "Linker Base Flags" FORCE)