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xtensa: update configuration overlay for esp32s3
From LX7_ESP32_S3_MP_linux_redist.tgz with SHA256: 63f305a982b2ee94cc78e5c20e3e3eb8bf0edeeaf703af0227a418bc34f7b848 copied from xtensa-elf/arch/include/xtensa/config/ with changes: 1) pre-commit fixes applied 2) re-added CONFIGID0 and CONFIGID1 in specreg.h
This commit is contained in:
Ivan Grokhotkov
parent
d28417edbc
commit
ca5ed172a5
File diff suppressed because it is too large
Load Diff
@ -1,6 +1,6 @@
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/*
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* xtensa/config/core-matmap.h -- Memory access and translation mapping
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* parameters (CHAL) of the Xtensa processor core configuration.
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* parameters (CHAL) of the Xtensa processor core configuration.
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*
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* If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
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* this file) for more details.
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@ -9,20 +9,20 @@
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* defined in this file are derivable (at least in theory) from
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* information contained in the core-isa.h header file.
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* In particular, the following core configuration parameters are relevant:
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* XCHAL_HAVE_CACHEATTR
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* XCHAL_HAVE_MIMIC_CACHEATTR
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* XCHAL_HAVE_XLT_CACHEATTR
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* XCHAL_HAVE_PTP_MMU
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* XCHAL_ITLB_ARF_ENTRIES_LOG2
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* XCHAL_DTLB_ARF_ENTRIES_LOG2
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* XCHAL_DCACHE_IS_WRITEBACK
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* XCHAL_ICACHE_SIZE (presence of I-cache)
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* XCHAL_DCACHE_SIZE (presence of D-cache)
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* XCHAL_HW_VERSION_MAJOR
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* XCHAL_HW_VERSION_MINOR
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* XCHAL_HAVE_CACHEATTR
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* XCHAL_HAVE_MIMIC_CACHEATTR
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* XCHAL_HAVE_XLT_CACHEATTR
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* XCHAL_HAVE_PTP_MMU
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* XCHAL_ITLB_ARF_ENTRIES_LOG2
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* XCHAL_DTLB_ARF_ENTRIES_LOG2
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* XCHAL_DCACHE_IS_WRITEBACK
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* XCHAL_ICACHE_SIZE (presence of I-cache)
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* XCHAL_DCACHE_SIZE (presence of D-cache)
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* XCHAL_HW_VERSION_MAJOR
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* XCHAL_HW_VERSION_MINOR
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*/
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/* Customer ID=15127; Build=0x86d67; Copyright (c) 1999-2020 Tensilica Inc.
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/* Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Tensilica Inc.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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@ -49,60 +49,60 @@
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/*----------------------------------------------------------------------
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CACHE (MEMORY ACCESS) ATTRIBUTES
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CACHE (MEMORY ACCESS) ATTRIBUTES
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----------------------------------------------------------------------*/
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/* Cache Attribute encodings -- lists of access modes for each cache attribute: */
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#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_BYPASS XCHAL_SEP \
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XTHAL_FAM_BYPASS XCHAL_SEP \
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XTHAL_FAM_BYPASS XCHAL_SEP \
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XTHAL_FAM_BYPASS XCHAL_SEP \
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XTHAL_FAM_BYPASS XCHAL_SEP \
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XTHAL_FAM_BYPASS XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION
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#define XCHAL_LCA_LIST XTHAL_LAM_BYPASSG XCHAL_SEP \
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XTHAL_LAM_BYPASSG XCHAL_SEP \
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XTHAL_LAM_BYPASSG XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_BYPASSG XCHAL_SEP \
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XTHAL_LAM_BYPASSG XCHAL_SEP \
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XTHAL_LAM_BYPASSG XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION
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#define XCHAL_SCA_LIST XTHAL_SAM_BYPASS XCHAL_SEP \
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XTHAL_SAM_BYPASS XCHAL_SEP \
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XTHAL_SAM_BYPASS XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_BYPASS XCHAL_SEP \
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XTHAL_SAM_BYPASS XCHAL_SEP \
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XTHAL_SAM_BYPASS XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION
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#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_BYPASS XCHAL_SEP \
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XTHAL_FAM_BYPASS XCHAL_SEP \
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XTHAL_FAM_BYPASS XCHAL_SEP \
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XTHAL_FAM_BYPASS XCHAL_SEP \
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XTHAL_FAM_BYPASS XCHAL_SEP \
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XTHAL_FAM_BYPASS XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION
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#define XCHAL_LCA_LIST XTHAL_LAM_BYPASSG XCHAL_SEP \
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XTHAL_LAM_BYPASSG XCHAL_SEP \
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XTHAL_LAM_BYPASSG XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_BYPASSG XCHAL_SEP \
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XTHAL_LAM_BYPASSG XCHAL_SEP \
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XTHAL_LAM_BYPASSG XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION
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#define XCHAL_SCA_LIST XTHAL_SAM_BYPASS XCHAL_SEP \
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XTHAL_SAM_BYPASS XCHAL_SEP \
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XTHAL_SAM_BYPASS XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_BYPASS XCHAL_SEP \
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XTHAL_SAM_BYPASS XCHAL_SEP \
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XTHAL_SAM_BYPASS XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION
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#define XCHAL_CA_R (0xC0 | 0x40000000)
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#define XCHAL_CA_RX (0xD0 | 0x40000000)
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@ -115,204 +115,207 @@
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* one is returned instead (eg. writethru instead of writeback,
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* bypass instead of writethru).
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*/
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#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */
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#define XCHAL_CA_BYPASSBUF 6 /* cache disabled (bypassed) bufferable mode */
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#define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */
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#define XCHAL_CA_WRITEBACK 2 /* cache enabled (write-back) mode */
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#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 0 /* write-back no-allocate availability */
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#define XCHAL_CA_WRITEBACK_NOALLOC 2 /* cache enabled (write-back no-allocate) mode */
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#define XCHAL_CA_BYPASS_RW 0 /* cache disabled (bypassed) mode (no exec) */
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#define XCHAL_CA_WRITETHRU_RW 0 /* cache enabled (write-through) mode (no exec) (FALLBACK) */
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#define XCHAL_CA_WRITEBACK_RW 0 /* cache enabled (write-back) mode (no exec) */
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#define XCHAL_CA_WRITEBACK_NOALLOC_RW 0 /* cache enabled (write-back no-allocate) mode (no exec) */
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#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */
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#define XCHAL_CA_ISOLATE 0 /* cache isolate (accesses go to cache not memory) mode */
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#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */
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#define XCHAL_CA_BYPASSBUF 6 /* cache disabled (bypassed) bufferable mode */
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#define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */
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#define XCHAL_CA_WRITEBACK 2 /* cache enabled (write-back) mode */
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#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 0 /* write-back no-allocate availability */
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#define XCHAL_CA_WRITEBACK_NOALLOC 2 /* cache enabled (write-back no-allocate) mode */
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#define XCHAL_CA_BYPASS_RW 0 /* cache disabled (bypassed) mode (no exec) */
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#define XCHAL_CA_WRITETHRU_RW 0 /* cache enabled (write-through) mode (no exec) (FALLBACK) */
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#define XCHAL_CA_WRITEBACK_RW 0 /* cache enabled (write-back) mode (no exec) */
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#define XCHAL_CA_WRITEBACK_NOALLOC_RW 0 /* cache enabled (write-back no-allocate) mode (no exec) */
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#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */
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#define XCHAL_CA_ISOLATE 0 /* cache isolate (accesses go to cache not memory) mode */
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/*----------------------------------------------------------------------
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MMU
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MMU
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----------------------------------------------------------------------*/
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/*
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* General notes on MMU parameters.
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*
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* Terminology:
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* ASID = address-space ID (acts as an "extension" of virtual addresses)
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* VPN = virtual page number
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* PPN = physical page number
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* CA = encoded cache attribute (access modes)
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* TLB = translation look-aside buffer (term is stretched somewhat here)
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* I = instruction (fetch accesses)
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* D = data (load and store accesses)
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* way = each TLB (ITLB and DTLB) consists of a number of "ways"
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* that simultaneously match the virtual address of an access;
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* a TLB successfully translates a virtual address if exactly
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* one way matches the vaddr; if none match, it is a miss;
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* if multiple match, one gets a "multihit" exception;
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* each way can be independently configured in terms of number of
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* entries, page sizes, which fields are writable or constant, etc.
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* set = group of contiguous ways with exactly identical parameters
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* ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
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* from the page table and storing it in one of the auto-refill ways;
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* if this PTE load also misses, a miss exception is posted for s/w.
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* min-wired = a "min-wired" way can be used to map a single (minimum-sized)
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* page arbitrarily under program control; it has a single entry,
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* is non-auto-refill (some other way(s) must be auto-refill),
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* all its fields (VPN, PPN, ASID, CA) are all writable, and it
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* supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
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* restriction is that this be the only page size it supports).
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* ASID = address-space ID (acts as an "extension" of virtual addresses)
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* VPN = virtual page number
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* PPN = physical page number
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* CA = encoded cache attribute (access modes)
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* TLB = translation look-aside buffer (term is stretched somewhat here)
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* I = instruction (fetch accesses)
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* D = data (load and store accesses)
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* way = each TLB (ITLB and DTLB) consists of a number of "ways"
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* that simultaneously match the virtual address of an access;
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* a TLB successfully translates a virtual address if exactly
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* one way matches the vaddr; if none match, it is a miss;
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* if multiple match, one gets a "multihit" exception;
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* each way can be independently configured in terms of number of
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* entries, page sizes, which fields are writable or constant, etc.
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* set = group of contiguous ways with exactly identical parameters
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* ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
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* from the page table and storing it in one of the auto-refill ways;
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* if this PTE load also misses, a miss exception is posted for s/w.
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* min-wired = a "min-wired" way can be used to map a single (minimum-sized)
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* page arbitrarily under program control; it has a single entry,
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* is non-auto-refill (some other way(s) must be auto-refill),
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* all its fields (VPN, PPN, ASID, CA) are all writable, and it
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* supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
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* restriction is that this be the only page size it supports).
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*
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* TLB way entries are virtually indexed.
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* TLB ways that support multiple page sizes:
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* - must have all writable VPN and PPN fields;
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* - can only use one page size at any given time (eg. setup at startup),
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* selected by the respective ITLBCFG or DTLBCFG special register,
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* whose bits n*4+3 .. n*4 index the list of page sizes for way n
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* (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
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* this list may be sparse for auto-refill ways because auto-refill
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* ways have independent lists of supported page sizes sharing a
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* common encoding with PTE entries; the encoding is the index into
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* this list; unsupported sizes for a given way are zero in the list;
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* selecting unsupported sizes results in undefine hardware behaviour;
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* - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
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* - must have all writable VPN and PPN fields;
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* - can only use one page size at any given time (eg. setup at startup),
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* selected by the respective ITLBCFG or DTLBCFG special register,
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* whose bits n*4+3 .. n*4 index the list of page sizes for way n
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* (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
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* this list may be sparse for auto-refill ways because auto-refill
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* ways have independent lists of supported page sizes sharing a
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* common encoding with PTE entries; the encoding is the index into
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* this list; unsupported sizes for a given way are zero in the list;
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* selecting unsupported sizes results in undefine hardware behaviour;
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* - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
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*/
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#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
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#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */
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#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
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#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
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#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */
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#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */
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#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
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#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */
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#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
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#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
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#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */
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#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */
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/*** Instruction TLB: ***/
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#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
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#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
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#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
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#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */
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#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
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#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
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#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
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#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */
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/* Way set to which each way belongs: */
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#define XCHAL_ITLB_WAY0_SET 0
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#define XCHAL_ITLB_WAY0_SET 0
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/* Ways sets that are used by hardware auto-refill (ARF): */
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#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */
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#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */
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/* Way sets that are "min-wired" (see terminology comment above): */
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#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
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#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
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/* ITLB way set 0 (group of ways 0 thru 0): */
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#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
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#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
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#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
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#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
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#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
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#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
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#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
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#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
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#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
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#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
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2^PAGESZ_BITS entries in list, unsupported entries are zero */
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#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
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#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
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#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
|
||||
#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
|
||||
#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
|
||||
#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
|
||||
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
|
||||
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
|
||||
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */
|
||||
#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000
|
||||
#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000
|
||||
#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000
|
||||
#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000
|
||||
#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000
|
||||
#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000
|
||||
#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000
|
||||
#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000
|
||||
#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000
|
||||
#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000
|
||||
#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000
|
||||
#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000
|
||||
#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000
|
||||
#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000
|
||||
#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000
|
||||
#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000
|
||||
/* Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero): */
|
||||
#define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000
|
||||
#define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000
|
||||
#define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000
|
||||
#define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000
|
||||
#define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000
|
||||
#define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000
|
||||
#define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000
|
||||
#define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000
|
||||
#define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000
|
||||
#define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000
|
||||
#define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000
|
||||
#define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000
|
||||
#define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000
|
||||
#define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000
|
||||
#define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000
|
||||
#define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000
|
||||
/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */
|
||||
#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02
|
||||
|
||||
|
||||
/*** Data TLB: ***/
|
||||
|
||||
#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */
|
||||
#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
|
||||
#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */
|
||||
#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */
|
||||
#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */
|
||||
#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
|
||||
#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */
|
||||
#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */
|
||||
|
||||
/* Way set to which each way belongs: */
|
||||
#define XCHAL_DTLB_WAY0_SET 0
|
||||
#define XCHAL_DTLB_WAY0_SET 0
|
||||
|
||||
/* Ways sets that are used by hardware auto-refill (ARF): */
|
||||
#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */
|
||||
#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */
|
||||
|
||||
/* Way sets that are "min-wired" (see terminology comment above): */
|
||||
#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
|
||||
#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
|
||||
|
||||
|
||||
/* DTLB way set 0 (group of ways 0 thru 0): */
|
||||
#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
|
||||
#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
|
||||
#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
|
||||
#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
|
||||
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
|
||||
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
|
||||
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
|
||||
#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
|
||||
#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
|
||||
#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
|
||||
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
|
||||
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
|
||||
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */
|
||||
#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000
|
||||
#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000
|
||||
#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000
|
||||
#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000
|
||||
#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000
|
||||
#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000
|
||||
#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000
|
||||
#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000
|
||||
#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000
|
||||
#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000
|
||||
#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000
|
||||
#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000
|
||||
#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000
|
||||
#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000
|
||||
#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000
|
||||
#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000
|
||||
/* Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero): */
|
||||
#define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000
|
||||
#define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000
|
||||
#define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000
|
||||
#define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000
|
||||
#define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000
|
||||
#define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000
|
||||
#define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000
|
||||
#define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000
|
||||
#define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000
|
||||
#define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000
|
||||
#define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000
|
||||
#define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000
|
||||
#define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000
|
||||
#define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000
|
||||
#define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000
|
||||
#define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000
|
||||
/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */
|
||||
#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02
|
||||
|
||||
|
||||
|
||||
|
||||
#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/* Definitions for Xtensa instructions, types, and protos. */
|
||||
|
||||
/* Customer ID=15127; Build=0x86d67; Copyright (c) 2003-2004 Tensilica Inc.
|
||||
/* Customer ID=15128; Build=0x90f1f; Copyright (c) 2003-2004 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
|
||||
/* $Id: //depot/rel/Foxhill/dot.12/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
|
||||
|
||||
/* Customer ID=15127; Build=0x86d67; Copyright (c) 1998-2002 Tensilica Inc.
|
||||
/* Customer ID=15128; Build=0x90f1f; Copyright (c) 1998-2002 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
@ -33,86 +33,86 @@
|
||||
|
||||
|
||||
/* Special registers: */
|
||||
#define LBEG 0
|
||||
#define LEND 1
|
||||
#define LCOUNT 2
|
||||
#define SAR 3
|
||||
#define BR 4
|
||||
#define SCOMPARE1 12
|
||||
#define ACCLO 16
|
||||
#define ACCHI 17
|
||||
#define MR_0 32
|
||||
#define MR_1 33
|
||||
#define MR_2 34
|
||||
#define MR_3 35
|
||||
#define WINDOWBASE 72
|
||||
#define WINDOWSTART 73
|
||||
#define IBREAKENABLE 96
|
||||
#define MEMCTL 97
|
||||
#define ATOMCTL 99
|
||||
#define DDR 104
|
||||
#define IBREAKA_0 128
|
||||
#define IBREAKA_1 129
|
||||
#define DBREAKA_0 144
|
||||
#define DBREAKA_1 145
|
||||
#define DBREAKC_0 160
|
||||
#define DBREAKC_1 161
|
||||
#define LBEG 0
|
||||
#define LEND 1
|
||||
#define LCOUNT 2
|
||||
#define SAR 3
|
||||
#define BR 4
|
||||
#define SCOMPARE1 12
|
||||
#define ACCLO 16
|
||||
#define ACCHI 17
|
||||
#define MR_0 32
|
||||
#define MR_1 33
|
||||
#define MR_2 34
|
||||
#define MR_3 35
|
||||
#define WINDOWBASE 72
|
||||
#define WINDOWSTART 73
|
||||
#define IBREAKENABLE 96
|
||||
#define MEMCTL 97
|
||||
#define ATOMCTL 99
|
||||
#define DDR 104
|
||||
#define IBREAKA_0 128
|
||||
#define IBREAKA_1 129
|
||||
#define DBREAKA_0 144
|
||||
#define DBREAKA_1 145
|
||||
#define DBREAKC_0 160
|
||||
#define DBREAKC_1 161
|
||||
#define CONFIGID0 176
|
||||
#define EPC_1 177
|
||||
#define EPC_2 178
|
||||
#define EPC_3 179
|
||||
#define EPC_4 180
|
||||
#define EPC_5 181
|
||||
#define EPC_6 182
|
||||
#define EPC_7 183
|
||||
#define DEPC 192
|
||||
#define EPS_2 194
|
||||
#define EPS_3 195
|
||||
#define EPS_4 196
|
||||
#define EPS_5 197
|
||||
#define EPS_6 198
|
||||
#define EPS_7 199
|
||||
#define EPC_1 177
|
||||
#define EPC_2 178
|
||||
#define EPC_3 179
|
||||
#define EPC_4 180
|
||||
#define EPC_5 181
|
||||
#define EPC_6 182
|
||||
#define EPC_7 183
|
||||
#define DEPC 192
|
||||
#define EPS_2 194
|
||||
#define EPS_3 195
|
||||
#define EPS_4 196
|
||||
#define EPS_5 197
|
||||
#define EPS_6 198
|
||||
#define EPS_7 199
|
||||
#define CONFIGID1 208
|
||||
#define EXCSAVE_1 209
|
||||
#define EXCSAVE_2 210
|
||||
#define EXCSAVE_3 211
|
||||
#define EXCSAVE_4 212
|
||||
#define EXCSAVE_5 213
|
||||
#define EXCSAVE_6 214
|
||||
#define EXCSAVE_7 215
|
||||
#define CPENABLE 224
|
||||
#define INTERRUPT 226
|
||||
#define INTENABLE 228
|
||||
#define PS 230
|
||||
#define VECBASE 231
|
||||
#define EXCCAUSE 232
|
||||
#define DEBUGCAUSE 233
|
||||
#define CCOUNT 234
|
||||
#define PRID 235
|
||||
#define ICOUNT 236
|
||||
#define ICOUNTLEVEL 237
|
||||
#define EXCVADDR 238
|
||||
#define CCOMPARE_0 240
|
||||
#define CCOMPARE_1 241
|
||||
#define CCOMPARE_2 242
|
||||
#define MISC_REG_0 244
|
||||
#define MISC_REG_1 245
|
||||
#define MISC_REG_2 246
|
||||
#define MISC_REG_3 247
|
||||
#define EXCSAVE_1 209
|
||||
#define EXCSAVE_2 210
|
||||
#define EXCSAVE_3 211
|
||||
#define EXCSAVE_4 212
|
||||
#define EXCSAVE_5 213
|
||||
#define EXCSAVE_6 214
|
||||
#define EXCSAVE_7 215
|
||||
#define CPENABLE 224
|
||||
#define INTERRUPT 226
|
||||
#define INTENABLE 228
|
||||
#define PS 230
|
||||
#define VECBASE 231
|
||||
#define EXCCAUSE 232
|
||||
#define DEBUGCAUSE 233
|
||||
#define CCOUNT 234
|
||||
#define PRID 235
|
||||
#define ICOUNT 236
|
||||
#define ICOUNTLEVEL 237
|
||||
#define EXCVADDR 238
|
||||
#define CCOMPARE_0 240
|
||||
#define CCOMPARE_1 241
|
||||
#define CCOMPARE_2 242
|
||||
#define MISC_REG_0 244
|
||||
#define MISC_REG_1 245
|
||||
#define MISC_REG_2 246
|
||||
#define MISC_REG_3 247
|
||||
|
||||
/* Special cases (bases of special register series): */
|
||||
#define MR 32
|
||||
#define IBREAKA 128
|
||||
#define DBREAKA 144
|
||||
#define DBREAKC 160
|
||||
#define EPC 176
|
||||
#define EPS 192
|
||||
#define EXCSAVE 208
|
||||
#define CCOMPARE 240
|
||||
#define MR 32
|
||||
#define IBREAKA 128
|
||||
#define DBREAKA 144
|
||||
#define DBREAKC 160
|
||||
#define EPC 176
|
||||
#define EPS 192
|
||||
#define EXCSAVE 208
|
||||
#define CCOMPARE 240
|
||||
|
||||
/* Special names for read-only and write-only interrupt registers: */
|
||||
#define INTREAD 226
|
||||
#define INTSET 226
|
||||
#define INTCLEAR 227
|
||||
#define INTREAD 226
|
||||
#define INTSET 226
|
||||
#define INTCLEAR 227
|
||||
|
||||
#endif /* XTENSA_SPECREG_H */
|
||||
|
||||
@ -10,7 +10,7 @@
|
||||
* core-specific but system independent.
|
||||
*/
|
||||
|
||||
/* Customer ID=15127; Build=0x86d67; Copyright (c) 2000-2010 Tensilica Inc.
|
||||
/* Customer ID=15128; Build=0x90f1f; Copyright (c) 2000-2010 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
@ -40,41 +40,41 @@
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CONFIGURED SOFTWARE OPTIONS
|
||||
CONFIGURED SOFTWARE OPTIONS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */
|
||||
#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */
|
||||
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
|
||||
|
||||
#define XSHAL_ABI XTHAL_ABI_WINDOWED /* (sw-only option, selected ABI) */
|
||||
#define XSHAL_ABI XTHAL_ABI_WINDOWED /* (sw-only option, selected ABI) */
|
||||
/* The above maps to one of the following constants: */
|
||||
#define XTHAL_ABI_WINDOWED 0
|
||||
#define XTHAL_ABI_CALL0 1
|
||||
#define XTHAL_ABI_WINDOWED 0
|
||||
#define XTHAL_ABI_CALL0 1
|
||||
/* Alternatives: */
|
||||
/*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */
|
||||
/*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */
|
||||
/*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */
|
||||
/*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */
|
||||
|
||||
#define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */
|
||||
#define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */
|
||||
/* The above maps to one of the following constants: */
|
||||
#define XTHAL_CLIB_NEWLIB 0
|
||||
#define XTHAL_CLIB_UCLIBC 1
|
||||
#define XTHAL_CLIB_XCLIB 2
|
||||
#define XTHAL_CLIB_NEWLIB 0
|
||||
#define XTHAL_CLIB_UCLIBC 1
|
||||
#define XTHAL_CLIB_XCLIB 2
|
||||
/* Alternatives: */
|
||||
/*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */
|
||||
/*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */
|
||||
/*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */
|
||||
/*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */
|
||||
/*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */
|
||||
/*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */
|
||||
|
||||
#define XSHAL_USE_FLOATING_POINT 1
|
||||
#define XSHAL_USE_FLOATING_POINT 1
|
||||
|
||||
#define XSHAL_FLOATING_POINT_ABI 0
|
||||
#define XSHAL_FLOATING_POINT_ABI 0
|
||||
|
||||
/* SW workarounds enabled for HW errata: */
|
||||
|
||||
/* SW options for functional safety: */
|
||||
#define XSHAL_FUNC_SAFETY_ENABLED 0
|
||||
#define XSHAL_FUNC_SAFETY_ENABLED 0
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
DEVICE ADDRESSES
|
||||
DEVICE ADDRESSES
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
@ -85,31 +85,31 @@
|
||||
*/
|
||||
|
||||
/* I/O Block areas: */
|
||||
#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000
|
||||
#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000
|
||||
#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
|
||||
#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000
|
||||
#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000
|
||||
#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
|
||||
|
||||
#define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000
|
||||
#define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000
|
||||
#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
|
||||
#define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000
|
||||
#define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000
|
||||
#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
|
||||
|
||||
/* System ROM: */
|
||||
#define XSHAL_ROM_VADDR 0x50000000
|
||||
#define XSHAL_ROM_PADDR 0x50000000
|
||||
#define XSHAL_ROM_SIZE 0x01000000
|
||||
#define XSHAL_ROM_VADDR 0x50000000
|
||||
#define XSHAL_ROM_PADDR 0x50000000
|
||||
#define XSHAL_ROM_SIZE 0x01000000
|
||||
/* Largest available area (free of vectors): */
|
||||
#define XSHAL_ROM_AVAIL_VADDR 0x50000000
|
||||
#define XSHAL_ROM_AVAIL_VSIZE 0x01000000
|
||||
#define XSHAL_ROM_AVAIL_VADDR 0x50000000
|
||||
#define XSHAL_ROM_AVAIL_VSIZE 0x01000000
|
||||
|
||||
/* System RAM: */
|
||||
#define XSHAL_RAM_VADDR 0x60000000
|
||||
#define XSHAL_RAM_PADDR 0x60000000
|
||||
#define XSHAL_RAM_VSIZE 0x20000000
|
||||
#define XSHAL_RAM_PSIZE 0x20000000
|
||||
#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
|
||||
#define XSHAL_RAM_VADDR 0x60000000
|
||||
#define XSHAL_RAM_PADDR 0x60000000
|
||||
#define XSHAL_RAM_VSIZE 0x20000000
|
||||
#define XSHAL_RAM_PSIZE 0x20000000
|
||||
#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
|
||||
/* Largest available area (free of vectors): */
|
||||
#define XSHAL_RAM_AVAIL_VADDR 0x60000000
|
||||
#define XSHAL_RAM_AVAIL_VSIZE 0x20000000
|
||||
#define XSHAL_RAM_AVAIL_VADDR 0x60000000
|
||||
#define XSHAL_RAM_AVAIL_VSIZE 0x20000000
|
||||
|
||||
/*
|
||||
* Shadow system RAM (same device as system RAM, at different address).
|
||||
@ -120,35 +120,35 @@
|
||||
* addresses are viewed through the BYPASS static map rather than
|
||||
* the CACHED static map.
|
||||
*/
|
||||
#define XSHAL_RAM_BYPASS_VADDR 0xA0000000
|
||||
#define XSHAL_RAM_BYPASS_PADDR 0xA0000000
|
||||
#define XSHAL_RAM_BYPASS_PSIZE 0x20000000
|
||||
#define XSHAL_RAM_BYPASS_VADDR 0xA0000000
|
||||
#define XSHAL_RAM_BYPASS_PADDR 0xA0000000
|
||||
#define XSHAL_RAM_BYPASS_PSIZE 0x20000000
|
||||
|
||||
/* Alternate system RAM (different device than system RAM): */
|
||||
/*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/
|
||||
/*#define XSHAL_ALTRAM_SIZE ...not configured...*/
|
||||
/*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/
|
||||
/*#define XSHAL_ALTRAM_SIZE ...not configured...*/
|
||||
|
||||
/* Some available location in which to place devices in a simulation (eg. XTMP): */
|
||||
#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000
|
||||
#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000
|
||||
#define XSHAL_SIMIO_PADDR 0xC0000000
|
||||
#define XSHAL_SIMIO_SIZE 0x20000000
|
||||
#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000
|
||||
#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000
|
||||
#define XSHAL_SIMIO_PADDR 0xC0000000
|
||||
#define XSHAL_SIMIO_SIZE 0x20000000
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* For use by reference testbench exit and diagnostic routines.
|
||||
*/
|
||||
#define XSHAL_MAGIC_EXIT 0x0
|
||||
#define XSHAL_MAGIC_EXIT 0x0
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* DEVICE-ADDRESS DEPENDENT...
|
||||
* DEVICE-ADDRESS DEPENDENT...
|
||||
*
|
||||
* Values written to CACHEATTR special register (or its equivalent)
|
||||
* to enable and disable caches in various modes.
|
||||
*----------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
BACKWARD COMPATIBILITY ...
|
||||
BACKWARD COMPATIBILITY ...
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
@ -156,56 +156,56 @@
|
||||
* board-specific macros instead, which are specially tuned for the
|
||||
* particular target environments' memory maps.
|
||||
*/
|
||||
#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
|
||||
#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */
|
||||
#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
|
||||
#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
GENERIC
|
||||
GENERIC
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* For the following, a 512MB region is used if it contains a system (PIF) RAM,
|
||||
* system (PIF) ROM, local memory, or XLMI. */
|
||||
|
||||
/* These set any unused 512MB region to cache-BYPASS attribute: */
|
||||
#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22221112 /* enable caches in write-back mode */
|
||||
#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22221112 /* enable caches in write-allocate mode */
|
||||
#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22221112 /* enable caches in write-through mode */
|
||||
#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */
|
||||
#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */
|
||||
#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22221112 /* enable caches in write-back mode */
|
||||
#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22221112 /* enable caches in write-allocate mode */
|
||||
#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22221112 /* enable caches in write-through mode */
|
||||
#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */
|
||||
#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */
|
||||
|
||||
/* These set any unused 512MB region to ILLEGAL attribute: */
|
||||
#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFFFF111F /* enable caches in write-back mode */
|
||||
#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFF111F /* enable caches in write-allocate mode */
|
||||
#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFFFF111F /* enable caches in write-through mode */
|
||||
#define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFF222F /* disable caches in bypass mode */
|
||||
#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */
|
||||
#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFFFF111F /* enable caches in write-back mode */
|
||||
#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFF111F /* enable caches in write-allocate mode */
|
||||
#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFFFF111F /* enable caches in write-through mode */
|
||||
#define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFF222F /* disable caches in bypass mode */
|
||||
#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */
|
||||
|
||||
/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch
|
||||
* NULL-pointer dereference bugs; all other unused 512MB regions are set
|
||||
* to cache-BYPASS attribute: */
|
||||
#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222111F /* enable caches in write-back mode */
|
||||
#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2222111F /* enable caches in write-allocate mode */
|
||||
#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2222111F /* enable caches in write-through mode */
|
||||
#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
|
||||
#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */
|
||||
#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222111F /* enable caches in write-back mode */
|
||||
#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2222111F /* enable caches in write-allocate mode */
|
||||
#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2222111F /* enable caches in write-through mode */
|
||||
#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
|
||||
#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
ISS (Instruction Set Simulator) SPECIFIC ...
|
||||
ISS (Instruction Set Simulator) SPECIFIC ...
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* For now, ISS defaults to the TRAPNULL settings: */
|
||||
#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
|
||||
#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
|
||||
#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
|
||||
#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS
|
||||
#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
|
||||
#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
|
||||
#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
|
||||
#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
|
||||
#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS
|
||||
#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
|
||||
|
||||
#define XSHAL_ISS_PIPE_REGIONS 0
|
||||
#define XSHAL_ISS_SDRAM_REGIONS 0
|
||||
#define XSHAL_ISS_PIPE_REGIONS 0
|
||||
#define XSHAL_ISS_SDRAM_REGIONS 0
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
XT2000 BOARD SPECIFIC ...
|
||||
XT2000 BOARD SPECIFIC ...
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* For the following, a 512MB region is used if it contains any system RAM,
|
||||
@ -214,24 +214,24 @@
|
||||
* of whether the macro is _WRITEBACK vs. _BYPASS etc. */
|
||||
|
||||
/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */
|
||||
#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF22111F /* enable caches in write-back mode */
|
||||
#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF22111F /* enable caches in write-allocate mode */
|
||||
#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF22111F /* enable caches in write-through mode */
|
||||
#define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */
|
||||
#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
|
||||
#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF22111F /* enable caches in write-back mode */
|
||||
#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF22111F /* enable caches in write-allocate mode */
|
||||
#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF22111F /* enable caches in write-through mode */
|
||||
#define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */
|
||||
#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
|
||||
|
||||
#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */
|
||||
#define XSHAL_XT2000_SDRAM_REGIONS 0x00000440 /* BusInt SDRAM regions */
|
||||
#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */
|
||||
#define XSHAL_XT2000_SDRAM_REGIONS 0x00000440 /* BusInt SDRAM regions */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
VECTOR INFO AND SIZES
|
||||
VECTOR INFO AND SIZES
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XSHAL_VECTORS_PACKED 0
|
||||
#define XSHAL_STATIC_VECTOR_SELECT 1
|
||||
#define XSHAL_RESET_VECTOR_VADDR 0x40000400
|
||||
#define XSHAL_RESET_VECTOR_PADDR 0x40000400
|
||||
#define XSHAL_VECTORS_PACKED 0
|
||||
#define XSHAL_STATIC_VECTOR_SELECT 1
|
||||
#define XSHAL_RESET_VECTOR_VADDR 0x40000400
|
||||
#define XSHAL_RESET_VECTOR_PADDR 0x40000400
|
||||
|
||||
/*
|
||||
* Sizes allocated to vectors by the system (memory map) configuration.
|
||||
@ -242,35 +242,35 @@
|
||||
* Whether or not each vector happens to be in a system ROM is also
|
||||
* a system configuration matter, sometimes useful, included here also:
|
||||
*/
|
||||
#define XSHAL_RESET_VECTOR_SIZE 0x00000300
|
||||
#define XSHAL_RESET_VECTOR_ISROM 0
|
||||
#define XSHAL_USER_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_USER_VECTOR_ISROM 0
|
||||
#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
|
||||
#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
|
||||
#define XSHAL_KERNEL_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_KERNEL_VECTOR_ISROM 0
|
||||
#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
|
||||
#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
|
||||
#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040
|
||||
#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
|
||||
#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178
|
||||
#define XSHAL_WINDOW_VECTORS_ISROM 0
|
||||
#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
|
||||
#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
|
||||
#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_INTLEVEL4_VECTOR_ISROM 0
|
||||
#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_INTLEVEL5_VECTOR_ISROM 0
|
||||
#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_INTLEVEL6_VECTOR_ISROM 0
|
||||
#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE
|
||||
#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM
|
||||
#define XSHAL_NMI_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_NMI_VECTOR_ISROM 0
|
||||
#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE
|
||||
#define XSHAL_RESET_VECTOR_SIZE 0x00000300
|
||||
#define XSHAL_RESET_VECTOR_ISROM 0
|
||||
#define XSHAL_USER_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_USER_VECTOR_ISROM 0
|
||||
#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
|
||||
#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
|
||||
#define XSHAL_KERNEL_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_KERNEL_VECTOR_ISROM 0
|
||||
#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
|
||||
#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
|
||||
#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040
|
||||
#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
|
||||
#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178
|
||||
#define XSHAL_WINDOW_VECTORS_ISROM 0
|
||||
#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
|
||||
#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
|
||||
#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_INTLEVEL4_VECTOR_ISROM 0
|
||||
#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_INTLEVEL5_VECTOR_ISROM 0
|
||||
#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_INTLEVEL6_VECTOR_ISROM 0
|
||||
#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE
|
||||
#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM
|
||||
#define XSHAL_NMI_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_NMI_VECTOR_ISROM 0
|
||||
#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE
|
||||
|
||||
|
||||
#endif /*XTENSA_CONFIG_SYSTEM_H*/
|
||||
|
||||
@ -8,7 +8,7 @@
|
||||
macros, etc.) for this specific Xtensa processor's TIE extensions
|
||||
and options. It is customized to this Xtensa processor configuration.
|
||||
|
||||
Customer ID=15127; Build=0x86d67; Copyright (c) 1999-2020 Cadence Design Systems Inc.
|
||||
Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Cadence Design Systems Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
@ -34,388 +34,396 @@
|
||||
|
||||
/* Selection parameter values for save-area save/restore macros: */
|
||||
/* Option vs. TIE: */
|
||||
#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
|
||||
#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
|
||||
#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
|
||||
#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
|
||||
#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
|
||||
#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
|
||||
/* Whether used automatically by compiler: */
|
||||
#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
|
||||
#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
|
||||
#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
|
||||
#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
|
||||
#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
|
||||
#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
|
||||
/* ABI handling across function calls: */
|
||||
#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
|
||||
#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
|
||||
#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
|
||||
#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
|
||||
#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
|
||||
#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
|
||||
#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
|
||||
#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
|
||||
/* Misc */
|
||||
#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
|
||||
#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
|
||||
| ((ccuse) & XTHAL_SAS_ANYCC) \
|
||||
| ((abi) & XTHAL_SAS_ANYABI) )
|
||||
#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
|
||||
#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
|
||||
| ((ccuse) & XTHAL_SAS_ANYCC) \
|
||||
| ((abi) & XTHAL_SAS_ANYABI) )
|
||||
|
||||
|
||||
/*
|
||||
* Macro to store all non-coprocessor (extra) custom TIE and optional state
|
||||
* (not including zero-overhead loop registers).
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 4 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters:
|
||||
* continue If macro invoked as part of a larger store sequence, set to 1
|
||||
* if this is not the first in the sequence. Defaults to 0.
|
||||
* ofs Offset from start of larger sequence (from value of first ptr
|
||||
* in sequence) at which to store. Defaults to next available space
|
||||
* (or 0 if <continue> is 0).
|
||||
* select Select what category(ies) of registers to store, as a bitmask
|
||||
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
|
||||
* alloc Select what category(ies) of registers to allocate; if any
|
||||
* category is selected here that is not in <select>, space for
|
||||
* the corresponding registers is skipped without doing any store.
|
||||
*/
|
||||
.macro xchal_ncp_store ptr at1 at2 at3 at4 continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Optional global registers used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
rur.THREADPTR \at1 // threadptr option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
// Optional caller-saved registers used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1012, 4, 4
|
||||
rsr.ACCLO \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
rsr.ACCHI \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1012, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.endif
|
||||
// Optional caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 996, 4, 4
|
||||
rsr.BR \at1 // boolean option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
rsr.SCOMPARE1 \at1 // conditional store option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 4
|
||||
rsr.M0 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 8
|
||||
rsr.M1 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 12
|
||||
rsr.M2 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 16
|
||||
rsr.M3 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 20
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 996, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.endif
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
rur.SAR_BYTE \at1 // ureg 13
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
.endm // xchal_ncp_store
|
||||
/*
|
||||
* Macro to store all non-coprocessor (extra) custom TIE and optional state
|
||||
* (not including zero-overhead loop registers).
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 4 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters:
|
||||
* continue If macro invoked as part of a larger store sequence, set to 1
|
||||
* if this is not the first in the sequence. Defaults to 0.
|
||||
* ofs Offset from start of larger sequence (from value of first ptr
|
||||
* in sequence) at which to store. Defaults to next available space
|
||||
* (or 0 if <continue> is 0).
|
||||
* select Select what category(ies) of registers to store, as a bitmask
|
||||
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
|
||||
* alloc Select what category(ies) of registers to allocate; if any
|
||||
* category is selected here that is not in <select>, space for
|
||||
* the corresponding registers is skipped without doing any store.
|
||||
*/
|
||||
.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Optional global registers used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
rur.THREADPTR \at1 // threadptr option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
// Optional caller-saved registers used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1012, 4, 4
|
||||
rsr.ACCLO \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
rsr.ACCHI \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1012, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.endif
|
||||
// Optional caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 996, 4, 4
|
||||
rsr.BR \at1 // boolean option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
rsr.SCOMPARE1 \at1 // conditional store option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
rsr.M0 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+8
|
||||
rsr.M1 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+12
|
||||
rsr.M2 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+16
|
||||
rsr.M3 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+20
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 996, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.endif
|
||||
.endm // xchal_ncp_store
|
||||
|
||||
/*
|
||||
* Macro to load all non-coprocessor (extra) custom TIE and optional state
|
||||
* (not including zero-overhead loop registers).
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 4 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters:
|
||||
* continue If macro invoked as part of a larger load sequence, set to 1
|
||||
* if this is not the first in the sequence. Defaults to 0.
|
||||
* ofs Offset from start of larger sequence (from value of first ptr
|
||||
* in sequence) at which to load. Defaults to next available space
|
||||
* (or 0 if <continue> is 0).
|
||||
* select Select what category(ies) of registers to load, as a bitmask
|
||||
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
|
||||
* alloc Select what category(ies) of registers to allocate; if any
|
||||
* category is selected here that is not in <select>, space for
|
||||
* the corresponding registers is skipped without doing any load.
|
||||
*/
|
||||
.macro xchal_ncp_load ptr at1 at2 at3 at4 continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Optional global registers used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
wur.THREADPTR \at1 // threadptr option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
// Optional caller-saved registers used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1012, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
wsr.ACCLO \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 4
|
||||
wsr.ACCHI \at1 // MAC16 option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1012, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.endif
|
||||
// Optional caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 996, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
wsr.BR \at1 // boolean option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 4
|
||||
wsr.SCOMPARE1 \at1 // conditional store option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 8
|
||||
wsr.M0 \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 12
|
||||
wsr.M1 \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 16
|
||||
wsr.M2 \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 20
|
||||
wsr.M3 \at1 // MAC16 option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 996, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.endif
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
wur.SAR_BYTE \at1 // ureg 13
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
.endm // xchal_ncp_load
|
||||
/*
|
||||
* Macro to load all non-coprocessor (extra) custom TIE and optional state
|
||||
* (not including zero-overhead loop registers).
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 4 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters:
|
||||
* continue If macro invoked as part of a larger load sequence, set to 1
|
||||
* if this is not the first in the sequence. Defaults to 0.
|
||||
* ofs Offset from start of larger sequence (from value of first ptr
|
||||
* in sequence) at which to load. Defaults to next available space
|
||||
* (or 0 if <continue> is 0).
|
||||
* select Select what category(ies) of registers to load, as a bitmask
|
||||
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
|
||||
* alloc Select what category(ies) of registers to allocate; if any
|
||||
* category is selected here that is not in <select>, space for
|
||||
* the corresponding registers is skipped without doing any load.
|
||||
*/
|
||||
.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Optional global registers used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
wur.THREADPTR \at1 // threadptr option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
// Optional caller-saved registers used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1012, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
wsr.ACCLO \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
wsr.ACCHI \at1 // MAC16 option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1012, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.endif
|
||||
// Optional caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 996, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
wsr.BR \at1 // boolean option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
wsr.SCOMPARE1 \at1 // conditional store option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+8
|
||||
wsr.M0 \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+12
|
||||
wsr.M1 \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+16
|
||||
wsr.M2 \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+20
|
||||
wsr.M3 \at1 // MAC16 option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 996, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.endif
|
||||
.endm // xchal_ncp_load
|
||||
|
||||
|
||||
#define XCHAL_NCP_NUM_ATMPS 1
|
||||
#define XCHAL_NCP_NUM_ATMPS 1
|
||||
|
||||
/*
|
||||
* Macro to store the state of TIE coprocessor FPU.
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 4 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters are the same as for xchal_ncp_store.
|
||||
*/
|
||||
#define xchal_cp_FPU_store xchal_cp0_store
|
||||
.macro xchal_cp0_store ptr at1 at2 at3 at4 continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 948, 4, 4
|
||||
rur.FCR \at1 // ureg 232
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
rur.FSR \at1 // ureg 233
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 4
|
||||
ssi f0, \ptr, .Lxchal_ofs_ + 8
|
||||
ssi f1, \ptr, .Lxchal_ofs_ + 12
|
||||
ssi f2, \ptr, .Lxchal_ofs_ + 16
|
||||
ssi f3, \ptr, .Lxchal_ofs_ + 20
|
||||
ssi f4, \ptr, .Lxchal_ofs_ + 24
|
||||
ssi f5, \ptr, .Lxchal_ofs_ + 28
|
||||
ssi f6, \ptr, .Lxchal_ofs_ + 32
|
||||
ssi f7, \ptr, .Lxchal_ofs_ + 36
|
||||
ssi f8, \ptr, .Lxchal_ofs_ + 40
|
||||
ssi f9, \ptr, .Lxchal_ofs_ + 44
|
||||
ssi f10, \ptr, .Lxchal_ofs_ + 48
|
||||
ssi f11, \ptr, .Lxchal_ofs_ + 52
|
||||
ssi f12, \ptr, .Lxchal_ofs_ + 56
|
||||
ssi f13, \ptr, .Lxchal_ofs_ + 60
|
||||
ssi f14, \ptr, .Lxchal_ofs_ + 64
|
||||
ssi f15, \ptr, .Lxchal_ofs_ + 68
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 948, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
|
||||
.endif
|
||||
.endm // xchal_cp0_store
|
||||
/*
|
||||
* Macro to store the state of TIE coprocessor FPU.
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 4 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters are the same as for xchal_ncp_store.
|
||||
*/
|
||||
#define xchal_cp_FPU_store xchal_cp0_store
|
||||
.macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 948, 4, 4
|
||||
rur.FCR \at1 // ureg 232
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
rur.FSR \at1 // ureg 233
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
ssi f0, \ptr, .Lxchal_ofs_+8
|
||||
ssi f1, \ptr, .Lxchal_ofs_+12
|
||||
ssi f2, \ptr, .Lxchal_ofs_+16
|
||||
ssi f3, \ptr, .Lxchal_ofs_+20
|
||||
ssi f4, \ptr, .Lxchal_ofs_+24
|
||||
ssi f5, \ptr, .Lxchal_ofs_+28
|
||||
ssi f6, \ptr, .Lxchal_ofs_+32
|
||||
ssi f7, \ptr, .Lxchal_ofs_+36
|
||||
ssi f8, \ptr, .Lxchal_ofs_+40
|
||||
ssi f9, \ptr, .Lxchal_ofs_+44
|
||||
ssi f10, \ptr, .Lxchal_ofs_+48
|
||||
ssi f11, \ptr, .Lxchal_ofs_+52
|
||||
ssi f12, \ptr, .Lxchal_ofs_+56
|
||||
ssi f13, \ptr, .Lxchal_ofs_+60
|
||||
ssi f14, \ptr, .Lxchal_ofs_+64
|
||||
ssi f15, \ptr, .Lxchal_ofs_+68
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 948, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
|
||||
.endif
|
||||
.endm // xchal_cp0_store
|
||||
|
||||
/*
|
||||
* Macro to load the state of TIE coprocessor FPU.
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 4 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters are the same as for xchal_ncp_load.
|
||||
*/
|
||||
#define xchal_cp_FPU_load xchal_cp0_load
|
||||
.macro xchal_cp0_load ptr at1 at2 at3 at4 continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 948, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
wur.FCR \at1 // ureg 232
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 4
|
||||
wur.FSR \at1 // ureg 233
|
||||
lsi f0, \ptr, .Lxchal_ofs_ + 8
|
||||
lsi f1, \ptr, .Lxchal_ofs_ + 12
|
||||
lsi f2, \ptr, .Lxchal_ofs_ + 16
|
||||
lsi f3, \ptr, .Lxchal_ofs_ + 20
|
||||
lsi f4, \ptr, .Lxchal_ofs_ + 24
|
||||
lsi f5, \ptr, .Lxchal_ofs_ + 28
|
||||
lsi f6, \ptr, .Lxchal_ofs_ + 32
|
||||
lsi f7, \ptr, .Lxchal_ofs_ + 36
|
||||
lsi f8, \ptr, .Lxchal_ofs_ + 40
|
||||
lsi f9, \ptr, .Lxchal_ofs_ + 44
|
||||
lsi f10, \ptr, .Lxchal_ofs_ + 48
|
||||
lsi f11, \ptr, .Lxchal_ofs_ + 52
|
||||
lsi f12, \ptr, .Lxchal_ofs_ + 56
|
||||
lsi f13, \ptr, .Lxchal_ofs_ + 60
|
||||
lsi f14, \ptr, .Lxchal_ofs_ + 64
|
||||
lsi f15, \ptr, .Lxchal_ofs_ + 68
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 948, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
|
||||
.endif
|
||||
.endm // xchal_cp0_load
|
||||
/*
|
||||
* Macro to load the state of TIE coprocessor FPU.
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 4 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters are the same as for xchal_ncp_load.
|
||||
*/
|
||||
#define xchal_cp_FPU_load xchal_cp0_load
|
||||
.macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 948, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
wur.FCR \at1 // ureg 232
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
wur.FSR \at1 // ureg 233
|
||||
lsi f0, \ptr, .Lxchal_ofs_+8
|
||||
lsi f1, \ptr, .Lxchal_ofs_+12
|
||||
lsi f2, \ptr, .Lxchal_ofs_+16
|
||||
lsi f3, \ptr, .Lxchal_ofs_+20
|
||||
lsi f4, \ptr, .Lxchal_ofs_+24
|
||||
lsi f5, \ptr, .Lxchal_ofs_+28
|
||||
lsi f6, \ptr, .Lxchal_ofs_+32
|
||||
lsi f7, \ptr, .Lxchal_ofs_+36
|
||||
lsi f8, \ptr, .Lxchal_ofs_+40
|
||||
lsi f9, \ptr, .Lxchal_ofs_+44
|
||||
lsi f10, \ptr, .Lxchal_ofs_+48
|
||||
lsi f11, \ptr, .Lxchal_ofs_+52
|
||||
lsi f12, \ptr, .Lxchal_ofs_+56
|
||||
lsi f13, \ptr, .Lxchal_ofs_+60
|
||||
lsi f14, \ptr, .Lxchal_ofs_+64
|
||||
lsi f15, \ptr, .Lxchal_ofs_+68
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 948, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
|
||||
.endif
|
||||
.endm // xchal_cp0_load
|
||||
|
||||
#define XCHAL_CP0_NUM_ATMPS 1
|
||||
/*
|
||||
* Macro to store the state of TIE coprocessor cop_ai.
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 16 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_CP3_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters are the same as for xchal_ncp_store.
|
||||
*/
|
||||
#define xchal_cp_cop_ai_store xchal_cp3_store
|
||||
.macro xchal_cp3_store ptr at1 at2 at3 at4 continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 0, 16, 16
|
||||
rur.ACCX_0 \at1 // ureg 0
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
rur.ACCX_1 \at1 // ureg 1
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 4
|
||||
rur.QACC_H_0 \at1 // ureg 2
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 8
|
||||
rur.QACC_H_1 \at1 // ureg 3
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 12
|
||||
rur.QACC_H_2 \at1 // ureg 4
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 16
|
||||
rur.QACC_H_3 \at1 // ureg 5
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 20
|
||||
rur.QACC_H_4 \at1 // ureg 6
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 24
|
||||
rur.QACC_L_0 \at1 // ureg 7
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 28
|
||||
rur.QACC_L_1 \at1 // ureg 8
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 32
|
||||
rur.QACC_L_2 \at1 // ureg 9
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 36
|
||||
rur.QACC_L_3 \at1 // ureg 10
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 40
|
||||
rur.QACC_L_4 \at1 // ureg 11
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 44
|
||||
st.qr q0, \ptr, .Lxchal_ofs_ + 48
|
||||
st.qr q1, \ptr, .Lxchal_ofs_ + 64
|
||||
st.qr q2, \ptr, .Lxchal_ofs_ + 80
|
||||
st.qr q3, \ptr, .Lxchal_ofs_ + 96
|
||||
st.qr q4, \ptr, .Lxchal_ofs_ + 112
|
||||
addi \ptr, \ptr, 128
|
||||
st.qr q5, \ptr, .Lxchal_ofs_ + 0
|
||||
.set .Lxchal_pofs_, .Lxchal_pofs_ + 128
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 16
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 0, 16, 16
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 144
|
||||
.endif
|
||||
.endm // xchal_cp3_store
|
||||
#define XCHAL_CP0_NUM_ATMPS 1
|
||||
/*
|
||||
* Macro to store the state of TIE coprocessor cop_ai.
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 16 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_CP3_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters are the same as for xchal_ncp_store.
|
||||
*/
|
||||
#define xchal_cp_cop_ai_store xchal_cp3_store
|
||||
.macro xchal_cp3_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 0, 16, 16
|
||||
rur.ACCX_0 \at1 // ureg 0
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
rur.ACCX_1 \at1 // ureg 1
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
rur.QACC_H_0 \at1 // ureg 2
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+8
|
||||
rur.QACC_H_1 \at1 // ureg 3
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+12
|
||||
rur.QACC_H_2 \at1 // ureg 4
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+16
|
||||
rur.QACC_H_3 \at1 // ureg 5
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+20
|
||||
rur.QACC_H_4 \at1 // ureg 6
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+24
|
||||
rur.QACC_L_0 \at1 // ureg 7
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+28
|
||||
rur.QACC_L_1 \at1 // ureg 8
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+32
|
||||
rur.QACC_L_2 \at1 // ureg 9
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+36
|
||||
rur.QACC_L_3 \at1 // ureg 10
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+40
|
||||
rur.QACC_L_4 \at1 // ureg 11
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+44
|
||||
rur.SAR_BYTE \at1 // ureg 13
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+48
|
||||
rur.FFT_BIT_WIDTH \at1 // ureg 14
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+52
|
||||
rur.UA_STATE_0 \at1 // ureg 15
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+56
|
||||
rur.UA_STATE_1 \at1 // ureg 16
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+60
|
||||
rur.UA_STATE_2 \at1 // ureg 17
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+64
|
||||
rur.UA_STATE_3 \at1 // ureg 18
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+68
|
||||
st.qr q0, \ptr, .Lxchal_ofs_+80
|
||||
st.qr q1, \ptr, .Lxchal_ofs_+96
|
||||
st.qr q2, \ptr, .Lxchal_ofs_+112
|
||||
addi \ptr, \ptr, 128
|
||||
st.qr q3, \ptr, .Lxchal_ofs_+0
|
||||
st.qr q4, \ptr, .Lxchal_ofs_+16
|
||||
st.qr q5, \ptr, .Lxchal_ofs_+32
|
||||
st.qr q6, \ptr, .Lxchal_ofs_+48
|
||||
st.qr q7, \ptr, .Lxchal_ofs_+64
|
||||
.set .Lxchal_pofs_, .Lxchal_pofs_ + 128
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 80
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 0, 16, 16
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 208
|
||||
.endif
|
||||
.endm // xchal_cp3_store
|
||||
|
||||
/*
|
||||
* Macro to load the state of TIE coprocessor cop_ai.
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 16 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_CP3_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters are the same as for xchal_ncp_load.
|
||||
*/
|
||||
#define xchal_cp_cop_ai_load xchal_cp3_load
|
||||
.macro xchal_cp3_load ptr at1 at2 at3 at4 continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 0, 16, 16
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
wur.ACCX_0 \at1 // ureg 0
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 4
|
||||
wur.ACCX_1 \at1 // ureg 1
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 8
|
||||
wur.QACC_H_0 \at1 // ureg 2
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 12
|
||||
wur.QACC_H_1 \at1 // ureg 3
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 16
|
||||
wur.QACC_H_2 \at1 // ureg 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 20
|
||||
wur.QACC_H_3 \at1 // ureg 5
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 24
|
||||
wur.QACC_H_4 \at1 // ureg 6
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 28
|
||||
wur.QACC_L_0 \at1 // ureg 7
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 32
|
||||
wur.QACC_L_1 \at1 // ureg 8
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 36
|
||||
wur.QACC_L_2 \at1 // ureg 9
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 40
|
||||
wur.QACC_L_3 \at1 // ureg 10
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 44
|
||||
wur.QACC_L_4 \at1 // ureg 11
|
||||
ld.qr q0, \ptr, .Lxchal_ofs_ + 48
|
||||
ld.qr q1, \ptr, .Lxchal_ofs_ + 64
|
||||
ld.qr q2, \ptr, .Lxchal_ofs_ + 80
|
||||
ld.qr q3, \ptr, .Lxchal_ofs_ + 96
|
||||
ld.qr q4, \ptr, .Lxchal_ofs_ + 112
|
||||
addi \ptr, \ptr, 128
|
||||
ld.qr q5, \ptr, .Lxchal_ofs_ + 0
|
||||
.set .Lxchal_pofs_, .Lxchal_pofs_ + 128
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 16
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 0, 16, 16
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 144
|
||||
.endif
|
||||
.endm // xchal_cp3_load
|
||||
/*
|
||||
* Macro to load the state of TIE coprocessor cop_ai.
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 16 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_CP3_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters are the same as for xchal_ncp_load.
|
||||
*/
|
||||
#define xchal_cp_cop_ai_load xchal_cp3_load
|
||||
.macro xchal_cp3_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 0, 16, 16
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
wur.ACCX_0 \at1 // ureg 0
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
wur.ACCX_1 \at1 // ureg 1
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+8
|
||||
wur.QACC_H_0 \at1 // ureg 2
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+12
|
||||
wur.QACC_H_1 \at1 // ureg 3
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+16
|
||||
wur.QACC_H_2 \at1 // ureg 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+20
|
||||
wur.QACC_H_3 \at1 // ureg 5
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+24
|
||||
wur.QACC_H_4 \at1 // ureg 6
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+28
|
||||
wur.QACC_L_0 \at1 // ureg 7
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+32
|
||||
wur.QACC_L_1 \at1 // ureg 8
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+36
|
||||
wur.QACC_L_2 \at1 // ureg 9
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+40
|
||||
wur.QACC_L_3 \at1 // ureg 10
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+44
|
||||
wur.QACC_L_4 \at1 // ureg 11
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+48
|
||||
wur.SAR_BYTE \at1 // ureg 13
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+52
|
||||
wur.FFT_BIT_WIDTH \at1 // ureg 14
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+56
|
||||
wur.UA_STATE_0 \at1 // ureg 15
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+60
|
||||
wur.UA_STATE_1 \at1 // ureg 16
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+64
|
||||
wur.UA_STATE_2 \at1 // ureg 17
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+68
|
||||
wur.UA_STATE_3 \at1 // ureg 18
|
||||
ld.qr q0, \ptr, .Lxchal_ofs_+80
|
||||
ld.qr q1, \ptr, .Lxchal_ofs_+96
|
||||
ld.qr q2, \ptr, .Lxchal_ofs_+112
|
||||
addi \ptr, \ptr, 128
|
||||
ld.qr q3, \ptr, .Lxchal_ofs_+0
|
||||
ld.qr q4, \ptr, .Lxchal_ofs_+16
|
||||
ld.qr q5, \ptr, .Lxchal_ofs_+32
|
||||
ld.qr q6, \ptr, .Lxchal_ofs_+48
|
||||
ld.qr q7, \ptr, .Lxchal_ofs_+64
|
||||
.set .Lxchal_pofs_, .Lxchal_pofs_ + 128
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 80
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 0, 16, 16
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 208
|
||||
.endif
|
||||
.endm // xchal_cp3_load
|
||||
|
||||
#define XCHAL_CP3_NUM_ATMPS 1
|
||||
#define XCHAL_SA_NUM_ATMPS 1
|
||||
#define XCHAL_CP3_NUM_ATMPS 1
|
||||
#define XCHAL_SA_NUM_ATMPS 1
|
||||
|
||||
/* Empty macros for unconfigured coprocessors: */
|
||||
.macro xchal_cp1_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm
|
||||
.macro xchal_cp1_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm
|
||||
.macro xchal_cp2_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm
|
||||
.macro xchal_cp2_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm
|
||||
.macro xchal_cp4_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm
|
||||
.macro xchal_cp4_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm
|
||||
.macro xchal_cp5_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm
|
||||
.macro xchal_cp5_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm
|
||||
.macro xchal_cp6_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm
|
||||
.macro xchal_cp6_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm
|
||||
.macro xchal_cp7_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm
|
||||
.macro xchal_cp7_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm
|
||||
/* Empty macros for unconfigured coprocessors: */
|
||||
.macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
|
||||
#endif /*_XTENSA_CORE_TIE_ASM_H*/
|
||||
|
||||
@ -8,7 +8,7 @@
|
||||
that extend basic Xtensa core functionality. It is customized to this
|
||||
Xtensa processor configuration.
|
||||
|
||||
Customer ID=15127; Build=0x86d67; Copyright (c) 1999-2020 Cadence Design Systems Inc.
|
||||
Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Cadence Design Systems Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
@ -32,44 +32,44 @@
|
||||
#ifndef _XTENSA_CORE_TIE_H
|
||||
#define _XTENSA_CORE_TIE_H
|
||||
|
||||
#define XCHAL_CP_NUM 2 /* number of coprocessors */
|
||||
#define XCHAL_CP_MAX 4 /* max CP ID + 1 (0 if none) */
|
||||
#define XCHAL_CP_MASK 0x09 /* bitmask of all CPs by ID */
|
||||
#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
|
||||
#define XCHAL_CP_NUM 2 /* number of coprocessors */
|
||||
#define XCHAL_CP_MAX 4 /* max CP ID + 1 (0 if none) */
|
||||
#define XCHAL_CP_MASK 0x09 /* bitmask of all CPs by ID */
|
||||
#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
|
||||
|
||||
/* Basic parameters of each coprocessor: */
|
||||
#define XCHAL_CP0_NAME "FPU"
|
||||
#define XCHAL_CP0_IDENT FPU
|
||||
#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */
|
||||
#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */
|
||||
#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
|
||||
#define XCHAL_CP3_NAME "cop_ai"
|
||||
#define XCHAL_CP3_IDENT cop_ai
|
||||
#define XCHAL_CP3_SA_SIZE 144 /* size of state save area */
|
||||
#define XCHAL_CP3_SA_ALIGN 16 /* min alignment of save area */
|
||||
#define XCHAL_CP_ID_COP_AI 3 /* coprocessor ID (0..7) */
|
||||
#define XCHAL_CP0_NAME "FPU"
|
||||
#define XCHAL_CP0_IDENT FPU
|
||||
#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */
|
||||
#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */
|
||||
#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
|
||||
#define XCHAL_CP3_NAME "cop_ai"
|
||||
#define XCHAL_CP3_IDENT cop_ai
|
||||
#define XCHAL_CP3_SA_SIZE 208 /* size of state save area */
|
||||
#define XCHAL_CP3_SA_ALIGN 16 /* min alignment of save area */
|
||||
#define XCHAL_CP_ID_COP_AI 3 /* coprocessor ID (0..7) */
|
||||
|
||||
/* Filler info for unassigned coprocessors, to simplify arrays etc: */
|
||||
#define XCHAL_CP1_SA_SIZE 0
|
||||
#define XCHAL_CP1_SA_ALIGN 1
|
||||
#define XCHAL_CP2_SA_SIZE 0
|
||||
#define XCHAL_CP2_SA_ALIGN 1
|
||||
#define XCHAL_CP4_SA_SIZE 0
|
||||
#define XCHAL_CP4_SA_ALIGN 1
|
||||
#define XCHAL_CP5_SA_SIZE 0
|
||||
#define XCHAL_CP5_SA_ALIGN 1
|
||||
#define XCHAL_CP6_SA_SIZE 0
|
||||
#define XCHAL_CP6_SA_ALIGN 1
|
||||
#define XCHAL_CP7_SA_SIZE 0
|
||||
#define XCHAL_CP7_SA_ALIGN 1
|
||||
#define XCHAL_CP1_SA_SIZE 0
|
||||
#define XCHAL_CP1_SA_ALIGN 1
|
||||
#define XCHAL_CP2_SA_SIZE 0
|
||||
#define XCHAL_CP2_SA_ALIGN 1
|
||||
#define XCHAL_CP4_SA_SIZE 0
|
||||
#define XCHAL_CP4_SA_ALIGN 1
|
||||
#define XCHAL_CP5_SA_SIZE 0
|
||||
#define XCHAL_CP5_SA_ALIGN 1
|
||||
#define XCHAL_CP6_SA_SIZE 0
|
||||
#define XCHAL_CP6_SA_ALIGN 1
|
||||
#define XCHAL_CP7_SA_SIZE 0
|
||||
#define XCHAL_CP7_SA_ALIGN 1
|
||||
|
||||
/* Save area for non-coprocessor optional and custom (TIE) state: */
|
||||
#define XCHAL_NCP_SA_SIZE 40
|
||||
#define XCHAL_NCP_SA_ALIGN 4
|
||||
#define XCHAL_NCP_SA_SIZE 36
|
||||
#define XCHAL_NCP_SA_ALIGN 4
|
||||
|
||||
/* Total save area for optional and custom state (NCP + CPn): */
|
||||
#define XCHAL_TOTAL_SA_SIZE 272 /* with 16-byte align padding */
|
||||
#define XCHAL_TOTAL_SA_ALIGN 16 /* actual minimum alignment */
|
||||
#define XCHAL_TOTAL_SA_SIZE 336 /* with 16-byte align padding */
|
||||
#define XCHAL_TOTAL_SA_ALIGN 16 /* actual minimum alignment */
|
||||
|
||||
/*
|
||||
* Detailed contents of save areas.
|
||||
@ -77,42 +77,42 @@
|
||||
* before expanding the XCHAL_xxx_SA_LIST() macros.
|
||||
*
|
||||
* XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
|
||||
* dbnum,base,regnum,bitsz,gapsz,reset,x...)
|
||||
* dbnum,base,regnum,bitsz,gapsz,reset,x...)
|
||||
*
|
||||
* s = passed from XCHAL_*_LIST(s), eg. to select how to expand
|
||||
* ccused = set if used by compiler without special options or code
|
||||
* abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
|
||||
* kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
|
||||
* opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
|
||||
* name = lowercase reg name (no quotes)
|
||||
* galign = group byte alignment (power of 2) (galign >= align)
|
||||
* align = register byte alignment (power of 2)
|
||||
* asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
|
||||
* (not including any pad bytes required to galign this or next reg)
|
||||
* dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
|
||||
* base = reg shortname w/o index (or sr=special, ur=TIE user reg)
|
||||
* regnum = reg index in regfile, or special/TIE-user reg number
|
||||
* bitsz = number of significant bits (regfile width, or ur/sr mask bits)
|
||||
* gapsz = intervening bits, if bitsz bits not stored contiguously
|
||||
* (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
|
||||
* reset = register reset value (or 0 if undefined at reset)
|
||||
* x = reserved for future use (0 until then)
|
||||
* s = passed from XCHAL_*_LIST(s), eg. to select how to expand
|
||||
* ccused = set if used by compiler without special options or code
|
||||
* abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
|
||||
* kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
|
||||
* opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
|
||||
* name = lowercase reg name (no quotes)
|
||||
* galign = group byte alignment (power of 2) (galign >= align)
|
||||
* align = register byte alignment (power of 2)
|
||||
* asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
|
||||
* (not including any pad bytes required to galign this or next reg)
|
||||
* dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
|
||||
* base = reg shortname w/o index (or sr=special, ur=TIE user reg)
|
||||
* regnum = reg index in regfile, or special/TIE-user reg number
|
||||
* bitsz = number of significant bits (regfile width, or ur/sr mask bits)
|
||||
* gapsz = intervening bits, if bitsz bits not stored contiguously
|
||||
* (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
|
||||
* reset = register reset value (or 0 if undefined at reset)
|
||||
* x = reserved for future use (0 until then)
|
||||
*
|
||||
* To filter out certain registers, e.g. to expand only the non-global
|
||||
* registers used by the compiler, you can do something like this:
|
||||
*
|
||||
* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
|
||||
* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
|
||||
* #define SELCC0(p...)
|
||||
* #define SELCC1(abikind,p...) SELAK##abikind(p)
|
||||
* #define SELAK0(p...) REG(p)
|
||||
* #define SELAK1(p...) REG(p)
|
||||
* #define SELCC1(abikind,p...) SELAK##abikind(p)
|
||||
* #define SELAK0(p...) REG(p)
|
||||
* #define SELAK1(p...) REG(p)
|
||||
* #define SELAK2(p...)
|
||||
* #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
|
||||
* ...what you want to expand...
|
||||
* ...what you want to expand...
|
||||
*/
|
||||
|
||||
#define XCHAL_NCP_SA_NUM 10
|
||||
#define XCHAL_NCP_SA_LIST(s) \
|
||||
#define XCHAL_NCP_SA_NUM 9
|
||||
#define XCHAL_NCP_SA_LIST(s) \
|
||||
XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
|
||||
@ -121,11 +121,10 @@
|
||||
XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, sar_byte, 4, 4, 4,0x030D, ur,13 , 5,0,0,0)
|
||||
XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
|
||||
|
||||
#define XCHAL_CP0_SA_NUM 18
|
||||
#define XCHAL_CP0_SA_LIST(s) \
|
||||
#define XCHAL_CP0_SA_NUM 18
|
||||
#define XCHAL_CP0_SA_LIST(s) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \
|
||||
@ -145,14 +144,14 @@
|
||||
XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0)
|
||||
|
||||
#define XCHAL_CP1_SA_NUM 0
|
||||
#define XCHAL_CP1_SA_LIST(s) /* empty */
|
||||
#define XCHAL_CP1_SA_NUM 0
|
||||
#define XCHAL_CP1_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP2_SA_NUM 0
|
||||
#define XCHAL_CP2_SA_LIST(s) /* empty */
|
||||
#define XCHAL_CP2_SA_NUM 0
|
||||
#define XCHAL_CP2_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP3_SA_NUM 18
|
||||
#define XCHAL_CP3_SA_LIST(s) \
|
||||
#define XCHAL_CP3_SA_NUM 26
|
||||
#define XCHAL_CP3_SA_LIST(s) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, accx_0,16, 4, 4,0x0300, ur,0 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, accx_1, 4, 4, 4,0x0301, ur,1 , 8,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, qacc_h_0, 4, 4, 4,0x0302, ur,2 , 32,0,0,0) \
|
||||
@ -165,36 +164,44 @@
|
||||
XCHAL_SA_REG(s,0,0,1,0, qacc_l_2, 4, 4, 4,0x0309, ur,9 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, qacc_l_3, 4, 4, 4,0x030A, ur,10 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, qacc_l_4, 4, 4, 4,0x030B, ur,11 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, sar_byte, 4, 4, 4,0x030D, ur,13 , 4,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, fft_bit_width, 4, 4, 4,0x030E, ur,14 , 4,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ua_state_0, 4, 4, 4,0x030F, ur,15 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ua_state_1, 4, 4, 4,0x0310, ur,16 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ua_state_2, 4, 4, 4,0x0311, ur,17 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ua_state_3, 4, 4, 4,0x0312, ur,18 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, q0,16,16,16,0x1008, q,0 ,128,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, q1,16,16,16,0x1009, q,1 ,128,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, q2,16,16,16,0x100A, q,2 ,128,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, q3,16,16,16,0x100B, q,3 ,128,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, q4,16,16,16,0x100C, q,4 ,128,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, q5,16,16,16,0x100D, q,5 ,128,0,0,0)
|
||||
XCHAL_SA_REG(s,0,0,2,0, q5,16,16,16,0x100D, q,5 ,128,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, q6,16,16,16,0x100E, q,6 ,128,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, q7,16,16,16,0x100F, q,7 ,128,0,0,0)
|
||||
|
||||
#define XCHAL_CP4_SA_NUM 0
|
||||
#define XCHAL_CP4_SA_LIST(s) /* empty */
|
||||
#define XCHAL_CP4_SA_NUM 0
|
||||
#define XCHAL_CP4_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP5_SA_NUM 0
|
||||
#define XCHAL_CP5_SA_LIST(s) /* empty */
|
||||
#define XCHAL_CP5_SA_NUM 0
|
||||
#define XCHAL_CP5_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP6_SA_NUM 0
|
||||
#define XCHAL_CP6_SA_LIST(s) /* empty */
|
||||
#define XCHAL_CP6_SA_NUM 0
|
||||
#define XCHAL_CP6_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP7_SA_NUM 0
|
||||
#define XCHAL_CP7_SA_LIST(s) /* empty */
|
||||
#define XCHAL_CP7_SA_NUM 0
|
||||
#define XCHAL_CP7_SA_LIST(s) /* empty */
|
||||
|
||||
/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
|
||||
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3
|
||||
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4
|
||||
/* Byte length of instruction from its first byte, per FLIX. */
|
||||
#define XCHAL_BYTE0_FORMAT_LENGTHS \
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3
|
||||
#define XCHAL_BYTE0_FORMAT_LENGTHS \
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4
|
||||
|
||||
#endif /*_XTENSA_CORE_TIE_H*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user