diff --git a/components/driver/gpio/gpio_etm.c b/components/driver/gpio/gpio_etm.c index aa2de292dd..61fe15de98 100644 --- a/components/driver/gpio/gpio_etm.c +++ b/components/driver/gpio/gpio_etm.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/driver/i2s/i2s_pdm.c b/components/driver/i2s/i2s_pdm.c index 22add6c175..6aa29dbef5 100644 --- a/components/driver/i2s/i2s_pdm.c +++ b/components/driver/i2s/i2s_pdm.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/driver/i2s/i2s_std.c b/components/driver/i2s/i2s_std.c index 0bc86f340b..fe48c98981 100644 --- a/components/driver/i2s/i2s_std.c +++ b/components/driver/i2s/i2s_std.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/driver/i2s/i2s_tdm.c b/components/driver/i2s/i2s_tdm.c index 3eb465db12..ff36f2f240 100644 --- a/components/driver/i2s/i2s_tdm.c +++ b/components/driver/i2s/i2s_tdm.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index f74f9b20c6..578eecfc03 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -25,6 +25,7 @@ if(NOT BOOTLOADER_BUILD) "sleep_gpio.c" "sleep_modem.c" "regi2c_ctrl.c" + "esp_gpio_reserve.c" "port/${target}/io_mux.c" "port/${target}/clk_tree.c" "port/clk_tree_common.c") diff --git a/components/esp_hw_support/esp_gpio_reserve.c b/components/esp_hw_support/esp_gpio_reserve.c new file mode 100644 index 0000000000..dba3893422 --- /dev/null +++ b/components/esp_hw_support/esp_gpio_reserve.c @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_types.h" +#include "esp_bit_defs.h" +#include "soc/soc_caps.h" + +static uint64_t s_reserve_status = 0; + +void esp_gpio_reserve_pins(uint64_t mask) +{ +#if SOC_GPIO_PIN_COUNT < 64 + mask &= BIT64(SOC_GPIO_PIN_COUNT) - 1; +#endif + s_reserve_status |= mask; +} + +bool esp_gpio_is_pin_reserved(uint32_t gpio_num) +{ + if (gpio_num >= SOC_GPIO_PIN_COUNT) { + return false; + } + return !!(s_reserve_status & BIT64(gpio_num)); +} + +// TODO: IDF-6968 reserve the pins that not fanned out regarding the SiP version diff --git a/components/esp_hw_support/include/esp_private/esp_gpio_reserve.h b/components/esp_hw_support/include/esp_private/esp_gpio_reserve.h new file mode 100644 index 0000000000..068386536a --- /dev/null +++ b/components/esp_hw_support/include/esp_private/esp_gpio_reserve.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/** + * File Introduction: + * This file is used to reserve the GPIOs runtime, which has been occupied by FLASH/PSRAM or + * the GPIOs that not fan out. + * + * The FLASH pins can be tuned according to eFuse, pins will be reserved in the `esp_mspi_pin_init` + * while starting the CPU. + * + * As for the PSRAM pins, they are initialized after CPU started. They will be reserved in + * the `psram_gpio_config` when enabling the PSRAM. + */ + +#pragma once + +#include "esp_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Set the reserved pin + * @note A same gpio can be reserve repetitively, but can't be clear once it is reserved + * + * @param[in] mask Mask of GPIO reserved pins + */ +void esp_gpio_reserve_pins(uint64_t mask); + +/** + * @brief Check whether the pin has been reserved + * + * @param[in] gpio_num GPIO pin number, please input a gpio number within `SOC_GPIO_PIN_COUNT` + * @return + * - true This gpio is reserved for FLASH or PSRAM + * - false This gpio is available for other purposes + */ +bool esp_gpio_is_pin_reserved(uint32_t gpio_num); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf index 864467b6fb..4680358c2c 100644 --- a/components/esp_hw_support/linker.lf +++ b/components/esp_hw_support/linker.lf @@ -13,6 +13,8 @@ entries: cpu: esp_cpu_compare_and_set (noflash) esp_memory_utils (noflash) rtc_clk (noflash) + esp_gpio_reserve: esp_gpio_reserve_pins (noflash) + esp_gpio_reserve: esp_gpio_is_pin_reserved (noflash) if SOC_CONFIGURABLE_VDDSDIO_SUPPORTED: rtc_init:rtc_vddsdio_set_config (noflash) if IDF_TARGET_ESP32C6 = n && IDF_TARGET_ESP32H2 = n: # TODO: IDF-5645 diff --git a/components/esp_hw_support/port/esp32c6/chip_info.c b/components/esp_hw_support/port/esp32c6/chip_info.c index dbf1f4f195..3924d78f5a 100644 --- a/components/esp_hw_support/port/esp32c6/chip_info.c +++ b/components/esp_hw_support/port/esp32c6/chip_info.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/esp_hw_support/port/esp32h2/chip_info.c b/components/esp_hw_support/port/esp32h2/chip_info.c index 203db166fc..161de7c161 100644 --- a/components/esp_hw_support/port/esp32h2/chip_info.c +++ b/components/esp_hw_support/port/esp32h2/chip_info.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/esp_psram/esp32/esp_psram_impl_quad.c b/components/esp_psram/esp32/esp_psram_impl_quad.c index e02de31360..fea64b358a 100644 --- a/components/esp_psram/esp32/esp_psram_impl_quad.c +++ b/components/esp_psram/esp32/esp_psram_impl_quad.c @@ -14,6 +14,7 @@ #include "esp_attr.h" #include "esp_err.h" #include "esp_types.h" +#include "esp_bit_defs.h" #include "esp_log.h" #include "../esp_psram_impl.h" #include "esp32/rom/spi_flash.h" @@ -34,6 +35,7 @@ #include "bootloader_common.h" #include "esp_rom_gpio.h" #include "bootloader_flash_config.h" +#include "esp_private/esp_gpio_reserve.h" #if CONFIG_SPIRAM #include "soc/rtc.h" @@ -807,6 +809,16 @@ static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io, psram_cache_speed_ SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spihd_sd2_io], FUN_DRV_V, 3, FUN_DRV_S); SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spiwp_sd3_io], FUN_DRV_V, 3, FUN_DRV_S); } + + // Reserve psram pins + esp_gpio_reserve_pins(BIT64(psram_io->flash_clk_io) | + BIT64(psram_io->flash_cs_io) | + BIT64(psram_io->psram_clk_io) | + BIT64(psram_io->psram_cs_io) | + BIT64(psram_io->psram_spiq_sd0_io) | + BIT64(psram_io->psram_spid_sd1_io) | + BIT64(psram_io->psram_spihd_sd2_io) | + BIT64(psram_io->psram_spiwp_sd3_io) ); } //used in UT only diff --git a/components/esp_psram/esp32s2/esp_psram_impl_quad.c b/components/esp_psram/esp32s2/esp_psram_impl_quad.c index 0f4a0a003b..afa900fdb8 100644 --- a/components/esp_psram/esp32s2/esp_psram_impl_quad.c +++ b/components/esp_psram/esp32s2/esp_psram_impl_quad.c @@ -14,6 +14,7 @@ #include "esp_attr.h" #include "esp_err.h" #include "esp_types.h" +#include "esp_bit_defs.h" #include "esp_log.h" #include "../esp_psram_impl.h" #include "esp32s2/rom/spi_flash.h" @@ -22,6 +23,7 @@ #include "esp_rom_efuse.h" #include "soc/spi_reg.h" #include "soc/io_mux_reg.h" +#include "esp_private/esp_gpio_reserve.h" static const char* TAG = "quad_psram"; @@ -377,6 +379,16 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_speed_t mode) } esp_rom_spiflash_select_qio_pins(psram_io.psram_spiwp_sd3_io, spiconfig); s_psram_cs_io = psram_io.psram_cs_io; + + // Preserve psram pins + esp_gpio_reserve_pins(BIT64(psram_io.flash_clk_io) | + BIT64(psram_io.flash_cs_io) | + BIT64(psram_io.psram_clk_io) | + BIT64(psram_io.psram_cs_io) | + BIT64(psram_io.psram_spiq_sd0_io) | + BIT64(psram_io.psram_spid_sd1_io) | + BIT64(psram_io.psram_spihd_sd2_io) | + BIT64(psram_io.psram_spiwp_sd3_io) ); } //used in UT only diff --git a/components/esp_psram/esp32s3/esp_psram_impl_octal.c b/components/esp_psram/esp32s3/esp_psram_impl_octal.c index 6aa5f4ae1e..d8d54a3a18 100644 --- a/components/esp_psram/esp32s3/esp_psram_impl_octal.c +++ b/components/esp_psram/esp32s3/esp_psram_impl_octal.c @@ -9,6 +9,7 @@ #include "esp_attr.h" #include "esp_err.h" #include "esp_types.h" +#include "esp_bit_defs.h" #include "esp_log.h" #include "../esp_psram_impl.h" #include "esp32s3/rom/ets_sys.h" @@ -20,6 +21,7 @@ #include "soc/syscon_reg.h" #include "esp_private/spi_flash_os.h" #include "esp_private/mspi_timing_tuning.h" +#include "esp_private/esp_gpio_reserve.h" #define OPI_PSRAM_SYNC_READ 0x0000 #define OPI_PSRAM_SYNC_WRITE 0x8080 @@ -263,6 +265,9 @@ static void s_init_psram_pins(void) PIN_SET_DRV(GPIO_PIN_MUX_REG[OCT_PSRAM_CS1_IO], 3); //Set psram clock pin drive strength REG_SET_FIELD(SPI_MEM_DATE_REG(0), SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV, 3); + + // Preserve psram pins + esp_gpio_reserve_pins(BIT64(OCT_PSRAM_CS1_IO)); } /** diff --git a/components/esp_psram/esp32s3/esp_psram_impl_quad.c b/components/esp_psram/esp32s3/esp_psram_impl_quad.c index 626f1bfa4f..db9827fcdc 100644 --- a/components/esp_psram/esp32s3/esp_psram_impl_quad.c +++ b/components/esp_psram/esp32s3/esp_psram_impl_quad.c @@ -10,6 +10,7 @@ #include "esp_attr.h" #include "esp_err.h" #include "esp_types.h" +#include "esp_bit_defs.h" #include "esp_log.h" #include "../esp_psram_impl.h" #include "esp32s3/rom/spi_flash.h" @@ -19,6 +20,7 @@ #include "hal/gpio_hal.h" #include "esp_private/spi_flash_os.h" #include "esp_private/mspi_timing_tuning.h" +#include "esp_private/esp_gpio_reserve.h" static const char* TAG = "quad_psram"; @@ -296,6 +298,9 @@ static void psram_gpio_config(void) } //This ROM function will init both WP and HD pins. esp_rom_spiflash_select_qio_pins(wp_io, spiconfig); + + // Reserve psram pins + esp_gpio_reserve_pins(BIT64(cs1_io) | BIT64(wp_io)); } esp_err_t esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode) //psram init diff --git a/components/spi_flash/flash_ops.c b/components/spi_flash/flash_ops.c index b195038cfa..8aa98777c0 100644 --- a/components/spi_flash/flash_ops.c +++ b/components/spi_flash/flash_ops.c @@ -24,6 +24,7 @@ #include "esp_private/system_internal.h" #include "esp_private/spi_flash_os.h" #include "esp_private/esp_clk.h" +#include "esp_private/esp_gpio_reserve.h" #if CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/cache.h" #include "esp32/rom/spi_flash.h" @@ -171,6 +172,12 @@ void IRAM_ATTR esp_mspi_pin_init(void) } //Set F4R4 board pin drive strength. TODO: IDF-3663 #endif + /* Reserve the GPIO pins */ + uint64_t reserve_pin_mask = 0; + for (esp_mspi_io_t i = 0; i < ESP_MSPI_IO_MAX; i++) { + reserve_pin_mask |= BIT64(esp_mspi_get_io(i)); + } + esp_gpio_reserve_pins(reserve_pin_mask); } esp_err_t IRAM_ATTR spi_flash_init_chip_state(void) diff --git a/components/spi_flash/include/esp_private/spi_flash_os.h b/components/spi_flash/include/esp_private/spi_flash_os.h index 0283909262..15ef0bf4a2 100644 --- a/components/spi_flash/include/esp_private/spi_flash_os.h +++ b/components/spi_flash/include/esp_private/spi_flash_os.h @@ -40,8 +40,9 @@ typedef enum { ESP_MSPI_IO_D7, #endif // SOC_SPI_MEM_SUPPORT_OPI_MODE #if CONFIG_SPIRAM - ESP_MSPI_IO_CS1 /* cs for spi ram */ + ESP_MSPI_IO_CS1, /* cs for spi ram */ #endif + ESP_MSPI_IO_MAX, /* Maximum IO MSPI occupied */ } esp_mspi_io_t; /**