diff --git a/components/esp_wifi/include/phy.h b/components/esp_wifi/include/phy.h index 74eae0e6c2..507ffcdacf 100644 --- a/components/esp_wifi/include/phy.h +++ b/components/esp_wifi/include/phy.h @@ -71,6 +71,16 @@ void phy_wakeup_init(void); */ void phy_close_rf(void); +/** + * @brief Store and load PHY digital registers. + * + * @param backup_en if backup_en is true, store PHY digital registers to memory. Otherwise load PHY digital registers from memory + * @param mem_addr Memory address to store and load PHY digital registers + * + * @return memory size + */ +uint8_t phy_dig_reg_backup(bool backup_en, uint32_t *mem_addr); + #ifdef __cplusplus } #endif diff --git a/components/esp_wifi/src/phy_init.c b/components/esp_wifi/src/phy_init.c index 6b32f32cf9..45fc3fc336 100644 --- a/components/esp_wifi/src/phy_init.c +++ b/components/esp_wifi/src/phy_init.c @@ -34,6 +34,7 @@ #include "esp_coexist_internal.h" #include "driver/periph_ctrl.h" #include "esp_private/wifi.h" +#include "soc/soc_caps.h" #if CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/ets_sys.h" @@ -79,6 +80,9 @@ static int64_t s_phy_rf_en_ts = 0; static DRAM_ATTR portMUX_TYPE s_phy_int_mux = portMUX_INITIALIZER_UNLOCKED; +/* Memory to store PHY digital registers */ +static uint32_t* s_phy_digital_regs_mem = NULL; + #if CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN /* The following static variables are only used by Wi-Fi tasks, so they can be handled without lock */ static phy_init_data_type_t s_phy_init_data_type = 0; @@ -199,6 +203,24 @@ IRAM_ATTR void esp_phy_common_clock_disable(void) wifi_bt_common_module_disable(); } +static inline void phy_digital_regs_store(void) +{ + if (s_phy_digital_regs_mem == NULL) { + s_phy_digital_regs_mem = (uint32_t *)malloc(SOC_PHY_DIG_REGS_MEM_SIZE); + } + + if (s_phy_digital_regs_mem != NULL) { + phy_dig_reg_backup(true, s_phy_digital_regs_mem); + } +} + +static inline void phy_digital_regs_load(void) +{ + if (s_phy_digital_regs_mem != NULL) { + phy_dig_reg_backup(false, s_phy_digital_regs_mem); + } +} + esp_err_t esp_phy_rf_init(const esp_phy_init_data_t* init_data, esp_phy_calibration_mode_t mode, esp_phy_calibration_data_t* calibration_data, phy_rf_module_t module) { @@ -254,6 +276,7 @@ esp_err_t esp_phy_rf_init(const esp_phy_init_data_t* init_data, esp_phy_calibrat #if CONFIG_IDF_TARGET_ESP32S2 if (module == PHY_MODEM_MODULE) { phy_wakeup_init(); + phy_digital_regs_load(); } else #endif @@ -335,6 +358,7 @@ esp_err_t esp_phy_rf_deinit(phy_rf_module_t module) } if (s_is_phy_rf_en == false) { + phy_digital_regs_store(); // Disable PHY and RF. phy_close_rf(); #if CONFIG_IDF_TARGET_ESP32 diff --git a/components/soc/soc/esp32/include/soc/soc_caps.h b/components/soc/soc/esp32/include/soc/soc_caps.h index f86798c316..b4c77f962c 100644 --- a/components/soc/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/soc/esp32/include/soc/soc_caps.h @@ -14,3 +14,7 @@ #define SOC_EMAC_SUPPORTED 1 #define SOC_CPU_CORES_NUM 2 + +/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ +#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) + diff --git a/components/soc/soc/esp32s2/include/soc/soc_caps.h b/components/soc/soc/esp32s2/include/soc/soc_caps.h index 8014ba7284..565409cda1 100644 --- a/components/soc/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/soc/esp32s2/include/soc/soc_caps.h @@ -8,3 +8,7 @@ #define SOC_TWAI_SUPPORTED 1 #define SOC_CPU_CORES_NUM 1 #define SOC_SUPPORTS_SECURE_DL_MODE 1 + +/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ +#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) +