diff --git a/components/driver/test_apps/uart/main/test_uart.c b/components/driver/test_apps/uart/main/test_uart.c
index ccf2fc7ff7..688040e649 100644
--- a/components/driver/test_apps/uart/main/test_uart.c
+++ b/components/driver/test_apps/uart/main/test_uart.c
@@ -389,7 +389,7 @@ TEST_CASE("uart int state restored after flush", "[uart]")
     };
 
     const uart_port_t uart_echo = UART_NUM_1;
-    const int uart_tx_signal = U1TXD_OUT_IDX;
+    const int uart_tx_signal = uart_periph_signal[uart_echo].pins[SOC_UART_TX_PIN_IDX].signal;
     const int uart_tx = UART1_TX_PIN;
     const int uart_rx = UART1_RX_PIN;
     const int buf_size = 256;
diff --git a/components/driver/uart/uart.c b/components/driver/uart/uart.c
index 543aeb4771..b4104ed020 100644
--- a/components/driver/uart/uart.c
+++ b/components/driver/uart/uart.c
@@ -159,6 +159,12 @@ static uart_context_t uart_context[UART_NUM_MAX] = {
 #if SOC_UART_HP_NUM > 2
     UART_CONTEX_INIT_DEF(UART_NUM_2),
 #endif
+#if SOC_UART_HP_NUM > 3
+    UART_CONTEX_INIT_DEF(UART_NUM_3),
+#endif
+#if SOC_UART_HP_NUM > 4
+    UART_CONTEX_INIT_DEF(UART_NUM_4),
+#endif
 #if (SOC_UART_LP_NUM >= 1)
     UART_CONTEX_INIT_DEF(LP_UART_NUM_0),
 #endif
@@ -643,7 +649,7 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r
         ESP_RETURN_ON_FALSE((rts_io_num < 0 || (GPIO_IS_VALID_OUTPUT_GPIO(rts_io_num))), ESP_FAIL, UART_TAG, "rts_io_num error");
         ESP_RETURN_ON_FALSE((cts_io_num < 0 || (GPIO_IS_VALID_GPIO(cts_io_num))), ESP_FAIL, UART_TAG, "cts_io_num error");
     }
-#if (SOC_UART_LP_NUM >= 1)
+#if (SOC_UART_LP_NUM >= 1 && !SOC_LP_GPIO_MATRIX_SUPPORTED)
     else { // LP_UART has its fixed IOs
         const uart_periph_sig_t *pins = uart_periph_signal[uart_num].pins;
         ESP_RETURN_ON_FALSE((tx_io_num < 0 || (tx_io_num == pins[SOC_UART_TX_PIN_IDX].default_gpio)), ESP_FAIL, UART_TAG, "tx_io_num error");
@@ -655,31 +661,76 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r
 
     /* In the following statements, if the io_num is negative, no need to configure anything. */
     if (tx_io_num >= 0 && !uart_try_set_iomux_pin(uart_num, tx_io_num, SOC_UART_TX_PIN_IDX)) {
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[tx_io_num], PIN_FUNC_GPIO);
+        if (uart_num < SOC_UART_HP_NUM) {
+            gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[tx_io_num], PIN_FUNC_GPIO);
         gpio_set_level(tx_io_num, 1);
         esp_rom_gpio_connect_out_signal(tx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_TX_PIN_IDX), 0, 0);
+        }
+#if SOC_LP_GPIO_MATRIX_SUPPORTED
+        else {
+            //TODO:IDF-7815
+            rtc_gpio_set_direction(tx_io_num, RTC_GPIO_MODE_OUTPUT_ONLY);
+            rtc_gpio_init(tx_io_num);
+            rtc_gpio_iomux_func_sel(tx_io_num, 1);
+            LP_GPIO.func10_out_sel_cfg.reg_gpio_func10_out_sel  = uart_periph_signal[uart_num].pins[SOC_UART_TX_PIN_IDX].signal;
+        }
+#endif
     }
 
     if (rx_io_num >= 0 && !uart_try_set_iomux_pin(uart_num, rx_io_num, SOC_UART_RX_PIN_IDX)) {
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rx_io_num], PIN_FUNC_GPIO);
-        gpio_set_pull_mode(rx_io_num, GPIO_PULLUP_ONLY);
-        gpio_set_direction(rx_io_num, GPIO_MODE_INPUT);
-        esp_rom_gpio_connect_in_signal(rx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), 0);
+        if (uart_num < SOC_UART_HP_NUM) {
+            gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rx_io_num], PIN_FUNC_GPIO);
+            gpio_set_pull_mode(rx_io_num, GPIO_PULLUP_ONLY);
+            gpio_set_direction(rx_io_num, GPIO_MODE_INPUT);
+            esp_rom_gpio_connect_in_signal(rx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), 0);
+        }
+#if SOC_LP_GPIO_MATRIX_SUPPORTED
+        else {
+            //TODO:IDF-7815
+            rtc_gpio_set_direction(rx_io_num, RTC_GPIO_MODE_INPUT_ONLY);
+            rtc_gpio_init(rx_io_num);
+            rtc_gpio_iomux_func_sel(rx_io_num, 1);
+            LP_GPIO.func2_in_sel_cfg.reg_gpio_sig2_in_sel = 1;
+            LP_GPIO.func2_in_sel_cfg.reg_gpio_func2_in_sel = 11;
+        }
+#endif
     }
 
     if (rts_io_num >= 0 && !uart_try_set_iomux_pin(uart_num, rts_io_num, SOC_UART_RTS_PIN_IDX)) {
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rts_io_num], PIN_FUNC_GPIO);
-        gpio_set_direction(rts_io_num, GPIO_MODE_OUTPUT);
-        esp_rom_gpio_connect_out_signal(rts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RTS_PIN_IDX), 0, 0);
+        if (uart_num < SOC_UART_HP_NUM) {
+            gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rts_io_num], PIN_FUNC_GPIO);
+            gpio_set_direction(rts_io_num, GPIO_MODE_OUTPUT);
+            esp_rom_gpio_connect_out_signal(rts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RTS_PIN_IDX), 0, 0);
+        }
+#if SOC_LP_GPIO_MATRIX_SUPPORTED
+        else {
+            //TODO:IDF-7815
+            rtc_gpio_set_direction(rts_io_num, RTC_GPIO_MODE_OUTPUT_ONLY);
+            rtc_gpio_init(rts_io_num);
+            rtc_gpio_iomux_func_sel(rts_io_num, 1);
+            LP_GPIO.func10_out_sel_cfg.reg_gpio_func12_out_sel  = uart_periph_signal[uart_num].pins[SOC_UART_RTS_PIN_IDX].signal;
+        }
+#endif
     }
 
     if (cts_io_num >= 0  && !uart_try_set_iomux_pin(uart_num, cts_io_num, SOC_UART_CTS_PIN_IDX)) {
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cts_io_num], PIN_FUNC_GPIO);
-        gpio_set_pull_mode(cts_io_num, GPIO_PULLUP_ONLY);
-        gpio_set_direction(cts_io_num, GPIO_MODE_INPUT);
-        esp_rom_gpio_connect_in_signal(cts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_CTS_PIN_IDX), 0);
+        if (uart_num < SOC_UART_HP_NUM) {
+            gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cts_io_num], PIN_FUNC_GPIO);
+            gpio_set_pull_mode(cts_io_num, GPIO_PULLUP_ONLY);
+            gpio_set_direction(cts_io_num, GPIO_MODE_INPUT);
+            esp_rom_gpio_connect_in_signal(cts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_CTS_PIN_IDX), 0);
+        }
+#if SOC_LP_GPIO_MATRIX_SUPPORTED
+        else {
+            //TODO:IDF-7815
+            rtc_gpio_set_direction(cts_io_num, RTC_GPIO_MODE_INPUT_ONLY);
+            rtc_gpio_init(cts_io_num);
+            rtc_gpio_iomux_func_sel(cts_io_num, 1);
+            LP_GPIO.func2_in_sel_cfg.reg_gpio_sig3_in_sel = 1;
+            LP_GPIO.func2_in_sel_cfg.reg_gpio_func3_in_sel = 13;
+        }
+#endif
     }
-
     return ESP_OK;
 }
 
diff --git a/components/esp_hw_support/port/esp32p4/esp_clk_tree.c b/components/esp_hw_support/port/esp32p4/esp_clk_tree.c
index 3a1c3598b3..b538989239 100644
--- a/components/esp_hw_support/port/esp32p4/esp_clk_tree.c
+++ b/components/esp_hw_support/port/esp32p4/esp_clk_tree.c
@@ -25,6 +25,12 @@ uint32_t *freq_value)
     case SOC_MOD_CLK_XTAL:
         clk_src_freq = 40 * MHZ;
         break;
+    case SOC_MOD_CLK_XTAL_D2:
+        clk_src_freq = (40* MHZ) >> 1;
+        break;
+    case SOC_MOD_CLK_LP_PLL:
+        clk_src_freq = 8 * MHZ;
+        break;
     default:
         break;
     }
diff --git a/components/hal/esp32p4/include/hal/uart_ll.h b/components/hal/esp32p4/include/hal/uart_ll.h
index 3b3dbbbc88..1607febcc3 100644
--- a/components/hal/esp32p4/include/hal/uart_ll.h
+++ b/components/hal/esp32p4/include/hal/uart_ll.h
@@ -10,24 +10,34 @@
 
 #pragma once
 
+#include "esp_attr.h"
 #include "hal/misc.h"
 #include "hal/assert.h"
 #include "hal/uart_types.h"
-#include "soc/uart_periph.h"
 #include "soc/uart_reg.h"
 #include "soc/uart_struct.h"
 #include "soc/hp_sys_clkrst_struct.h"
+#include "soc/lp_uart_reg.h"
+#include "soc/lp_clkrst_struct.h"
+#include "soc/lpperi_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-//TODO: IDF-6511
-
 // The default fifo depth
 #define UART_LL_FIFO_DEF_LEN  (SOC_UART_FIFO_LEN)
+#define LP_UART_LL_FIFO_DEF_LEN (SOC_LP_UART_FIFO_LEN)
+
 // Get UART hardware instance with giving uart num
-#define UART_LL_GET_HW(num) (((num) == 0) ? (&UART0) : (&UART1))
+#define UART_LL_GET_HW(num) \
+    ((num) == 0 ? (&UART0) : \
+    (num) == 1 ? (&UART1) : \
+    (num) == 2 ? (&UART2) : \
+    (num) == 3 ? (&UART3) : \
+    (num) == 4 ? (&UART4) : (&LP_UART))
+
+#define UART_LL_REG_FIELD_BIT_SHIFT(hw) (((hw) == &LP_UART) ? 3 : 0)
 
 #define UART_LL_MIN_WAKEUP_THRESH (2)
 #define UART_LL_INTR_MASK         (0x7ffff) //All interrupt mask
@@ -59,6 +69,83 @@ typedef enum {
     UART_INTR_WAKEUP           = (0x1 << 19),
 } uart_intr_t;
 
+/****************************************** LP_UART Specific ********************************************/
+/**
+ * @brief  Get the LP_UART source clock.
+ *
+ * @param hw Beginning address of the peripheral registers.
+ * @param source_clk Current LP_UART clock source, one in soc_periph_lp_uart_clk_src_t.
+ */
+FORCE_INLINE_ATTR void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
+{
+    (void)hw;
+    switch (LPPERI.core_clk_sel.lp_uart_clk_sel) {
+    default:
+    case 0:
+        *source_clk = (soc_module_clk_t)LP_UART_SCLK_LP_FAST;
+        break;
+    case 1:
+        *source_clk = (soc_module_clk_t)LP_UART_SCLK_XTAL_D2;
+        break;
+    }
+}
+
+/**
+ * @brief Set LP UART source clock
+ *
+ * @param  hw Address offset of the LP UART peripheral registers
+ * @param  src_clk Source clock for the LP UART peripheral
+ */
+static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_clk_src_t src_clk)
+{
+    (void)hw;
+    switch (src_clk) {
+    case LP_UART_SCLK_LP_FAST:
+        LPPERI.core_clk_sel.lp_uart_clk_sel = 0;
+        break;
+    case LP_UART_SCLK_XTAL_D2:
+        LPPERI.core_clk_sel.lp_uart_clk_sel = 1;
+        break;
+    default:
+        // Invalid LP_UART clock source
+        HAL_ASSERT(false);
+    }
+}
+
+/// LPPERI.core_clk_sel  is a shared register, so this function must be used in an atomic way
+#define lp_uart_ll_set_source_clk(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_set_source_clk(__VA_ARGS__)
+
+/**
+ * @brief Enable bus clock for the LP UART module
+ *
+ * @param hw_id LP UART instance ID
+ * @param enable True to enable, False to disable
+ */
+static inline void lp_uart_ll_enable_bus_clock(int hw_id, bool enable)
+{
+    (void)hw_id;
+    LPPERI.clk_en.ck_en_lp_uart = enable;
+}
+
+/// LPPERI.clk_en is a shared register, so this function must be used in an atomic way
+#define lp_uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_enable_bus_clock(__VA_ARGS__)
+
+/**
+ * @brief Reset LP UART module
+ *
+ * @param hw_id LP UART instance ID
+ */
+static inline void lp_uart_ll_reset_register(int hw_id)
+{
+    (void)hw_id;
+    LPPERI.reset_en.rst_en_lp_uart = 1;
+    LPPERI.reset_en.rst_en_lp_uart = 0;
+}
+
+/// LPPERI.reset_en is a shared register, so this function must be used in an atomic way
+#define lp_uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_reset_register(__VA_ARGS__)
+
+/*************************************** General LL functions ******************************************/
 /**
  * @brief Sync the update to UART core clock domain
  *
@@ -66,7 +153,7 @@ typedef enum {
  *
  * @return None.
  */
-static inline void uart_ll_update(uart_dev_t *hw)
+FORCE_INLINE_ATTR void uart_ll_update(uart_dev_t *hw)
 {
     hw->reg_update.reg_update = 1;
     while (hw->reg_update.reg_update);
@@ -80,10 +167,24 @@ static inline void uart_ll_update(uart_dev_t *hw)
  *
  * @return None.
  */
-static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
+FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
 {
-    // hw->clk_conf.rst_core = core_rst_en;
-    HAL_ASSERT(false);
+
+    if ((hw) == &UART0) {
+        HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart0_core = core_rst_en;
+    } else if ((hw) == &UART1) {
+        HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart1_core = core_rst_en;
+    } else if ((hw) == &UART2) {
+        HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart2_core = core_rst_en;
+    } else if ((hw) == &UART3) {
+        HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart3_core = core_rst_en;
+    } else if ((hw) == &UART4) {
+        HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart4_core = core_rst_en;
+    } else {
+        // LP_UART reset shares the same register with other LP peripherals
+        // Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c
+        abort();
+    }
 }
 
 /**
@@ -93,12 +194,39 @@ static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
  *
  * @return None.
  */
-static inline void uart_ll_sclk_enable(uart_dev_t *hw)
+
+FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw)
 {
-    // hw->clk_conf.sclk_en = 1;
-    // hw->clk_conf.rx_sclk_en = 1;
-    // hw->clk_conf.tx_sclk_en = 1;
-    HAL_ASSERT(false);
+    if ((hw) == &UART0) {
+        HP_SYS_CLKRST.peri_clk_ctrl110.reg_uart0_clk_en = 1;
+        //To do: call these two in clk_gate_ll.h
+        HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart0_sys_clk_en = 1;
+        HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart0_apb_clk_en = 1;
+    } else if ((hw) == &UART1) {
+        HP_SYS_CLKRST.peri_clk_ctrl111.reg_uart1_clk_en = 1;
+        //To do: call these two in clk_gate_ll.h
+        HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart1_sys_clk_en = 1;
+        HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart1_apb_clk_en = 1;
+    } else if ((hw) == &UART2) {
+        HP_SYS_CLKRST.peri_clk_ctrl112.reg_uart2_clk_en = 1;
+        //To do: call these two in clk_gate_ll.h
+        HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart2_sys_clk_en = 1;
+        HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart2_apb_clk_en = 1;
+    } else if ((hw) == &UART3) {
+        HP_SYS_CLKRST.peri_clk_ctrl113.reg_uart3_clk_en = 1;
+        //To do: call these two in clk_gate_ll.h
+        HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart3_sys_clk_en = 1;
+        HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart3_apb_clk_en = 1;
+    } else if ((hw) == &UART4) {
+        HP_SYS_CLKRST.peri_clk_ctrl114.reg_uart4_clk_en = 1;
+        //To do: call these two in clk_gate_ll.h
+        HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart4_sys_clk_en = 1;
+        HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart4_apb_clk_en = 1;
+    } else {
+        // LP_UART reset shares the same register with other LP peripherals
+        // Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c
+        abort();
+    }
 }
 
 /**
@@ -108,12 +236,38 @@ static inline void uart_ll_sclk_enable(uart_dev_t *hw)
  *
  * @return None.
  */
-static inline void uart_ll_sclk_disable(uart_dev_t *hw)
+FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
 {
-    // hw->clk_conf.sclk_en = 0;
-    // hw->clk_conf.rx_sclk_en = 0;
-    // hw->clk_conf.tx_sclk_en = 0;
-    HAL_ASSERT(false);
+    if ((hw) == &UART0) {
+        HP_SYS_CLKRST.peri_clk_ctrl110.reg_uart0_clk_en = 0;
+        //To do: call these two in clk_gate_ll.h
+        HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart0_sys_clk_en = 0;
+        HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart0_apb_clk_en = 0;
+    } else if ((hw) == &UART1) {
+        HP_SYS_CLKRST.peri_clk_ctrl111.reg_uart1_clk_en = 0;
+        //To do: call these two in clk_gate_ll.h
+        HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart1_sys_clk_en = 0;
+        HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart1_apb_clk_en = 0;
+    } else if ((hw) == &UART2) {
+        HP_SYS_CLKRST.peri_clk_ctrl112.reg_uart2_clk_en = 0;
+        //To do: call these two in clk_gate_ll.h
+        HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart2_sys_clk_en = 0;
+        HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart2_apb_clk_en = 0;
+    } else if ((hw) == &UART3) {
+        HP_SYS_CLKRST.peri_clk_ctrl113.reg_uart3_clk_en = 0;
+        //To do: call these two in clk_gate_ll.h
+        HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart3_sys_clk_en = 0;
+        HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart3_apb_clk_en = 0;
+    } else if ((hw) == &UART4) {
+        HP_SYS_CLKRST.peri_clk_ctrl114.reg_uart4_clk_en = 0;
+        //To do: call these two in clk_gate_ll.h
+        HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart4_sys_clk_en = 0;
+        HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart4_apb_clk_en = 0;
+    } else {
+        // LP_UART reset shares the same register with other LP peripherals
+        // Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c
+        abort();
+    }
 }
 
 /**
@@ -125,8 +279,38 @@ static inline void uart_ll_sclk_disable(uart_dev_t *hw)
  *
  * @return None.
  */
-static inline void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
+FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
 {
+    uint32_t sel_value = 0;
+    switch (source_clk) {
+    case UART_SCLK_XTAL:
+        sel_value = 0;
+        break;
+    case UART_SCLK_RTC:
+        sel_value = 1;
+        break;
+    case UART_SCLK_PLL_F80M:
+        sel_value = 2;
+        break;
+    default:
+        // Invalid HP_UART clock source
+        abort();
+    }
+    if ((hw) == &UART0) {
+        HP_SYS_CLKRST.peri_clk_ctrl110.reg_uart0_clk_src_sel = sel_value;
+    } else if ((hw) == &UART1) {
+        HP_SYS_CLKRST.peri_clk_ctrl111.reg_uart1_clk_src_sel = sel_value;
+    } else if ((hw) == &UART2) {
+        HP_SYS_CLKRST.peri_clk_ctrl112.reg_uart2_clk_src_sel = sel_value;
+    } else if ((hw) == &UART3) {
+        HP_SYS_CLKRST.peri_clk_ctrl113.reg_uart3_clk_src_sel = sel_value;
+    } else if ((hw) == &UART4) {
+        HP_SYS_CLKRST.peri_clk_ctrl114.reg_uart4_clk_src_sel = sel_value;
+    } else {
+        // LP_UART reset shares the same register with other LP peripherals
+        // Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c
+        abort();
+    }
 }
 
 /**
@@ -137,8 +321,36 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
  *
  * @return None.
  */
-static inline void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
+FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
 {
+    uint32_t sel_value = 0;
+    if ((hw) == &UART0) {
+        sel_value = HP_SYS_CLKRST.peri_clk_ctrl110.reg_uart0_clk_src_sel;
+    } else if ((hw) == &UART1) {
+        sel_value = HP_SYS_CLKRST.peri_clk_ctrl111.reg_uart1_clk_src_sel;
+    } else if ((hw) == &UART2) {
+        sel_value = HP_SYS_CLKRST.peri_clk_ctrl112.reg_uart2_clk_src_sel;
+    } else if ((hw) == &UART3) {
+        sel_value = HP_SYS_CLKRST.peri_clk_ctrl113.reg_uart3_clk_src_sel;
+    } else if ((hw) == &UART4) {
+        sel_value = HP_SYS_CLKRST.peri_clk_ctrl114.reg_uart4_clk_src_sel;
+    }
+    if ((hw) != &LP_UART) {
+        switch (sel_value) {
+        default:
+        case 1:
+            *source_clk = (soc_module_clk_t)UART_SCLK_RTC;
+            break;
+        case 0:
+            *source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
+            break;
+        case 2:
+            *source_clk = (soc_module_clk_t)UART_SCLK_PLL_F80M;
+            break;
+        }
+    } else {
+        lp_uart_ll_get_sclk(hw, source_clk);
+    }
 }
 
 /**
@@ -150,27 +362,37 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk
  *
  * @return None
  */
-static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
+FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
 {
-#define DIV_UP(a, b)    (((a) + (b) - 1) / (b))
-    const uint32_t max_div = BIT(12) - 1;   // UART divider integer part only has 12 bits
-    int sclk_div = DIV_UP(sclk_freq, max_div * baud);
-
-    uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
-    // The baud rate configuration register is divided into
-    // an integer part and a fractional part.
-    hw->clkdiv_sync.clkdiv = clk_div >> 4;
-    hw->clkdiv_sync.clkdiv_frag = clk_div &  0xf;
-
-    //needs force u32 write
-    if ((hw) == &UART0) {
-        HP_SYS_CLKRST.peri_clk_ctrl111.reg_uart0_sclk_div_num = sclk_div - 1;
+    if ((hw) == &LP_UART){
+        uint32_t clk_div = ((sclk_freq) << 4) / (baud);
+        hw->clkdiv_sync.clkdiv = clk_div >> 4;
+        hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
     } else {
-        HP_SYS_CLKRST.peri_clk_ctrl112.reg_uart1_sclk_div_num = sclk_div - 1;
-    }
+#define DIV_UP(a, b)    (((a) + (b) - 1) / (b))
+            const uint32_t max_div = BIT(12) - 1;   // UART divider integer part only has 12 bits
+            int sclk_div = DIV_UP(sclk_freq, max_div * baud);
 
+            uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
+            // The baud rate configuration register is divided into
+            // an integer part and a fractional part.
+            hw->clkdiv_sync.clkdiv = clk_div >> 4;
+            hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
+            //needs force u32 write
+            if ((hw) == &UART0) {
+                HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl111, reg_uart0_sclk_div_num, sclk_div - 1);
+            } else if ((hw) == &UART1){
+                HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl112, reg_uart1_sclk_div_num, sclk_div - 1);
+            } else if ((hw) == &UART2){
+                HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl113, reg_uart2_sclk_div_num, sclk_div - 1);
+            } else if ((hw) == &UART3){
+                HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl114, reg_uart3_sclk_div_num, sclk_div - 1);
+            } else {
+                HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl115, reg_uart4_sclk_div_num, sclk_div - 1);
+            }
+        }
 #undef DIV_UP
-    uart_ll_update(hw); // TODO: IDF-5338
+    uart_ll_update(hw);
 }
 
 /**
@@ -181,12 +403,25 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t
  *
  * @return The current baudrate
  */
-static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
+FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
 {
-    // typeof(hw->clkdiv_sync) div_reg = hw->clkdiv_sync;
-    // return ((sclk_freq << 4)) / (((div_reg.clkdiv << 4) | div_reg.clkdiv_frag) * (HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1));
-    HAL_ASSERT(false);
-    return 115200; // TODO: IDF-5338
+    typeof(hw->clkdiv_sync) div_reg;
+    div_reg.val = hw->clkdiv_sync.val;
+    int sclk_div = 0;
+    if ((hw) == &UART0) {
+        sclk_div = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl111, reg_uart0_sclk_div_num) + 1;
+    } else if ((hw) == &UART1){
+        sclk_div = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl112, reg_uart1_sclk_div_num) + 1;
+    } else if ((hw) == &UART2){
+        sclk_div = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl113, reg_uart2_sclk_div_num) + 1;
+    } else if ((hw) == &UART3){
+        sclk_div = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl114, reg_uart3_sclk_div_num) + 1;
+    } else if ((hw) == &UART4){
+        sclk_div = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl115, reg_uart4_sclk_div_num) + 1;
+    } else {
+        return ((sclk_freq << 4)) / (((div_reg.clkdiv << 4) | div_reg.clkdiv_frag));
+    }
+    return ((sclk_freq << 4)) / (((div_reg.clkdiv << 4) | div_reg.clkdiv_frag) * sclk_div);
 }
 
 /**
@@ -197,9 +432,9 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
  *
  * @return None
  */
-static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
+FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
 {
-    hw->int_ena.val |= mask;
+    hw->int_ena.val = hw->int_ena.val | mask;
 }
 
 /**
@@ -210,9 +445,9 @@ static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
  *
  * @return None
  */
-static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
+FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
 {
-    hw->int_ena.val &= (~mask);
+    hw->int_ena.val = hw->int_ena.val & (~mask);
 }
 
 /**
@@ -222,7 +457,7 @@ static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
  *
  * @return The UART interrupt status.
  */
-static inline uint32_t uart_ll_get_intraw_mask(uart_dev_t *hw)
+FORCE_INLINE_ATTR uint32_t uart_ll_get_intraw_mask(uart_dev_t *hw)
 {
     return hw->int_raw.val;
 }
@@ -234,7 +469,7 @@ static inline uint32_t uart_ll_get_intraw_mask(uart_dev_t *hw)
  *
  * @return The UART interrupt status.
  */
-static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
+FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
 {
     return hw->int_st.val;
 }
@@ -247,7 +482,7 @@ static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
  *
  * @return None
  */
-static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
+FORCE_INLINE_ATTR void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
 {
     hw->int_clr.val = mask;
 }
@@ -259,7 +494,7 @@ static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
  *
  * @return interrupt enable value
  */
-static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
+FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
 {
     return hw->int_ena.val;
 }
@@ -273,10 +508,10 @@ static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
  *
  * @return None.
  */
-static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
+FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
 {
     for (int i = 0; i < (int)rd_len; i++) {
-        buf[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->fifo, rxfifo_rd_byte);
+        buf[i] = hw->fifo.rxfifo_rd_byte;
     }
 }
 
@@ -289,10 +524,10 @@ static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd
  *
  * @return None
  */
-static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
+FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
 {
     for (int i = 0; i < (int)wr_len; i++) {
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->fifo, rxfifo_rd_byte, buf[i]);
+        hw->fifo.rxfifo_rd_byte = buf[i];
     }
 }
 
@@ -303,7 +538,7 @@ static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint
  *
  * @return None
  */
-static inline void uart_ll_rxfifo_rst(uart_dev_t *hw)
+FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw)
 {
     hw->conf0_sync.rxfifo_rst = 1;
     uart_ll_update(hw);
@@ -318,7 +553,7 @@ static inline void uart_ll_rxfifo_rst(uart_dev_t *hw)
  *
  * @return None
  */
-static inline void uart_ll_txfifo_rst(uart_dev_t *hw)
+FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw)
 {
     hw->conf0_sync.txfifo_rst = 1;
     uart_ll_update(hw);
@@ -333,9 +568,9 @@ static inline void uart_ll_txfifo_rst(uart_dev_t *hw)
  *
  * @return The readable data length in rxfifo.
  */
-static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
+FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
 {
-    return hw->status.rxfifo_cnt;
+    return (hw->status.rxfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
 }
 
 /**
@@ -345,9 +580,11 @@ static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
  *
  * @return The data length of txfifo can be written.
  */
-static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
+FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
 {
-    return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt;
+    uint32_t total_fifo_len = ((hw) == &LP_UART) ? LP_UART_LL_FIFO_DEF_LEN : UART_LL_FIFO_DEF_LEN;
+    uint32_t txfifo_len = (hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
+    return (total_fifo_len - txfifo_len);
 }
 
 /**
@@ -358,7 +595,7 @@ static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
  *
  * @return None.
  */
-static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
+FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
 {
     hw->conf0_sync.stop_bit_num = stop_bit;
     uart_ll_update(hw);
@@ -372,7 +609,7 @@ static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_b
  *
  * @return None.
  */
-static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
+FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
 {
     *stop_bit = (uart_stop_bits_t)hw->conf0_sync.stop_bit_num;
 }
@@ -385,7 +622,7 @@ static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_
  *
  * @return None.
  */
-static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
+FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
 {
     if (parity_mode != UART_PARITY_DISABLE) {
         hw->conf0_sync.parity = parity_mode & 0x1;
@@ -402,7 +639,7 @@ static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
  *
  * @return None.
  */
-static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode)
+FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode)
 {
     if (hw->conf0_sync.parity_en) {
         *parity_mode = (uart_parity_t)(0x2 | hw->conf0_sync.parity);
@@ -416,13 +653,13 @@ static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode
  *         it will produce rxfifo_full_int_raw interrupt.
  *
  * @param  hw Beginning address of the peripheral registers.
- * @param  full_thrhd The full threshold value of the rxfifo. `full_thrhd` should be less than `UART_LL_FIFO_DEF_LEN`.
+ * @param  full_thrhd The full threshold value of the rxfifo. `full_thrhd` should be less than `(LP_)UART_LL_FIFO_DEF_LEN`.
  *
  * @return None.
  */
-static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
+FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
 {
-    hw->conf1.rxfifo_full_thrhd = full_thrhd;
+    hw->conf1.rxfifo_full_thrhd = full_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw);
 }
 
 /**
@@ -434,9 +671,9 @@ static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thr
  *
  * @return None.
  */
-static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
+FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
 {
-    hw->conf1.txfifo_empty_thrhd = empty_thrhd;
+    hw->conf1.txfifo_empty_thrhd = empty_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw);
 }
 
 /**
@@ -448,7 +685,7 @@ static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_t
  *
  * @return None.
  */
-static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
+FORCE_INLINE_ATTR void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
 {
     hw->idle_conf_sync.rx_idle_thrhd = rx_idle_thr;
     uart_ll_update(hw);
@@ -462,7 +699,7 @@ static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
  *
  * @return None.
  */
-static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
+FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
 {
     hw->idle_conf_sync.tx_idle_num = idle_num;
     uart_ll_update(hw);
@@ -476,7 +713,7 @@ static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
  *
  * @return None.
  */
-static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
+FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
 {
     if (break_num > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf_sync, tx_brk_num, break_num);
@@ -496,11 +733,11 @@ static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
  *
  * @return None.
  */
-static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs)
+FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs)
 {
     //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
     if (flow_ctrl & UART_HW_FLOWCTRL_RTS) {
-        hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs;
+        hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs << UART_LL_REG_FIELD_BIT_SHIFT(hw);
         hw->hwfc_conf_sync.rx_flow_en = 1;
     } else {
         hw->hwfc_conf_sync.rx_flow_en = 0;
@@ -521,7 +758,7 @@ static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_
  *
  * @return None.
  */
-static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl)
+FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl)
 {
     *flow_ctrl = UART_HW_FLOWCTRL_DISABLE;
     if (hw->hwfc_conf_sync.rx_flow_en) {
@@ -541,13 +778,13 @@ static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_
  *
  * @return None.
  */
-static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en)
+FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en)
 {
     if (sw_flow_ctrl_en) {
         hw->swfc_conf0_sync.xonoff_del = 1;
         hw->swfc_conf0_sync.sw_flow_con_en = 1;
-        hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd;
-        hw->swfc_conf1.xoff_threshold = flow_ctrl->xoff_thrd;
+        hw->swfc_conf1.xon_threshold = (flow_ctrl->xon_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw);
+        hw->swfc_conf1.xoff_threshold = (flow_ctrl->xoff_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw);
         HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char);
         HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char);
     } else {
@@ -570,15 +807,14 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *
  *
  * @return None.
  */
-static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
+FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
 {
-    // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, data, cmd_char->cmd_char);
-    // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, char_num, cmd_char->char_num);
-    // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt_sync, post_idle_num, cmd_char->post_idle);
-    // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt_sync, pre_idle_num, cmd_char->pre_idle);
-    // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout_sync, rx_gap_tout, cmd_char->gap_tout);
-    // uart_ll_update(hw);
-    HAL_ASSERT(false);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, at_cmd_char, cmd_char->cmd_char);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, char_num, cmd_char->char_num);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt_sync, post_idle_num, cmd_char->post_idle);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt_sync, pre_idle_num, cmd_char->pre_idle);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout_sync, rx_gap_tout, cmd_char->gap_tout);
+    uart_ll_update(hw);
 }
 
 /**
@@ -589,7 +825,7 @@ static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_ch
  *
  * @return None.
  */
-static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit)
+FORCE_INLINE_ATTR void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit)
 {
     hw->conf0_sync.bit_num = data_bit;
     uart_ll_update(hw);
@@ -603,7 +839,7 @@ static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t d
  *
  * @return None.
  */
-static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
+FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
 {
     hw->conf0_sync.sw_rts = level & 0x1;
     uart_ll_update(hw);
@@ -617,7 +853,7 @@ static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
  *
  * @return None.
  */
-static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
+FORCE_INLINE_ATTR void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
 {
     hw->conf1.sw_dtr = level & 0x1;
 }
@@ -631,7 +867,7 @@ static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
  *
  * @return None.
  */
-static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
+FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
 {
     hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH;
 }
@@ -643,8 +879,12 @@ static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
  *
  * @return None.
  */
-static inline void uart_ll_set_mode_normal(uart_dev_t *hw)
+FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw)
 {
+    // This function is only for HP_UART use
+    // LP_UART can only work in normal mode
+    // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
+
     hw->rs485_conf_sync.rs485_en = 0;
     hw->rs485_conf_sync.rs485tx_rx_en = 0;
     hw->rs485_conf_sync.rs485rxby_tx_en = 0;
@@ -659,8 +899,12 @@ static inline void uart_ll_set_mode_normal(uart_dev_t *hw)
  *
  * @return None.
  */
-static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
+FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
 {
+    // This function is only for HP_UART use
+    // LP_UART can only work in normal mode
+    // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
+
     // Application software control, remove echo
     hw->rs485_conf_sync.rs485rxby_tx_en = 1;
     hw->conf0_sync.irda_en = 0;
@@ -679,8 +923,12 @@ static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
  *
  * @return None.
  */
-static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
+FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
 {
+    // This function is only for HP_UART use
+    // LP_UART can only work in normal mode
+    // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
+
     // Enable receiver, sw_rts = 1  generates low level on RTS pin
     hw->conf0_sync.sw_rts = 1;
     // Half duplex mode
@@ -702,8 +950,12 @@ static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
  *
  * @return None.
  */
-static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
+FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
 {
+    // This function is only for HP_UART use
+    // LP_UART can only work in normal mode
+    // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
+
     hw->conf0_sync.irda_en = 0;
     // Enable full-duplex mode
     hw->rs485_conf_sync.rs485tx_rx_en = 1;
@@ -723,8 +975,12 @@ static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
  *
  * @return None.
  */
-static inline void uart_ll_set_mode_irda(uart_dev_t *hw)
+FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
 {
+    // This function is only for HP_UART use
+    // LP_UART can only work in normal mode
+    // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
+
     hw->rs485_conf_sync.rs485_en = 0;
     hw->rs485_conf_sync.rs485tx_rx_en = 0;
     hw->rs485_conf_sync.rs485rxby_tx_en = 0;
@@ -741,7 +997,7 @@ static inline void uart_ll_set_mode_irda(uart_dev_t *hw)
  *
  * @return None.
  */
-static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
+FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
 {
     switch (mode) {
         default:
@@ -749,15 +1005,19 @@ static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
             uart_ll_set_mode_normal(hw);
             break;
         case UART_MODE_RS485_COLLISION_DETECT:
+            // Only HP_UART support this mode
             uart_ll_set_mode_collision_detect(hw);
             break;
         case UART_MODE_RS485_APP_CTRL:
+            // Only HP_UART support this mode
             uart_ll_set_mode_rs485_app_ctrl(hw);
             break;
         case UART_MODE_RS485_HALF_DUPLEX:
+            // Only HP_UART support this mode
             uart_ll_set_mode_rs485_half_duplex(hw);
             break;
         case UART_MODE_IRDA:
+            // Only HP_UART support this mode
             uart_ll_set_mode_irda(hw);
             break;
     }
@@ -772,11 +1032,10 @@ static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
  *
  * @return None.
  */
-static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
+FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
 {
-    // *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, data);
-    // *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, char_num);
-    HAL_ASSERT(false);
+    *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, at_cmd_char);
+    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, char_num);
 }
 
 /**
@@ -786,7 +1045,7 @@ static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, ui
  *
  * @return The UART wakeup threshold value.
  */
-static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
+FORCE_INLINE_ATTR uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
 {
     return hw->sleep_conf2.active_threshold + UART_LL_MIN_WAKEUP_THRESH;
 }
@@ -799,7 +1058,7 @@ static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
  *
  * @return The bit mode.
  */
-static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
+FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
 {
     *data_bit = (uart_word_length_t)hw->conf0_sync.bit_num;
 }
@@ -811,9 +1070,9 @@ static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *
  *
  * @return True if the state machine is in the IDLE state, otherwise false is returned.
  */
-static inline bool uart_ll_is_tx_idle(uart_dev_t *hw)
+FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
 {
-    return ((hw->status.txfifo_cnt == 0) && (hw->fsm_status.st_utx_out == 0));
+    return ((((hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw)) == 0) && (hw->fsm_status.st_utx_out == 0));
 }
 
 /**
@@ -823,7 +1082,7 @@ static inline bool uart_ll_is_tx_idle(uart_dev_t *hw)
  *
  * @return True if hw rts flow control is enabled, otherwise false is returned.
  */
-static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
+FORCE_INLINE_ATTR bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
 {
     return hw->hwfc_conf_sync.rx_flow_en;
 }
@@ -835,7 +1094,7 @@ static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
  *
  * @return True if hw cts flow control is enabled, otherwise false is returned.
  */
-static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
+FORCE_INLINE_ATTR bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
 {
     return hw->conf0_sync.tx_flow_en;
 }
@@ -848,13 +1107,13 @@ static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
  *
  * @return None
  */
-static inline void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
+FORCE_INLINE_ATTR void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
 {
     hw->conf0_sync.loopback = loop_back_en;
     uart_ll_update(hw);
 }
 
-static inline void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
+FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
 {
     hw->swfc_conf0_sync.force_xon = 1;
     uart_ll_update(hw);
@@ -873,8 +1132,11 @@ static inline void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
  *
  * @return None.
  */
-static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
+FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
 {
+    // LP_UART does not support UART_SIGNAL_IRDA_TX_INV and UART_SIGNAL_IRDA_RX_INV
+    // lp_uart_dev_t has no these fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
+
     typeof(hw->conf0_sync) conf0_reg;
     conf0_reg.val = hw->conf0_sync.val;
     conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0;
@@ -901,7 +1163,7 @@ static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
  *
  * @return None.
  */
-static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
+FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
 {
     uint16_t tout_val = tout_thrd;
     if(tout_thrd > 0) {
@@ -920,7 +1182,7 @@ static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
  *
  * @return tout_thr The timeout threshold value. If timeout feature is disabled returns 0.
  */
-static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
+FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
 {
     uint16_t tout_thrd = 0;
     if(hw->tout_conf_sync.rx_tout_en > 0) {
@@ -936,9 +1198,9 @@ static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
  *
  * @return maximum timeout threshold.
  */
-static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
+FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
 {
-    return UART_RX_TOUT_THRHD_V;
+    return ((hw) == &LP_UART) ? LP_UART_RX_TOUT_THRHD_V : UART_RX_TOUT_THRHD_V;
 }
 
 /**
@@ -947,8 +1209,11 @@ static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
  * @param  hw Beginning address of the peripheral registers.
  * @param  enable Boolean marking whether the auto baudrate should be enabled or not.
  */
-static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable)
+FORCE_INLINE_ATTR void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable)
 {
+    // LP_UART does not support autobaud
+    // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
+
     hw->conf0_sync.autobaud_en = enable ? 1 : 0;
     uart_ll_update(hw);
 }
@@ -958,7 +1223,7 @@ static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable)
  *
  * @param  hw Beginning address of the peripheral registers.
  */
-static inline uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw)
+FORCE_INLINE_ATTR uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw)
 {
     return hw->rxd_cnt.rxd_edge_cnt;
 }
@@ -968,7 +1233,7 @@ static inline uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw)
  *
  * @param  hw Beginning address of the peripheral registers.
  */
-static inline uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw)
+FORCE_INLINE_ATTR uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw)
 {
     return hw->pospulse.posedge_min_cnt;
 }
@@ -978,7 +1243,7 @@ static inline uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw)
  *
  * @param  hw Beginning address of the peripheral registers.
  */
-static inline uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw)
+FORCE_INLINE_ATTR uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw)
 {
     return hw->negpulse.negedge_min_cnt;
 }
@@ -988,7 +1253,7 @@ static inline uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw)
  *
  * @param  hw Beginning address of the peripheral registers.
  */
-static inline uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
+FORCE_INLINE_ATTR uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
 {
     return hw->highpulse.highpulse_min_cnt;
 }
@@ -998,7 +1263,7 @@ static inline uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
  *
  * @param  hw Beginning address of the peripheral registers.
  */
-static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
+FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
 {
     return hw->lowpulse.lowpulse_min_cnt;
 }
@@ -1010,12 +1275,13 @@ static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
  *
  * @return None.
  */
-static inline void uart_ll_force_xoff(uart_port_t uart_num)
+FORCE_INLINE_ATTR void uart_ll_force_xoff(uart_port_t uart_num)
 {
-    // REG_CLR_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_FORCE_XON);
-    // REG_SET_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XOFF);
-    // uart_ll_update(UART_LL_GET_HW(uart_num));
-    HAL_ASSERT(false);
+    uart_dev_t *hw = UART_LL_GET_HW(uart_num);
+    hw->swfc_conf0_sync.force_xon = 0;
+    hw->swfc_conf0_sync.sw_flow_con_en = 1;
+    hw->swfc_conf0_sync.force_xoff = 1;
+    uart_ll_update(hw);
 }
 
 /**
@@ -1025,13 +1291,14 @@ static inline void uart_ll_force_xoff(uart_port_t uart_num)
  *
  * @return None.
  */
-static inline void uart_ll_force_xon(uart_port_t uart_num)
+FORCE_INLINE_ATTR void uart_ll_force_xon(uart_port_t uart_num)
 {
-    // REG_CLR_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_FORCE_XOFF);
-    // REG_SET_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_FORCE_XON);
-    // REG_CLR_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XON);
-    // uart_ll_update(UART_LL_GET_HW(uart_num));
-    HAL_ASSERT(false);
+    uart_dev_t *hw = UART_LL_GET_HW(uart_num);
+    hw->swfc_conf0_sync.force_xoff = 0;
+    hw->swfc_conf0_sync.force_xon = 1;
+    hw->swfc_conf0_sync.sw_flow_con_en = 0;
+    hw->swfc_conf0_sync.force_xon = 0;
+    uart_ll_update(hw);
 }
 
 /**
@@ -1041,11 +1308,24 @@ static inline void uart_ll_force_xon(uart_port_t uart_num)
  *
  * @return UART module FSM status.
  */
-static inline uint32_t uart_ll_get_tx_fsm_status(uart_port_t uart_num)
+FORCE_INLINE_ATTR uint32_t uart_ll_get_tx_fsm_status(uart_port_t uart_num)
 {
     return REG_GET_FIELD(UART_FSM_STATUS_REG(uart_num), UART_ST_UTX_OUT);
 }
 
+/**
+ * @brief  Configure UART whether to discard when receiving wrong data
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ * @param  discard true: Receiver stops storing data into FIFO when data is wrong
+ *                false: Receiver continue storing data into FIFO when data is wrong
+ */
+FORCE_INLINE_ATTR void uart_ll_discard_error_data(uart_dev_t *hw, bool discard)
+{
+    hw->conf0_sync.err_wr_mask = discard ? 1 : 0;
+    uart_ll_update(hw);
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/include/hal/uart_types.h b/components/hal/include/hal/uart_types.h
index cef1ca85fb..b97944abea 100644
--- a/components/hal/include/hal/uart_types.h
+++ b/components/hal/include/hal/uart_types.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -25,6 +25,12 @@ typedef enum {
 #if SOC_UART_HP_NUM > 2
     UART_NUM_2,                         /*!< UART port 2 */
 #endif
+#if SOC_UART_HP_NUM > 3
+    UART_NUM_3,                         /*!< UART port 3 */
+#endif
+#if SOC_UART_HP_NUM > 4
+    UART_NUM_4,                         /*!< UART port 4 */
+#endif
 #if (SOC_UART_LP_NUM >= 1)
     LP_UART_NUM_0,                      /*!< LP UART port 0 */
 #endif
diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
index 36583829ab..ca2952ae5a 100644
--- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
@@ -1037,16 +1037,20 @@ config SOC_FLASH_ENCRYPTION_XTS_AES_128
 
 config SOC_UART_NUM
     int
-    default 2
+    default 5
 
 config SOC_UART_HP_NUM
     int
-    default 2
+    default 5
 
 config SOC_UART_FIFO_LEN
     int
     default 128
 
+config SOC_LP_UART_FIFO_LEN
+    int
+    default 16
+
 config SOC_UART_BITRATE_MAX
     int
     default 5000000
diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h
index 664e5d4b7b..9fb5ec412b 100644
--- a/components/soc/esp32p4/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h
@@ -151,7 +151,10 @@ typedef enum {
     SOC_MOD_CLK_RC_FAST,                       /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
     SOC_MOD_CLK_XTAL,                          /*!< XTAL_CLK comes from the external 40MHz crystal */
     SOC_MOD_CLK_APLL,                          /*!< Audio PLL is sourced from PLL, and its frequency is configurable through APLL configuration registers */
+    // For LP peripherals
+    SOC_MOD_CLK_XTAL_D2,                       /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */
     SOC_MOD_CLK_INVALID,                       /*!< Indication of the end of the available module clock sources */
+    SOC_MOD_CLK_LP_PLL,
 } soc_module_clk_t;
 
 //////////////////////////////////////////////////SYSTIMER//////////////////////////////////////////////////////////////
@@ -254,7 +257,6 @@ typedef enum {
 
 ///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
 
-//TODO: IDF-6511
 /**
  * @brief Type of UART clock source, reserved for the legacy UART driver
  */
@@ -262,9 +264,23 @@ typedef enum {
     UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M,           /*!< UART source clock is PLL_F80M */
     UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST,                /*!< UART source clock is RC_FAST */
     UART_SCLK_XTAL = SOC_MOD_CLK_XTAL,                  /*!< UART source clock is XTAL */
+#if SOC_CLK_TREE_SUPPORTED
     UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M,           /*!< UART source clock default choice is PLL_F80M */
+#else
+    UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL,               /*!< UART source clock default choice is XTAL for FPGA environment */
+#endif
 } soc_periph_uart_clk_src_legacy_t;
 
+/**
+ * @brief Type of LP_UART clock source
+ */
+typedef enum {
+    LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST,        /*!< LP_UART source clock is LP(RTC)_FAST */
+    LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2,         /*!< LP_UART source clock is XTAL_D2 */
+    LP_UART_SCLK_LP_PLL  = SOC_MOD_CLK_LP_PLL,          /*!< LP_UART source clock is LP_PLL (8M PLL) */
+    LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL_D2,        /*!< LP_UART source clock default choice is XTAL_D2 */
+} soc_periph_lp_uart_clk_src_t;
+
 //////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
 
 /**
diff --git a/components/soc/esp32p4/include/soc/lpperi_struct.h b/components/soc/esp32p4/include/soc/lpperi_struct.h
index 8fccb45de6..34cbda01df 100644
--- a/components/soc/esp32p4/include/soc/lpperi_struct.h
+++ b/components/soc/esp32p4/include/soc/lpperi_struct.h
@@ -348,7 +348,7 @@ typedef union {
 } lpperi_date_reg_t;
 
 
-typedef struct {
+typedef struct lpperi_dev_t {
     volatile lpperi_clk_en_reg_t clk_en;
     volatile lpperi_core_clk_sel_reg_t core_clk_sel;
     volatile lpperi_reset_en_reg_t reset_en;
@@ -364,6 +364,7 @@ typedef struct {
     volatile lpperi_date_reg_t date;
 } lpperi_dev_t;
 
+extern lpperi_dev_t LPPERI;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure");
diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h
index 857fdf8dff..a3d1d0a665 100644
--- a/components/soc/esp32p4/include/soc/soc_caps.h
+++ b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -208,6 +208,7 @@
 // Support to hold a single digital I/O when the digital domain is powered off
 #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP  (1)
 
+// #define SOC_LP_GPIO_MATRIX_SUPPORTED    (1)
 /*-------------------------- RTCIO CAPS --------------------------------------*/
 #define SOC_RTCIO_PIN_COUNT                 16
 #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED    1   /* This macro indicates that the target has separate RTC IOMUX hardware feature,
@@ -470,11 +471,13 @@
 /*-------------------------- MEMPROT CAPS ------------------------------------*/
 
 /*-------------------------- UART CAPS ---------------------------------------*/
-// ESP32-P4 has 2 UARTs
-#define SOC_UART_NUM                    (2)
-#define SOC_UART_HP_NUM                 (2)
+// ESP32-P4 has 6 UARTs (5 HP UART, and 1 LP UART)
+// The RTC GPIO and sigmap is not supported yet, so make SOC_UART_NUM->5 to avoid lp-uart build errors
+#define SOC_UART_NUM                    (5)
+#define SOC_UART_HP_NUM                 (5)
 // #define SOC_UART_LP_NUM                 (1U)
 #define SOC_UART_FIFO_LEN               (128)       /*!< The UART hardware FIFO length */
+#define SOC_LP_UART_FIFO_LEN            (16)        /*!< The LP UART hardware FIFO length */
 #define SOC_UART_BITRATE_MAX            (5000000)   /*!< Max bit rate supported by UART */
 #define SOC_UART_SUPPORT_PLL_F80M_CLK   (1)         /*!< Support PLL_F80M as the clock source */
 #define SOC_UART_SUPPORT_RTC_CLK        (1)         /*!< Support RTC clock as the clock source */
diff --git a/components/soc/esp32p4/include/soc/uart_channel.h b/components/soc/esp32p4/include/soc/uart_channel.h
index c04136b38d..cf01427ec9 100644
--- a/components/soc/esp32p4/include/soc/uart_channel.h
+++ b/components/soc/esp32p4/include/soc/uart_channel.h
@@ -4,6 +4,36 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C6.
+// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32P4.
 
 #pragma once
+
+//UART0 channels
+#define UART_GPIO37_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_TXD_DIRECT_GPIO_NUM  37
+#define UART_GPIO38_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_RXD_DIRECT_GPIO_NUM  38
+#define UART_GPIO8_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_RTS_DIRECT_GPIO_NUM  8
+#define UART_GPIO9_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_CTS_DIRECT_GPIO_NUM  9
+
+#define UART_TXD_GPIO37_DIRECT_CHANNEL  UART_GPIO38_DIRECT_CHANNEL
+#define UART_RXD_GPIO38_DIRECT_CHANNEL  UART_GPIO38_DIRECT_CHANNEL
+#define UART_RTS_GPIO8_DIRECT_CHANNEL   UART_GPIO8_DIRECT_CHANNEL
+#define UART_CTS_GPIO9_DIRECT_CHANNEL   UART_GPIO9_DIRECT_CHANNEL
+
+//UART1 channels
+#define UART_GPIO10_DIRECT_CHANNEL      UART_NUM_1
+#define UART_NUM_1_TXD_DIRECT_GPIO_NUM  10
+#define UART_GPIO11_DIRECT_CHANNEL      UART_NUM_1
+#define UART_NUM_1_RXD_DIRECT_GPIO_NUM  11
+#define UART_GPIO12_DIRECT_CHANNEL      UART_NUM_1
+#define UART_NUM_1_RTS_DIRECT_GPIO_NUM  12
+#define UART_GPIO13_DIRECT_CHANNEL      UART_NUM_1
+#define UART_NUM_1_CTS_DIRECT_GPIO_NUM  13
+
+#define UART_TXD_GPIO10_DIRECT_CHANNEL  UART_GPIO10_DIRECT_CHANNEL
+#define UART_RXD_GPIO11_DIRECT_CHANNEL  UART_GPIO11_DIRECT_CHANNEL
+#define UART_RTS_GPIO12_DIRECT_CHANNEL  UART_GPIO12_DIRECT_CHANNEL
+#define UART_CTS_GPIO13_DIRECT_CHANNEL  UART_GPIO13_DIRECT_CHANNEL
diff --git a/components/soc/esp32p4/include/soc/uart_pins.h b/components/soc/esp32p4/include/soc/uart_pins.h
index a5d49ea6e7..d7d8da9562 100644
--- a/components/soc/esp32p4/include/soc/uart_pins.h
+++ b/components/soc/esp32p4/include/soc/uart_pins.h
@@ -10,3 +10,68 @@
 
 /* Specify the number of pins for UART */
 #define SOC_UART_PINS_COUNT  (4)
+
+/* Specify the GPIO pin number for each UART signal in the IOMUX */
+#define U0RXD_GPIO_NUM 38
+#define U0TXD_GPIO_NUM 37
+#define U0RTS_GPIO_NUM 8
+#define U0CTS_GPIO_NUM 9
+
+#define U1RXD_GPIO_NUM 11
+#define U1TXD_GPIO_NUM 10
+#define U1RTS_GPIO_NUM 12
+#define U1CTS_GPIO_NUM 13
+
+#define U2RXD_GPIO_NUM (-1)
+#define U2TXD_GPIO_NUM (-1)
+#define U2RTS_GPIO_NUM (-1)
+#define U2CTS_GPIO_NUM (-1)
+
+#define U3RXD_GPIO_NUM (-1)
+#define U3TXD_GPIO_NUM (-1)
+#define U3RTS_GPIO_NUM (-1)
+#define U3CTS_GPIO_NUM (-1)
+
+#define U4RXD_GPIO_NUM (-1)
+#define U4TXD_GPIO_NUM (-1)
+#define U4RTS_GPIO_NUM (-1)
+#define U4CTS_GPIO_NUM (-1)
+
+#define LP_U0RXD_GPIO_NUM 15
+#define LP_U0TXD_GPIO_NUM 14
+#define LP_U0RTS_GPIO_NUM (-1)
+#define LP_U0CTS_GPIO_NUM (-1)
+
+/* The following defines are necessary for reconfiguring the UART
+ * to use IOMUX, at runtime. */
+#define U0TXD_MUX_FUNC  (FUNC_GPIO37_UART0_TXD_PAD)
+#define U0RXD_MUX_FUNC  (FUNC_GPIO38_UART0_RXD_PAD)
+#define U0RTS_MUX_FUNC  (FUNC_GPIO8_UART0_RTS_PAD)
+#define U0CTS_MUX_FUNC  (FUNC_GPIO9_UART0_CTS_PAD)
+
+/* Same goes for UART1 */
+#define U1TXD_MUX_FUNC  (FUNC_GPIO10_UART1_TXD_PAD)
+#define U1RXD_MUX_FUNC  (FUNC_GPIO11_UART1_RXD_PAD)
+#define U1RTS_MUX_FUNC  (FUNC_GPIO12_UART1_RTS_PAD)
+#define U1CTS_MUX_FUNC  (FUNC_GPIO13_UART1_CTS_PAD)
+
+/* No func for the following pins, they shall not be used */
+#define U2TXD_MUX_FUNC  (-1)
+#define U2RXD_MUX_FUNC  (-1)
+#define U2RTS_MUX_FUNC  (-1)
+#define U2CTS_MUX_FUNC  (-1)
+
+#define U3TXD_MUX_FUNC  (-1)
+#define U3RXD_MUX_FUNC  (-1)
+#define U3RTS_MUX_FUNC  (-1)
+#define U3CTS_MUX_FUNC  (-1)
+
+#define U4TXD_MUX_FUNC  (-1)
+#define U4RXD_MUX_FUNC  (-1)
+#define U4RTS_MUX_FUNC  (-1)
+#define U4CTS_MUX_FUNC  (-1)
+
+#define LP_U0TXD_MUX_FUNC  (0)
+#define LP_U0RXD_MUX_FUNC  (0)
+#define LP_U0RTS_MUX_FUNC  (-1)
+#define LP_U0CTS_MUX_FUNC  (-1)
diff --git a/components/soc/esp32p4/include/soc/uart_struct.h b/components/soc/esp32p4/include/soc/uart_struct.h
index 735f4ad96a..6c8375d5c1 100644
--- a/components/soc/esp32p4/include/soc/uart_struct.h
+++ b/components/soc/esp32p4/include/soc/uart_struct.h
@@ -19,8 +19,7 @@ typedef union {
         /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
          *  UART $n accesses FIFO via this register.
          */
-        uint32_t rxfifo_rd_byte:8;
-        uint32_t reserved_8:24;
+        uint32_t rxfifo_rd_byte:32;
     };
     uint32_t val;
 } uart_fifo_reg_t;
@@ -1216,7 +1215,7 @@ typedef union {
 } uart_id_reg_t;
 
 
-typedef struct {
+typedef struct uart_dev_t{
     volatile uart_fifo_reg_t fifo;
     volatile uart_int_raw_reg_t int_raw;
     volatile uart_int_st_reg_t int_st;
@@ -1246,12 +1245,12 @@ typedef struct {
     volatile uart_mem_tx_status_reg_t mem_tx_status;
     volatile uart_mem_rx_status_reg_t mem_rx_status;
     volatile uart_fsm_status_reg_t fsm_status;
-    volatile uart_pospulse_reg_t pospulse;
-    volatile uart_negpulse_reg_t negpulse;
-    volatile uart_lowpulse_reg_t lowpulse;
-    volatile uart_highpulse_reg_t highpulse;
-    volatile uart_rxd_cnt_reg_t rxd_cnt;
-    volatile uart_clk_conf_reg_t clk_conf;
+    volatile uart_pospulse_reg_t pospulse;      /* LP_UART instance has this register reserved */
+    volatile uart_negpulse_reg_t negpulse;      /* LP_UART instance has this register reserved */
+    volatile uart_lowpulse_reg_t lowpulse;      /* LP_UART instance has this register reserved */
+    volatile uart_highpulse_reg_t highpulse;    /* LP_UART instance has this register reserved */
+    volatile uart_rxd_cnt_reg_t rxd_cnt;        /* LP_UART instance has this register reserved */
+    volatile uart_clk_conf_reg_t clk_conf;      /* UART0/1/2/3/4 instance have this register reserved, configure in corresponding PCR registers */
     volatile uart_date_reg_t date;
     volatile uart_afifo_status_reg_t afifo_status;
     uint32_t reserved_094;
@@ -1261,6 +1260,10 @@ typedef struct {
 
 extern uart_dev_t UART0;
 extern uart_dev_t UART1;
+extern uart_dev_t UART2;
+extern uart_dev_t UART3;
+extern uart_dev_t UART4;
+extern uart_dev_t LP_UART;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure");
diff --git a/components/soc/esp32p4/ld/esp32p4.peripherals.ld b/components/soc/esp32p4/ld/esp32p4.peripherals.ld
index 40e8213dfd..059a30e4b7 100644
--- a/components/soc/esp32p4/ld/esp32p4.peripherals.ld
+++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld
@@ -68,6 +68,7 @@ PROVIDE ( PMU           = 0x50115000 );
 PROVIDE ( LP_SYS        = 0x50110000 );
 PROVIDE ( LP_AON_CLKRST = 0x50111000 );
 PROVIDE ( EFUSE         = 0x5012D000 );
+PROVIDE ( LPPERI        = 0x50120000 );
 PROVIDE ( LP_TIMER      = 0x50112000 );
 PROVIDE ( LP_UART       = 0x50121000 );
 PROVIDE ( LP_I2C        = 0x50122000 );
diff --git a/components/soc/esp32p4/uart_periph.c b/components/soc/esp32p4/uart_periph.c
index 2b0c63eb1b..76047b25a1 100644
--- a/components/soc/esp32p4/uart_periph.c
+++ b/components/soc/esp32p4/uart_periph.c
@@ -5,10 +5,213 @@
  */
 
 #include "soc/uart_periph.h"
+#include "soc/lp_gpio_sig_map.h"
 
 /*
  Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
 */
 const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
+   { // HP UART0
+        .pins = {
+            [SOC_UART_TX_PIN_IDX] = {
+                .default_gpio = U0TXD_GPIO_NUM,
+                .iomux_func = U0TXD_MUX_FUNC,
+                .input = 0,
+                .signal = UART0_TXD_PAD_OUT_IDX,
+            },
 
+            [SOC_UART_RX_PIN_IDX] = {
+                .default_gpio = U0RXD_GPIO_NUM,
+                .iomux_func = U0RXD_MUX_FUNC,
+                .input = 1,
+                .signal = UART0_RXD_PAD_IN_IDX,
+            },
+
+            [SOC_UART_RTS_PIN_IDX] = {
+                .default_gpio = U0RTS_GPIO_NUM,
+                .iomux_func = U0RTS_MUX_FUNC,
+                .input = 0,
+                .signal = UART0_RTS_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_CTS_PIN_IDX] = {
+                .default_gpio = U0CTS_GPIO_NUM,
+                .iomux_func = U0CTS_MUX_FUNC,
+                .input = 1,
+                .signal = UART0_CTS_PAD_IN_IDX,
+            }
+        },
+        .irq = ETS_UART0_INTR_SOURCE,
+        .module = PERIPH_UART0_MODULE,
+    },
+
+    { // HP UART1
+        .pins = {
+            [SOC_UART_TX_PIN_IDX] = {
+                .default_gpio = U1TXD_GPIO_NUM,
+                .iomux_func = U1TXD_MUX_FUNC,
+                .input = 0,
+                .signal = UART1_TXD_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_RX_PIN_IDX] = {
+                .default_gpio = U1RXD_GPIO_NUM,
+                .iomux_func = U1RXD_MUX_FUNC,
+                .input = 1,
+                .signal = UART1_RXD_PAD_IN_IDX,
+            },
+
+            [SOC_UART_RTS_PIN_IDX] = {
+                .default_gpio = U1RTS_GPIO_NUM,
+                .iomux_func = U1RTS_MUX_FUNC,
+                .input = 0,
+                .signal = UART1_RTS_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_CTS_PIN_IDX] = {
+                .default_gpio = U1CTS_GPIO_NUM,
+                .iomux_func = U1CTS_MUX_FUNC,
+                .input = 1,
+                .signal = UART1_CTS_PAD_IN_IDX,
+            },
+        },
+        .irq = ETS_UART1_INTR_SOURCE,
+        .module = PERIPH_UART1_MODULE,
+    },
+
+    { // HP UART2
+        .pins = {
+            [SOC_UART_TX_PIN_IDX] = {
+                .default_gpio = U2TXD_GPIO_NUM,
+                .iomux_func = U2TXD_MUX_FUNC,
+                .input = 0,
+                .signal = UART2_TXD_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_RX_PIN_IDX] = {
+                .default_gpio = U2RXD_GPIO_NUM,
+                .iomux_func = U2RXD_MUX_FUNC,
+                .input = 1,
+                .signal = UART2_RXD_PAD_IN_IDX,
+            },
+
+            [SOC_UART_RTS_PIN_IDX] = {
+                .default_gpio = U2RTS_GPIO_NUM,
+                .iomux_func = U2RTS_MUX_FUNC,
+                .input = 0,
+                .signal = UART2_RTS_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_CTS_PIN_IDX] = {
+                .default_gpio = U2CTS_GPIO_NUM,
+                .iomux_func = U2CTS_MUX_FUNC,
+                .input = 1,
+                .signal = UART2_CTS_PAD_IN_IDX,
+            },
+        },
+        .irq = ETS_UART2_INTR_SOURCE,
+        .module = PERIPH_UART2_MODULE,
+    },
+
+    { // HP UART3
+        .pins = {
+            [SOC_UART_TX_PIN_IDX] = {
+                .default_gpio = U3TXD_GPIO_NUM,
+                .iomux_func = U3TXD_MUX_FUNC,
+                .input = 0,
+                .signal = UART3_TXD_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_RX_PIN_IDX] = {
+                .default_gpio = U3RXD_GPIO_NUM,
+                .iomux_func = U3RXD_MUX_FUNC,
+                .input = 1,
+                .signal = UART3_RXD_PAD_IN_IDX,
+            },
+
+            [SOC_UART_RTS_PIN_IDX] = {
+                .default_gpio = U3RTS_GPIO_NUM,
+                .iomux_func = U3RTS_MUX_FUNC,
+                .input = 0,
+                .signal = UART3_RTS_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_CTS_PIN_IDX] = {
+                .default_gpio = U3CTS_GPIO_NUM,
+                .iomux_func = U3CTS_MUX_FUNC,
+                .input = 1,
+                .signal = UART3_CTS_PAD_IN_IDX,
+            },
+        },
+        .irq = ETS_UART3_INTR_SOURCE,
+        .module = PERIPH_UART3_MODULE,
+    },
+
+    { // HP UART4
+        .pins = {
+            [SOC_UART_TX_PIN_IDX] = {
+                .default_gpio = U4TXD_GPIO_NUM,
+                .iomux_func = U4TXD_MUX_FUNC,
+                .input = 0,
+                .signal = UART4_TXD_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_RX_PIN_IDX] = {
+                .default_gpio = U4RXD_GPIO_NUM,
+                .iomux_func = U4RXD_MUX_FUNC,
+                .input = 1,
+                .signal = UART4_RXD_PAD_IN_IDX,
+            },
+
+            [SOC_UART_RTS_PIN_IDX] = {
+                .default_gpio = U4RTS_GPIO_NUM,
+                .iomux_func = U4RTS_MUX_FUNC,
+                .input = 0,
+                .signal = UART4_RTS_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_CTS_PIN_IDX] = {
+                .default_gpio = U4CTS_GPIO_NUM,
+                .iomux_func = U4CTS_MUX_FUNC,
+                .input = 1,
+                .signal = UART4_CTS_PAD_IN_IDX,
+            },
+        },
+        .irq = ETS_UART4_INTR_SOURCE,
+        .module = PERIPH_UART4_MODULE,
+    },
+    //TODO:IDF-7815
+    // { // LP UART0
+    //     .pins = {
+    //         [SOC_UART_TX_PIN_IDX] = {
+    //             .default_gpio = LP_U0TXD_GPIO_NUM,
+    //             .iomux_func = LP_U0TXD_MUX_FUNC,
+    //             .input = 0,
+    //             .signal = LP_UART_TXD_PAD_OUT_IDX,
+    //         },
+
+    //         [SOC_UART_RX_PIN_IDX] = {
+    //             .default_gpio = LP_U0RXD_GPIO_NUM,
+    //             .iomux_func = LP_U0RXD_MUX_FUNC,
+    //             .input = 1,
+    //             .signal = LP_UART_RXD_PAD_IN_IDX,
+    //         },
+
+    //         [SOC_UART_RTS_PIN_IDX] = {
+    //             .default_gpio = LP_U0RTS_GPIO_NUM,
+    //             .iomux_func = LP_U0RTS_MUX_FUNC,
+    //             .input = 0,
+    //             .signal = LP_UART_RTSN_PAD_OUT_IDX,
+    //         },
+
+    //         [SOC_UART_CTS_PIN_IDX] = {
+    //             .default_gpio = LP_U0CTS_GPIO_NUM,
+    //             .iomux_func = LP_U0CTS_MUX_FUNC,
+    //             .input = 1,
+    //             .signal = LP_UART_CTSN_PAD_IN_IDX,
+    //         },
+    //     },
+    //     .irq = ETS_LP_UART_INTR_SOURCE,
+    //     .module = PERIPH_LP_UART0_MODULE,
+    // },
 };