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soc/rtc: reset another BBPLL related register

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Follow-up to b21ffc8a: an additional register needs to be reset.

Ref. https://github.com/espressif/esp-idf/issues/2711
This commit is contained in:
Ivan Grokhotkov 2018-12-12 12:22:48 +08:00
parent 19e96add8a
commit c7a297195f
1 changed files with 2 additions and 1 deletions
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3
components/soc/esp32/rtc_clk.c
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@ -48,7 +48,7 @@
#define BBPLL_IR_CAL_EXT_CAP_VAL 0x20
#define BBPLL_OC_ENB_FCAL_VAL 0x9a
#define BBPLL_OC_ENB_VCON_VAL 0x00
#define BBPLL_BBADC_CAL_7_0_VAL 0x00
#define APLL_SDM_STOP_VAL_1 0x09
#define APLL_SDM_STOP_VAL_2_REV0 0x69
@ -441,6 +441,7 @@ static void rtc_clk_bbpll_enable()
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, BBPLL_BBADC_CAL_7_0_VAL);
}
/**