From c796e149644f3a7f8beabded0f5e32a5f509d2b8 Mon Sep 17 00:00:00 2001 From: Li Shuai Date: Mon, 2 Mar 2020 20:40:07 +0800 Subject: [PATCH] added psram stack check in backtrace --- .../soc/include/soc/soc_memory_layout.h | 19 ++++++++++++++++++- components/spi_flash/cache_utils.c | 2 ++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/components/soc/include/soc/soc_memory_layout.h b/components/soc/include/soc/soc_memory_layout.h index 068890c8a7..a393f08419 100644 --- a/components/soc/include/soc/soc_memory_layout.h +++ b/components/soc/include/soc/soc_memory_layout.h @@ -251,9 +251,26 @@ inline static void * IRAM_ATTR esp_ptr_diram_iram_to_dram(const void *p) { #endif } -inline static bool IRAM_ATTR esp_stack_ptr_is_sane(uint32_t sp) +inline static bool IRAM_ATTR esp_stack_ptr_in_dram(uint32_t sp) { //Check if stack ptr is in between SOC_DRAM_LOW and SOC_DRAM_HIGH, and 16 byte aligned. return !(sp < SOC_DRAM_LOW + 0x10 || sp > SOC_DRAM_HIGH - 0x10 || ((sp & 0xF) != 0)); } +#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY +inline static bool IRAM_ATTR esp_stack_ptr_in_extram(uint32_t sp) +{ + //Check if stack ptr is in between SOC_EXTRAM_DATA_LOW and SOC_EXTRAM_DATA_HIGH, and 16 byte aligned. + return !(sp < SOC_EXTRAM_DATA_LOW + 0x10 || sp > SOC_EXTRAM_DATA_HIGH - 0x10 || ((sp & 0xF) != 0)); +} +#endif + +inline static bool IRAM_ATTR esp_stack_ptr_is_sane(uint32_t sp) +{ +#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY + return (esp_stack_ptr_in_dram(sp) || esp_stack_ptr_in_extram(sp)); +#else + return esp_stack_ptr_in_dram(sp); +#endif +} + diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c index 54a296fc63..495a748bee 100644 --- a/components/spi_flash/cache_utils.c +++ b/components/spi_flash/cache_utils.c @@ -113,6 +113,8 @@ void IRAM_ATTR spi_flash_op_block_func(void *arg) void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void) { + assert(esp_ptr_in_dram((const void *)get_sp())); + spi_flash_op_lock(); const uint32_t cpuid = xPortGetCoreID();